[ARM] Transform a fixed-point to floating-point conversion into a VCVT_fix

[samtebbs]

Summary

Conversion from a fixed-point number to a floating-point number is done by multiplying the fixed-point number by 2^(-n) where n is the number of fractional bits. Currently this is lowered to a vcvt (integer to floating-point) then a vmul, but it can instead be lowered directly to a vcvt (fixed-point to floating-point). This patch enables such transformations as long as the multiplication factor is a power of 2.

[dmgreen]

Nice one. Sounds funky.

llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp

3683

This is pretty chunky. I think it's worth moving to it's own function, like the other try* methods here.

3698

I think can be "IsUnsigned" too. The values out of range are 65520+, so can only happen under unsigned convertions.

3701

Bitcast can go wrong under BE if it's changing the type size. It can move the order of elements in the vector around. Is this only interested in cases where the element sizes are the same, and if so can it add a check?

3708

"valid" would be "Valid", but this may not be needed if this was a separate function. It can just return false out of the default then.

3712

If this is a vdup, it won't always have a constant operand.

3718

I think we ruled out 64bit floats above.

3744

Should this be in some range too? Not negative? Do you have a few tests for cases like that?

3753–3754

Perhaps add a default: llvm_unreachable(..); and then Opcode doesn't need a default value (but maybe 0 would be fine too?)

llvm/test/CodeGen/ARM/arm_q15_to_float_autovec.ll

2 ↗

(On Diff #350619)

Can you move the test to CodeGen/Thumb2/mve-<something>.ll, with all the others. Maybe mve-vcvt-fixed.ll? Also it shouldn't need -O3 on the llc line.

4 ↗

(On Diff #350619)

Remove dso_local and the local_unnamed_addr from all these tests, and add arm_aapcs_vfpcc. That should clean up a lot of the soft-float vmovs.

434 ↗

(On Diff #350619)

This kind of looks negative ;)

[samtebbs]

llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp

3683

Good idea. Does tryFMUL seem like a good name?

3698

👍

3701

It is indeed. I'll add a check to make sure that the element sizes are the same.

3712

👍

3718

Indeed we did

3744

I think you're right that there should be a range check, but I think it should come below where we compute FracBits as that must be less or equal to ScalarBits. Regarding it being negative, is that possible if it is a power of 2?

3753–3754

Good idea

llvm/test/CodeGen/ARM/arm_q15_to_float_autovec.ll

2 ↗

(On Diff #350619)

Ah yes! I totally forgot to rename the file.

4 ↗

(On Diff #350619)

👍

[samtebbs]

Move to a function, add IsUnsigned check to fp inf, check bitcast element size, remove IEEEdouble(), make sure FracBits <= ScalarBits, add llvm_unreachable, move test file and use arm_aapcs_vfpcc.

[samtebbs]

Rebase and check if FracBits == ScalarBits - 1 when not unsigned.

[samtebbs]

Check if the VDUP operand is constant and do clang-format.

[samtebbs]

llvm/test/CodeGen/ARM/arm_q15_to_float_autovec.ll

434 ↗

(On Diff #350619)

It does! I have added a check for fracbits == scalarbits - 1 when not unsigned.

[dmgreen]

llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp

199

Perhaps tryFMulFixed, to explain a little more what the function tries to match?

3190

Can use isa, as opposed to dyn_cast.

I'm not sure what the TODO is related to?

llvm/test/CodeGen/Thumb2/mve-vcvt-fixed.ll

305

Can you add a testcase that uses 0x3E00000000000000 as the constant too. Plus another one that perhaps uses 0xBF00000000000000. That should cover a few negative power of 2 cases.

[samtebbs]

llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp

199

Sounds good to me

3190

Good idea 👍

The TODO is saying that when we find examples of VDUPs that don't have a constant operand we should modify this to work with them.

llvm/test/CodeGen/Thumb2/mve-vcvt-fixed.ll

305

I certainly can

[samtebbs]

Rename tryFMUL, use isa instead of dyn_cast and add more negative factor tests

[dmgreen]

llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp

3190

I think we are only interested in constants. We have tests for all the cases, so I'm not sure there will be cases without the operand to the vdup being a constant. And if they weren't constants, it sounds difficult to try and do anything with them here.

i.e, I think you can remove the TODO :)

llvm/test/CodeGen/Thumb2/mve-vcvt-fixed.ll

772

This one shouldn't be converted, if the 0xBE00000000000000 is negative.

With a constant of 0x3E00000000000000 (which is really 0x30000000 as a float not a double, which is apparently 4.65661287308e-10, which is 1.0f/0x80000000) it should be converted, as far as I understand.

986

I think this one maybe can be converted? But the last one with a FracBits of 31 might be a difficult to prove, if the math becomes inexact.

[samtebbs]

llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp

3190

Agreed :)

llvm/test/CodeGen/Thumb2/mve-vcvt-fixed.ll

772

Ah yes. When checking if the immediate's top bit is set I also check if the vector is signed, but of course floats are always signed so I'll need to remove the !IsUnsigned check. Thanks!

[samtebbs]

Remove !IsUnsigned check and TODO

[samtebbs]

Remove FracBits == ScalarBits - 1 check and add more tests

[dmgreen]

Thanks. This LGTM

llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp

 //
 //===----------------------------------------------------------------------===//
 
 #include "ARM.h"
 #include "ARMBaseInstrInfo.h"
 #include "ARMTargetMachine.h"
 #include "MCTargetDesc/ARMAddressingModes.h"
 #include "Utils/ARMBaseInfo.h"
+#include "llvm/ADT/APSInt.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/SelectionDAGISel.h"
 #include "llvm/CodeGen/TargetLowering.h"

 private:
   void transferMemOperands(SDNode *Src, SDNode *Dst);
 
   /// Indexed (pre/post inc/dec) load matching code for ARM.
   bool tryARMIndexedLoad(SDNode *N);
   bool tryT1IndexedLoad(SDNode *N);
   bool tryT2IndexedLoad(SDNode *N);
   bool tryMVEIndexedLoad(SDNode *N);
+  bool tryFMUL(SDNode *N, SDLoc dl);
 
   /// SelectVLD - Select NEON load intrinsics.  NumVecs should be
   /// 1, 2, 3 or 4.  The opcode arrays specify the instructions used for
   /// loads of D registers and even subregs and odd subregs of Q registers.
   /// For NumVecs <= 2, QOpcodes1 is not used.
   void SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
                  const uint16_t *DOpcodes, const uint16_t *QOpcodes0,
                  const uint16_t *QOpcodes1);
SDValue NewIns =
                                       Ins2.getOperand(0), SDValue(VINS, 0));
     ReplaceUses(Ins1, NewIns);
     return true;
   }
 
   return false;
 }
 
+bool ARMDAGToDAGISel::tryFMUL(SDNode *N, SDLoc dl) {
+  // Transform a fixed-point to floating-point conversion to a VCVT
+  if (!Subtarget->hasMVEFloatOps())
+    return false;
+  auto Type = N->getValueType(0);
+  if (!Type.isVector())
+    return false;
+
+  auto ScalarType = Type.getVectorElementType();
+  unsigned ScalarBits = ScalarType.getSizeInBits();
+  auto LHS = N->getOperand(0);
+  auto RHS = N->getOperand(1);
+
+  if (ScalarBits > 32)
+    return false;
+
+  if (RHS.getOpcode() == ISD::BITCAST) {
+    if (RHS.getValueType().getVectorElementType().getSizeInBits() != ScalarBits)
+      return false;
+    RHS = RHS.getOperand(0);
+  }
+  if (RHS.getValueType().getVectorElementType().getSizeInBits() != ScalarBits)
+    return false;
+  if (LHS.getOpcode() != ISD::SINT_TO_FP && LHS.getOpcode() != ISD::UINT_TO_FP)
+    return false;
+
+  bool IsUnsigned = LHS.getOpcode() == ISD::UINT_TO_FP;
+  SDNodeFlags FMulFlags = N->getFlags();
+  // The fixed-point vcvt and vcvt+vmul are not always equivalent if inf is
+  // allowed in 16 bit unsigned floats
+  if (ScalarBits == 16 && !FMulFlags.hasNoInfs() && IsUnsigned)
+    return false;
+
+  APFloat ImmAPF(0.0f);
+  switch (RHS.getOpcode()) {
+  case ARMISD::VMOVIMM:
+  case ARMISD::VDUP: {
+    unsigned Imm = RHS.getConstantOperandVal(0);
+    if (RHS.getOpcode() == ARMISD::VMOVIMM)
+      Imm = ARM_AM::decodeVMOVModImm(Imm, ScalarBits);
+    ImmAPF =
+        APFloat(ScalarBits == 32 ? APFloat::IEEEsingle() : APFloat::IEEEhalf(),
+                APInt(ScalarBits, Imm));
+    break;
+  }
+  case ARMISD::VMOVFPIMM: {
+    ImmAPF = APFloat(ARM_AM::getFPImmFloat(RHS.getConstantOperandVal(0)));
+    break;
+  }
+  default:
+    return false;
+  }
+
+  // Multiplying by a factor of 2^(-n) will convert from fixed point to
+  // floating point, where n is the number of fractional bits in the fixed
+  // point number. Taking the inverse and log2 of the factor will give n
+  APFloat Inverse(0.0f);
+  if (!ImmAPF.getExactInverse(&Inverse))
+    return false;
+
+  APSInt Converted(ScalarBits, 0);
+  bool IsExact;
+  Inverse.convertToInteger(Converted, llvm::RoundingMode::NearestTiesToEven,
+                           &IsExact);
+  if (!IsExact || !Converted.isPowerOf2())
+    return false;
+
+  unsigned FracBits = Converted.logBase2();
+  if (FracBits > ScalarBits)
+    return false;
+
+  auto SintToFpOperand = LHS.getOperand(0);
+  SmallVector<SDValue, 3> Ops{SintToFpOperand,
+                              CurDAG->getConstant(FracBits, dl, MVT::i32)};
+  AddEmptyMVEPredicateToOps(Ops, dl, Type);
+
+  unsigned int Opcode;
+  switch (ScalarBits) {
+  case 16:
+    Opcode = IsUnsigned ? ARM::MVE_VCVTf16u16_fix : ARM::MVE_VCVTf16s16_fix;
+    break;
+  case 32:
+    Opcode = IsUnsigned ? ARM::MVE_VCVTf32u32_fix : ARM::MVE_VCVTf32s32_fix;
+    break;
+  default:
+    llvm_unreachable("unexpected number of scalar bits");
+    break;
+  }
+
+  ReplaceNode(N, CurDAG->getMachineNode(Opcode, dl, Type, Ops));
+  return true;
+}
+
 bool ARMDAGToDAGISel::tryV6T2BitfieldExtractOp(SDNode *N, bool isSigned) {
   if (!Subtarget->hasV6T2Ops())
     return false;
 
   unsigned Opc = isSigned
     ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
     : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
   SDLoc dl(N);
case ISD::SRL:
     if (tryV6T2BitfieldExtractOp(N, false))
       return;
     break;
   case ISD::SIGN_EXTEND_INREG:
   case ISD::SRA:
     if (tryV6T2BitfieldExtractOp(N, true))
       return;
     break;
+  case ISD::FMUL:
+    if (tryFMUL(N, dl))
+      return;
+    break;
   case ISD::MUL:
     if (Subtarget->isThumb1Only())
       break;
     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
       unsigned RHSV = C->getZExtValue();
       if (!RHSV) break;
       if (isPowerOf2_32(RHSV-1)) {  // 2^n+1?
         unsigned ShImm = Log2_32(RHSV-1);
         if (ShImm >= 32)
           break;
         SDValue V = N->getOperand(0);
         ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
         SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, dl, MVT::i32);
         SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
         if (Subtarget->isThumb()) {
           SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 };
           CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops);
           return;
         } else {
           SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0,
                             Reg0 };
           CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops);
           return;
         }
       }
       if (isPowerOf2_32(RHSV+1)) {  // 2^n-1?
         unsigned ShImm = Log2_32(RHSV+1);
         if (ShImm >= 32)
           break;
         SDValue V = N->getOperand(0);
         ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
         SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, dl, MVT::i32);
         SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
         if (Subtarget->isThumb()) {
           SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 };
           CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops);
           return;
         } else {
           SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0,
                             Reg0 };
           CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops);
           return;
         }
       }
case ISD::AND: {
     // can negate the immediate and use a BIC instead.
     auto *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1));
     if (N1C && N1C->hasOneUse() && Subtarget->isThumb()) {
       uint32_t Imm = (uint32_t) N1C->getZExtValue();
 
       // In Thumb2 mode, an AND can take a 12-bit immediate. If this
       // immediate can be negated and fit in the immediate operand of
       // a t2BIC, don't do any manual transform here as this can be
       // handled by the generic ISel machinery.
       bool PreferImmediateEncoding =
         Subtarget->hasThumb2() && (is_t2_so_imm(Imm) || is_t2_so_imm_not(Imm));
       if (!PreferImmediateEncoding &&
           ConstantMaterializationCost(Imm, Subtarget) >
               ConstantMaterializationCost(~Imm, Subtarget)) {
         // The current immediate costs more to materialize than a negated
         // immediate, so negate the immediate and use a BIC.
         SDValue NewImm =
           CurDAG->getConstant(~N1C->getZExtValue(), dl, MVT::i32);
         // If the new constant didn't exist before, reposition it in the topological
         // ordering so it is just before N. Otherwise, don't touch its location.
         if (NewImm->getNodeId() == -1)
           CurDAG->RepositionNode(N->getIterator(), NewImm.getNode());
 
         if (!Subtarget->hasThumb2()) {
           SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32),
                            N->getOperand(0), NewImm, getAL(CurDAG, dl),
                            CurDAG->getRegister(0, MVT::i32)};

llvm/test/CodeGen/Thumb2/mve-vcvt-fixed.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi %s -o - -mattr=+mve.fp | FileCheck %s
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_i32_1(<4 x i32> %0) {
+; CHECK-LABEL: vcvt_i32_1:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #1
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_i32_2(<4 x i32> %0) {
+; CHECK-LABEL: vcvt_i32_2:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #2
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 2.500000e-01, float 2.500000e-01, float 2.500000e-01, float 2.500000e-01>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_i32_3(<4 x i32> %0) {
+; CHECK-LABEL: vcvt_i32_3:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #3
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 1.250000e-01, float 1.250000e-01, float 1.250000e-01, float 1.250000e-01>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_i32_4(<4 x i32> %0) {
+; CHECK-LABEL: vcvt_i32_4:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #4
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 6.250000e-02, float 6.250000e-02, float 6.250000e-02, float 6.250000e-02>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_i32_5(<4 x i32> %0) {
+; CHECK-LABEL: vcvt_i32_5:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #5
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 3.125000e-02, float 3.125000e-02, float 3.125000e-02, float 3.125000e-02>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_i32_6(<4 x i32> %0) {
+; CHECK-LABEL: vcvt_i32_6:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #6
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 1.562500e-02, float 1.562500e-02, float 1.562500e-02, float 1.562500e-02>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_i32_7(<4 x i32> %0) {
+; CHECK-LABEL: vcvt_i32_7:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #7
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 7.812500e-03, float 7.812500e-03, float 7.812500e-03, float 7.812500e-03>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_i32_8(<4 x i32> %0) {
+; CHECK-LABEL: vcvt_i32_8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #8
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 3.906250e-03, float 3.906250e-03, float 3.906250e-03, float 3.906250e-03>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_i32_9(<4 x i32> %0) {
+; CHECK-LABEL: vcvt_i32_9:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #9
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3F60000000000000, float 0x3F60000000000000, float 0x3F60000000000000, float 0x3F60000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_i32_10(<4 x i32> %0) {
+; CHECK-LABEL: vcvt_i32_10:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #10
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3F50000000000000, float 0x3F50000000000000, float 0x3F50000000000000, float 0x3F50000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_i32_11(<4 x i32> %0) {
+; CHECK-LABEL: vcvt_i32_11:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #11
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3F40000000000000, float 0x3F40000000000000, float 0x3F40000000000000, float 0x3F40000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_i32_12(<4 x i32> %0) {
+; CHECK-LABEL: vcvt_i32_12:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #12
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3F30000000000000, float 0x3F30000000000000, float 0x3F30000000000000, float 0x3F30000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_i32_13(<4 x i32> %0) {
+; CHECK-LABEL: vcvt_i32_13:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #13
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3F20000000000000, float 0x3F20000000000000, float 0x3F20000000000000, float 0x3F20000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_i32_14(<4 x i32> %0)  {
+; CHECK-LABEL: vcvt_i32_14:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #14
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_i32_15(<4 x i32> %0) {
+; CHECK-LABEL: vcvt_i32_15:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #15
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3F00000000000000, float 0x3F00000000000000, float 0x3F00000000000000, float 0x3F00000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_i32_16(<4 x i32> %0) {
+; CHECK-LABEL: vcvt_i32_16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #16
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3EF0000000000000, float 0x3EF0000000000000, float 0x3EF0000000000000, float 0x3EF0000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_i32_17(<4 x i32> %0) {
+; CHECK-LABEL: vcvt_i32_17:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #17
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3EE0000000000000, float 0x3EE0000000000000, float 0x3EE0000000000000, float 0x3EE0000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_i32_18(<4 x i32> %0) {
+; CHECK-LABEL: vcvt_i32_18:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #18
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3ED0000000000000, float 0x3ED0000000000000, float 0x3ED0000000000000, float 0x3ED0000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_i32_19(<4 x i32> %0) {
+; CHECK-LABEL: vcvt_i32_19:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #19
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3EC0000000000000, float 0x3EC0000000000000, float 0x3EC0000000000000, float 0x3EC0000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_i32_20(<4 x i32> %0) {
+; CHECK-LABEL: vcvt_i32_20:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #20
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3EB0000000000000, float 0x3EB0000000000000, float 0x3EB0000000000000, float 0x3EB0000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_i32_21(<4 x i32> %0) {
+; CHECK-LABEL: vcvt_i32_21:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #21
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3EA0000000000000, float 0x3EA0000000000000, float 0x3EA0000000000000, float 0x3EA0000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_i32_22(<4 x i32> %0) {
+; CHECK-LABEL: vcvt_i32_22:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #22
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3E90000000000000, float 0x3E90000000000000, float 0x3E90000000000000, float 0x3E90000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_i32_23(<4 x i32> %0) {
+; CHECK-LABEL: vcvt_i32_23:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #23
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3E80000000000000, float 0x3E80000000000000, float 0x3E80000000000000, float 0x3E80000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_i32_24(<4 x i32> %0) {
+; CHECK-LABEL: vcvt_i32_24:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #24
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3E70000000000000, float 0x3E70000000000000, float 0x3E70000000000000, float 0x3E70000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_i32_25(<4 x i32> %0) {
+; CHECK-LABEL: vcvt_i32_25:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #25
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3E60000000000000, float 0x3E60000000000000, float 0x3E60000000000000, float 0x3E60000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_i32_26(<4 x i32> %0) {
+; CHECK-LABEL: vcvt_i32_26:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #26
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3E50000000000000, float 0x3E50000000000000, float 0x3E50000000000000, float 0x3E50000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_i32_27(<4 x i32> %0) {
+; CHECK-LABEL: vcvt_i32_27:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #27
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3E40000000000000, float 0x3E40000000000000, float 0x3E40000000000000, float 0x3E40000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_i32_28(<4 x i32> %0) {
+; CHECK-LABEL: vcvt_i32_28:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #28
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3E30000000000000, float 0x3E30000000000000, float 0x3E30000000000000, float 0x3E30000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_i32_29(<4 x i32> %0) {
+; CHECK-LABEL: vcvt_i32_29:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #29
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3E20000000000000, float 0x3E20000000000000, float 0x3E20000000000000, float 0x3E20000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_i32_30(<4 x i32> %0) {
+; CHECK-LABEL: vcvt_i32_30:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #30
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3E10000000000000, float 0x3E10000000000000, float 0x3E10000000000000, float 0x3E10000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_i32_31(<4 x i32> %0) {
+; CHECK-LABEL: vcvt_i32_31:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.s32 q0, q0, #31
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0xBE00000000000000, float 0xBE00000000000000, float 0xBE00000000000000, float 0xBE00000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcvt_i16_1(<8 x i16> %0) #0 {
+; CHECK-LABEL: vcvt_i16_1:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f16.s16 q0, q0, #1
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <8 x i16> %0 to <8 x half>
+  %3 = fmul ninf <8 x half> %2, <half 0xH3800, half 0xH3800, half 0xH3800, half 0xH3800, half 0xH3800, half 0xH3800, half 0xH3800, half 0xH3800>
+  ret <8 x half> %3
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcvt_i16_2(<8 x i16> %0) #0 {
+; CHECK-LABEL: vcvt_i16_2:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f16.s16 q0, q0, #2
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <8 x i16> %0 to <8 x half>
+  %3 = fmul ninf <8 x half> %2, <half 0xH3400, half 0xH3400, half 0xH3400, half 0xH3400, half 0xH3400, half 0xH3400, half 0xH3400, half 0xH3400>
+  ret <8 x half> %3
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcvt_i16_3(<8 x i16> %0) #0 {
+; CHECK-LABEL: vcvt_i16_3:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f16.s16 q0, q0, #3
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <8 x i16> %0 to <8 x half>
+  %3 = fmul ninf <8 x half> %2, <half 0xH3000, half 0xH3000, half 0xH3000, half 0xH3000, half 0xH3000, half 0xH3000, half 0xH3000, half 0xH3000>
+  ret <8 x half> %3
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcvt_i16_4(<8 x i16> %0) #0 {
+; CHECK-LABEL: vcvt_i16_4:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f16.s16 q0, q0, #4
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <8 x i16> %0 to <8 x half>
+  %3 = fmul ninf <8 x half> %2, <half 0xH2C00, half 0xH2C00, half 0xH2C00, half 0xH2C00, half 0xH2C00, half 0xH2C00, half 0xH2C00, half 0xH2C00>
+  ret <8 x half> %3
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcvt_i16_5(<8 x i16> %0) #0 {
+; CHECK-LABEL: vcvt_i16_5:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f16.s16 q0, q0, #5
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <8 x i16> %0 to <8 x half>
+  %3 = fmul ninf <8 x half> %2, <half 0xH2800, half 0xH2800, half 0xH2800, half 0xH2800, half 0xH2800, half 0xH2800, half 0xH2800, half 0xH2800>
+  ret <8 x half> %3
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcvt_i16_6(<8 x i16> %0) #0 {
+; CHECK-LABEL: vcvt_i16_6:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f16.s16 q0, q0, #6
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <8 x i16> %0 to <8 x half>
+  %3 = fmul ninf <8 x half> %2, <half 0xH2400, half 0xH2400, half 0xH2400, half 0xH2400, half 0xH2400, half 0xH2400, half 0xH2400, half 0xH2400>
+  ret <8 x half> %3
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcvt_i16_7(<8 x i16> %0) #0 {
+; CHECK-LABEL: vcvt_i16_7:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f16.s16 q0, q0, #7
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <8 x i16> %0 to <8 x half>
+  %3 = fmul ninf <8 x half> %2, <half 0xH2000, half 0xH2000, half 0xH2000, half 0xH2000, half 0xH2000, half 0xH2000, half 0xH2000, half 0xH2000>
+  ret <8 x half> %3
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcvt_i16_8(<8 x i16> %0) #0 {
+; CHECK-LABEL: vcvt_i16_8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f16.s16 q0, q0, #8
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <8 x i16> %0 to <8 x half>
+  %3 = fmul ninf <8 x half> %2, <half 0xH1C00, half 0xH1C00, half 0xH1C00, half 0xH1C00, half 0xH1C00, half 0xH1C00, half 0xH1C00, half 0xH1C00>
+  ret <8 x half> %3
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcvt_i16_9(<8 x i16> %0) #0 {
+; CHECK-LABEL: vcvt_i16_9:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f16.s16 q0, q0, #9
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <8 x i16> %0 to <8 x half>
+  %3 = fmul ninf <8 x half> %2, <half 0xH1800, half 0xH1800, half 0xH1800, half 0xH1800, half 0xH1800, half 0xH1800, half 0xH1800, half 0xH1800>
+  ret <8 x half> %3
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcvt_i16_10(<8 x i16> %0) #0 {
+; CHECK-LABEL: vcvt_i16_10:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f16.s16 q0, q0, #10
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <8 x i16> %0 to <8 x half>
+  %3 = fmul ninf <8 x half> %2, <half 0xH1400, half 0xH1400, half 0xH1400, half 0xH1400, half 0xH1400, half 0xH1400, half 0xH1400, half 0xH1400>
+  ret <8 x half> %3
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcvt_i16_11(<8 x i16> %0) #0 {
+; CHECK-LABEL: vcvt_i16_11:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f16.s16 q0, q0, #11
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <8 x i16> %0 to <8 x half>
+  %3 = fmul ninf <8 x half> %2, <half 0xH1000, half 0xH1000, half 0xH1000, half 0xH1000, half 0xH1000, half 0xH1000, half 0xH1000, half 0xH1000>
+  ret <8 x half> %3
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcvt_i16_12(<8 x i16> %0) #0 {
+; CHECK-LABEL: vcvt_i16_12:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f16.s16 q0, q0, #12
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <8 x i16> %0 to <8 x half>
+  %3 = fmul ninf <8 x half> %2, <half 0xH0C00, half 0xH0C00, half 0xH0C00, half 0xH0C00, half 0xH0C00, half 0xH0C00, half 0xH0C00, half 0xH0C00>
+  ret <8 x half> %3
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcvt_i16_13(<8 x i16> %0) #0 {
+; CHECK-LABEL: vcvt_i16_13:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f16.s16 q0, q0, #13
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <8 x i16> %0 to <8 x half>
+  %3 = fmul ninf <8 x half> %2, <half 0xH0800, half 0xH0800, half 0xH0800, half 0xH0800, half 0xH0800, half 0xH0800, half 0xH0800, half 0xH0800>
+  ret <8 x half> %3
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcvt_i16_14(<8 x i16> %0) #0 {
+; CHECK-LABEL: vcvt_i16_14:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f16.s16 q0, q0, #14
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <8 x i16> %0 to <8 x half>
+  %3 = fmul ninf <8 x half> %2, <half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400>
+  ret <8 x half> %3
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcvt_i16_15(<8 x i16> %0) #0 {
+; CHECK-LABEL: vcvt_i16_15:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmov.i16 q1, #0x200
+; CHECK-NEXT:    vcvt.f16.s16 q0, q0
+; CHECK-NEXT:    vmul.f16 q0, q0, q1
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <8 x i16> %0 to <8 x half>
+  %3 = fmul ninf <8 x half> %2, <half 0xH0200, half 0xH0200, half 0xH0200, half 0xH0200, half 0xH0200, half 0xH0200, half 0xH0200, half 0xH0200>
+  ret <8 x half> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_u32_1(<4 x i32> %0) #0 {
+; CHECK-LABEL: vcvt_u32_1:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #1
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_u32_2(<4 x i32> %0) #0 {
+; CHECK-LABEL: vcvt_u32_2:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #2
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 2.500000e-01, float 2.500000e-01, float 2.500000e-01, float 2.500000e-01>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_u32_3(<4 x i32> %0) #0 {
+; CHECK-LABEL: vcvt_u32_3:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #3
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 1.250000e-01, float 1.250000e-01, float 1.250000e-01, float 1.250000e-01>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_u32_4(<4 x i32> %0) #0 {
+; CHECK-LABEL: vcvt_u32_4:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #4
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 6.250000e-02, float 6.250000e-02, float 6.250000e-02, float 6.250000e-02>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_u32_5(<4 x i32> %0) #0 {
+; CHECK-LABEL: vcvt_u32_5:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #5
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 3.125000e-02, float 3.125000e-02, float 3.125000e-02, float 3.125000e-02>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_u32_6(<4 x i32> %0) #0 {
+; CHECK-LABEL: vcvt_u32_6:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #6
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 1.562500e-02, float 1.562500e-02, float 1.562500e-02, float 1.562500e-02>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_u32_7(<4 x i32> %0) #0 {
+; CHECK-LABEL: vcvt_u32_7:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #7
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 7.812500e-03, float 7.812500e-03, float 7.812500e-03, float 7.812500e-03>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_u32_8(<4 x i32> %0) #0 {
+; CHECK-LABEL: vcvt_u32_8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #8
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 3.906250e-03, float 3.906250e-03, float 3.906250e-03, float 3.906250e-03>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_u32_9(<4 x i32> %0) #0 {
+; CHECK-LABEL: vcvt_u32_9:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #9
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3F60000000000000, float 0x3F60000000000000, float 0x3F60000000000000, float 0x3F60000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_u32_10(<4 x i32> %0) #0 {
+; CHECK-LABEL: vcvt_u32_10:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #10
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3F50000000000000, float 0x3F50000000000000, float 0x3F50000000000000, float 0x3F50000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_u32_11(<4 x i32> %0) #0 {
+; CHECK-LABEL: vcvt_u32_11:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #11
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3F40000000000000, float 0x3F40000000000000, float 0x3F40000000000000, float 0x3F40000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_u32_12(<4 x i32> %0) #0 {
+; CHECK-LABEL: vcvt_u32_12:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #12
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3F30000000000000, float 0x3F30000000000000, float 0x3F30000000000000, float 0x3F30000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_u32_13(<4 x i32> %0) #0 {
+; CHECK-LABEL: vcvt_u32_13:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #13
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3F20000000000000, float 0x3F20000000000000, float 0x3F20000000000000, float 0x3F20000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_u32_14(<4 x i32> %0) #0 {
+; CHECK-LABEL: vcvt_u32_14:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #14
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_u32_15(<4 x i32> %0) #0 {
+; CHECK-LABEL: vcvt_u32_15:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #15
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3F00000000000000, float 0x3F00000000000000, float 0x3F00000000000000, float 0x3F00000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_u32_16(<4 x i32> %0) #0 {
+; CHECK-LABEL: vcvt_u32_16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #16
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3EF0000000000000, float 0x3EF0000000000000, float 0x3EF0000000000000, float 0x3EF0000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_u32_17(<4 x i32> %0) #0 {
+; CHECK-LABEL: vcvt_u32_17:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #17
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3EE0000000000000, float 0x3EE0000000000000, float 0x3EE0000000000000, float 0x3EE0000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_u32_18(<4 x i32> %0) #0 {
+; CHECK-LABEL: vcvt_u32_18:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #18
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3ED0000000000000, float 0x3ED0000000000000, float 0x3ED0000000000000, float 0x3ED0000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_u32_19(<4 x i32> %0) #0 {
+; CHECK-LABEL: vcvt_u32_19:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #19
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3EC0000000000000, float 0x3EC0000000000000, float 0x3EC0000000000000, float 0x3EC0000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_u32_20(<4 x i32> %0) #0 {
+; CHECK-LABEL: vcvt_u32_20:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #20
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3EB0000000000000, float 0x3EB0000000000000, float 0x3EB0000000000000, float 0x3EB0000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_u32_21(<4 x i32> %0) #0 {
+; CHECK-LABEL: vcvt_u32_21:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #21
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3EA0000000000000, float 0x3EA0000000000000, float 0x3EA0000000000000, float 0x3EA0000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_u32_22(<4 x i32> %0) #0 {
+; CHECK-LABEL: vcvt_u32_22:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #22
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3E90000000000000, float 0x3E90000000000000, float 0x3E90000000000000, float 0x3E90000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_u32_23(<4 x i32> %0) #0 {
+; CHECK-LABEL: vcvt_u32_23:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #23
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3E80000000000000, float 0x3E80000000000000, float 0x3E80000000000000, float 0x3E80000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_u32_24(<4 x i32> %0) #0 {
+; CHECK-LABEL: vcvt_u32_24:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #24
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3E70000000000000, float 0x3E70000000000000, float 0x3E70000000000000, float 0x3E70000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_u32_25(<4 x i32> %0) #0 {
+; CHECK-LABEL: vcvt_u32_25:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #25
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3E60000000000000, float 0x3E60000000000000, float 0x3E60000000000000, float 0x3E60000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_u32_26(<4 x i32> %0) #0 {
+; CHECK-LABEL: vcvt_u32_26:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #26
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3E50000000000000, float 0x3E50000000000000, float 0x3E50000000000000, float 0x3E50000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_u32_27(<4 x i32> %0) #0 {
+; CHECK-LABEL: vcvt_u32_27:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #27
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3E40000000000000, float 0x3E40000000000000, float 0x3E40000000000000, float 0x3E40000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_u32_28(<4 x i32> %0) #0 {
+; CHECK-LABEL: vcvt_u32_28:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #28
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3E30000000000000, float 0x3E30000000000000, float 0x3E30000000000000, float 0x3E30000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_u32_29(<4 x i32> %0) #0 {
+; CHECK-LABEL: vcvt_u32_29:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #29
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3E20000000000000, float 0x3E20000000000000, float 0x3E20000000000000, float 0x3E20000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_u32_30(<4 x i32> %0) #0 {
+; CHECK-LABEL: vcvt_u32_30:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #30
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3E10000000000000, float 0x3E10000000000000, float 0x3E10000000000000, float 0x3E10000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_u32_31(<4 x i32> %0) #0 {
+; CHECK-LABEL: vcvt_u32_31:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f32.u32 q0, q0, #31
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0xBE00000000000000, float 0xBE00000000000000, float 0xBE00000000000000, float 0xBE00000000000000>
+  ret <4 x float> %3
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcvt_u16_1(<8 x i16> %0) #0 {
+; CHECK-LABEL: vcvt_u16_1:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f16.u16 q0, q0, #1
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <8 x i16> %0 to <8 x half>
+  %3 = fmul ninf <8 x half> %2, <half 0xH3800, half 0xH3800, half 0xH3800, half 0xH3800, half 0xH3800, half 0xH3800, half 0xH3800, half 0xH3800>
+  ret <8 x half> %3
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcvt_u16_2(<8 x i16> %0) #0 {
+; CHECK-LABEL: vcvt_u16_2:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f16.u16 q0, q0, #2
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <8 x i16> %0 to <8 x half>
+  %3 = fmul ninf <8 x half> %2, <half 0xH3400, half 0xH3400, half 0xH3400, half 0xH3400, half 0xH3400, half 0xH3400, half 0xH3400, half 0xH3400>
+  ret <8 x half> %3
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcvt_u16_3(<8 x i16> %0) #0 {
+; CHECK-LABEL: vcvt_u16_3:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f16.u16 q0, q0, #3
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <8 x i16> %0 to <8 x half>
+  %3 = fmul ninf <8 x half> %2, <half 0xH3000, half 0xH3000, half 0xH3000, half 0xH3000, half 0xH3000, half 0xH3000, half 0xH3000, half 0xH3000>
+  ret <8 x half> %3
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcvt_u16_4(<8 x i16> %0) #0 {
+; CHECK-LABEL: vcvt_u16_4:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f16.u16 q0, q0, #4
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <8 x i16> %0 to <8 x half>
+  %3 = fmul ninf <8 x half> %2, <half 0xH2C00, half 0xH2C00, half 0xH2C00, half 0xH2C00, half 0xH2C00, half 0xH2C00, half 0xH2C00, half 0xH2C00>
+  ret <8 x half> %3
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcvt_u16_5(<8 x i16> %0) #0 {
+; CHECK-LABEL: vcvt_u16_5:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f16.u16 q0, q0, #5
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <8 x i16> %0 to <8 x half>
+  %3 = fmul ninf <8 x half> %2, <half 0xH2800, half 0xH2800, half 0xH2800, half 0xH2800, half 0xH2800, half 0xH2800, half 0xH2800, half 0xH2800>
+  ret <8 x half> %3
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcvt_u16_6(<8 x i16> %0) #0 {
+; CHECK-LABEL: vcvt_u16_6:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f16.u16 q0, q0, #6
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <8 x i16> %0 to <8 x half>
+  %3 = fmul ninf <8 x half> %2, <half 0xH2400, half 0xH2400, half 0xH2400, half 0xH2400, half 0xH2400, half 0xH2400, half 0xH2400, half 0xH2400>
+  ret <8 x half> %3
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcvt_u16_7(<8 x i16> %0) #0 {
+; CHECK-LABEL: vcvt_u16_7:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f16.u16 q0, q0, #7
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <8 x i16> %0 to <8 x half>
+  %3 = fmul ninf <8 x half> %2, <half 0xH2000, half 0xH2000, half 0xH2000, half 0xH2000, half 0xH2000, half 0xH2000, half 0xH2000, half 0xH2000>
+  ret <8 x half> %3
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcvt_u16_8(<8 x i16> %0) #0 {
+; CHECK-LABEL: vcvt_u16_8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f16.u16 q0, q0, #8
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <8 x i16> %0 to <8 x half>
+  %3 = fmul ninf <8 x half> %2, <half 0xH1C00, half 0xH1C00, half 0xH1C00, half 0xH1C00, half 0xH1C00, half 0xH1C00, half 0xH1C00, half 0xH1C00>
+  ret <8 x half> %3
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcvt_u16_9(<8 x i16> %0) #0 {
+; CHECK-LABEL: vcvt_u16_9:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f16.u16 q0, q0, #9
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <8 x i16> %0 to <8 x half>
+  %3 = fmul ninf <8 x half> %2, <half 0xH1800, half 0xH1800, half 0xH1800, half 0xH1800, half 0xH1800, half 0xH1800, half 0xH1800, half 0xH1800>
+  ret <8 x half> %3
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcvt_u16_10(<8 x i16> %0) #0 {
+; CHECK-LABEL: vcvt_u16_10:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f16.u16 q0, q0, #10
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <8 x i16> %0 to <8 x half>
+  %3 = fmul ninf <8 x half> %2, <half 0xH1400, half 0xH1400, half 0xH1400, half 0xH1400, half 0xH1400, half 0xH1400, half 0xH1400, half 0xH1400>
+  ret <8 x half> %3
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcvt_u16_11(<8 x i16> %0) #0 {
+; CHECK-LABEL: vcvt_u16_11:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f16.u16 q0, q0, #11
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <8 x i16> %0 to <8 x half>
+  %3 = fmul ninf <8 x half> %2, <half 0xH1000, half 0xH1000, half 0xH1000, half 0xH1000, half 0xH1000, half 0xH1000, half 0xH1000, half 0xH1000>
+  ret <8 x half> %3
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcvt_u16_12(<8 x i16> %0) #0 {
+; CHECK-LABEL: vcvt_u16_12:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f16.u16 q0, q0, #12
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <8 x i16> %0 to <8 x half>
+  %3 = fmul ninf <8 x half> %2, <half 0xH0C00, half 0xH0C00, half 0xH0C00, half 0xH0C00, half 0xH0C00, half 0xH0C00, half 0xH0C00, half 0xH0C00>
+  ret <8 x half> %3
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcvt_u16_13(<8 x i16> %0) #0 {
+; CHECK-LABEL: vcvt_u16_13:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f16.u16 q0, q0, #13
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <8 x i16> %0 to <8 x half>
+  %3 = fmul ninf <8 x half> %2, <half 0xH0800, half 0xH0800, half 0xH0800, half 0xH0800, half 0xH0800, half 0xH0800, half 0xH0800, half 0xH0800>
+  ret <8 x half> %3
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcvt_u16_14(<8 x i16> %0) #0 {
+; CHECK-LABEL: vcvt_u16_14:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f16.u16 q0, q0, #14
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <8 x i16> %0 to <8 x half>
+  %3 = fmul ninf <8 x half> %2, <half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400>
+  ret <8 x half> %3
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcvt_u16_15(<8 x i16> %0) #0 {
+; CHECK-LABEL: vcvt_u16_15:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmov.i16 q1, #0x200
+; CHECK-NEXT:    vcvt.f16.u16 q0, q0
+; CHECK-NEXT:    vmul.f16 q0, q0, q1
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <8 x i16> %0 to <8 x half>
+  %3 = fmul ninf <8 x half> %2, <half 0xH0200, half 0xH0200, half 0xH0200, half 0xH0200, half 0xH0200, half 0xH0200, half 0xH0200, half 0xH0200>
+  ret <8 x half> %3
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcvt_u16_inf(<8 x i16> %0) #0 {
+; CHECK-LABEL: vcvt_u16_inf:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmov.i16 q1, #0x400
+; CHECK-NEXT:    vcvt.f16.u16 q0, q0
+; CHECK-NEXT:    vmul.f16 q0, q0, q1
+; CHECK-NEXT:    bx lr
+  %2 = uitofp <8 x i16> %0 to <8 x half>
+  %3 = fmul <8 x half> %2, <half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400>
+  ret <8 x half> %3
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcvt_s16_inf(<8 x i16> %0) #0 {
+; CHECK-LABEL: vcvt_s16_inf:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vcvt.f16.s16 q0, q0, #14
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <8 x i16> %0 to <8 x half>
+  %3 = fmul <8 x half> %2, <half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400, half 0xH0400>
+  ret <8 x half> %3
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcvt_bad_imm(<4 x i32> %0) {
+; CHECK-LABEL: vcvt_bad_imm:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    adr r0, .LCPI94_0
+; CHECK-NEXT:    vcvt.f32.s32 q0, q0
+; CHECK-NEXT:    vldrw.u32 q1, [r0]
+; CHECK-NEXT:    vmul.f32 q0, q0, q1
+; CHECK-NEXT:    bx lr
+  %2 = sitofp <4 x i32> %0 to <4 x float>
+  %3 = fmul <4 x float> %2, <float 0x3F60010000000000, float 0x3F60010000000000, float 0x3F60010000000000, float 0x3F60010000000000>
+  ret <4 x float> %3
+}