[RISCV] Optimize bitwise and with constant for the Zbs extension

[benshi001]

Summary

This patch optimizes (and r i) to
(BCLRI (BCLRI r, i0), i1) in which i = ~((1<<i0) | (1<<i1)).
or
(BCLRI (ANDI r, i0), i1) in which i = i0 & ~(1<<i1).

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

140

What if the type is i32 and bit 31 is one of the clear bits. This sign extend won't handle that case.

[benshi001]

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

140

I have handled the special case you concerned, and two tests are added along, which show improvements of the special case.

It is not needed to pre-commit the tests, since the difference among the pattern

RV32I, RV32IB and RV32IBS shows this improvement.

[luismarques]

Are you planning on extending this to use bclriw on RV64? (Would that clash with the use of tablegen? Personally, I tend to find C++ custom lowering of longer stuff easier to read and more cohesive, not sure how others feel)

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

140

Drop the explicit cast to uint64_t?

141–143

I found this a bit confusing when I first read it. I suppose an alternative would be to replace the three lines with something like return countPopulation(I) == XLen - 2?

[benshi001]

In D103743#2802540, @luismarques wrote:

Are you planning on extending this to use bclriw on RV64? (Would that clash with the use of tablegen? Personally, I tend to find C++ custom lowering of longer stuff easier to read and more cohesive, not sure how others feel)

I have not consider BSETIW/BINVIW/BCLRIW, maybe I will do it in next patch. And this patch will just focuses on BCLRI.

I do not like C++ custom lowering for that, since it needs even more lines than current form.

[craig.topper]

In D103743#2802747, @benshi001 wrote:

In D103743#2802540, @luismarques wrote:

Are you planning on extending this to use bclriw on RV64? (Would that clash with the use of tablegen? Personally, I tend to find C++ custom lowering of longer stuff easier to read and more cohesive, not sure how others feel)

I have not consider BSETIW/BINVIW/BCLRIW, maybe I will do it in next patch. And this patch will just focuses on BCLRI.

I do not like C++ custom lowering for that, since it needs even more lines than current form.

Weren’t the W Zbs instructions removed from the 0.94 spec?

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

def BSETINVORIMask : PatLeaf<(imm), [{
   return isPowerOf2_64(N->getZExtValue() & ~0x7ff);
 }]>;
 
 def BSETINVORIMaskLow : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(N->getZExtValue() & 0x7ff,
                                    SDLoc(N), N->getValueType(0));
 }]>;
 
+// Check if (and r, i) can be optimized to (BCLRI (BCLRI r, i0), i1),
+// in which i = ~((1<<i0) | (1<<i1)).
+def BCLRITwoBitsMask : PatLeaf<(imm), [{
+  if (!N->hasOneUse())
+    return false;
+  // The immediate should not be a simm12.
+  if (isInt<12>(N->getSExtValue()))
+    return false;
+  // The immediate must have exactly two bits clear.
+  return countPopulation(N->getZExtValue()) == Subtarget->getXLen() - 2;
+}]>;
+
+def BCLRITwoBitsMaskLow : SDNodeXForm<imm, [{
+  return CurDAG->getTargetConstant(countTrailingZeros(~N->getZExtValue()),
+                                   SDLoc(N), N->getValueType(0));
+}]>;
+
+def BCLRITwoBitsMaskHigh : SDNodeXForm<imm, [{
+  uint64_t I = N->getSExtValue();
+  if (!Subtarget->is64Bit())
+    I |= 0xffffffffull << 32;
+  return CurDAG->getTargetConstant(63 - countLeadingZeros(~I), SDLoc(N),
+                                   N->getValueType(0));
+}]>;
+
+// Check if (and r, i) can be optimized to (BCLRI (ANDI r, i0), i1),
+// in which i = i0 & ~(1<<i1).
+def BCLRIANDIMask : PatLeaf<(imm), [{
+  if (!N->hasOneUse())
+    return false;
+  // The immediate should not be a simm12.
+  if (isInt<12>(N->getSExtValue()))
+    return false;
+  // There should be only one clear bit from bit 11 to the top.
+  uint64_t I = N->getZExtValue() | 0x7ff;
+  return Subtarget->is64Bit() ? isPowerOf2_64(~I) : isPowerOf2_32(~I);
+}]>;
+
+def BCLRIANDIMaskLow : SDNodeXForm<imm, [{
+  return CurDAG->getTargetConstant((N->getZExtValue() & 0x7ff) | ~0x7ffull,
+                                   SDLoc(N), N->getValueType(0));
+}]>;
+
 //===----------------------------------------------------------------------===//
 // Instruction class templates
 //===----------------------------------------------------------------------===//
 
 // Some of these templates should be moved to RISCVInstrFormats.td once the B
 // extension has been ratified.
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
def : Pat<(xor GPR:$r, BSETINVTwoBitsMask:$i),
           (BINVI (BINVI GPR:$r, (BSETINVTwoBitsMaskLow BSETINVTwoBitsMask:$i)),
                  (BSETINVTwoBitsMaskHigh BSETINVTwoBitsMask:$i))>;
 def : Pat<(or GPR:$r, BSETINVORIMask:$i),
           (BSETI (ORI GPR:$r, (BSETINVORIMaskLow BSETINVORIMask:$i)),
                  (BSETINVTwoBitsMaskHigh BSETINVORIMask:$i))>;
 def : Pat<(xor GPR:$r, BSETINVORIMask:$i),
           (BINVI (XORI GPR:$r, (BSETINVORIMaskLow BSETINVORIMask:$i)),
                  (BSETINVTwoBitsMaskHigh BSETINVORIMask:$i))>;
+def : Pat<(and GPR:$r, BCLRITwoBitsMask:$i),
+          (BCLRI (BCLRI GPR:$r, (BCLRITwoBitsMaskLow BCLRITwoBitsMask:$i)),
+                 (BCLRITwoBitsMaskHigh BCLRITwoBitsMask:$i))>;
+def : Pat<(and GPR:$r, BCLRIANDIMask:$i),
+          (BCLRI (ANDI GPR:$r, (BCLRIANDIMaskLow BCLRIANDIMask:$i)),
+                 (BCLRITwoBitsMaskHigh BCLRIANDIMask:$i))>;
 }
 
 // There's no encoding for roli in the the 'B' extension as it can be
 // implemented with rori by negating the immediate.
 let Predicates = [HasStdExtZbbOrZbp] in {
 def : PatGprImm<rotr, RORI, uimmlog2xlen>;
 def : Pat<(rotl GPR:$rs1, uimmlog2xlen:$shamt),
           (RORI GPR:$rs1, (ImmSubFromXLen uimmlog2xlen:$shamt))>;

llvm/test/CodeGen/RISCV/rv32zbs.ll

 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 1044480
 ; RV32I-NEXT:    addi a1, a1, -256
 ; RV32I-NEXT:    and a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: sbclri_i32_large0:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    lui a1, 1044480
-; RV32IB-NEXT:    addi a1, a1, -256
-; RV32IB-NEXT:    and a0, a0, a1
+; RV32IB-NEXT:    andi a0, a0, -256
+; RV32IB-NEXT:    bclri a0, a0, 24
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBS-LABEL: sbclri_i32_large0:
 ; RV32IBS:       # %bb.0:
-; RV32IBS-NEXT:    lui a1, 1044480
-; RV32IBS-NEXT:    addi a1, a1, -256
-; RV32IBS-NEXT:    and a0, a0, a1
+; RV32IBS-NEXT:    andi a0, a0, -256
+; RV32IBS-NEXT:    bclri a0, a0, 24
 ; RV32IBS-NEXT:    ret
   %and = and i32 %a, -16777472
   ret i32 %and
 }
 
 define i32 @sbclri_i32_large1(i32 %a) nounwind {
 ; RV32I-LABEL: sbclri_i32_large1:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 1044464
 ; RV32I-NEXT:    addi a1, a1, -1
 ; RV32I-NEXT:    and a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: sbclri_i32_large1:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    lui a1, 1044464
-; RV32IB-NEXT:    addi a1, a1, -1
-; RV32IB-NEXT:    and a0, a0, a1
+; RV32IB-NEXT:    bclri a0, a0, 16
+; RV32IB-NEXT:    bclri a0, a0, 24
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBS-LABEL: sbclri_i32_large1:
 ; RV32IBS:       # %bb.0:
-; RV32IBS-NEXT:    lui a1, 1044464
-; RV32IBS-NEXT:    addi a1, a1, -1
-; RV32IBS-NEXT:    and a0, a0, a1
+; RV32IBS-NEXT:    bclri a0, a0, 16
+; RV32IBS-NEXT:    bclri a0, a0, 24
 ; RV32IBS-NEXT:    ret
   %and = and i32 %a, -16842753
   ret i32 %and
 }
 
+define i32 @sbclri_i32_large2(i32 %0) {
+; RV32I-LABEL: sbclri_i32_large2:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a1, 524288
+; RV32I-NEXT:    addi a1, a1, -5
+; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32IB-LABEL: sbclri_i32_large2:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    bclri a0, a0, 2
+; RV32IB-NEXT:    bclri a0, a0, 31
+; RV32IB-NEXT:    ret
+;
+; RV32IBS-LABEL: sbclri_i32_large2:
+; RV32IBS:       # %bb.0:
+; RV32IBS-NEXT:    bclri a0, a0, 2
+; RV32IBS-NEXT:    bclri a0, a0, 31
+; RV32IBS-NEXT:    ret
+  %2 = and i32 %0, 2147483643
+  ret i32 %2
+}
+
+define i32 @sbclri_i32_large3(i32 %0) {
+; RV32I-LABEL: sbclri_i32_large3:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a1, 524288
+; RV32I-NEXT:    addi a1, a1, -6
+; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32IB-LABEL: sbclri_i32_large3:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    andi a0, a0, -6
+; RV32IB-NEXT:    bclri a0, a0, 31
+; RV32IB-NEXT:    ret
+;
+; RV32IBS-LABEL: sbclri_i32_large3:
+; RV32IBS:       # %bb.0:
+; RV32IBS-NEXT:    andi a0, a0, -6
+; RV32IBS-NEXT:    bclri a0, a0, 31
+; RV32IBS-NEXT:    ret
+  %2 = and i32 %0, 2147483642
+  ret i32 %2
+}
+
 define i32 @sbseti_i32_10(i32 %a) nounwind {
 ; RV32I-LABEL: sbseti_i32_10:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    ori a0, a0, 1024
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: sbseti_i32_10:
 ; RV32IB:       # %bb.0:

llvm/test/CodeGen/RISCV/rv64zbs.ll

 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 1044480
 ; RV64I-NEXT:    addiw a1, a1, -256
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbclri_i64_large0:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    lui a1, 1044480
-; RV64IB-NEXT:    addiw a1, a1, -256
-; RV64IB-NEXT:    and a0, a0, a1
+; RV64IB-NEXT:    andi a0, a0, -256
+; RV64IB-NEXT:    bclri a0, a0, 24
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbclri_i64_large0:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    lui a1, 1044480
-; RV64IBS-NEXT:    addiw a1, a1, -256
-; RV64IBS-NEXT:    and a0, a0, a1
+; RV64IBS-NEXT:    andi a0, a0, -256
+; RV64IBS-NEXT:    bclri a0, a0, 24
 ; RV64IBS-NEXT:    ret
   %and = and i64 %a, -16777472
   ret i64 %and
 }
 
 define i64 @sbclri_i64_large1(i64 %a) nounwind {
 ; RV64I-LABEL: sbclri_i64_large1:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 1044464
 ; RV64I-NEXT:    addiw a1, a1, -1
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbclri_i64_large1:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    lui a1, 1044464
-; RV64IB-NEXT:    addiw a1, a1, -1
-; RV64IB-NEXT:    and a0, a0, a1
+; RV64IB-NEXT:    bclri a0, a0, 16
+; RV64IB-NEXT:    bclri a0, a0, 24
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbclri_i64_large1:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    lui a1, 1044464
-; RV64IBS-NEXT:    addiw a1, a1, -1
-; RV64IBS-NEXT:    and a0, a0, a1
+; RV64IBS-NEXT:    bclri a0, a0, 16
+; RV64IBS-NEXT:    bclri a0, a0, 24
 ; RV64IBS-NEXT:    ret
   %and = and i64 %a, -16842753
   ret i64 %and
 }
 
 define signext i32 @sbseti_i32_10(i32 signext %a) nounwind {
 ; RV64I-LABEL: sbseti_i32_10:
 ; RV64I:       # %bb.0: