[AArch64][GlobalISel] Implement moreElements legalization for G_SHUFFLE_VECTOR.

[aemerson]

Summary

Currently we can't fully legalize the AArch64 test for this, that support will be coming in the form of an additional artifact combiner in a later patch.

[paquette]

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

4848

static cast?

llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector-wip.mir

2

-verify-machineinstrs?

11

might as well drop the liveins and other similar cruft?

llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp

4053

is this an unfinished comment?

[paquette]

all my comments were pretty minor so LGTM

llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h

public:
   LegalizeResult
   fewerElementsVectorSelect(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);
 
   LegalizeResult fewerElementsVectorPhi(MachineInstr &MI,
                                         unsigned TypeIdx, LLT NarrowTy);
 
   LegalizeResult moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
                                        LLT MoreTy);
+  LegalizeResult moreElementsVectorShuffle(MachineInstr &MI, unsigned TypeIdx,
+                                           LLT MoreTy);
 
   LegalizeResult fewerElementsVectorUnmergeValues(MachineInstr &MI,
                                                   unsigned TypeIdx,
                                                   LLT NarrowTy);
   LegalizeResult fewerElementsVectorMerge(MachineInstr &MI, unsigned TypeIdx,
                                           LLT NarrowTy);
   LegalizeResult fewerElementsVectorExtractInsertVectorElt(MachineInstr &MI,
                                                            unsigned TypeIdx,

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

for (int I = NumDst; I != NewNumDst; ++I)
       MIB.addDef(MRI.createGenericVirtualRegister(DstTy));
 
     MIB.addUse(MI.getOperand(NumDst).getReg());
     MI.eraseFromParent();
     return Legalized;
   }
   case TargetOpcode::G_PHI:
     return moreElementsVectorPhi(MI, TypeIdx, MoreTy);
+  case TargetOpcode::G_SHUFFLE_VECTOR:
+    return moreElementsVectorShuffle(MI, TypeIdx, MoreTy);
   default:
     return UnableToLegalize;
   }
 }
 
+LegalizerHelper::LegalizeResult
+LegalizerHelper::moreElementsVectorShuffle(MachineInstr &MI,
+                                           unsigned int TypeIdx, LLT MoreTy) {
+  if (TypeIdx != 0)
+    return UnableToLegalize;
+
+  Register DstReg = MI.getOperand(0).getReg();
+  Register Src1Reg = MI.getOperand(1).getReg();
+  Register Src2Reg = MI.getOperand(2).getReg();
+  ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask();
+  LLT DstTy = MRI.getType(DstReg);
+  LLT Src1Ty = MRI.getType(Src1Reg);
+  LLT Src2Ty = MRI.getType(Src2Reg);
+  unsigned NumElts = DstTy.getNumElements();
+  unsigned WidenNumElts = MoreTy.getNumElements();
+
+  // Expect a canonicalized shuffle.
+  if (DstTy != Src1Ty || DstTy != Src2Ty)
+    return UnableToLegalize;
+
+  moreElementsVectorSrc(MI, MoreTy, 1);
+  moreElementsVectorSrc(MI, MoreTy, 2);
+
+  // Adjust mask based on new input vector length.
+  SmallVector<int, 16> NewMask;
+  for (unsigned I = 0; I != NumElts; ++I) {
+    int Idx = Mask[I];
+    if (Idx < (int)NumElts)
+      NewMask.push_back(Idx);
+    else
+      NewMask.push_back(Idx - NumElts + WidenNumElts);
+  }
+  for (unsigned I = NumElts; I != WidenNumElts; ++I)
+    NewMask.push_back(-1);
+  moreElementsVectorDst(MI, MoreTy, 0);
+  MIRBuilder.buildShuffleVector(MI.getOperand(0).getReg(),
+                                MI.getOperand(1).getReg(),
+                                MI.getOperand(2).getReg(), NewMask);
+  MI.eraseFromParent();
+  return Legalized;
+}
+
 void LegalizerHelper::multiplyRegisters(SmallVectorImpl<Register> &DstRegs,
                                         ArrayRef<Register> Src1Regs,
                                         ArrayRef<Register> Src2Regs,
                                         LLT NarrowTy) {
   MachineIRBuilder &B = MIRBuilder;
   unsigned SrcParts = Src1Regs.size();
   unsigned DstParts = DstRegs.size();
 

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

getActionDefinitionsBuilder(G_SHUFFLE_VECTOR)
         }
         return false;
       })
       // G_SHUFFLE_VECTOR can have scalar sources (from 1 x s vectors), we
       // just want those lowered into G_BUILD_VECTOR
       .lowerIf([=](const LegalityQuery &Query) {
         return !Query.Types[1].isVector();
       })
+      .moreElementsToNextPow2(0)
       .clampNumElements(0, v4s32, v4s32)
       .clampNumElements(0, v2s64, v2s64);
 
   getActionDefinitionsBuilder(G_CONCAT_VECTORS)
       .legalFor({{v4s32, v2s32}, {v8s16, v4s16}});
 
   getActionDefinitionsBuilder(G_JUMP_TABLE).legalFor({{p0}, {s64}});
 

llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector-wip.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64 -O0 -run-pass=legalizer -global-isel-abort=2 %s -o - | FileCheck %s
+# This test runs with -global-isel-abort=2 because we currently don't have support
+# to deal with the inserts/extracts. Once we do, we can merge this with the main shufflevector
+# test and run it with aborts enabled.
+---
+name:            oversize_shuffle_v6i64
+alignment:       4
+tracksRegLiveness: true
+liveins:
+  - { reg: '$d0' }
+  - { reg: '$d1' }
+  - { reg: '$d2' }
+  - { reg: '$d3' }
+  - { reg: '$d4' }
+  - { reg: '$d5' }
+  - { reg: '$d6' }
+  - { reg: '$d7' }
+  - { reg: '$x0' }
+frameInfo:
+  maxAlignment:    8
+fixedStack:
+  - { id: 0, offset: 24, size: 8, alignment: 8, isImmutable: true }
+  - { id: 1, offset: 16, size: 8, alignment: 16, isImmutable: true }
+  - { id: 2, offset: 8, size: 8, alignment: 8, isImmutable: true }
+  - { id: 3, size: 8, alignment: 16, isImmutable: true }
+body:             |
+  bb.1:
+    liveins: $d0, $d1, $d2, $d3, $d4, $d5, $d6, $d7, $x0
+
+    ; CHECK-LABEL: name: oversize_shuffle_v6i64
+    ; CHECK: liveins: $d0, $d1, $d2, $d3, $d4, $d5, $d6, $d7, $x0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $d1
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $d2
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $d3
+    ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $d4
+    ; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY $d5
+    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<6 x s64>) = G_BUILD_VECTOR [[COPY]](s64), [[COPY1]](s64), [[COPY2]](s64), [[COPY3]](s64), [[COPY4]](s64), [[COPY5]](s64)
+    ; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY $d6
+    ; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY $d7
+    ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+    ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 8 from %fixed-stack.0, align 16)
+    ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+    ; CHECK: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 8 from %fixed-stack.1)
+    ; CHECK: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
+    ; CHECK: [[LOAD2:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX2]](p0) :: (invariant load 8 from %fixed-stack.2, align 16)
+    ; CHECK: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
+    ; CHECK: [[LOAD3:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX3]](p0) :: (invariant load 8 from %fixed-stack.3)
+    ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<6 x s64>) = G_BUILD_VECTOR [[COPY6]](s64), [[COPY7]](s64), [[LOAD]](s64), [[LOAD1]](s64), [[LOAD2]](s64), [[LOAD3]](s64)
+    ; CHECK: [[COPY8:%[0-9]+]]:_(p0) = COPY $x0
+    ; CHECK: [[DEF:%[0-9]+]]:_(<8 x s64>) = G_IMPLICIT_DEF
+    ; CHECK: [[INSERT:%[0-9]+]]:_(<8 x s64>) = G_INSERT [[DEF]], [[BUILD_VECTOR]](<6 x s64>), 0
+    ; CHECK: [[INSERT1:%[0-9]+]]:_(<8 x s64>) = G_INSERT [[DEF]], [[BUILD_VECTOR1]](<6 x s64>), 0
+    ; CHECK: [[UV:%[0-9]+]]:_(<4 x s64>), [[UV1:%[0-9]+]]:_(<4 x s64>) = G_UNMERGE_VALUES [[INSERT]](<8 x s64>)
+    ; CHECK: [[UV2:%[0-9]+]]:_(<4 x s64>), [[UV3:%[0-9]+]]:_(<4 x s64>) = G_UNMERGE_VALUES [[INSERT1]](<8 x s64>)
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+    ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[C]](s32)
+    ; CHECK: [[UV4:%[0-9]+]]:_(<2 x s64>), [[UV5:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[UV]](<4 x s64>)
+    ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+    ; CHECK: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[UV5]](<2 x s64>), [[C1]](s64)
+    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; CHECK: [[SEXT1:%[0-9]+]]:_(s64) = G_SEXT [[C2]](s32)
+    ; CHECK: [[UV6:%[0-9]+]]:_(<2 x s64>), [[UV7:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[UV1]](<4 x s64>)
+    ; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+    ; CHECK: [[EVEC1:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[UV6]](<2 x s64>), [[C3]](s64)
+    ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: [[SEXT2:%[0-9]+]]:_(s64) = G_SEXT [[C4]](s32)
+    ; CHECK: [[UV8:%[0-9]+]]:_(<2 x s64>), [[UV9:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[UV2]](<4 x s64>)
+    ; CHECK: [[EVEC2:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[UV8]](<2 x s64>), [[C1]](s64)
+    ; CHECK: [[SEXT3:%[0-9]+]]:_(s64) = G_SEXT [[C2]](s32)
+    ; CHECK: [[UV10:%[0-9]+]]:_(<2 x s64>), [[UV11:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[UV]](<4 x s64>)
+    ; CHECK: [[EVEC3:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[UV10]](<2 x s64>), [[C3]](s64)
+    ; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[EVEC]](s64), [[EVEC1]](s64), [[EVEC2]](s64), [[EVEC3]](s64)
+    ; CHECK: [[UV12:%[0-9]+]]:_(<2 x s64>), [[UV13:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[UV]](<4 x s64>)
+    ; CHECK: [[UV14:%[0-9]+]]:_(<2 x s64>), [[UV15:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[UV3]](<4 x s64>)
+    ; CHECK: [[SHUF:%[0-9]+]]:_(<2 x s64>) = G_SHUFFLE_VECTOR [[UV12]](<2 x s64>), [[UV14]], shufflemask(1, 3)
+    ; CHECK: [[DEF1:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
+    ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[SHUF]](<2 x s64>), [[DEF1]](<2 x s64>)
+    ; CHECK: [[CONCAT_VECTORS1:%[0-9]+]]:_(<8 x s64>) = G_CONCAT_VECTORS [[BUILD_VECTOR2]](<4 x s64>), [[CONCAT_VECTORS]](<4 x s64>)
+    ; CHECK: [[CONCAT_VECTORS2:%[0-9]+]]:_(<24 x s64>) = G_CONCAT_VECTORS [[CONCAT_VECTORS1]](<8 x s64>), [[DEF]](<8 x s64>), [[DEF]](<8 x s64>)
+    ; CHECK: [[UV16:%[0-9]+]]:_(<6 x s64>), [[UV17:%[0-9]+]]:_(<6 x s64>), [[UV18:%[0-9]+]]:_(<6 x s64>), [[UV19:%[0-9]+]]:_(<6 x s64>) = G_UNMERGE_VALUES [[CONCAT_VECTORS2]](<24 x s64>)
+    ; CHECK: [[UV20:%[0-9]+]]:_(<2 x s64>), [[UV21:%[0-9]+]]:_(<2 x s64>), [[UV22:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[UV16]](<6 x s64>)
+    ; CHECK: G_STORE [[UV20]](<2 x s64>), [[COPY8]](p0) :: (store 16, align 64)
+    ; CHECK: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+    ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY8]], [[C5]](s64)
+    ; CHECK: G_STORE [[UV21]](<2 x s64>), [[PTR_ADD]](p0) :: (store 16 into unknown-address + 16)
+    ; CHECK: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
+    ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY8]], [[C6]](s64)
+    ; CHECK: G_STORE [[UV22]](<2 x s64>), [[PTR_ADD1]](p0) :: (store 16 into unknown-address + 32, align 32)
+    ; CHECK: RET_ReallyLR
+    %3:_(s64) = COPY $d0
+    %4:_(s64) = COPY $d1
+    %5:_(s64) = COPY $d2
+    %6:_(s64) = COPY $d3
+    %7:_(s64) = COPY $d4
+    %8:_(s64) = COPY $d5
+    %0:_(<6 x s64>) = G_BUILD_VECTOR %3(s64), %4(s64), %5(s64), %6(s64), %7(s64), %8(s64)
+    %9:_(s64) = COPY $d6
+    %10:_(s64) = COPY $d7
+    %15:_(p0) = G_FRAME_INDEX %fixed-stack.3
+    %11:_(s64) = G_LOAD %15(p0) :: (invariant load 8 from %fixed-stack.3, align 16)
+    %16:_(p0) = G_FRAME_INDEX %fixed-stack.2
+    %12:_(s64) = G_LOAD %16(p0) :: (invariant load 8 from %fixed-stack.2)
+    %17:_(p0) = G_FRAME_INDEX %fixed-stack.1
+    %13:_(s64) = G_LOAD %17(p0) :: (invariant load 8 from %fixed-stack.1, align 16)
+    %18:_(p0) = G_FRAME_INDEX %fixed-stack.0
+    %14:_(s64) = G_LOAD %18(p0) :: (invariant load 8 from %fixed-stack.0)
+    %1:_(<6 x s64>) = G_BUILD_VECTOR %9(s64), %10(s64), %11(s64), %12(s64), %13(s64), %14(s64)
+    %2:_(p0) = COPY $x0
+    %19:_(<6 x s64>) = G_SHUFFLE_VECTOR %0(<6 x s64>), %1, shufflemask(3, 4, 7, 0, 1, 11)
+    G_STORE %19(<6 x s64>), %2(p0) :: (store 48, align 64)
+    RET_ReallyLR
+
+...

llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp

TEST_F(AArch64GISelMITest, widenScalarUnmerge) {
   CHECK: [[MERGE:%[0-9]+]]:_(s48) = G_MERGE_VALUES [[UNMERGE3]]:_(s16), [[UNMERGE4]]:_(s16), [[UNMERGE5]]:_(s16)
   CHECK: [[MERGE1:%[0-9]+]]:_(s48) = G_MERGE_VALUES [[UNMERGE6]]:_(s16), [[UNMERGE7]]:_(s16), [[UNMERGE8]]:_(s16)
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
+// Test moreElements of G_SHUFFLE_VECTOR.
+TEST_F(AArch64GISelMITest, moreElementsShuffle) {
+  setUp();
+  if (!TM)
+    return;
+
+  DefineLegalizerInfo(A, {});
+
+  LLT S64{LLT::scalar(64)};
+  LLT V6S64 = LLT::vector(6, S64);
+
+  auto V1 = B.buildBuildVector(V6S64, {Copies[0], Copies[1], Copies[0],
+                                       Copies[1], Copies[0], Copies[1]});
+  auto V2 = B.buildBuildVector(V6S64, {Copies[0], Copies[1], Copies[0],
+                                       Copies[1], Copies[0], Copies[1]});
+  auto Shuffle = B.buildShuffleVector(V6S64, V1, V2, {3, 4, 7, 0, 1, 11});
+
+  AInfo Info(MF->getSubtarget());
+  DummyGISelObserver Observer;
+  LegalizerHelper Helper(*MF, Info, Observer, B);
+
+  // Perform Legalization
+  B.setInsertPt(*EntryMBB, Shuffle->getIterator());
+
+  EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized,
+            Helper.moreElementsVector(*Shuffle, 0, LLT::vector(8, S64)));
+
+  const auto *CheckStr = R"(
+  CHECK: [[COPY0:%[0-9]+]]:_(s64) = COPY
+  CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY
+  CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY
+  CHECK: [[BV1:%[0-9]+]]:_(<6 x s64>) = G_BUILD_VECTOR
+  CHECK: [[BV2:%[0-9]+]]:_(<6 x s64>) = G_BUILD_VECTOR
+  CHECK: [[IMPDEF1:%[0-9]+]]:_(<8 x s64>) = G_IMPLICIT_DEF
+  CHECK: [[INSERT1:%[0-9]+]]:_(<8 x s64>) = G_INSERT [[IMPDEF1]]:_, [[BV1]]:_(<6 x s64>), 0
+  CHECK: [[IMPDEF2:%[0-9]+]]:_(<8 x s64>) = G_IMPLICIT_DEF
+  CHECK: [[INSERT2:%[0-9]+]]:_(<8 x s64>) = G_INSERT [[IMPDEF2]]:_, [[BV2]]:_(<6 x s64>), 0
+  CHECK: [[SHUF:%[0-9]+]]:_(<8 x s64>) = G_SHUFFLE_VECTOR [[INSERT1]]:_(<8 x s64>), [[INSERT2]]:_, shufflemask(3, 4, 9, 0, 1, 13, undef, undef)
+  CHECK: [[IMPDEF3:%[0-9]+]]:_(<8 x s64>) = G_IMPLICIT_DEF
+  CHECK: [[CONCAT:%[0-9]+]]:_(<24 x s64>) = G_CONCAT_VECTORS [[SHUF]]:_(<8 x s64>), [[IMPDEF3]]:_(<8 x s64>), [[IMPDEF3]]:_(<8 x s64>)
+  CHECK: [[UNMERGE:%[0-9]+]]:_(<6 x s64>), [[UNMERGE2:%[0-9]+]]:_(<6 x s64>), [[UNMERGE3:%[0-9]+]]:_(<6 x s64>), [[UNMERGE4:%[0-9]+]]:_(<6 x s64>) = G_UNMERGE_VALUES [[CONCAT]]:_(<24 x s64>)
+  )";
+
+  // Check
+  EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
+}
+
 } // namespace