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Differential D102396

[RISCV][test] Add new tests for or/xor
ClosedPublic

Authored by benshi001 on May 13 2021, 5:44 AM.

Details

Reviewers
craig.topper
asb
luismarques
MaskRay
Commits
rG1dfd7d5041e5: [RISCV][test] Add new tests of or/xor in the zbs extension

Diff Detail

Unit TestsFailed

TimeTest
170 msx64 windows > LLVM.Other::new-pm-lto-defaults.ll

Event Timeline

benshi001 created this revision.May 13 2021, 5:44 AM
Herald added subscribers: vkmr, frasercrmck, evandro and 23 others. · View Herald TranscriptMay 13 2021, 5:45 AM
benshi001 requested review of this revision.May 13 2021, 5:45 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 13 2021, 5:45 AM
Herald added subscribers: llvm-commits, MaskRay. · View Herald Transcript
benshi001 added a comment.May 13 2021, 5:46 AM

The new test will should how

; RV32IBS-NEXT:    lui a1, 1
; RV32IBS-NEXT:    addi a1, a1, 2
; RV32IBS-NEXT:    xor a0, a0, a1

are optimized to

binvi a0, 12
binvi a0, 2
benshi001 added a child revision: D102398: [RISCV] Optimize or/xor with immediate in Zbs extension.May 13 2021, 6:01 AM
Harbormaster completed remote builds in B104255: Diff 345101.May 13 2021, 6:45 AM
benshi001 updated this revision to Diff 345140.May 13 2021, 7:45 AM
Harbormaster completed remote builds in B104285: Diff 345140.May 13 2021, 8:21 AM
benshi001 added a reviewer: luismarques.May 13 2021, 8:11 PM
benshi001 mentioned this in D102398: [RISCV] Optimize or/xor with immediate in Zbs extension.May 16 2021, 5:38 PM
MaskRay accepted this revision.May 16 2021, 6:22 PM
This revision is now accepted and ready to land.May 16 2021, 6:22 PM
This revision was landed with ongoing or failed builds.May 16 2021, 6:47 PM
Closed by commit rG1dfd7d5041e5: [RISCV][test] Add new tests of or/xor in the zbs extension (authored by benshi001). · Explain Why
This revision was automatically updated to reflect the committed changes.
benshi001 added a commit: rG1dfd7d5041e5: [RISCV][test] Add new tests of or/xor in the zbs extension.

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
138 lines
144 lines

Diff 345140

llvm/test/CodeGen/RISCV/rv32zbs.ll

Show First 20 Lines • Show All 703 Lines • ▼ Show 20 Lines
; ;
; RV32IBS-LABEL: sbinvi_i32_31: ; RV32IBS-LABEL: sbinvi_i32_31:
; RV32IBS: # %bb.0: ; RV32IBS: # %bb.0:
; RV32IBS-NEXT: binvi a0, a0, 31 ; RV32IBS-NEXT: binvi a0, a0, 31
; RV32IBS-NEXT: ret ; RV32IBS-NEXT: ret
%xor = xor i32 %a, 2147483648 %xor = xor i32 %a, 2147483648
ret i32 %xor ret i32 %xor
} }
define i32 @xor_i32_4098(i32 %a) nounwind {
; RV32I-LABEL: xor_i32_4098:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 1
; RV32I-NEXT: addi a1, a1, 2
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: ret
;
; RV32IB-LABEL: xor_i32_4098:
; RV32IB: # %bb.0:
; RV32IB-NEXT: lui a1, 1
; RV32IB-NEXT: addi a1, a1, 2
; RV32IB-NEXT: xor a0, a0, a1
; RV32IB-NEXT: ret
;
; RV32IBS-LABEL: xor_i32_4098:
; RV32IBS: # %bb.0:
; RV32IBS-NEXT: lui a1, 1
; RV32IBS-NEXT: addi a1, a1, 2
; RV32IBS-NEXT: xor a0, a0, a1
; RV32IBS-NEXT: ret
%xor = xor i32 %a, 4098
ret i32 %xor
}
define i32 @xor_i32_4099(i32 %a) nounwind {
; RV32I-LABEL: xor_i32_4099:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 1
; RV32I-NEXT: addi a1, a1, 3
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: ret
;
; RV32IB-LABEL: xor_i32_4099:
; RV32IB: # %bb.0:
; RV32IB-NEXT: lui a1, 1
; RV32IB-NEXT: addi a1, a1, 3
; RV32IB-NEXT: xor a0, a0, a1
; RV32IB-NEXT: ret
;
; RV32IBS-LABEL: xor_i32_4099:
; RV32IBS: # %bb.0:
; RV32IBS-NEXT: lui a1, 1
; RV32IBS-NEXT: addi a1, a1, 3
; RV32IBS-NEXT: xor a0, a0, a1
; RV32IBS-NEXT: ret
%xor = xor i32 %a, 4099
ret i32 %xor
}
define i32 @xor_i32_96(i32 %a) nounwind {
; RV32I-LABEL: xor_i32_96:
; RV32I: # %bb.0:
; RV32I-NEXT: xori a0, a0, 96
; RV32I-NEXT: ret
;
; RV32IB-LABEL: xor_i32_96:
; RV32IB: # %bb.0:
; RV32IB-NEXT: xori a0, a0, 96
; RV32IB-NEXT: ret
;
; RV32IBS-LABEL: xor_i32_96:
; RV32IBS: # %bb.0:
; RV32IBS-NEXT: xori a0, a0, 96
; RV32IBS-NEXT: ret
%xor = xor i32 %a, 96
ret i32 %xor
}
define i32 @or_i32_4098(i32 %a) nounwind {
; RV32I-LABEL: or_i32_4098:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 1
; RV32I-NEXT: addi a1, a1, 2
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
; RV32IB-LABEL: or_i32_4098:
; RV32IB: # %bb.0:
; RV32IB-NEXT: lui a1, 1
; RV32IB-NEXT: addi a1, a1, 2
; RV32IB-NEXT: or a0, a0, a1
; RV32IB-NEXT: ret
;
; RV32IBS-LABEL: or_i32_4098:
; RV32IBS: # %bb.0:
; RV32IBS-NEXT: lui a1, 1
; RV32IBS-NEXT: addi a1, a1, 2
; RV32IBS-NEXT: or a0, a0, a1
; RV32IBS-NEXT: ret
%or = or i32 %a, 4098
ret i32 %or
}
define i32 @or_i32_4099(i32 %a) nounwind {
; RV32I-LABEL: or_i32_4099:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 1
; RV32I-NEXT: addi a1, a1, 3
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
; RV32IB-LABEL: or_i32_4099:
; RV32IB: # %bb.0:
; RV32IB-NEXT: lui a1, 1
; RV32IB-NEXT: addi a1, a1, 3
; RV32IB-NEXT: or a0, a0, a1
; RV32IB-NEXT: ret
;
; RV32IBS-LABEL: or_i32_4099:
; RV32IBS: # %bb.0:
; RV32IBS-NEXT: lui a1, 1
; RV32IBS-NEXT: addi a1, a1, 3
; RV32IBS-NEXT: or a0, a0, a1
; RV32IBS-NEXT: ret
%or = or i32 %a, 4099
ret i32 %or
}
define i32 @or_i32_96(i32 %a) nounwind {
; RV32I-LABEL: or_i32_96:
; RV32I: # %bb.0:
; RV32I-NEXT: ori a0, a0, 96
; RV32I-NEXT: ret
;
; RV32IB-LABEL: or_i32_96:
; RV32IB: # %bb.0:
; RV32IB-NEXT: ori a0, a0, 96
; RV32IB-NEXT: ret
;
; RV32IBS-LABEL: or_i32_96:
; RV32IBS: # %bb.0:
; RV32IBS-NEXT: ori a0, a0, 96
; RV32IBS-NEXT: ret
%or = or i32 %a, 96
ret i32 %or
}

llvm/test/CodeGen/RISCV/rv64zbs.ll

Show First 20 Lines • Show All 1,203 Lines • ▼ Show 20 Lines
; ;
; RV64IBS-LABEL: sbinvi_i64_63: ; RV64IBS-LABEL: sbinvi_i64_63:
; RV64IBS: # %bb.0: ; RV64IBS: # %bb.0:
; RV64IBS-NEXT: binvi a0, a0, 63 ; RV64IBS-NEXT: binvi a0, a0, 63
; RV64IBS-NEXT: ret ; RV64IBS-NEXT: ret
%xor = xor i64 %a, 9223372036854775808 %xor = xor i64 %a, 9223372036854775808
ret i64 %xor ret i64 %xor
} }
define i64 @xor_i64_large(i64 %a) nounwind {
; RV64I-LABEL: xor_i64_large:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 1
; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: addi a1, a1, 1
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
; RV64IB-LABEL: xor_i64_large:
; RV64IB: # %bb.0:
; RV64IB-NEXT: addi a1, zero, 1
; RV64IB-NEXT: slli a1, a1, 32
; RV64IB-NEXT: addi a1, a1, 1
; RV64IB-NEXT: xor a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBS-LABEL: xor_i64_large:
; RV64IBS: # %bb.0:
; RV64IBS-NEXT: addi a1, zero, 1
; RV64IBS-NEXT: slli a1, a1, 32
; RV64IBS-NEXT: addi a1, a1, 1
; RV64IBS-NEXT: xor a0, a0, a1
; RV64IBS-NEXT: ret
%xor = xor i64 %a, 4294967297
ret i64 %xor
}
define i64 @xor_i64_4099(i64 %a) nounwind {
; RV64I-LABEL: xor_i64_4099:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, 3
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
; RV64IB-LABEL: xor_i64_4099:
; RV64IB: # %bb.0:
; RV64IB-NEXT: lui a1, 1
; RV64IB-NEXT: addiw a1, a1, 3
; RV64IB-NEXT: xor a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBS-LABEL: xor_i64_4099:
; RV64IBS: # %bb.0:
; RV64IBS-NEXT: lui a1, 1
; RV64IBS-NEXT: addiw a1, a1, 3
; RV64IBS-NEXT: xor a0, a0, a1
; RV64IBS-NEXT: ret
%xor = xor i64 %a, 4099
ret i64 %xor
}
define i64 @xor_i64_96(i64 %a) nounwind {
; RV64I-LABEL: xor_i64_96:
; RV64I: # %bb.0:
; RV64I-NEXT: xori a0, a0, 96
; RV64I-NEXT: ret
;
; RV64IB-LABEL: xor_i64_96:
; RV64IB: # %bb.0:
; RV64IB-NEXT: xori a0, a0, 96
; RV64IB-NEXT: ret
;
; RV64IBS-LABEL: xor_i64_96:
; RV64IBS: # %bb.0:
; RV64IBS-NEXT: xori a0, a0, 96
; RV64IBS-NEXT: ret
%xor = xor i64 %a, 96
ret i64 %xor
}
define i64 @or_i64_large(i64 %a) nounwind {
; RV64I-LABEL: or_i64_large:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 1
; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: addi a1, a1, 1
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV64IB-LABEL: or_i64_large:
; RV64IB: # %bb.0:
; RV64IB-NEXT: addi a1, zero, 1
; RV64IB-NEXT: slli a1, a1, 32
; RV64IB-NEXT: addi a1, a1, 1
; RV64IB-NEXT: or a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBS-LABEL: or_i64_large:
; RV64IBS: # %bb.0:
; RV64IBS-NEXT: addi a1, zero, 1
; RV64IBS-NEXT: slli a1, a1, 32
; RV64IBS-NEXT: addi a1, a1, 1
; RV64IBS-NEXT: or a0, a0, a1
; RV64IBS-NEXT: ret
%or = or i64 %a, 4294967297
ret i64 %or
}
define i64 @or_i64_4099(i64 %a) nounwind {
; RV64I-LABEL: or_i64_4099:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, 3
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV64IB-LABEL: or_i64_4099:
; RV64IB: # %bb.0:
; RV64IB-NEXT: lui a1, 1
; RV64IB-NEXT: addiw a1, a1, 3
; RV64IB-NEXT: or a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBS-LABEL: or_i64_4099:
; RV64IBS: # %bb.0:
; RV64IBS-NEXT: lui a1, 1
; RV64IBS-NEXT: addiw a1, a1, 3
; RV64IBS-NEXT: or a0, a0, a1
; RV64IBS-NEXT: ret
%or = or i64 %a, 4099
ret i64 %or
}
define i64 @or_i64_96(i64 %a) nounwind {
; RV64I-LABEL: or_i64_96:
; RV64I: # %bb.0:
; RV64I-NEXT: ori a0, a0, 96
; RV64I-NEXT: ret
;
; RV64IB-LABEL: or_i64_96:
; RV64IB: # %bb.0:
; RV64IB-NEXT: ori a0, a0, 96
; RV64IB-NEXT: ret
;
; RV64IBS-LABEL: or_i64_96:
; RV64IBS: # %bb.0:
; RV64IBS-NEXT: ori a0, a0, 96
; RV64IBS-NEXT: ret
%or = or i64 %a, 96
ret i64 %or
}