[COFF] Fix ARM and ARM64 REL32 relocations to be relative to the end of the relocation

[mstorsjo]

Summary

This matches how they are defined on X86.

This should fix the relative lookup tables pass for COFF, allowing
it to be reenabled.

[mstorsjo]

Rebased, rerunning CI.

[rnk]

lgtm

llvm/lib/MC/WinCOFFObjectWriter.cpp

837

This is kind of the same thing. There's probably a refactoring here, but not without lots of surgery to the comments.

[mstorsjo]

llvm/lib/MC/WinCOFFObjectWriter.cpp

837

Yeah, I'm leaving that out as a potential future improvement.

llvm/lib/MC/WinCOFFObjectWriter.cpp

void WinCOFFObjectWriter::recordRelocation(MCAssembler &Asm,
   }
 
   ++Reloc.Symb->Relocations;
 
   Reloc.Data.VirtualAddress += Fixup.getOffset();
   Reloc.Data.Type = TargetObjectWriter->getRelocType(
       Asm.getContext(), Target, Fixup, SymB, Asm.getBackend());
 
-  // FIXME: Can anyone explain what this does other than adjust for the size
-  // of the offset?
+  // The *_REL32 relocations are relative to the end of the relocation,
+  // not to the start.
   if ((Header.Machine == COFF::IMAGE_FILE_MACHINE_AMD64 &&
        Reloc.Data.Type == COFF::IMAGE_REL_AMD64_REL32) ||
       (Header.Machine == COFF::IMAGE_FILE_MACHINE_I386 &&
-       Reloc.Data.Type == COFF::IMAGE_REL_I386_REL32))
+       Reloc.Data.Type == COFF::IMAGE_REL_I386_REL32) ||
+      (Header.Machine == COFF::IMAGE_FILE_MACHINE_ARMNT &&
+       Reloc.Data.Type == COFF::IMAGE_REL_ARM_REL32) ||
+      (Header.Machine == COFF::IMAGE_FILE_MACHINE_ARM64 &&
+       Reloc.Data.Type == COFF::IMAGE_REL_ARM64_REL32))
     FixedValue += 4;
 
   if (Header.Machine == COFF::IMAGE_FILE_MACHINE_ARMNT) {
     switch (Reloc.Data.Type) {
     case COFF::IMAGE_REL_ARM_ABSOLUTE:
     case COFF::IMAGE_REL_ARM_ADDR32:
     case COFF::IMAGE_REL_ARM_ADDR32NB:
     case COFF::IMAGE_REL_ARM_TOKEN:
case COFF::IMAGE_REL_ARM_MOV32T:
       break;
     case COFF::IMAGE_REL_ARM_BRANCH20T:
     case COFF::IMAGE_REL_ARM_BRANCH24T:
     case COFF::IMAGE_REL_ARM_BLX23T:
       // IMAGE_REL_BRANCH20T, IMAGE_REL_ARM_BRANCH24T, IMAGE_REL_ARM_BLX23T all
       // perform a 4 byte adjustment to the relocation.  Relative branches are
       // offset by 4 on ARM, however, because there is no RELA relocations, all
       // branches are offset by 4.
       FixedValue = FixedValue + 4;
       break;
     }
   }
 
   // The fixed value never makes sense for section indices, ignore it.
   if (Fixup.getKind() == FK_SecRel_2)
     FixedValue = 0;
 

llvm/test/MC/AArch64/coff-relocations.s

 // DISASM: 38:       00 14 4d 39     ldrb    w0, [x0, #837]
 // DISASM: 3c:       00 a4 41 f9     ldr     x0, [x0, #840]
 // DISASM: 40:       00 00 00 91     add     x0, x0, #0
 // DISASM: 44:       00 00 40 91     add     x0, x0, #0, lsl #12
 // DISASM: 48:       00 00 40 f9     ldr     x0, [x0]
 // DISASM: 4c:       20 1a 09 30     adr     x0, #74565
 
 // DATA: Contents of section .rdata:
-// DATA-NEXT:  0000 2c000000 04000000
+// DATA-NEXT:  0000 30000000 08000000

llvm/test/MC/ARM/coff-relocations.s

 @ CHECK-RELOCATION:   }
 @ CHECK-RELOCATION:   Section (4) .rdata {
 @ CHECK-RELOCATION:     0x0 IMAGE_REL_ARM_REL32
 @ CHECK-RELOCATION:     0x4 IMAGE_REL_ARM_REL32
 @ CHECK-RELOCATION:   }
 @ CHECK-RELOCATION: ]
 
 @ CHECK-DATA: Contents of section .rdata:
-@ CHECK-DATA-NEXT: 0000 00000000 04000000
+@ CHECK-DATA-NEXT: 0000 04000000 08000000