[RISCV] Optimize addition with immediate

[jrtc27]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1307

Misleading name given the hasOneUse

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1307

I think the more common way to do this is to have to have an "add_oneuse" PatFrag that call N->hasOneUse()

See and_su, xor_su, fmul_su in ARMInstrInfo.td or and_su, srl_su, trunc_su in X86/X86InstrInfo.td. _su in all of those stands for "single use", but "_oneuse" is more readable

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

348

I'm confused why this works. The types on RV64 are all i64. I don't think tablegen should be accepting an i32. Does the pattern work if you use AddiPair?

[benshi001]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

348

Yes. It works with only AddiPair, and I have removed the Addi32Pair.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 // Return an immediate subtracted from 32.
 def ImmSubFrom32 : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(32 - N->getZExtValue(), SDLoc(N),
                                    N->getValueType(0));
 }]>;
 
 // Check if an addition can be broken to a pair of ADDI.
 def AddiPair : ComplexPattern<XLenVT, 1, "selectAddiPair">;
+def Addi32Pair : ComplexPattern<i32, 1, "selectAddiPair">;
 
 // Return imm/2.
 def AddiPairImmA : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(N->getSExtValue() / 2, SDLoc(N),
                                    N->getValueType(0));
 }]>;
 
 // Return imm - imm/2.

 
 // Check that it is a SLLIUW (Shift Logical Left Immediate Unsigned i32
 // on RV64). Also used to optimize the same sequence without SLLIUW.
 def SLLIUWPat : PatFrag<(ops node:$A, node:$B),
                         (and (shl node:$A, node:$B), imm), [{
   return MatchSLLIUW(N);
 }]>;
 
+def add_oneuse : PatFrag<(ops node:$A, node:$B), (add node:$A, node:$B), [{
+  return N->hasOneUse();
+}]>;
+
 /// Simple arithmetic operations
 
 def : PatGprGpr<add, ADD>;
 def : PatGprSimm12<add, ADDI>;
 def : PatGprGpr<sub, SUB>;
 def : PatGprGpr<or, OR>;
 def : PatGprSimm12<or, ORI>;
 def : PatGprGpr<and, AND>;

 // debugger if possible.
 def : Pat<(debugtrap), (EBREAK)>;
 
 /// Simple optimization
 def : Pat<(add GPR:$rs1, (AddiPair GPR:$rs2)),
           (ADDI (ADDI GPR:$rs1, (AddiPairImmB GPR:$rs2)),
                 (AddiPairImmA GPR:$rs2))>;
 
+let Predicates = [IsRV64] in {
+def : Pat<(sext_inreg (add_oneuse GPR:$rs1, (Addi32Pair GPR:$rs2)), i32),
+          (ADDIW (ADDIW GPR:$rs1, (AddiPairImmB GPR:$rs2)),
+                 (AddiPairImmA GPR:$rs2))>;
+}
+
 //===----------------------------------------------------------------------===//
 // Standard extensions
 //===----------------------------------------------------------------------===//
 
 include "RISCVInstrInfoM.td"
 include "RISCVInstrInfoA.td"
 include "RISCVInstrInfoF.td"
 include "RISCVInstrInfoD.td"
 include "RISCVInstrInfoC.td"
 include "RISCVInstrInfoB.td"
 include "RISCVInstrInfoV.td"
 include "RISCVInstrInfoZfh.td"

llvm/test/CodeGen/RISCV/add-imm.ll

 ; RV32I-LABEL: add32_sext_accept:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a0, a0, 1500
 ; RV32I-NEXT:    addi a0, a0, 1499
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: add32_sext_accept:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a1, 1
-; RV64I-NEXT:    addiw a1, a1, -1097
-; RV64I-NEXT:    addw a0, a0, a1
+; RV64I-NEXT:    addiw a0, a0, 1500
+; RV64I-NEXT:    addiw a0, a0, 1499
 ; RV64I-NEXT:    ret
   %1 = add i32 %a, 2999
   ret i32 %1
 }
 
+@gv0 = global i32 0, align 4
+define signext i32 @add32_sext_reject_on_rv64(i32 signext %a) nounwind {
+; RV32I-LABEL: add32_sext_reject_on_rv64:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a0, a0, 1500
+; RV32I-NEXT:    addi a0, a0, 1500
+; RV32I-NEXT:    lui a1, %hi(gv0)
+; RV32I-NEXT:    sw a0, %lo(gv0)(a1)
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: add32_sext_reject_on_rv64:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a1, 1
+; RV64I-NEXT:    addiw a1, a1, -1096
+; RV64I-NEXT:    add a2, a0, a1
+; RV64I-NEXT:    lui a3, %hi(gv0)
+; RV64I-NEXT:    addw a0, a0, a1
+; RV64I-NEXT:    sw a2, %lo(gv0)(a3)
+; RV64I-NEXT:    ret
+  %b = add nsw i32 %a, 3000
+  store i32 %b, i32* @gv0, align 4
+  ret i32 %b
+}
+
 define i64 @add64_accept(i64 %a) nounwind {
 ; RV32I-LABEL: add64_accept:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, a0, 1500
 ; RV32I-NEXT:    addi a2, a2, 1499
 ; RV32I-NEXT:    sltu a0, a2, a0
 ; RV32I-NEXT:    add a1, a1, a0
 ; RV32I-NEXT:    mv a0, a2