[CSKY] Add more basic instructions including some privilege instructions

[zixuan-wu]

Summary

This patch adds more basic CSKY instructions including some privilege instructions. It involves a special operand representing register sequence like r0-r3. This operand is used at ldm/stm to load/store a sequence of register.

[rengolin]

The old 7 is now 9 and there's no 8? This is confusing.

Given that we have already merged the initial part, I think you can stop numbering the patches unless they're meant as a set, which then you start from one again (ex: 1/3, 2/3, 3/3).

Normally we would have gone all the way down small programs being generated (including ALU), but we started wrong, so let's not make it more confusing. :)

However, it's still important to know which patch depends on which, so make sure to still mark the parent/child dependencies correctly.

[myhsu]

In D101027#2708534, @rengolin wrote:

The old 7 is now 9 and there's no 8? This is confusing.

+1

Given that we have already merged the initial part, I think you can stop numbering the patches unless they're meant as a set, which then you start from one again (ex: 1/3, 2/3, 3/3).

Normally we would have gone all the way down small programs being generated (including ALU), but we started wrong, so let's not make it more confusing. :)

Agree. the now 9-th patch, which contains more fundamental instructions, might be better to come before this one

However, it's still important to know which patch depends on which, so make sure to still mark the parent/child dependencies correctly.

+1 I was not able to find this patch in the review stack either

[myhsu]

llvm/lib/Target/CSKY/CSKYInstrInfo.td

464

from 426 to this line there seems to be leading whitespaces before each line, can you remove it?

477

can you remove the leading whitespaces?

[zixuan-wu]

In D101027#2708534, @rengolin wrote:

The old 7 is now 9 and there's no 8? This is confusing.

Given that we have already merged the initial part, I think you can stop numbering the patches unless they're meant as a set, which then you start from one again (ex: 1/3, 2/3, 3/3).

Normally we would have gone all the way down small programs being generated (including ALU), but we started wrong, so let's not make it more confusing. :)

However, it's still important to know which patch depends on which, so make sure to still mark the parent/child dependencies correctly.

Because there is other patch between 7 and 9, which I will make a revision later. As I plan to delay the patch of number 9 (codegen) until all basic instructions have been upstreamed, I renumber the 9 to next and next as need. Or we just abandon the prefix pattern like [CSKY 7/n]?

[rengolin]

In D101027#2711116, @zixuan-wu wrote:

Because there is other patch between 7 and 9, which I will make a revision later.

I thought as much, but it's confusing because it's not public. :)

As I plan to delay the patch of number 9 (codegen) until all basic instructions have been upstreamed, I renumber the 9 to next and next as need.

The number series is an information for the reviewers to know there are more dependencies up front, on a closed series.

So, either you upload all patches at once and number them from 1 to N, or you don't number and just link them via parent/child.

Also, avoid posting patches that can't be merged on the current tree (like one after a private one). It makes review a lot harder because we don't know your internal order, only what's public.

Or we just abandon the prefix pattern like [CSKY 7/n]?

I think we better drop the numbers for now. Just make sure you have the right parent/child relationship and post patches that can be merged directly (with all the clear public dependencies merged before).

Thanks!
--renato

[zixuan-wu]

llvm/lib/Target/CSKY/CSKYInstrInfo.td

464

It's reserved for predicts at next patch.

[myhsu]

llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp

208

As clang tidy suggested, I think local variables should be capitalized

210

Is this debug message? If that's the case please use LLVM_DEBUG macro and errs() / dbgs() stream

230

Can we use std::make_pair here? The current syntax is a little too verbose

672

Can we use explicit type here?

687

ditto

llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.cpp

101

Can we use explicit type for Ry and Rz?

[zixuan-wu]

This comment was removed by zixuan-wu.

[zixuan-wu]

Because of out-of-date.

llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp

 //===-- CSKYAsmParser.cpp - Parse CSKY assembly to MCInst instructions --===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #include "MCTargetDesc/CSKYMCExpr.h"
 #include "MCTargetDesc/CSKYMCTargetDesc.h"
 #include "TargetInfo/CSKYTargetInfo.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/CodeGen/Register.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"

 #define GET_ASSEMBLER_HEADER
 #include "CSKYGenAsmMatcher.inc"
 
   OperandMatchResultTy parseImmediate(OperandVector &Operands);
   OperandMatchResultTy parseRegister(OperandVector &Operands);
   OperandMatchResultTy parseBaseRegImm(OperandVector &Operands);
   OperandMatchResultTy parseCSKYSymbol(OperandVector &Operands);
   OperandMatchResultTy parseConstpoolSymbol(OperandVector &Operands);
+  OperandMatchResultTy parseRegSeq(OperandVector &Operands);
 
   bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
 
 public:
   enum CSKYMatchResultTy {
     Match_Dummy = FIRST_TARGET_MATCH_RESULT_TY,
 #define GET_OPERAND_DIAGNOSTIC_TYPES
 #include "CSKYGenAsmMatcher.inc"
 #undef GET_OPERAND_DIAGNOSTIC_TYPES
   };
 
   CSKYAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
                 const MCInstrInfo &MII, const MCTargetOptions &Options)
       : MCTargetAsmParser(Options, STI, MII) {
     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
   }
 };
 
 /// Instances of this class represent a parsed machine instruction.
 struct CSKYOperand : public MCParsedAsmOperand {
   enum KindTy {
     Token,
     Register,
+    RegisterSeq,
     Immediate,
   } Kind;
 
   struct RegOp {
     unsigned RegNum;
   };
 
   struct ImmOp {
     const MCExpr *Val;
   };
 
+  struct RegSeqOp {
+    unsigned RegNumFrom;
+    unsigned RegNumTo;
+  };
+
   SMLoc StartLoc, EndLoc;
   union {
     StringRef Tok;
     RegOp Reg;
+    RegSeqOp RegSeq;
     ImmOp Imm;
   };
 
   CSKYOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
 
 public:
   CSKYOperand(const CSKYOperand &o) : MCParsedAsmOperand() {
     Kind = o.Kind;
     StartLoc = o.StartLoc;
     EndLoc = o.EndLoc;
     switch (Kind) {
     case Register:
       Reg = o.Reg;
       break;
+    case RegisterSeq:
+      RegSeq = o.RegSeq;
+      break;
     case Immediate:
       Imm = o.Imm;
       break;
     case Token:
       Tok = o.Tok;
       break;
     }
   }
 
   bool isToken() const override { return Kind == Token; }
   bool isReg() const override { return Kind == Register; }
+  bool isRegisterSeq() const { return Kind == RegisterSeq; }
   bool isImm() const override { return Kind == Immediate; }
   bool isMem() const override { return false; }
 
   static bool evaluateConstantImm(const MCExpr *Expr, int64_t &Imm) {
     if (auto CE = dyn_cast<MCConstantExpr>(Expr)) {
       Imm = CE->getValue();
       return true;
     }
template <unsigned num, unsigned shift = 0> bool isSImm() const {
     return IsConstantImm && isShiftedInt<num, shift>(Imm);
   }
 
   bool isUImm2() const { return isUImm<2>(); }
   bool isUImm5() const { return isUImm<5>(); }
   bool isUImm12() const { return isUImm<12>(); }
   bool isUImm16() const { return isUImm<16>(); }
 
+  bool isOImm5() const { return isOImm<5>(); }
   bool isOImm12() const { return isOImm<12>(); }
   bool isOImm16() const { return isOImm<16>(); }
 
   bool isUImm12Shift1() { return isUImm<12, 1>(); }
   bool isUImm12Shift2() { return isUImm<12, 2>(); }
 
   bool isSImm16Shift1() { return isSImm<16, 1>(); }
 
   bool isCSKYSymbol() const {
     int64_t Imm;
     // Must be of 'immediate' type but not a constant.
     return isImm() && !evaluateConstantImm(getImm(), Imm);
   }
 
   bool isConstpoolSymbol() const {
     int64_t Imm;
     // Must be of 'immediate' type but not a constant.
     return isImm() && !evaluateConstantImm(getImm(), Imm);
   }
 
+  template <unsigned Min, unsigned Max> bool isRegSeq() const {
+    if (!isRegisterSeq())
+      return false;
+
+    std::pair<unsigned, unsigned> regSeq = getRegSeq();
+
+    fprintf(stderr, "regSeq = %d, %d\n", regSeq.first, regSeq.second);
+
+    return regSeq.first <= regSeq.second && Min <= regSeq.first &&
+           regSeq.second <= Max;
+  }
+
+  bool isRegSeqGPR() const { return isRegSeq<CSKY::R0, CSKY::R31>(); }
+
   /// Gets location of the first token of this operand.
   SMLoc getStartLoc() const override { return StartLoc; }
   /// Gets location of the last token of this operand.
   SMLoc getEndLoc() const override { return EndLoc; }
 
   unsigned getReg() const override {
     assert(Kind == Register && "Invalid type access!");
     return Reg.RegNum;
   }
 
+  std::pair<unsigned, unsigned> getRegSeq() const {
+    assert(Kind == RegisterSeq && "Invalid type access!");
+    return std::pair<unsigned, unsigned>(RegSeq.RegNumFrom, RegSeq.RegNumTo);
+  }
+
   const MCExpr *getImm() const {
     assert(Kind == Immediate && "Invalid type access!");
     return Imm.Val;
   }
 
   StringRef getToken() const {
     assert(Kind == Token && "Invalid type access!");
     return Tok;
   }
 
   void print(raw_ostream &OS) const override {
     switch (Kind) {
     case Immediate:
       OS << *getImm();
       break;
     case Register:
       OS << "<register x" << getReg() << ">";
       break;
+    case RegisterSeq:
+      OS << "<register-seq r";
+      OS << getRegSeq().first << "-" << getRegSeq().second << ">";
+      break;
     case Token:
       OS << "'" << getToken() << "'";
       break;
     }
   }
 
   static std::unique_ptr<CSKYOperand> createToken(StringRef Str, SMLoc S) {
     auto Op = std::make_unique<CSKYOperand>(Token);
     Op->Tok = Str;
     Op->StartLoc = S;
     Op->EndLoc = S;
     return Op;
   }
 
   static std::unique_ptr<CSKYOperand> createReg(unsigned RegNo, SMLoc S,
                                                 SMLoc E) {
     auto Op = std::make_unique<CSKYOperand>(Register);
     Op->Reg.RegNum = RegNo;
     Op->StartLoc = S;
     Op->EndLoc = E;
     return Op;
   }
 
+  static std::unique_ptr<CSKYOperand> createRegSeq(unsigned RegNoFrom,
+                                                   unsigned RegNoTo, SMLoc S) {
+    auto Op = std::make_unique<CSKYOperand>(RegisterSeq);
+    Op->RegSeq.RegNumFrom = RegNoFrom;
+    Op->RegSeq.RegNumTo = RegNoTo;
+    Op->StartLoc = S;
+    Op->EndLoc = S;
+    return Op;
+  }
+
   static std::unique_ptr<CSKYOperand> createImm(const MCExpr *Val, SMLoc S,
                                                 SMLoc E) {
     auto Op = std::make_unique<CSKYOperand>(Immediate);
     Op->Imm.Val = Val;
     Op->StartLoc = S;
     Op->EndLoc = E;
     return Op;
   }
void addRegOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(getReg()));
   }
 
   void addImmOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     addExpr(Inst, getImm());
   }
+
+  void addRegSeqOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    auto regSeq = getRegSeq();
+
+    Inst.addOperand(MCOperand::createReg(regSeq.first));
+    Inst.addOperand(MCOperand::createImm(regSeq.second));
+  }
 };
 } // end anonymous namespace.
 
 #define GET_REGISTER_MATCHER
 #define GET_SUBTARGET_FEATURE_NAME
 #define GET_MATCHER_IMPLEMENTATION
 #define GET_MNEMONIC_SPELL_CHECKER
 #include "CSKYGenAsmMatcher.inc"
if (Result > FIRST_TARGET_MATCH_RESULT_TY) {
     SMLoc ErrorLoc = IDLoc;
     if (ErrorInfo != ~0U && ErrorInfo >= Operands.size())
       return Error(ErrorLoc, "too few operands for instruction");
   }
 
   switch (Result) {
   default:
     break;
+  case Match_InvalidOImm5:
+    return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 5));
   case Match_InvalidOImm12:
     return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 12));
   case Match_InvalidOImm16:
     return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 16));
   case Match_InvalidUImm2:
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 2) - 1);
   case Match_InvalidUImm5:
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 5) - 1);
bool CSKYAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_InvalidCSKYSymbol: {
     SMLoc ErrorLoc = ((CSKYOperand &)*Operands[ErrorInfo]).getStartLoc();
     return Error(ErrorLoc, "operand must be a symbol name");
   }
   case Match_InvalidConstpool: {
     SMLoc ErrorLoc = ((CSKYOperand &)*Operands[ErrorInfo]).getStartLoc();
     return Error(ErrorLoc, "operand must be a constpool symbol name");
   }
+  case Match_InvalidRegSeq: {
+    SMLoc ErrorLoc = ((CSKYOperand &)*Operands[ErrorInfo]).getStartLoc();
+    return Error(ErrorLoc,
+                 "operand must be a register sequence like (rN-rM, N<=M)");
+  }
   }
 
   llvm_unreachable("Unknown match type detected!");
 }
 
 // Attempts to match Name as a register (either using the default name or
 // alternative ABI names), setting RegNo to the matching register. Upon
 // failure, returns true and sets RegNo to 0.
OperandMatchResultTy CSKYAsmParser::parseBaseRegImm(OperandVector &Operands) {
   auto Tok = getParser().Lex(); // Eat '('
 
   if (parseRegister(Operands) != MatchOperand_Success) {
     getLexer().UnLex(Tok);
     Operands.pop_back();
     return MatchOperand_ParseFail;
   }
 
+  if (getLexer().is(AsmToken::RParen)) {
+    Operands.push_back(CSKYOperand::createToken(")", getLoc()));
+    getParser().Lex(); // Eat ')'
+    return MatchOperand_Success;
+  }
+
   if (getLexer().isNot(AsmToken::Comma)) {
     Error(getLoc(), "expected ','");
     return MatchOperand_ParseFail;
   }
 
   getParser().Lex(); // Eat ','
 
   if (parseRegister(Operands) == MatchOperand_Success) {
CSKYAsmParser::parseConstpoolSymbol(OperandVector &Operands) {
 
   MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier);
   const MCExpr *Res =
       MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext());
   Operands.push_back(CSKYOperand::createImm(Res, S, E));
   return MatchOperand_Success;
 }
 
+OperandMatchResultTy CSKYAsmParser::parseRegSeq(OperandVector &Operands) {
+  SMLoc S = getLoc();
+
+  if (parseRegister(Operands) != MatchOperand_Success)
+    return MatchOperand_ParseFail;
+
+  auto Ry = Operands.back()->getReg();
+  Operands.pop_back();
+
+  if (getLexer().isNot(AsmToken::Minus)) {
+    Error(getLoc(), "expected '-'");
+    return MatchOperand_ParseFail;
+  }
+
+  getLexer().Lex(); // eat '-'
+
+  if (parseRegister(Operands) != MatchOperand_Success) {
+    Error(getLoc(), "invalid register");
+    return MatchOperand_ParseFail;
+  }
+
+  auto Rz = Operands.back()->getReg();
+  Operands.pop_back();
+
+  Operands.push_back(CSKYOperand::createRegSeq(Ry, Rz, S));
+  return MatchOperand_Success;
+}
+
 bool CSKYAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
                                      SMLoc NameLoc, OperandVector &Operands) {
   // First operand is token for instruction.
   Operands.push_back(CSKYOperand::createToken(Name, NameLoc));
 
   // If there are no more operands, then finish.
   if (getLexer().is(AsmToken::EndOfStatement))
     return false;

llvm/lib/Target/CSKY/CSKYInstrFormats.td

class I_12_PP<bits<5> sop, bits<5> pcode, dag outs, dag ins, string op>
   let Inst{11 - 0} = regs;
 }
 
 // Format< OP[6] | RZ[5] | RX[5] | SOP[6] | PCODE[5] | IMM[5]>
 // Instructions(4): incf32, inct32, decf32, dect32
 class I_5_ZX<bits<6> sop, bits<5> pcode, string op, ImmLeaf ImmType,
              list<dag> pattern>
     : CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz),
-    (ins GPR:$false, GPR:$rx, ImmType:$imm5),
+    (ins CARRY:$cond, GPR:$false, GPR:$rx, ImmType:$imm5),
     !strconcat(op, "\t$rz, $rx, $imm5"), pattern> {
   bits<5> rz;
   bits<5> rx;
   bits<5> imm5;
   let Inst{25 - 21} = rz;
   let Inst{20 - 16} = rx;
   let Inst{15 - 10} = sop;
   let Inst{9 - 5} = pcode;
   let Inst{4 - 0} = imm5;
   let Constraints = "$rz = $false";
 }
-
 // Format< OP[6] | IMM[5] | RX[5] | SOP[6] | PCODE[5] | RZ[5]>
 // Instructions(13): decgt32, declt32, decne32, lsli32, lslc32, lsri32
 //                   lsrc32, asri32, asrc32, rotli32, xsr32, bclri32, bseti32
 class I_5_XZ<bits<6> sop, bits<5> pcode, string op, dag ins, dag outs,
              list<dag> pattern>
     : CSKY32Inst<AddrModeNone, 0x31, ins, outs,
                  !strconcat(op, "\t$rz, $rx, $imm5"), pattern> {
   bits<5> imm5;
   bits<5> rx;
   bits<5> rz;
   let Inst{25 - 21} = imm5;
   let Inst{20 - 16} = rx;
   let Inst{15 - 10} = sop;
   let Inst{9 - 5} = pcode;
   let Inst{4 - 0} = rz;
 }
 
 // Format< OP[6] | RY[5] | RX[5] | SOP[6] | PCODE[5] | IMM[5]>
 // Instructions(2): ldm32, (ldq32), stm32, (stq32)
-class I_5_YX<bits<6> opcode, dag outs, dag ins, string op, list<dag> pattern,
-             bits<5> imm5>
-    : CSKY32Inst<AddrModeNone, opcode, outs, ins,
-                 op #"\t${ry}, (${rx}), " #!cast<int>(imm5), pattern> {
+class I_5_YX<bits<6> opcode, bits<6> sop, dag outs, dag ins, string opStr, list<dag> pattern>
+    : CSKY32Inst<AddrModeNone, opcode, outs, ins, opStr, pattern> {
+  bits<10> regs;
   bits<5> rx;
-  bits<5> ry;
-  let Inst{25 - 21} = ry; // ry
+
+  let Inst{25 - 21} = regs{9 - 5}; // ry
   let Inst{20 - 16} = rx;
-  let Inst{15 - 10} = 0b000111;
+  let Inst{15 - 10} = sop;
   let Inst{9 - 5} = 0b00001;
-  let Inst{4 - 0} = imm5{4 - 0}; // imm5
+  let Inst{4 - 0} = regs{4 - 0}; // imm5
 }
 
 // Format< OP[6] | LSB[5] | RX[5] | SOP[6] | MSB[5] | RZ[5]>
 // Instructions(6): zext32, zextb32, zexth32, sext32, sextb32, sexth32
 class I_5_XZ_U<bits<6> sop, dag outs, dag ins, string op, list<dag> pattern>
     : CSKY32Inst<AddrModeNone, 0x31, outs, ins, op #"\t$rz, $rx, $msb, $lsb",
                  pattern> {
   bits<5> rx;
   bits<5> rz;
   bits<5> msb;
   bits<5> lsb;
   let Inst{25 - 21} = lsb; // lsb
   let Inst{20 - 16} = rx;
   let Inst{15 - 10} = sop;
   let Inst{9 - 5} = msb; // msb
   let Inst{4 - 0} = rz;
 }
 
+// Format< OP[6] | LSB[5] | RX[5] | SOP[6] | MSB[5] | RZ[5]>
+// Instructions(6): zext32, zextb32, zexth32, sext32, sextb32, sexth32
+class I_5_XZ_U2<bits<6> sop, bits<5> lsb, bits<5> msb, dag outs, dag ins,
+  string op, list<dag> pattern>
+  : CSKY32Inst<AddrModeNone, 0x31, outs, ins, !strconcat(op, "\t$rz, $rx"), pattern> {
+  bits<5> rx;
+  bits<5> rz;
+  let Inst{25 - 21} = lsb;     // lsb
+  let Inst{20 - 16} = rx;
+  let Inst{15 - 10} = sop;
+  let Inst{9 - 5} = msb;       // msb
+  let Inst{4 - 0} = rz;
+}
+
 // sextb, sexth
-class I_5_XZ_US<bits<6> sop, string op, SDNode opnode,
-  ValueType type> : I_5_XZ_U<sop, (outs GPR:$rz), (ins GPR:$rx, uimm5:$msb, uimm5:$lsb), op,
-    [(set GPR:$rz, (opnode GPR:$rx, type))]>;
+class I_5_XZ_US<bits<6> sop, bits<5> lsb, bits<5> msb, string op,
+  SDNode opnode, ValueType type>
+  : I_5_XZ_U2<sop, lsb, msb, (outs GPR:$rz), (ins GPR:$rx), op,
 
-class I_5_XZ_UZ<bits<6> sop, string op, int v>
-    : I_5_XZ_U<sop, (outs GPR:$rz), (ins GPR:$rx, uimm5:$msb, uimm5:$lsb), op,
-    [(set GPR:$rz, (and GPR:$rx, (i32 v)))]>;
+class I_5_XZ_UZ<bits<6> sop, bits<5> lsb, bits<5> msb, string op, int v>
+  : I_5_XZ_U2<sop, lsb, msb, (outs GPR:$rz), (ins GPR:$rx), op,
 
 // Format< OP[6] | RZ[5] | RX[5] | SOP[6] | SIZE[5] | LSB[5]>
 // Instructions(1): ins32
 class I_5_ZX_U<bits<6> sop, string op, Operand operand, list<dag> pattern>
     : CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz), (ins operand:$size_lsb),
                  !strconcat(op, "\t$rz, operand:$size_lsb"), pattern> {
   bits<10> size_lsb;
   bits<5> rz;
class R_ZX<bits<6> sop, bits<5> pcode, string op, list<dag> pattern>
   let Inst{9 - 5} = pcode;
   let Inst{4 - 0} = 0;
   let Constraints = "$rz = $false";
   let isSelect = 1;
 }
 
 // Format< OP[6] | 00000[5] | RX[5] | SOP[6] | PCODE[5] | 00000[5] >
 // Instructions:(1) tstnbz32
-class R_X<bits<6> sop, bits<5> pcode, string op, list<dag> pattern>
-    : CSKY32Inst<AddrModeNone, 0x31, (outs CARRY:$ca),(ins GPR:$rx),
-                 !strconcat(op, "\t$rx"), pattern> {
+class R_X<bits<6> sop, bits<5> pcode, dag outs, dag ins, string op, list<dag> pattern>
+    : CSKY32Inst<AddrModeNone, 0x31, outs, ins, !strconcat(op, "\t$rx"), pattern> {
   bits<5> rx;
   let Inst{25 - 21} = 0;
   let Inst{20 - 16} = rx;
   let Inst{15 - 10} = sop;
   let Inst{9 - 5} = pcode;
   let Inst{4 - 0} = 0;
 }
 
class R_Z_2<bits<6> sop, bits<5> pcode, string op, list<dag> pattern>
   bits<5> rz;
   let Inst{25 - 21} = rz;
   let Inst{20 - 16} = 0;
   let Inst{15 - 10} = sop;
   let Inst{9 - 5} = pcode;
   let Inst{4 - 0} = 0;
   let Constraints = "$rz = $false";
 }
+
+// sync
+class I_5_XZ_SYNC<bits<6> sop, bits<5> pcode, string opStr, bits<1> S, bits<1> I>
+    : CSKY32Inst<AddrModeNone, 0x30, (outs), (ins), opStr, []> {
+  let Inst{25 - 21} = 0;
+  let Inst{20 - 16} = 0;
+  let Inst{15 - 10} = sop;
+  let Inst{9 - 5} = pcode;
+  let Inst{4 - 0} = 0;
+  let Inst{25} = S;
+  let Inst{21} = I;
+}
+
+// Priviledged Instructions
+class I_5_XZ_PRIVI<bits<6> sop, bits<5> pcode, string opStr>
+    : CSKY32Inst<AddrModeNone, 0x30, (outs), (ins), opStr, []> {
+  let Inst{25 - 21} = 0;
+  let Inst{20 - 16} = 0;
+  let Inst{15 - 10} = sop;
+  let Inst{9 - 5} = pcode;
+  let Inst{4 - 0} = 0;
+}
+
+class BAR<bits<5> sop, string op, bits<1> signed>
+  : CSKY32Inst<AddrModeNone, 0x30, (outs), (ins), op, []> {
+  let Inst{25} = signed;
+  let Inst{24 - 16} = 0;
+  let Inst{15 - 5} = 0x421;
+  let Inst{4 - 0} = sop;
+  let hasSideEffects = 1;
+  let mayLoad = 0;
+  let mayStore = 0;
+}

llvm/lib/Target/CSKY/CSKYInstrInfo.td

let EncoderMethod =
     "getConstpoolSymbolOpValue<CSKY::fixup_csky_pcrel_uimm16_scale4>";
 }
 
 def bare_symbol : Operand<iPTR> {
   let ParserMatchClass = CSKYSymbol;
   let EncoderMethod = "getBareSymbolOpValue";
 }
 
+def oimm5 : oimm<5>;
 def oimm12 : oimm<12>;
 def oimm16 : oimm<16>;
 
 def nimm12 : nimm<12>;
 
 def uimm5 : uimm<5>;
 def uimm12 : uimm<12>;
 def uimm12_1 : uimm<12, 1>;
 def uimm12_2 : uimm<12, 2>;
 def uimm16 : uimm<16>;
 
 
+class RegSeq<string suffix> : AsmOperandClass {
+  let Name = "RegSeq" # suffix;
+  let RenderMethod = "addRegSeqOperands";
+  let DiagnosticType = "InvalidRegSeq";
+  let ParserMethod = "parseRegSeq";
+}
+
+class regseq_t<RegisterClass regtype, string suffix> : Operand<iPTR> {
+  let MIOperandInfo = (ops regtype:$ry, uimm5:$imm);
+  let ParserMatchClass = RegSeq<suffix>;
+  let EncoderMethod = "getRegSeqImmOpValue";
+  let PrintMethod = "printRegSeq";
+}
+
+def regseq : regseq_t<GPR, "GPR">;
+
 //===----------------------------------------------------------------------===//
 // Instruction Formats
 //===----------------------------------------------------------------------===//
 
 include "CSKYInstrFormats.td"
 
 //===----------------------------------------------------------------------===//
 // Instruction definitions.
 //===----------------------------------------------------------------------===//
 
 class TriOpFrag<dag res> : PatFrag<(ops node: $LHS, node:$MHS, node:$RHS), res>;
 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
 class UnOpFrag<dag res> : PatFrag<(ops node:$Src), res>;
 
 
 
 //===----------------------------------------------------------------------===//
 // Basic ALU instructions.
 //===----------------------------------------------------------------------===//
-
+  let isAdd = 1 in
   def ADDI32 : I_12<0x0, "addi32", add, oimm12>;
   def SUBI32 : I_12<0x1, "subi32", sub, oimm12>;
   def ORI32 : I_16_ZX<"ori32", uimm16,
   [(set GPR:$rz, (or GPR:$rx, uimm16:$imm16))]>;
   def XORI32 : I_12<0x4, "xori32", xor, uimm12>;
   def ANDI32 : I_12<0x2, "andi32", and, uimm12>;
   def ANDNI32 : I_12<0x3, "andni32", and, nimm12>;
   def LSLI32 : I_5_XZ<0x12, 0x1, "lsli32",
     (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
     [(set GPR:$rz, (shl GPR:$rx, uimm5:$imm5))]>;
   def LSRI32 : I_5_XZ<0x12, 0x2, "lsri32",
     (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
     [(set GPR:$rz, (srl GPR:$rx, uimm5:$imm5))]>;
   def ASRI32 : I_5_XZ<0x12, 0x4, "asri32",
     (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
     [(set GPR:$rz, (sra GPR:$rx, uimm5:$imm5))]>;
   def ROTLI32 : I_5_XZ<0x12, 0x8, "rotli32",
     (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
     [(set GPR:$rz, (rotl GPR:$rx, uimm5:$imm5))]>;
 
-
+  let isAdd = 1 in
   def ADDU32 : R_YXZ_SP_F1<0x0, 0x1,
     BinOpFrag<(add node:$LHS, node:$RHS)>, "addu32", 1>;
   def SUBU32 : R_YXZ_SP_F1<0x0, 0x4,
     BinOpFrag<(sub node:$LHS, node:$RHS)>, "subu32">;
   def MULT32 : R_YXZ_SP_F1<0x21, 0x1,
     BinOpFrag<(mul node:$LHS, node:$RHS)>, "mult32", 1>;
   def AND32 : R_YXZ_SP_F1<0x8, 0x1,
     BinOpFrag<(and node:$LHS, node:$RHS)>, "and32", 1>;
   def ANDN32 : R_YXZ_SP_F1<0x8, 0x2,
     BinOpFrag<(and node:$LHS, (not node:$RHS))>, "andn32">;
   def OR32: R_YXZ_SP_F1<0x9, 0x1,
     BinOpFrag<(or node:$LHS, node:$RHS)>, "or32", 1>;
   def XOR32 : R_YXZ_SP_F1<0x9, 0x2,
     BinOpFrag<(xor node:$LHS, node:$RHS)>, "xor32", 1>;
   def NOR32 : R_YXZ_SP_F1<0x9, 0x4,
     BinOpFrag<(not (or node:$LHS, node:$RHS))>, "nor32", 1>;
+
   def NOT32 : R_XXZ<0b001001, 0b00100, (outs GPR:$rz), (ins GPR:$rx),
     "not32", [(set GPR:$rz, (not GPR:$rx))]>;
   def LSL32 : R_YXZ_SP_F1<0x10, 0x1,
     BinOpFrag<(shl node:$LHS, node:$RHS)>, "lsl32">;
   def LSR32 : R_YXZ_SP_F1<0x10, 0x2,
     BinOpFrag<(srl node:$LHS, node:$RHS)>, "lsr32">;
   def ASR32 : R_YXZ_SP_F1<0x10, 0x4,
     BinOpFrag<(sra node:$LHS, node:$RHS)>, "asr32">;
   def ROTL32 : R_YXZ_SP_F1<0x10, 0x8,
     BinOpFrag<(rotl node:$LHS, (and node:$RHS, 0x1f))>, "rotl32">;
 
-  // TODO: Shift series instr. with carry.
+  def LSLC32 : I_5_XZ<0x13, 0x1, "lslc32",
+    (outs GPR:$rz, CARRY:$cout), (ins GPR:$rx, oimm5:$imm5), []>;
+  def LSRC32 : I_5_XZ<0x13, 0x2, "lsrc32",
+    (outs GPR:$rz, CARRY:$cout), (ins GPR:$rx, oimm5:$imm5), []>;
+  def ASRC32 : I_5_XZ<0x13, 0x4, "asrc32",
+    (outs GPR:$rz, CARRY:$cout), (ins GPR:$rx, oimm5:$imm5), []>;
+  def XSR32 : I_5_XZ<0x13, 0x8, "xsr32",
+    (outs GPR:$rz, CARRY:$cout), (ins GPR:$rx, oimm5:$imm5, CARRY:$cin), []>;
 
   def IXH32 : R_YXZ_SP_F1<0x2, 0x1,
     BinOpFrag<(add node:$LHS, (shl node:$RHS, (i32 1)))>, "ixh32">;
   def IXW32 : R_YXZ_SP_F1<0x2, 0x2,
     BinOpFrag<(add node:$LHS, (shl node:$RHS, (i32 2)))>, "ixw32">;
 
   def IXD32 : R_YXZ_SP_F1<0x2, 0x4,
     BinOpFrag<(add node:$LHS, (shl node:$RHS, (i32 3)))>, "ixd32">;
 
-  let isCommutable = 1 in
+  let isCommutable = 1, isAdd = 1 in
   def ADDC32 : R_YXZ<0x31, 0x0, 0x2, (outs GPR:$rz, CARRY:$cout),
     (ins GPR:$rx, GPR:$ry, CARRY:$cin), "addc32", []>;
   def SUBC32 : R_YXZ<0x31, 0x0, 0x8, (outs GPR:$rz, CARRY:$cout),
     (ins GPR:$rx, GPR:$ry, CARRY:$cin), "subc32", []>;
 
-  // TODO: incf32.
+  def INCF32 : I_5_ZX<0x3, 0x1, "incf32", uimm5, []>;
+  def INCT32 : I_5_ZX<0x3, 0x2, "inct32", uimm5, []>;
+  def DECF32 : I_5_ZX<0x3, 0x4, "decf32", uimm5, []>;
+  def DECT32 : I_5_ZX<0x3, 0x8, "dect32", uimm5, []>;
+
+
   def DIVS32 : R_YXZ_SP_F1<0x20, 0x2,
     BinOpFrag<(sdiv node:$LHS, node:$RHS)>, "divs32">;
   def DIVU32 : R_YXZ_SP_F1<0x20, 0x1,
     BinOpFrag<(udiv node:$LHS, node:$RHS)>, "divu32">;
 
   def DECGT32 : I_5_XZ<0x4, 0x1, "decgt32",
     (outs GPR:$rz, CARRY:$cout), (ins GPR:$rx, uimm5:$imm5), []>;
   def DECLT32 : I_5_XZ<0x4, 0x2, "declt32",
     (outs GPR:$rz, CARRY:$cout), (ins GPR:$rx, uimm5:$imm5), []>;
   def DECNE32 : I_5_XZ<0x4, 0x4, "decne32",
     (outs GPR:$rz, CARRY:$cout), (ins GPR:$rx, uimm5:$imm5), []>;
 
-  // TODO: s/zext.
-  def ZEXT32 : I_5_XZ_U<0x15, (outs GPR:$rz),
-    (ins GPR:$rx, uimm5:$msb, uimm5:$lsb), "zext32",[]>;
-  def SEXT32 : I_5_XZ_U<0x16, (outs GPR:$rz),
-    (ins GPR:$rx, uimm5:$msb, uimm5:$lsb), "sext32", []>;
+  def SEXT32 : I_5_XZ_U<0x16, (outs GPR:$rz), (ins GPR:$rx, uimm5:$msb, uimm5:$lsb), "sext32", []>;
+  def SEXTB32 : I_5_XZ_US<0x16, 0, 7, "sextb32", sext_inreg, i8>;
+  def SEXTH32 : I_5_XZ_US<0x16, 0, 15, "sexth32", sext_inreg, i16>;
+  def ZEXTB32 : I_5_XZ_UZ<0x15, 0, 7, "zextb32", 255>;
+  def ZEXTH32 : I_5_XZ_UZ<0x15, 0, 15, "zexth32", 65535>;
+  def ZEXT32 : I_5_XZ_U<0x15, (outs GPR:$rz), (ins GPR:$rx, uimm5:$msb, uimm5:$lsb), "zext32",[]>;
+
 
 //===----------------------------------------------------------------------===//
 // Load & Store instructions.
 //===----------------------------------------------------------------------===//
 
 def LD32B : I_LD<AddrMode32B, 0x0, "ld32.b", uimm12>;
 def LD32H : I_LD<AddrMode32H, 0x1, "ld32.h", uimm12_1>;
 def LD32W : I_LD<AddrMode32WD, 0x2, "ld32.w", uimm12_2>;
 
 
   def LD32BS : I_LD<AddrMode32B, 0x4, "ld32.bs", uimm12>;
   def LD32HS : I_LD<AddrMode32H, 0x5, "ld32.hs", uimm12_1>;
 
-  // TODO: LDM and STM.
+  def LDM32 : I_5_YX<0b110100, 0b000111,
+    (outs regseq:$regs), (ins GPR:$rx), "ldm32\t$regs, (${rx})", []>;
+  def STM32 : I_5_YX<0b110101, 0b000111,
+    (outs), (ins regseq:$regs, GPR:$rx), "stm32\t$regs, (${rx})", []>;
 
 
 def ST32B : I_ST<AddrMode32B, 0x0, "st32.b", uimm12>;
 def ST32H : I_ST<AddrMode32H, 0x1, "st32.h", uimm12_1>;
 def ST32W : I_ST<AddrMode32WD, 0x2, "st32.w", uimm12_2>;
 
 
   def LDR32B :  I_LDR<0x0, "ldr32.b">;
   def LDR32BS :  I_LDR<0x4, "ldr32.bs">;
   def LDR32H :  I_LDR<0x1, "ldr32.h">;
   def LDR32HS :  I_LDR<0x5, "ldr32.hs">;
   def LDR32W :  I_LDR<0x2, "ldr32.w">;
   def STR32B :  I_STR<0x0, "str32.b">;
   def STR32H :  I_STR<0x1, "str32.h">;
   def STR32W :  I_STR<0x2, "str32.w">;
 
-  //TODO: SPILL_CARRY and RESTORE_CARRY.
-
 //===----------------------------------------------------------------------===//
 // Compare instructions.
 //===----------------------------------------------------------------------===//
 
   def CMPNEI32 : I_16_X<0x1A, "cmpnei32", uimm16>;
   def CMPHSI32 : I_16_X<0x18, "cmphsi32", oimm16>;
   def CMPLTI32 : I_16_X<0x19, "cmplti32", oimm16>;
 
 
   def CMPNE32 : R_YX<0x1, 0x4, "cmpne32">;
   def CMPHS32 : R_YX<0x1, 0x1, "cmphs32">;
   def CMPLT32 : R_YX<0x1, 0x2, "cmplt32">;
 
-  // TODO: setc and clrc.
-  // TODO: test32 and tstnbz.
+  def SETC32 : CSKY32Inst<AddrModeNone, 0x31,
+    (outs CARRY:$ca), (ins), "setc32", []> {
+    let Inst{25 - 21} = 0; //rx
+    let Inst{20 - 16} = 0; //ry
+    let Inst{15 - 10} = 0x1;
+    let Inst{9 - 5} = 0x1;
+    let Inst{4 - 0} = 0;
+    let isCompare = 1;
+  }
+  def CLRC32 : CSKY32Inst<AddrModeNone, 0x31,
+    (outs CARRY:$ca), (ins), "clrc32", []> {
+    let Inst{25 - 21} = 0; //rx
+    let Inst{20 - 16} = 0; //ry
+    let Inst{15 - 10} = 0x1;
+    let Inst{9 - 5} = 0x4;
+    let Inst{4 - 0} = 0;
+    let isCompare = 1;
+  }
+
+  def TST32 : R_YX<0x8, 0x4, "tst32">;
+  def TSTNBZ32 : R_X<0x8, 0x8,
+    (outs CARRY:$ca), (ins GPR:$rx), "tstnbz32", []>;
+
 
 //===----------------------------------------------------------------------===//
 // Data move instructions.
 //===----------------------------------------------------------------------===//
 
+
   def MOVT32 : R_ZX<0x3, 0x2, "movt32", []>;
   def MOVF32 : R_ZX<0x3, 0x1, "movf32", []>;
   def MOVI32 : I_16_MOV<0x10, "movi32", uimm16>;
   def MOVIH32 : I_16_MOV<0x11, "movih32", uimm16_16_xform>;
   def MVC32 : R_Z_1<0x1, 0x8, "mvc32">;
   def MOV32 : R_XZ<0x12, 0x1, "mov32">;
 
-  // TODO: ISEL Pseudo.
-
   def MVCV32 : R_Z_1<0x1, 0x10, "mvcv32">;
-  // TODO: clrf and clrt.
   def CLRF32 : R_Z_2<0xB, 0x1, "clrf32", []>;
   def CLRT32 : R_Z_2<0xB, 0x2, "clrt32", []>;
 
+
 //===----------------------------------------------------------------------===//
 // Branch and call instructions.
 //===----------------------------------------------------------------------===//
 
 let isBranch = 1, isTerminator = 1 in {
   let isBarrier = 1, isPredicable = 1 in
     def BR32 : I_16_L<0x0, (outs), (ins br_symbol:$imm16), "br32\t$imm16",
                      [(br bb:$imm16)]>;
 
   def BT32 : I_16_L<0x3, (outs), (ins CARRY:$ca, br_symbol:$imm16),
     "bt32\t$imm16", [(brcond CARRY:$ca, bb:$imm16)]>;
   def BF32 : I_16_L<0x2, (outs), (ins CARRY:$ca, br_symbol:$imm16),
     "bf32\t$imm16", []>;
 }
 
-
   def BEZ32 : I_16_X_L<0x8, "bez32", br_symbol>;
   def BNEZ32 : I_16_X_L<0x9, "bnez32", br_symbol>;
   def BHZ32 : I_16_X_L<0xA, "bhz32", br_symbol>;
   def BLSZ32 : I_16_X_L<0xB, "blsz32", br_symbol>;
   def BLZ32 : I_16_X_L<0xC, "blz32", br_symbol>;
   def BHSZ32 : I_16_X_L<0xD, "bhsz32", br_symbol>;
 
   let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {

 
 //===----------------------------------------------------------------------===//
 // Symbol address instructions.
 //===----------------------------------------------------------------------===//
 
 def GRS32 : I_18_Z_L<0x3, "grs32\t$rz, $offset",
                     (outs GPR:$rz), (ins bare_symbol:$offset), []>;
 
+
 let mayLoad = 1, mayStore = 0 in {
 def LRW32 : I_16_Z_L<0x14, "lrw32", (ins constpool_symbol:$imm16), []>;
 let isCodeGenOnly = 1 in
-def LRW32_Gen : I_16_Z_L<0x14, "lrw32",
-  (ins bare_symbol:$src1, constpool_symbol:$imm16), []>;
+def LRW32_Gen : I_16_Z_L<0x14, "lrw32", (ins bare_symbol:$src1, constpool_symbol:$imm16), []>;
 }
 
-// TODO: Atomic and fence instructions.
-// TODO: Other operations.
+//===----------------------------------------------------------------------===//
+// Atomic and fence instructions.
+//===----------------------------------------------------------------------===//
+
+  def BRWARW : BAR<0b01111, "bar.brwarw", 0>;
+  def BRWARWS : BAR<0b01111, "bar.brwarws", 1>;
+  def BRARW : BAR<0b00111, "bar.brarw", 0>;
+  def BRARWS : BAR<0b00111, "bar.brarws", 1>;
+  def BRWAW : BAR<0b01110, "bar.brwaw", 0>;
+  def BRWAWS : BAR<0b01110, "bar.brwaws", 1>;
+  def BRAR : BAR<0b00101, "bar.brar", 0>;
+  def BRARS : BAR<0b00101, "bar.brars", 1>;
+  def BWAW : BAR<0b01010, "bar.bwaw", 0>;
+  def BWAWS : BAR<0b01010, "bar.bwaws", 1>;
+
+  def LDEX32W : I_LD<AddrMode32WD, 0x7, "ldex32.w", uimm12_2>;
+  let Constraints = "$rd = $rz" in
+    def STEX32W : I_LDST<AddrMode32WD, 0x37, 7,
+      (outs GPR:$rd), (ins GPR:$rz, GPR:$rx, uimm12_2:$imm12), "stex32.w", []>;
+
+
+//===----------------------------------------------------------------------===//
+// Other operation instructions.
+//===----------------------------------------------------------------------===//
+
+  def BREV32 : R_XZ<0x18, 0x10, "brev32">;
+  def ABS32 : R_XZ<0x0, 0x10, "abs32">;
+  def BGENR32 : R_XZ<0x14, 0x2, "bgenr32">;
+
+
+  def REVB32 : R_XZ<0x18, 0x4, "revb32">;
+  def REVH32 : R_XZ<0x18, 0x8, "revh32">;
+  def FF0 : R_XZ<0x1F, 0x1, "ff0.32">;
+  def FF1 : R_XZ<0x1F, 0x2, "ff1.32">;
+  def XTRB0 : R_XZ<0x1C, 0x1, "xtrb0.32">;
+  def XTRB1 : R_XZ<0x1C, 0x2, "xtrb1.32">;
+  def XTRB2 : R_XZ<0x1C, 0x4, "xtrb2.32">;
+  def XTRB3 : R_XZ<0x1C, 0x8, "xtrb3.32">;
+  def BTSTI32 : I_5_X<0x0A, 0x4, "btsti32", uimm5, []>;
+  def BCLRI32 : I_5_XZ<0xA, 0x1, "bclri32",
+  (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5), []>;
+  def BSETI32 : I_5_XZ<0xA, 0x2, "bseti32",
+  (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5), []>;
+
+
+//===----------------------------------------------------------------------===//
+// Special instructions.
+//===----------------------------------------------------------------------===//
+
+def SYNC32 : I_5_XZ_SYNC<1, 1, "sync32", 0, 0>;
+def SYNC32S : I_5_XZ_SYNC<1, 1, "sync32.s", 1, 0>;
+def SYNC32I : I_5_XZ_SYNC<1, 1, "sync32.i", 0, 1>;
+def SYNC32IS : I_5_XZ_SYNC<1, 1, "sync32.is", 1, 1>;
+
+
+  def RFI32 : I_5_XZ_PRIVI<0x11, 0x1, "rfi32">;
+
+def STOP32 : I_5_XZ_PRIVI<0x12, 0x1, "stop32">;
+def WAIT32 : I_5_XZ_PRIVI<0x13, 0x1, "wait32">;
+def DOZE32 : I_5_XZ_PRIVI<0x14, 0x1, "doze32">;
+
 // TODO: Special instructions.
-// TODO: Pseudo for assembly.
+// TODO: Pseudo for assembly.
 No newline at end of file

llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.h

 //===-- CSKYInstPrinter.h - Convert CSKY MCInst to asm syntax ---*- C++ -*----//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This class prints a CSKY MCInst to a .s file.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_CSKY_MCTARGETDESC_CSKYINSTPRINTER_H
 #define LLVM_LIB_TARGET_CSKY_MCTARGETDESC_CSKYINSTPRINTER_H
 
 #include "MCTargetDesc/CSKYMCTargetDesc.h"
 #include "llvm/MC/MCInstPrinter.h"
 
 namespace llvm {
 
 class CSKYInstPrinter : public MCInstPrinter {
 public:
   CSKYInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
                   const MCRegisterInfo &MRI)
public:
   std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
   void printInstruction(const MCInst *MI, uint64_t Address,
                         const MCSubtargetInfo &STI, raw_ostream &O);
   bool printAliasInstr(const MCInst *MI, uint64_t Address,
                        const MCSubtargetInfo &STI, raw_ostream &O);
   void printCustomAliasOperand(const MCInst *MI, uint64_t Address,
                                unsigned OpIdx, unsigned PrintMethodIdx,
                                const MCSubtargetInfo &STI, raw_ostream &O);
+  void printRegSeq(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
+                   raw_ostream &O);
 
   static const char *getRegisterName(unsigned RegNo);
   static const char *getRegisterName(unsigned RegNo, unsigned AltIdx);
 };
 
 } // namespace llvm
 
 #endif // LLVM_LIB_TARGET_CSKY_MCTARGETDESC_CSKYINSTPRINTER_H

llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.cpp

if (MO.isImm()) {
     O << formatImm(MO.getImm());
     return;
   }
 
   assert(MO.isExpr() && "Unknown operand kind in printOperand");
   MO.getExpr()->print(O, &MAI);
 }
 
+void CSKYInstPrinter::printRegSeq(const MCInst *MI, unsigned OpNo,
+                                  const MCSubtargetInfo &STI, raw_ostream &O) {
+  auto Ry = MI->getOperand(OpNo).getReg();
+  auto Rz = MI->getOperand(OpNo + 1).getImm();
+
+  printRegName(O, Ry);
+  O << "-";
+  printRegName(O, Rz);
+}
+
 const char *CSKYInstPrinter::getRegisterName(unsigned RegNo) {
   return getRegisterName(RegNo, ArchRegNames ? CSKY::NoRegAltName
                                              : CSKY::ABIRegAltName);
 }

llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.h

 //===-- CSKYMCCodeEmitter.cpp - CSKY Code Emitter interface ---------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the CSKYMCCodeEmitter class.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_CSKY_MCTARGETDESC_CSKYMCCODEEMITTER_H
 #define LLVM_LIB_TARGET_CSKY_MCTARGETDESC_CSKYMCCODEEMITTER_H
 
 #include "CSKYMCExpr.h"
 #include "MCTargetDesc/CSKYFixupKinds.h"
 #include "llvm/MC/MCCodeEmitter.h"
 #include "llvm/MC/MCContext.h"
 
 namespace llvm {
 
 class CSKYMCCodeEmitter : public MCCodeEmitter {
   MCContext &Ctx;
   const MCInstrInfo &MII;
public:
   unsigned getImmOpValue(const MCInst &MI, unsigned Idx,
                          SmallVectorImpl<MCFixup> &Fixups,
                          const MCSubtargetInfo &STI) const {
     const MCOperand &MO = MI.getOperand(Idx);
     assert(MO.isImm() && "Unexpected MO type.");
     return (MO.getImm() >> shift);
   }
 
+  unsigned getRegSeqImmOpValue(const MCInst &MI, unsigned Idx,
+                               SmallVectorImpl<MCFixup> &Fixups,
+                               const MCSubtargetInfo &STI) const;
+
   unsigned getOImmOpValue(const MCInst &MI, unsigned Idx,
                           SmallVectorImpl<MCFixup> &Fixups,
                           const MCSubtargetInfo &STI) const;
 
   unsigned getImmShiftOpValue(const MCInst &MI, unsigned Idx,
                               SmallVectorImpl<MCFixup> &Fixups,
                               const MCSubtargetInfo &STI) const {
     const MCOperand &MO = MI.getOperand(Idx);

llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.cpp

 unsigned CSKYMCCodeEmitter::getOImmOpValue(const MCInst &MI, unsigned Idx,
                                            SmallVectorImpl<MCFixup> &Fixups,
                                            const MCSubtargetInfo &STI) const {
   const MCOperand &MO = MI.getOperand(Idx);
   assert(MO.isImm() && "Unexpected MO type.");
   return MO.getImm() - 1;
 }
 
+unsigned
+CSKYMCCodeEmitter::getRegSeqImmOpValue(const MCInst &MI, unsigned Idx,
+                                       SmallVectorImpl<MCFixup> &Fixups,
+                                       const MCSubtargetInfo &STI) const {
+  assert(MI.getOperand(Idx).isReg() && "Unexpected MO type.");
+  assert(MI.getOperand(Idx + 1).isImm() && "Unexpected MO type.");
+
+  unsigned Ry = MI.getOperand(Idx).getReg();
+  unsigned Rz = MI.getOperand(Idx + 1).getImm();
+
+  unsigned Imm = Ctx.getRegisterInfo()->getEncodingValue(Rz) -
+                 Ctx.getRegisterInfo()->getEncodingValue(Ry);
+
+  return ((Ctx.getRegisterInfo()->getEncodingValue(Ry) << 5) | Imm);
+}
+
 void CSKYMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
                                           SmallVectorImpl<MCFixup> &Fixups,
                                           const MCSubtargetInfo &STI) const {
   const MCInstrDesc &Desc = MII.get(MI.getOpcode());
   unsigned Size = Desc.getSize();
   uint32_t Bin = getBinaryCodeForInstr(MI, Fixups, STI);
 
   uint16_t LO16 = static_cast<uint16_t>(Bin);

llvm/test/MC/CSKY/basic.s

-# RUN: llvm-mc %s -triple=csky -show-encoding | FileCheck -check-prefixes=CHECK-ASM %s
+# RUN: llvm-mc %s -triple=csky -show-encoding -csky-no-aliases | FileCheck -check-prefixes=CHECK-ASM %s
 
 # CHECK-ASM: addi32 a0, sp, 2
 # CHECK-ASM: encoding: [0x0e,0xe4,0x01,0x00]
 addi32 a0, sp, 2
 
 # CHECK-ASM: subi32 a0, sp, 2
 # CHECK-ASM: encoding: [0x0e,0xe4,0x01,0x10]
 subi32 a0, sp, 2

 # CHECK-ASM: ori32 a0, sp, 2
 # CHECK-ASM: encoding: [0x0e,0xec,0x02,0x00]
 ori32 a0, sp, 2
 
 # CHECK-ASM: rotli32 a0, sp, 2
 # CHECK-ASM: encoding: [0x4e,0xc4,0x00,0x49]
 rotli32 a0, sp, 2
 
+# CHECK-ASM: incf32 a0, sp, 2
+# CHECK-ASM: encoding: [0x0e,0xc4,0x22,0x0c]
+incf32 a0, sp, 2
+
+# CHECK-ASM: inct32 a0, sp, 2
+# CHECK-ASM: encoding: [0x0e,0xc4,0x42,0x0c]
+inct32 a0, sp, 2
+
+# CHECK-ASM: decf32 a0, sp, 2
+# CHECK-ASM: encoding: [0x0e,0xc4,0x82,0x0c]
+decf32 a0, sp, 2
+
+# CHECK-ASM: dect32 a0, sp, 2
+# CHECK-ASM: encoding: [0x0e,0xc4,0x02,0x0d]
+dect32 a0, sp, 2
+
+# CHECK-ASM: decgt32 a0, sp, 2
+# CHECK-ASM: encoding: [0x4e,0xc4,0x20,0x10]
+decgt32 a0, sp, 2
+
+# CHECK-ASM: declt32 a0, sp, 2
+# CHECK-ASM: encoding: [0x4e,0xc4,0x40,0x10]
+declt32 a0, sp, 2
+
+# CHECK-ASM: decne32 a0, sp, 2
+# CHECK-ASM: encoding: [0x4e,0xc4,0x80,0x10]
+decne32 a0, sp, 2
+
+# CHECK-ASM: btsti32 a0, 2
+# CHECK-ASM: encoding: [0x40,0xc4,0x80,0x28]
+btsti32 a0, 2
+
+# CHECK-ASM: bclri32 a0, sp, 2
+# CHECK-ASM: encoding: [0x4e,0xc4,0x20,0x28]
+bclri32 a0, sp, 2
+
+# CHECK-ASM: bseti32 a0, sp, 2
+# CHECK-ASM: encoding: [0x4e,0xc4,0x40,0x28]
+bseti32 a0, sp, 2
+
 # CHECK-ASM: cmpnei32 a0, 2
 # CHECK-ASM: encoding: [0x40,0xeb,0x02,0x00]
 cmpnei32 a0, 2
 
 # CHECK-ASM: cmphsi32 a0, 2
 # CHECK-ASM: encoding: [0x00,0xeb,0x01,0x00]
 cmphsi32 a0, 2
 

 # CHECK-ASM: nor32 a3, l0, l1
 # CHECK-ASM: encoding: [0xa4,0xc4,0x83,0x24]
 nor32 a3, l0, l1
 
 # CHECK-ASM: lsl32 a3, l0, l1
 # CHECK-ASM: encoding: [0xa4,0xc4,0x23,0x40]
 lsl32 a3, l0, l1
 
+# CHECK-ASM: rotl32 a3, l0, l1
+# CHECK-ASM: encoding: [0xa4,0xc4,0x03,0x41]
+rotl32 a3, l0, l1
+
 # CHECK-ASM: lsr32 a3, l0, l1
 # CHECK-ASM: encoding: [0xa4,0xc4,0x43,0x40]
 lsr32 a3, l0, l1
 
 # CHECK-ASM: asr32 a3, l0, l1
 # CHECK-ASM: encoding: [0xa4,0xc4,0x83,0x40]
 asr32 a3, l0, l1
 
+# CHECK-ASM: lslc32 a0, sp, 2
+# CHECK-ASM: encoding: [0x2e,0xc4,0x20,0x4c]
+lslc32 a0, sp, 2
+
+# CHECK-ASM: lsrc32 a0, sp, 2
+# CHECK-ASM: encoding: [0x2e,0xc4,0x40,0x4c]
+lsrc32 a0, sp, 2
+
+# CHECK-ASM: asrc32 a0, sp, 2
+# CHECK-ASM: encoding: [0x2e,0xc4,0x80,0x4c]
+asrc32 a0, sp, 2
+
+# CHECK-ASM: xsr32 a0, sp, 2
+# CHECK-ASM: encoding: [0x2e,0xc4,0x00,0x4d]
+xsr32 a0, sp, 2
+
 # CHECK-ASM: mult32 a3, l0, l1
 # CHECK-ASM: encoding: [0xa4,0xc4,0x23,0x84]
 mult32 a3, l0, l1
 
 # CHECK-ASM: divs32 a3, l0, l1
 # CHECK-ASM: encoding: [0xa4,0xc4,0x43,0x80]
 divs32 a3, l0, l1
 

 # CHECK-ASM: ld32.hs a0, (sp, 2)
 # CHECK-ASM: encoding: [0x0e,0xd8,0x01,0x50]
 ld32.hs a0, (sp, 2)
 
 # CHECK-ASM: ld32.w a0, (sp, 4)
 # CHECK-ASM: encoding: [0x0e,0xd8,0x01,0x20]
 ld32.w a0, (sp, 4)
 
+# CHECK-ASM: ldex32.w a0, (sp, 4)
+# CHECK-ASM: encoding: [0x0e,0xd8,0x01,0x70]
+ldex32.w a0, (sp, 4)
+
 # CHECK-ASM: ldr32.b a0, (sp, l1 << 2)
 # CHECK-ASM: encoding: [0xae,0xd0,0x80,0x00]
 ldr32.b a0, (sp, l1 << 2)
 
 # CHECK-ASM: ldr32.bs a0, (sp, l1 << 2)
 # CHECK-ASM: encoding: [0xae,0xd0,0x80,0x10]
 ldr32.bs a0, (sp, l1 << 2)
 

 # CHECK-ASM: st32.h a0, (sp, 2)
 # CHECK-ASM: encoding: [0x0e,0xdc,0x01,0x10]
 st32.h a0, (sp, 2)
 
 # CHECK-ASM: st32.w a0, (sp, 4)
 # CHECK-ASM: encoding: [0x0e,0xdc,0x01,0x20]
 st32.w a0, (sp, 4)
 
+# CHECK-ASM: stex32.w a0, (sp, 4)
+# CHECK-ASM: encoding: [0x0e,0xdc,0x01,0x70]
+stex32.w a0, (sp, 4)
+
 # CHECK-ASM: str32.b a0, (sp, l1 << 2)
 # CHECK-ASM: encoding: [0xae,0xd4,0x80,0x00]
 str32.b a0, (sp, l1 << 2)
 
 # CHECK-ASM: str32.h a0, (sp, l1 << 3)
 # CHECK-ASM: encoding: [0xae,0xd4,0x00,0x05]
 str32.h a0, (sp, l1 << 3)
 

 # CHECK-ASM: movt32 a3, l0
 # CHECK-ASM: encoding: [0x64,0xc4,0x40,0x0c]
 movt32 a3, l0
 
 # CHECK-ASM: movf32 a3, l0
 # CHECK-ASM: encoding: [0x64,0xc4,0x20,0x0c]
 movf32 a3, l0
 
+# CHECK-ASM: brev32 a3, l0
+# CHECK-ASM: encoding: [0x04,0xc4,0x03,0x62]
+brev32 a3, l0
+
+# CHECK-ASM: abs32 a3, l0
+# CHECK-ASM: encoding: [0x04,0xc4,0x03,0x02]
+abs32 a3, l0
+
+# CHECK-ASM: bgenr32 a3, l0
+# CHECK-ASM: encoding: [0x04,0xc4,0x43,0x50]
+bgenr32 a3, l0
+
+# CHECK-ASM: revb32 a3, l0
+# CHECK-ASM: encoding: [0x04,0xc4,0x83,0x60]
+revb32 a3, l0
+
+# CHECK-ASM: revh32 a3, l0
+# CHECK-ASM: encoding: [0x04,0xc4,0x03,0x61]
+revh32 a3, l0
+
+# CHECK-ASM: ff0.32 a3, l0
+# CHECK-ASM: encoding: [0x04,0xc4,0x23,0x7c]
+ff0.32 a3, l0
+
+# CHECK-ASM: ff1.32 a3, l0
+# CHECK-ASM: encoding: [0x04,0xc4,0x43,0x7c]
+ff1.32 a3, l0
+
+# CHECK-ASM: xtrb0.32 a3, l0
+# CHECK-ASM: encoding: [0x04,0xc4,0x23,0x70]
+xtrb0.32 a3, l0
+
+# CHECK-ASM: xtrb1.32 a3, l0
+# CHECK-ASM: encoding: [0x04,0xc4,0x43,0x70]
+xtrb1.32 a3, l0
+
+# CHECK-ASM: xtrb2.32 a3, l0
+# CHECK-ASM: encoding: [0x04,0xc4,0x83,0x70]
+xtrb2.32 a3, l0
+
+# CHECK-ASM: xtrb3.32 a3, l0
+# CHECK-ASM: encoding: [0x04,0xc4,0x03,0x71]
+xtrb3.32 a3, l0
+
 # CHECK-ASM: mvc32 a3
 # CHECK-ASM: encoding: [0x00,0xc4,0x03,0x05]
 mvc32 a3
 
 # CHECK-ASM: mvcv32 a3
 # CHECK-ASM: encoding: [0x00,0xc4,0x03,0x06]
 mvcv32 a3
 
 # CHECK-ASM: cmpne32 a3, l0
 # CHECK-ASM: encoding: [0x83,0xc4,0x80,0x04]
 cmpne32 a3, l0
 
 # CHECK-ASM: cmphs32 a3, l0
 # CHECK-ASM: encoding: [0x83,0xc4,0x20,0x04]
 cmphs32 a3, l0
 
 # CHECK-ASM: cmplt32 a3, l0
 # CHECK-ASM: encoding: [0x83,0xc4,0x40,0x04]
 cmplt32 a3, l0
 
 # CHECK-ASM: zext32 a3, l0, 7, 0
 # CHECK-ASM: encoding: [0x04,0xc4,0xe3,0x54]
 zext32 a3, l0, 7, 0
 
+# CHECK-ASM: zextb32 a3, l0
+# CHECK-ASM: encoding: [0x04,0xc4,0xe3,0x54]
+zextb32 a3, l0
+
+# CHECK-ASM: zexth32 a3, l0
+# CHECK-ASM: encoding: [0x04,0xc4,0xe3,0x55]
+zexth32 a3, l0
+
 # CHECK-ASM: sext32 a3, l0, 7, 0
 # CHECK-ASM: encoding: [0x04,0xc4,0xe3,0x58]
 sext32 a3, l0, 7, 0
 
+# CHECK-ASM: sextb32 a3, l0
+# CHECK-ASM: encoding: [0x04,0xc4,0xe3,0x58]
+sextb32 a3, l0
+
+# CHECK-ASM: sexth32 a3, l0
+# CHECK-ASM: encoding: [0x04,0xc4,0xe3,0x59]
+sexth32 a3, l0
+
+# CHECK-ASM: ldm32 l1-l3, (a0)
+# CHECK-ASM: encoding: [0xa0,0xd0,0x22,0x1c]
+ldm32 r5-r7, (a0)
+
+# CHECK-ASM: stm32 l1-l3, (a0)
+# CHECK-ASM: encoding: [0xa0,0xd4,0x22,0x1c]
+stm32 r5-r7, (a0)
+
+# CHECK-ASM: setc32
+# CHECK-ASM: encoding: [0x00,0xc4,0x20,0x04]
+setc32
+
+# CHECK-ASM: clrc32
+# CHECK-ASM: encoding: [0x00,0xc4,0x80,0x04]
+clrc32
+
+# CHECK-ASM: tst32 a3, l0
+# CHECK-ASM: encoding: [0x83,0xc4,0x80,0x20]
+tst32 a3, l0
+
+# CHECK-ASM: tstnbz32 a3
+# CHECK-ASM: encoding: [0x03,0xc4,0x00,0x21]
+tstnbz32 a3
+
+# CHECK-ASM: clrf32 a3
+# CHECK-ASM: encoding: [0x60,0xc4,0x20,0x2c]
+clrf32 a3
+
+# CHECK-ASM: clrt32 a3
+# CHECK-ASM: encoding: [0x60,0xc4,0x40,0x2c]
+clrt32 a3
+
+# CHECK-ASM: bar.brwarw
+# CHECK-ASM: encoding: [0x00,0xc0,0x2f,0x84]
+bar.brwarw
+
+# CHECK-ASM: bar.brwarws
+# CHECK-ASM: encoding: [0x00,0xc2,0x2f,0x84]
+bar.brwarws
+
+# CHECK-ASM: bar.brarw
+# CHECK-ASM: encoding: [0x00,0xc0,0x27,0x84]
+bar.brarw
+
+# CHECK-ASM: bar.brarws
+# CHECK-ASM: encoding: [0x00,0xc2,0x27,0x84]
+bar.brarws
+
+# CHECK-ASM: bar.brwaw
+# CHECK-ASM: encoding: [0x00,0xc0,0x2e,0x84]
+bar.brwaw
+
+# CHECK-ASM: bar.brwaws
+# CHECK-ASM: encoding: [0x00,0xc2,0x2e,0x84]
+bar.brwaws
+
+# CHECK-ASM: bar.brar
+# CHECK-ASM: encoding: [0x00,0xc0,0x25,0x84]
+bar.brar
+
+# CHECK-ASM: bar.brars
+# CHECK-ASM: encoding: [0x00,0xc2,0x25,0x84]
+bar.brars
+
+# CHECK-ASM: bar.bwaw
+# CHECK-ASM: encoding: [0x00,0xc0,0x2a,0x84]
+bar.bwaw
+
+# CHECK-ASM: bar.bwaws
+# CHECK-ASM: encoding: [0x00,0xc2,0x2a,0x84]
+bar.bwaws
+
+# CHECK-ASM: sync32
+# CHECK-ASM: encoding: [0x00,0xc0,0x20,0x04]
+sync32
+
+# CHECK-ASM: sync32.s
+# CHECK-ASM: encoding: [0x00,0xc2,0x20,0x04]
+sync32.s
+
+# CHECK-ASM: sync32.i
+# CHECK-ASM: encoding: [0x20,0xc0,0x20,0x04]
+sync32.i
+
+# CHECK-ASM: sync32.is
+# CHECK-ASM: encoding: [0x20,0xc2,0x20,0x04]
+sync32.is
+
+# CHECK-ASM: rfi32
+# CHECK-ASM: encoding: [0x00,0xc0,0x20,0x44]
+rfi32
+
+# CHECK-ASM: stop32
+# CHECK-ASM: encoding: [0x00,0xc0,0x20,0x48]
+stop32
+
+# CHECK-ASM: wait32
+# CHECK-ASM: encoding: [0x00,0xc0,0x20,0x4c]
+wait32
+
+# CHECK-ASM: doze32
+# CHECK-ASM: encoding: [0x00,0xc0,0x20,0x50]
+doze32
+
 # CHECK-ASM: br32 .L.test
 # CHECK-ASM: encoding: [A,0xe8'A',A,A]
 # CHECK-ASM: fixup A - offset: 0, value: .L.test, kind: fixup_csky_pcrel_imm16_scale2
 .L.test:
 br32 .L.test
 
 # CHECK-ASM: bt32 .L.test2
 # CHECK-ASM: encoding: [0x60'A',0xe8'A',A,A]

 # CHECK-ASM: fixup A - offset: 0, value: .L.test12, kind: fixup_csky_pcrel_uimm16_scale4
 .L.test12:
 jsri32 [.L.test12]
 
 # CHECK-ASM: rts32
 # CHECK-ASM: encoding: [0xcf,0xe8,0x00,0x00]
 rts32
 
+# CHECK-ASM: rte32
+# CHECK-ASM: encoding: [0x00,0xc0,0x20,0x40]
+rte32
+
 # CHECK-ASM: grs32 a0, .L.test13
 # CHECK-ASM: encoding: [0x0c'A',0xcc'A',A,A]
 # CHECK-ASM: fixup A - offset: 0, value: .L.test13, kind: fixup_csky_pcrel_imm18_scale2
 .L.test13:
 grs32 a0, .L.test13
 
 # CHECK-ASM: lrw32 a0, .L.test14
 # CHECK-ASM: encoding: [0x80'A',0xea'A',A,A]
 # CHECK-ASM: fixup A - offset: 0, value: .L.test14, kind: fixup_csky_pcrel_uimm16_scale4
 .L.test14:
 lrw32 a0, [.L.test14]
 
 # RUN: not llvm-mc -triple csky --defsym=ERR=1 < %s 2>&1 | FileCheck %s
 
 .ifdef ERR
 
 # uimm12/oimm12/nimm12
 addi32 a0, a0, 0 # CHECK: :[[#@LINE]]:16: error: immediate must be an integer in the range [1, 4096]
 subi32 a0, a0, 4097 # CHECK: :[[#@LINE]]:16: error: immediate must be an integer in the range [1, 4096]
 andi32 a0, a0, 4096 # CHECK: :[[#@LINE]]:16: error: immediate must be an integer in the range [0, 4095]
 andni32 a0, a0, 4096 # CHECK: :[[#@LINE]]:17: error: immediate must be an integer in the range [0, 4095]
 xori32 a0, a0, 4096 # CHECK: :[[#@LINE]]:16: error: immediate must be an integer in the range [0, 4095]
 
+# oimm5
+lslc32 a0, a0, 33 # CHECK: :[[#@LINE]]:16: error: immediate must be an integer in the range [1, 32]
+lsrc32 a0, a0, 33 # CHECK: :[[#@LINE]]:16: error: immediate must be an integer in the range [1, 32]
+asrc32 a0, a0, 33 # CHECK: :[[#@LINE]]:16: error: immediate must be an integer in the range [1, 32]
+xsr32 a0, a0, 33 # CHECK: :[[#@LINE]]:15: error: immediate must be an integer in the range [1, 32]
 
 # uimm5
 lsli32 a0, a0, 32 # CHECK: :[[#@LINE]]:16: error: immediate must be an integer in the range [0, 31]
 lsri32 a0, a0, 32 # CHECK: :[[#@LINE]]:16: error: immediate must be an integer in the range [0, 31]
 asri32 a0, a0, 32 # CHECK: :[[#@LINE]]:16: error: immediate must be an integer in the range [0, 31]
 rotli32 a0, a0, 32 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 31]
+incf32 a0, a0, 32 # CHECK: :[[#@LINE]]:16: error: immediate must be an integer in the range [0, 31]
+inct32 a0, a0, 32 # CHECK: :[[#@LINE]]:16: error: immediate must be an integer in the range [0, 31]
+decf32 a0, a0, 32 # CHECK: :[[#@LINE]]:16: error: immediate must be an integer in the range [0, 31]
+dect32 a0, a0, 32 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31]
+decgt32 a0, a0, 32 # CHECK: :[[#@LINE]]:17: error: immediate must be an integer in the range [0, 31]
+declt32 a0, a0, 32 # CHECK: :[[#@LINE]]:17: error: immediate must be an integer in the range [0, 31]
+decne32 a0, a0, 32 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 31]
+btsti32 a0, 32 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 31]
+bclri32 a0, a0, 32 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 31]
+bseti32 a0, a0, 32 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 31]
 
 # uimm12(shift0)/uimm12_1/uimm12_2
 ld32.b a0, (a0, -1)  # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 4095]
 ld32.h a0, (a0, 4095)  # CHECK: :[[@LINE]]:17: error: immediate must be a multiple of 2 bytes in the range [0, 4094]
 ld32.h a0, (a0, 4093)  # CHECK: :[[@LINE]]:17: error: immediate must be a multiple of 2 bytes in the range [0, 4094]
 ld32.w a0, (a0, 4093)  # CHECK: :[[@LINE]]:17: error: immediate must be a multiple of 4 bytes in the range [0, 4092]
 ld32.w a0, (a0, 2)  # CHECK: :[[@LINE]]:17: error: immediate must be a multiple of 4 bytes in the range [0, 4092]
+ldex32.w a0, (a0, 2)  # CHECK: :[[@LINE]]:19: error: immediate must be a multiple of 4 bytes in the range [0, 4092]
+
 ldr32.b a0, (a0, a1 << 4) # CHECK: :[[@LINE]]:24: error: immediate must be an integer in the range [0, 3]
 ldr32.bs a0, (a0, a1 << 4) # CHECK: :[[@LINE]]:25: error: immediate must be an integer in the range [0, 3]
 ldr32.h a0, (a0, a1 << -1) # CHECK: :[[@LINE]]:24: error: immediate must be an integer in the range [0, 3]
 ldr32.hs a0, (a0, a1 << 4) # CHECK: :[[@LINE]]:25: error: immediate must be an integer in the range [0, 3]
 ldr32.w a0, (a0, a1 << 4) # CHECK: :[[@LINE]]:24: error: immediate must be an integer in the range [0, 3]
 
 st32.b a0, (a0, -1)  # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 4095]
 st32.h a0, (a0, 4095)  # CHECK: :[[@LINE]]:17: error: immediate must be a multiple of 2 bytes in the range [0, 4094]
 st32.h a0, (a0, 4093)  # CHECK: :[[@LINE]]:17: error: immediate must be a multiple of 2 bytes in the range [0, 4094]
 st32.w a0, (a0, 4093)  # CHECK: :[[@LINE]]:17: error: immediate must be a multiple of 4 bytes in the range [0, 4092]
 st32.w a0, (a0, 2)  # CHECK: :[[@LINE]]:17: error: immediate must be a multiple of 4 bytes in the range [0, 4092]
+stex32.w a0, (a0, 2)  # CHECK: :[[@LINE]]:19: error: immediate must be a multiple of 4 bytes in the range [0, 4092]
 
 str32.b a0, (a0, a1 << 4) # CHECK: :[[@LINE]]:24: error: immediate must be an integer in the range [0, 3]
 str32.h a0, (a0, a1 << -1) # CHECK: :[[@LINE]]:24: error: immediate must be an integer in the range [0, 3]
 str32.w a0, (a0, a1 << 4) # CHECK: :[[@LINE]]:24: error: immediate must be an integer in the range [0, 3]
 
 # uimm16/oimm16
 ori32 a0, a0, 0x10000 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 65535]
 cmpnei32 a0, 0x10000 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 65535]

 xori32 a0, a1 # CHECK: :[[#@LINE]]:1: error: too few operands for instruction
 xor32 a0, a2 # CHECK: :[[#@LINE]]:1: error: too few operands for instruction
 
 # Need label
 br32 0x100 # CHECK: :[[@LINE]]:6: error: operand must be a symbol name
 jmpi32 0x100 # CHECK: :[[@LINE]]:8: error: operand must be a constpool symbol name
 bsr32 0x100 # CHECK: :[[@LINE]]:7: error: operand must be a symbol name
 
+# Reg Sequence
+ldm32 r2-r0, (a0) # CHECK: :[[@LINE]]:7: error: operand must be a register sequence like (rN-rM, N<=M)
+ldm32 r0-r34, (a0) # CHECK: :[[@LINE]]:10: error: invalid register
+
 .endif