[AMDGPU] Allow multiple uses of the same literal

[foad]

Summary

In GFX10 VOP3 can have a literal, which opens up the possibility of two
operands using the same literal value, which is allowed and only counts
as one use of the constant bus.

AMDGPUAsmParser::validateConstantBusLimitations already knew about this
but SIInstrInfo::verifyInstruction did not.

[arsenm]

llvm/test/CodeGen/AMDGPU/verify-duplicate-literal.mir

14

Should probably add a few more tests for other instruction types (in particular ones without an implicit vcc use and would be a more sensible place for this to happen)

[rampitec]

I wonder if a 16 bit literal + non-default opsel and the same literal with different opsel, or different literal which turns into the same literal after opsel is applied constitutes a same value? I.e. is it checked on decoding or after?

[foad]

Add a test with fma.

[foad]

In D100770#2698974, @rampitec wrote:

I wonder if a 16 bit literal + non-default opsel and the same literal with different opsel, or different literal which turns into the same literal after opsel is applied constitutes a same value? I.e. is it checked on decoding or after?

AMDGPUAsmParser::validateConstantBusLimitations says that if different operands use the same literal with different sizes, then that counts as two scalar values. So I guess we may need to refine this code a bit, but I would prefer to leave that for later patches.

llvm/test/CodeGen/AMDGPU/verify-duplicate-literal.mir

14

Added an fma test which is slightly more realistic.

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
   if (Desc.getOpcode() != AMDGPU::V_WRITELANE_B32
       && (isVOP1(MI) || isVOP2(MI) || isVOP3(MI) || isVOPC(MI) || isSDWA(MI))) {
     // Only look at the true operands. Only a real operand can use the constant
     // bus, and we don't want to check pseudo-operands like the source modifier
     // flags.
     const int OpIndices[] = { Src0Idx, Src1Idx, Src2Idx };
 
     unsigned ConstantBusCount = 0;
-    unsigned LiteralCount = 0;
+    bool UsesLiteral = false;
+    const MachineOperand *LiteralVal = nullptr;
 
     if (AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::imm) != -1)
       ++ConstantBusCount;
 
     SmallVector<Register, 2> SGPRsUsed;
     Register SGPRUsed;
 
     for (int OpIdx : OpIndices) {
       if (OpIdx == -1)
         break;
       const MachineOperand &MO = MI.getOperand(OpIdx);
       if (usesConstantBus(MRI, MO, MI.getDesc().OpInfo[OpIdx])) {
         if (MO.isReg()) {
           SGPRUsed = MO.getReg();
           if (llvm::all_of(SGPRsUsed, [SGPRUsed](unsigned SGPR) {
                 return SGPRUsed != SGPR;
               })) {
             ++ConstantBusCount;
             SGPRsUsed.push_back(SGPRUsed);
           }
         } else {
+          if (!UsesLiteral) {
             ++ConstantBusCount;
-          ++LiteralCount;
+            UsesLiteral = true;
+            LiteralVal = &MO;
+          } else if (!MO.isIdenticalTo(*LiteralVal)) {
+            assert(isVOP3(MI));
+            ErrInfo = "VOP3 instruction uses more than one literal";
+            return false;
+          }
         }
       }
     }
 
     SGPRUsed = findImplicitSGPRRead(MI);
     if (SGPRUsed != AMDGPU::NoRegister) {
       // Implicit uses may safely overlap true overands
       if (llvm::all_of(SGPRsUsed, [this, SGPRUsed](unsigned SGPR) {
             return !RI.regsOverlap(SGPRUsed, SGPR);
           })) {
         ++ConstantBusCount;
         SGPRsUsed.push_back(SGPRUsed);
       }
     }
 
     // v_writelane_b32 is an exception from constant bus restriction:
     // vsrc0 can be sgpr, const or m0 and lane select sgpr, m0 or inline-const
     if (ConstantBusCount > ST.getConstantBusLimit(Opcode) &&
         Opcode != AMDGPU::V_WRITELANE_B32) {
       ErrInfo = "VOP* instruction violates constant bus restriction";
       return false;
     }
 
-    if (isVOP3(MI) && LiteralCount) {
-      if (!ST.hasVOP3Literal()) {
-        ErrInfo = "VOP3 instruction uses literal";
-        return false;
-      }
-      if (LiteralCount > 1) {
-        ErrInfo = "VOP3 instruction uses more than one literal";
-        return false;
-      }
-    }
+    if (isVOP3(MI) && UsesLiteral && !ST.hasVOP3Literal()) {
   }
 
   // Special case for writelane - this can break the multiple constant bus rule,
   // but still can't use more than one SGPR register
   if (Desc.getOpcode() == AMDGPU::V_WRITELANE_B32) {
     unsigned SGPRCount = 0;
     Register SGPRUsed = AMDGPU::NoRegister;
 

llvm/test/CodeGen/AMDGPU/verify-duplicate-literal.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass machineverifier -o - %s | FileCheck %s
+
+# Two uses of the same literal only count as one use of the constant bus.
+---
+name: use_duplicate_literal
+tracksRegLiveness: true
+body:            |
+  bb.0:
+    liveins: $vcc_lo
+    ; CHECK-LABEL: name: use_duplicate_literal
+    ; CHECK: liveins: $vcc_lo
+    ; CHECK: $vgpr0 = V_CNDMASK_B32_e64 0, 1234567, 0, 1234567, killed $vcc_lo, implicit $exec
+    $vgpr0 = V_CNDMASK_B32_e64 0, 1234567, 0, 1234567, killed $vcc_lo, implicit $exec
+...