[AMDGPU] NFC, Comment in disassembler for dpp8

[Joe_Nash]

Summary

Gives reasoning for convertDPP8.
Also corrects typo in Operand type comment.

llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table,
   if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) {
     MI = TmpInst;
     return MCDisassembler::Success;
   }
   Bytes = SavedBytes;
   return MCDisassembler::Fail;
 }
 
+// The disassembler is greedy, so we need to check FI operand value to
+// not parse a dpp if the correct literal is not set. For dpp16 the
+// autogenerated decoder checks the dpp literal
 static bool isValidDPP8(const MCInst &MI) {
   using namespace llvm::AMDGPU::DPP;
   int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi);
   assert(FiIdx != -1);
   if ((unsigned)FiIdx >= MI.getNumOperands())
     return false;
   unsigned Fi = MI.getOperand(FiIdx).getImm();
   return Fi == DPP8_FI_0 || Fi == DPP8_FI_1;
if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
     } else {
       // VOP1/2 - insert omod if present in instruction
       insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod);
     }
   }
   return MCDisassembler::Success;
 }
 
+// We must check FI == literal to reject not genuine dpp8 insts, and we must
+// first add optional MI operands to check FI
 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const {
   unsigned Opc = MI.getOpcode();
   unsigned DescNumOps = MCII->get(Opc).getNumOperands();
 
   // Insert dummy unused src modifiers.
   if (MI.getNumOperands() < DescNumOps &&
       AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1)
     insertNamedMCOperand(MI, MCOperand::createImm(0),

llvm/lib/Target/AMDGPU/SIRegisterInfo.td

 
 defm VSrc : RegImmOperand<"VS", "VSrc">;
 
 def VSrc_128 : RegisterOperand<VReg_128> {
   let DecoderMethod = "DecodeVS_128RegisterClass";
 }
 
 //===----------------------------------------------------------------------===//
-//  VSrc_* Operands with an VGPR
+//  VRegSrc_* Operands with a VGPR
 //===----------------------------------------------------------------------===//
 
 // This is for operands with the enum(9), VSrc encoding restriction,
 // but only allows VGPRs.
 def VRegSrc_32 : RegisterOperand<VGPR_32> {
   //let ParserMatchClass = RegImmMatcher<"VRegSrc32">;
   let DecoderMethod = "DecodeVS_32RegisterClass";
 }