[AMDGPU] IsFlatScratch/Global -> FlatScratch/Global

[sebastian-ne]

Summary

Remove 'Is' from IsFlatScratch/Global. NFC

Should I do the same for is_flat_scratch/global?

[foad]

Should I do the same for is_flat_scratch/global?

I don't think it matters, since it is only used in FLATInstructions.td.

[foad]

Seems fine to me. There is not much consistency in the naming of the SIInstrFlags flags.

[foad]

... but adding @rampitec for awareness.

[rampitec]

LGTM

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

bool AMDGPUAsmParser::validateFlatOffset(const MCInst &Inst,
   if (!hasFlatOffsets() && Op.getImm() != 0) {
     Error(getFlatOffsetLoc(Operands),
           "flat offset modifier is not supported on this GPU");
     return false;
   }
 
   // For FLAT segment the offset must be positive;
   // MSB is ignored and forced to zero.
-  if (TSFlags & (SIInstrFlags::IsFlatGlobal | SIInstrFlags::IsFlatScratch)) {
+  if (TSFlags & (SIInstrFlags::FlatGlobal | SIInstrFlags::FlatScratch)) {
     unsigned OffsetSize = AMDGPU::getNumFlatOffsetBits(getSTI(), true);
     if (!isIntN(OffsetSize, Op.getImm())) {
       Error(getFlatOffsetLoc(Operands),
             Twine("expected a ") + Twine(OffsetSize) + "-bit signed offset");
       return false;
     }
   } else {
     unsigned OffsetSize = AMDGPU::getNumFlatOffsetBits(getSTI(), false);

llvm/lib/Target/AMDGPU/FLATInstructions.td

class FLAT_Pseudo<string opName, dag outs, dag ins,
   let Uses = !if(is_flat_global, [EXEC], [EXEC, FLAT_SCR]);
 
   // Internally, FLAT instruction are executed as both an LDS and a
   // Buffer instruction; so, they increment both VM_CNT and LGKM_CNT
   // and are not considered done until both have been decremented.
   let VM_CNT = 1;
   let LGKM_CNT = !not(!or(is_flat_global, is_flat_scratch));
 
-  let IsFlatGlobal = is_flat_global;
+  let FlatGlobal = is_flat_global;
 
-  let IsFlatScratch = is_flat_scratch;
+  let FlatScratch = is_flat_scratch;
 }
 
 class FLAT_Real <bits<7> op, FLAT_Pseudo ps> :
   InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
   Enc64 {
 
   let isPseudo = 0;
   let isCodeGenOnly = 0;

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
                                         const MCSubtargetInfo &STI,
                                         raw_ostream &O) {
   uint16_t Imm = MI->getOperand(OpNo).getImm();
   if (Imm != 0) {
     O << " offset:";
 
     const MCInstrDesc &Desc = MII.get(MI->getOpcode());
     bool IsFlatSeg = !(Desc.TSFlags &
-        (SIInstrFlags::IsFlatGlobal | SIInstrFlags::IsFlatScratch));
+                       (SIInstrFlags::FlatGlobal | SIInstrFlags::FlatScratch));
 
     if (IsFlatSeg) { // Unsigned offset
       printU16ImmDecOperand(MI, OpNo, O);
     } else {         // Signed offset
       if (AMDGPU::isGFX10Plus(STI)) {
         O << formatDec(SignExtend32<12>(MI->getOperand(OpNo).getImm()));
       } else {
         O << formatDec(SignExtend32<13>(MI->getOperand(OpNo).getImm()));

llvm/lib/Target/AMDGPU/SIDefines.h

enum : uint64_t {
 
   // Is a packed VOP3P instruction.
   IsPacked = UINT64_C(1) << 49,
 
   // Is a D16 buffer instruction.
   D16Buf = UINT64_C(1) << 50,
 
   // FLAT instruction accesses FLAT_GLBL segment.
-  IsFlatGlobal = UINT64_C(1) << 51,
+  FlatGlobal = UINT64_C(1) << 51,
 
   // Uses floating point double precision rounding mode
   FPDPRounding = UINT64_C(1) << 52,
 
   // Instruction is FP atomic.
   FPAtomic = UINT64_C(1) << 53,
 
   // Is a MFMA instruction.
   IsMAI = UINT64_C(1) << 54,
 
   // Is a DOT instruction.
   IsDOT = UINT64_C(1) << 55,
 
   // FLAT instruction accesses FLAT_SCRATCH segment.
-  IsFlatScratch = UINT64_C(1) << 56,
+  FlatScratch = UINT64_C(1) << 56,
 
   // Atomic without return.
   IsAtomicNoRet = UINT64_C(1) << 57,
 
   // Atomic with return.
   IsAtomicRet = UINT64_C(1) << 58
 };
 

llvm/lib/Target/AMDGPU/SIInstrFormats.td

class InstSI <dag outs, dag ins, string asm = "",
   // This bit indicates that this is a packed VOP3P instruction
   field bit IsPacked = 0;
 
   // This bit indicates that this is a D16 buffer instruction.
   field bit D16Buf = 0;
 
   // This field indicates that FLAT instruction accesses FLAT_GLBL segment.
   // Must be 0 for non-FLAT instructions.
-  field bit IsFlatGlobal = 0;
+  field bit FlatGlobal = 0;
 
   // Reads the mode register, usually for FP environment.
   field bit ReadsModeReg = 0;
 
   // This bit indicates that this uses the floating point double precision
   // rounding mode flags
   field bit FPDPRounding = 0;
 
   // Instruction is FP atomic.
   field bit FPAtomic = 0;
 
   // This bit indicates that this is one of MFMA instructions.
   field bit IsMAI = 0;
 
   // This bit indicates that this is one of DOT instructions.
   field bit IsDOT = 0;
 
   // This field indicates that FLAT instruction accesses FLAT_SCRATCH segment.
   // Must be 0 for non-FLAT instructions.
-  field bit IsFlatScratch = 0;
+  field bit FlatScratch = 0;
 
   // Atomic without a return.
   field bit IsAtomicNoRet = 0;
 
   // Atomic with return.
   field bit IsAtomicRet = 0;
 
   // These need to be kept in sync with the enum in SIInstrFlags.
class InstSI <dag outs, dag ins, string asm = "",
   let TSFlags{46} = IntClamp;
   let TSFlags{47} = ClampLo;
   let TSFlags{48} = ClampHi;
 
   let TSFlags{49} = IsPacked;
 
   let TSFlags{50} = D16Buf;
 
-  let TSFlags{51} = IsFlatGlobal;
+  let TSFlags{51} = FlatGlobal;
 
   let TSFlags{52} = FPDPRounding;
 
   let TSFlags{53} = FPAtomic;
 
   let TSFlags{54} = IsMAI;
 
   let TSFlags{55} = IsDOT;
 
-  let TSFlags{56} = IsFlatScratch;
+  let TSFlags{56} = FlatScratch;
 
   let TSFlags{57} = IsAtomicNoRet;
 
   let TSFlags{58} = IsAtomicRet;
 
   let SchedRW = [Write32Bit];
 
   let AsmVariantName = AMDGPUAsmVariants.Default;

llvm/lib/Target/AMDGPU/SIInstrInfo.h

public:
   static bool isFLAT(const MachineInstr &MI) {
     return MI.getDesc().TSFlags & SIInstrFlags::FLAT;
   }
 
   // Is a FLAT encoded instruction which accesses a specific segment,
   // i.e. global_* or scratch_*.
   static bool isSegmentSpecificFLAT(const MachineInstr &MI) {
     auto Flags = MI.getDesc().TSFlags;
-    return Flags & (SIInstrFlags::IsFlatGlobal | SIInstrFlags::IsFlatScratch);
+    return Flags & (SIInstrFlags::FlatGlobal | SIInstrFlags::FlatScratch);
   }
 
   bool isSegmentSpecificFLAT(uint16_t Opcode) const {
     auto Flags = get(Opcode).TSFlags;
-    return Flags & (SIInstrFlags::IsFlatGlobal | SIInstrFlags::IsFlatScratch);
+    return Flags & (SIInstrFlags::FlatGlobal | SIInstrFlags::FlatScratch);
   }
 
   static bool isFLATGlobal(const MachineInstr &MI) {
-    return MI.getDesc().TSFlags & SIInstrFlags::IsFlatGlobal;
+    return MI.getDesc().TSFlags & SIInstrFlags::FlatGlobal;
   }
 
   bool isFLATGlobal(uint16_t Opcode) const {
-    return get(Opcode).TSFlags & SIInstrFlags::IsFlatGlobal;
+    return get(Opcode).TSFlags & SIInstrFlags::FlatGlobal;
   }
 
   static bool isFLATScratch(const MachineInstr &MI) {
-    return MI.getDesc().TSFlags & SIInstrFlags::IsFlatScratch;
+    return MI.getDesc().TSFlags & SIInstrFlags::FlatScratch;
   }
 
   bool isFLATScratch(uint16_t Opcode) const {
-    return get(Opcode).TSFlags & SIInstrFlags::IsFlatScratch;
+    return get(Opcode).TSFlags & SIInstrFlags::FlatScratch;
   }
 
   // Any FLAT encoded instruction, including global_* and scratch_*.
   bool isFLAT(uint16_t Opcode) const {
     return get(Opcode).TSFlags & SIInstrFlags::FLAT;
   }
 
   static bool isEXP(const MachineInstr &MI) {