[Clang][RISCV] Implement vlseg builtins.

[HsiangKai]

Summary

Implement vlseg builtins.

[rogfer01]

This is just a suggestion, feel free to ignore: a sequence of Ts was easy to parse for the prototype but may be want to consider something like T3v rather than TTTv. I think it would simplify the TString tblgen class and those std::string(N, 'T').

clang/utils/TableGen/RISCVVEmitter.cpp

594

Was this meant to be static here?

714

We say Tv is invalid, looks like we should check this here and PrintFatalError?

[khchen]

clang/utils/TableGen/RISCVVEmitter.cpp

594

Maybe we can create a new complex type transformer (Tuple:Value), so (Tuple:3) means TTTv. It can avoid to use static here. You could ref https://github.com/llvm/llvm-project/blob/main/clang/utils/TableGen/RISCVVEmitter.cpp#L638

[HsiangKai]

Address comments.

clang/include/clang/Basic/riscv_vector.td

 //      no-op if the vector was already LMUL=1
 //   (Log2EEW:Value): Log2EEW value could be 3/4/5/6 (8/16/32/64), given a
 //      vector type (SEW and LMUL) and EEW (8/16/32/64), computes its
 //      equivalent integer vector type with EEW and corresponding ELMUL (elmul =
 //      (eew/sew) * lmul). For example, vector type is __rvv_float16m4
 //      (SEW=16, LMUL=4) and Log2EEW is 3 (EEW=8), and then equivalent vector
 //      type is __rvv_uint8m2_t (elmul=(8/16)*4 = 2). Ignore to define a new
 //      builtins if its equivalent type has illegal lmul.
+//   (Tuple:Value): given a vector type, compute a tuple type with a single
+//      element of the vector type. A tuple of a single element (e.g (Tuple:1)v)
+//      is not valid, so the minimum valid tuple must have two elements
+//      (e.g. (Tuple:2)v)
 //
 // Following with the example above, if t is "i", then "Ue" will yield unsigned
 // int and "Fv" will yield __rvv_float32m1_t (again assuming LMUL=1), Fw would
 // yield __rvv_float64m2_t, etc.
 //
 // Each builtin is then defined by applying each type in TypeRange against the
 // sequence of type transformers described in Suffix and Prototype.
 //
class RVVIntExt<string intrinsic_name, string suffix, string prototype,
   let IntrinsicTypes = [-1, 0];
 }
 
 defvar TypeList = ["c","s","i","l","f","d"];
 defvar EEWList = [["8", "(Log2EEW:3)"],
                   ["16", "(Log2EEW:4)"],
                   ["32", "(Log2EEW:5)"],
                   ["64", "(Log2EEW:6)"]];
+defvar NFList = [2, 3, 4, 5, 6, 7, 8];
 
 class IsFloat<string type> {
   bit val = !or(!eq(type, "h"), !eq(type, "f"), !eq(type, "d"));
 }
 
 multiclass RVVVLEBuiltin<list<string> types> {
   let Name = NAME # "_v",
       IRName = "vle",
foreach type = types in {
       def : RVVBuiltin<"v", "0vPe", type>;
       if !not(IsFloat<type>.val) then {
         def : RVVBuiltin<"Uv", "0UvPUe", type>;
       }
     }
   }
 }
 
+multiclass RVVUnitStridedSegLoad<string op> {
+  foreach type = TypeList in {
+    defvar eew = !cond(!eq(type, "c") : "8",
+                       !eq(type, "s") : "16",
+                       !eq(type, "i") : "32",
+                       !eq(type, "l") : "64",
+                       !eq(type, "h") : "16",
+                       !eq(type, "f") : "32",
+                       !eq(type, "d") : "64");
+      foreach nf = NFList in {
+        let Name = op # nf # "e" # eew # "_v",
+            IRName = op # nf,
+            IRNameMask = op # nf # "_mask",
+            HasNoMaskedOverloaded = false,
+            ManualCodegen = [{
+
+    {
+      // arguments are: (ptr, vl)
+      IntrinsicTypes = {cast<StructType>(ResultType)->elements()[0],
+                        Ops[1]->getType()};
+      llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
+      llvm::Value *LoadValue = Builder.CreateCall(F, Ops, "");
+      llvm::Value *V = llvm::UndefValue::get(ResultType);
+      unsigned NF = cast<StructType>(ResultType)->getNumElements();
+      for (unsigned I = 0; I < NF; ++I) {
+        V = Builder.CreateInsertValue(V,
+               Builder.CreateExtractValue(LoadValue, {I}), {I});
+      }
+      if (ReturnValue.isNull())
+        return V;
+      else
+        return Builder.CreateStore(V, ReturnValue.getValue());
+    }
+            }],
+            ManualCodegenMask = [{
+    {
+      // arguments are: (maskedoff, ptr, mask, vl)
+      IntrinsicTypes = {cast<StructType>(ResultType)->elements()[0],
+                        Ops[3]->getType()};
+      SmallVector<llvm::Value*, 12> Operands;
+      unsigned NF = cast<StructType>(ResultType)->getNumElements();
+      for (unsigned I = 0; I < NF; ++I)
+        Operands.push_back(Builder.CreateExtractValue(Ops[0], {I}));
+      Operands.append(Ops.begin() + 1, Ops.end());
+      std::swap(Operands, Ops);
+      assert(Ops.size() == NF + 3);
+      llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
+      llvm::Value *LoadValue = Builder.CreateCall(F, Ops, "");
+      llvm::Value *V = llvm::UndefValue::get(ResultType);
+      for (unsigned I = 0; I < NF; ++I) {
+        V = Builder.CreateInsertValue(V,
+              Builder.CreateExtractValue(LoadValue, {I}), {I});
+      }
+      if (ReturnValue.isNull())
+        return V;
+      else
+        return Builder.CreateStore(V, ReturnValue.getValue());
+    }
+            }] in {
+          defvar T = "(Tuple:" # nf # ")";
+          def : RVVBuiltin<T # "v", T # "vPCe", type>;
+          if !not(IsFloat<type>.val) then {
+            def : RVVBuiltin<T # "Uv", T # "UvPCUe", type>;
+        }
+      }
+    }
+  }
+}
+
 // 6. Configuration-Setting Instructions
 // 6.1. vsetvli/vsetvl instructions
 let HasVL = false,
     HasMask = false,
     HasSideEffects = true,
     Log2LMUL = [0],
     ManualCodegen = [{IntrinsicTypes = {ResultType};}] in // Set XLEN type
 {

 defm vse16: RVVVSEBuiltin<["s"]>;
 defm vse32: RVVVSEBuiltin<["i","f"]>;
 defm vse64: RVVVSEBuiltin<["l","d"]>;
 
 // 7.6. Vector Indexed Instructions
 defm : RVVIndexedLoad<"vluxei">;
 defm : RVVIndexedLoad<"vloxei">;
 
+// 7.8 Vector Load/Store Segment Instructions
+defm : RVVUnitStridedSegLoad<"vlseg">;
+
 // 12. Vector Integer Arithmetic Instructions
 // 12.1. Vector Single-Width Integer Add and Subtract
 defm vadd : RVVIntBinBuiltinSet;
 defm vsub : RVVIntBinBuiltinSet;
 defm vrsub : RVVOutOp1BuiltinSet<"vrsub", "csil",
                                  [["vx", "v", "vve"],
                                   ["vx", "Uv", "UvUvUe"]]>;
 

clang/lib/AST/ASTContext.cpp

case BuiltinType::Id:                                                        \
     break;
 #include "clang/Basic/AArch64SVEACLETypes.def"
 #define PPC_VECTOR_TYPE(Name, Id, Size)                                        \
   case BuiltinType::Id:                                                        \
     Width = Size;                                                              \
     Align = Size;                                                              \
     break;
 #include "clang/Basic/PPCTypes.def"
-#define RVV_VECTOR_TYPE(Name, Id, SingletonId, ElKind, ElBits, IsSigned, IsFP) \
+#define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, IsSigned, IsFP) \
   case BuiltinType::Id:                                                        \
-    Width = 0;                                                                 \
+    Width = NumEls * ElBits;                                                   \
     Align = ElBits;                                                            \
     break;
 #define RVV_PREDICATE_TYPE(Name, Id, SingletonId, ElKind)                      \
   case BuiltinType::Id:                                                        \
     Width = 0;                                                                 \
     Align = 8;                                                                 \
     break;
 #include "clang/Basic/RISCVVTypes.def"

clang/lib/CodeGen/CGBuiltin.cpp

 }
 
 Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
                                              const CallExpr *E,
                                              ReturnValueSlot ReturnValue) {
   SmallVector<Value *, 4> Ops;
   llvm::Type *ResultType = ConvertType(E->getType());
 
-  for (unsigned i = 0, e = E->getNumArgs(); i != e; i++)
+  for (unsigned i = 0, e = E->getNumArgs(); i != e; i++) {
+    const Expr *Arg = E->getArg(i);
+    if (hasAggregateEvaluationKind(Arg->getType())) {
+      LValue L = EmitAggExprToLValue(Arg);
+      llvm::Value *AggValue = Builder.CreateLoad(L.getAddress(*this));
+      Ops.push_back(AggValue);
+    } else
       Ops.push_back(EmitScalarExpr(E->getArg(i)));
+  }
 
   Intrinsic::ID ID = Intrinsic::not_intrinsic;
 
   // Required for overloaded intrinsics.
   llvm::SmallVector<llvm::Type *, 2> IntrinsicTypes;
   switch (BuiltinID) {
   default: llvm_unreachable("unexpected builtin ID");
   case RISCV::BI__builtin_riscv_orc_b_32:

clang/lib/CodeGen/TargetInfo.cpp

if (IsCandidate && NeededArgGPRs <= ArgGPRsLeft &&
         NeededArgFPRs <= ArgFPRsLeft) {
       ArgGPRsLeft -= NeededArgGPRs;
       ArgFPRsLeft -= NeededArgFPRs;
       return coerceAndExpandFPCCEligibleStruct(Field1Ty, Field1Off, Field2Ty,
                                                Field2Off);
     }
   }
 
+  if (const auto *RTy = Ty->getAs<RecordType>()) {
+    if (RTy->hasSizelessFields())
+      return ABIArgInfo::getDirect(CGT.ConvertType(Ty));
+  }
+
   uint64_t NeededAlign = getContext().getTypeAlign(Ty);
   bool MustUseStack = false;
   // Determine the number of GPRs needed to pass the current argument
   // according to the ABI. 2*XLen-aligned varargs are passed in "aligned"
   // register pairs, so may consume 3 registers.
   int NeededArgGPRs = 1;
   if (!IsFixed && NeededAlign == 2 * XLen)
     NeededArgGPRs = 2 + (ArgGPRsLeft % 2);

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d -target-feature +experimental-v \
+// RUN:   -target-feature +experimental-zfh -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
+// RUN:   -target-feature +experimental-zfh -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
+// RUN:   -target-feature +experimental-zfh -target-feature +m -fallow-half-arguments-and-returns -Werror -Wall -S -o - %s >/dev/null 2>%t
+// RUN: FileCheck --check-prefix=ASM --allow-empty %s <%t
+
+// ASM-NOT: warning
+#include <riscv_vector.h>
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_i8mf8x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X2_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X2_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg2.mask.nxv1i8.i32(<vscale x 1 x i8> [[TMP6]], <vscale x 1 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7:#.*]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X2_T]] undef, <vscale x 1 x i8> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X2_T]] [[TMP10]], <vscale x 1 x i8> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF8X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_i8mf8x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X2_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X2_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg2.mask.nxv1i8.i64(<vscale x 1 x i8> [[TMP6]], <vscale x 1 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7:#.*]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X2_T]] undef, <vscale x 1 x i8> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X2_T]] [[TMP10]], <vscale x 1 x i8> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF8X2_T]] [[TMP12]]
+//
+vint8mf8x2_t test_vlseg2e8_v_i8mf8x2_m (vbool64_t mask, vint8mf8x2_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg2e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e8_v_i8mf8x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg3.mask.nxv1i8.i32(<vscale x 1 x i8> [[TMP9]], <vscale x 1 x i8> [[TMP10]], <vscale x 1 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T]] undef, <vscale x 1 x i8> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP14]], <vscale x 1 x i8> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP16]], <vscale x 1 x i8> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF8X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e8_v_i8mf8x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg3.mask.nxv1i8.i64(<vscale x 1 x i8> [[TMP9]], <vscale x 1 x i8> [[TMP10]], <vscale x 1 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T]] undef, <vscale x 1 x i8> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP14]], <vscale x 1 x i8> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP16]], <vscale x 1 x i8> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF8X3_T]] [[TMP18]]
+//
+vint8mf8x3_t test_vlseg3e8_v_i8mf8x3_m (vbool64_t mask, vint8mf8x3_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg3e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e8_v_i8mf8x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg4.mask.nxv1i8.i32(<vscale x 1 x i8> [[TMP12]], <vscale x 1 x i8> [[TMP13]], <vscale x 1 x i8> [[TMP14]], <vscale x 1 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] undef, <vscale x 1 x i8> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP18]], <vscale x 1 x i8> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP20]], <vscale x 1 x i8> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP22]], <vscale x 1 x i8> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF8X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e8_v_i8mf8x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg4.mask.nxv1i8.i64(<vscale x 1 x i8> [[TMP12]], <vscale x 1 x i8> [[TMP13]], <vscale x 1 x i8> [[TMP14]], <vscale x 1 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] undef, <vscale x 1 x i8> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP18]], <vscale x 1 x i8> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP20]], <vscale x 1 x i8> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP22]], <vscale x 1 x i8> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF8X4_T]] [[TMP24]]
+//
+vint8mf8x4_t test_vlseg4e8_v_i8mf8x4_m (vbool64_t mask, vint8mf8x4_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg4e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e8_v_i8mf8x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP3]], <vscale x 1 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg5.mask.nxv1i8.i32(<vscale x 1 x i8> [[TMP15]], <vscale x 1 x i8> [[TMP16]], <vscale x 1 x i8> [[TMP17]], <vscale x 1 x i8> [[TMP18]], <vscale x 1 x i8> [[TMP19]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] undef, <vscale x 1 x i8> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP22]], <vscale x 1 x i8> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP24]], <vscale x 1 x i8> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP26]], <vscale x 1 x i8> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP28]], <vscale x 1 x i8> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF8X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e8_v_i8mf8x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP3]], <vscale x 1 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg5.mask.nxv1i8.i64(<vscale x 1 x i8> [[TMP15]], <vscale x 1 x i8> [[TMP16]], <vscale x 1 x i8> [[TMP17]], <vscale x 1 x i8> [[TMP18]], <vscale x 1 x i8> [[TMP19]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] undef, <vscale x 1 x i8> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP22]], <vscale x 1 x i8> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP24]], <vscale x 1 x i8> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP26]], <vscale x 1 x i8> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP28]], <vscale x 1 x i8> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF8X5_T]] [[TMP30]]
+//
+vint8mf8x5_t test_vlseg5e8_v_i8mf8x5_m (vbool64_t mask, vint8mf8x5_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg5e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e8_v_i8mf8x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP3]], <vscale x 1 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP4]], <vscale x 1 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg6.mask.nxv1i8.i32(<vscale x 1 x i8> [[TMP18]], <vscale x 1 x i8> [[TMP19]], <vscale x 1 x i8> [[TMP20]], <vscale x 1 x i8> [[TMP21]], <vscale x 1 x i8> [[TMP22]], <vscale x 1 x i8> [[TMP23]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] undef, <vscale x 1 x i8> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP26]], <vscale x 1 x i8> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP28]], <vscale x 1 x i8> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP30]], <vscale x 1 x i8> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP32]], <vscale x 1 x i8> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP34]], <vscale x 1 x i8> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF8X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e8_v_i8mf8x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP3]], <vscale x 1 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP4]], <vscale x 1 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg6.mask.nxv1i8.i64(<vscale x 1 x i8> [[TMP18]], <vscale x 1 x i8> [[TMP19]], <vscale x 1 x i8> [[TMP20]], <vscale x 1 x i8> [[TMP21]], <vscale x 1 x i8> [[TMP22]], <vscale x 1 x i8> [[TMP23]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] undef, <vscale x 1 x i8> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP26]], <vscale x 1 x i8> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP28]], <vscale x 1 x i8> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP30]], <vscale x 1 x i8> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP32]], <vscale x 1 x i8> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP34]], <vscale x 1 x i8> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF8X6_T]] [[TMP36]]
+//
+vint8mf8x6_t test_vlseg6e8_v_i8mf8x6_m (vbool64_t mask, vint8mf8x6_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg6e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e8_v_i8mf8x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP3]], <vscale x 1 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP4]], <vscale x 1 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP5]], <vscale x 1 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg7.mask.nxv1i8.i32(<vscale x 1 x i8> [[TMP21]], <vscale x 1 x i8> [[TMP22]], <vscale x 1 x i8> [[TMP23]], <vscale x 1 x i8> [[TMP24]], <vscale x 1 x i8> [[TMP25]], <vscale x 1 x i8> [[TMP26]], <vscale x 1 x i8> [[TMP27]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] undef, <vscale x 1 x i8> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP30]], <vscale x 1 x i8> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP32]], <vscale x 1 x i8> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP34]], <vscale x 1 x i8> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP36]], <vscale x 1 x i8> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP38]], <vscale x 1 x i8> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP40]], <vscale x 1 x i8> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF8X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e8_v_i8mf8x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP3]], <vscale x 1 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP4]], <vscale x 1 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP5]], <vscale x 1 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg7.mask.nxv1i8.i64(<vscale x 1 x i8> [[TMP21]], <vscale x 1 x i8> [[TMP22]], <vscale x 1 x i8> [[TMP23]], <vscale x 1 x i8> [[TMP24]], <vscale x 1 x i8> [[TMP25]], <vscale x 1 x i8> [[TMP26]], <vscale x 1 x i8> [[TMP27]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] undef, <vscale x 1 x i8> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP30]], <vscale x 1 x i8> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP32]], <vscale x 1 x i8> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP34]], <vscale x 1 x i8> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP36]], <vscale x 1 x i8> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP38]], <vscale x 1 x i8> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP40]], <vscale x 1 x i8> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF8X7_T]] [[TMP42]]
+//
+vint8mf8x7_t test_vlseg7e8_v_i8mf8x7_m (vbool64_t mask, vint8mf8x7_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg7e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e8_v_i8mf8x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP3]], <vscale x 1 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP4]], <vscale x 1 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP5]], <vscale x 1 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP6]], <vscale x 1 x i8> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg8.mask.nxv1i8.i32(<vscale x 1 x i8> [[TMP24]], <vscale x 1 x i8> [[TMP25]], <vscale x 1 x i8> [[TMP26]], <vscale x 1 x i8> [[TMP27]], <vscale x 1 x i8> [[TMP28]], <vscale x 1 x i8> [[TMP29]], <vscale x 1 x i8> [[TMP30]], <vscale x 1 x i8> [[TMP31]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] undef, <vscale x 1 x i8> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP34]], <vscale x 1 x i8> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP36]], <vscale x 1 x i8> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP38]], <vscale x 1 x i8> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP40]], <vscale x 1 x i8> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP42]], <vscale x 1 x i8> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP44]], <vscale x 1 x i8> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP46]], <vscale x 1 x i8> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF8X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e8_v_i8mf8x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP3]], <vscale x 1 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP4]], <vscale x 1 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP5]], <vscale x 1 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP6]], <vscale x 1 x i8> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg8.mask.nxv1i8.i64(<vscale x 1 x i8> [[TMP24]], <vscale x 1 x i8> [[TMP25]], <vscale x 1 x i8> [[TMP26]], <vscale x 1 x i8> [[TMP27]], <vscale x 1 x i8> [[TMP28]], <vscale x 1 x i8> [[TMP29]], <vscale x 1 x i8> [[TMP30]], <vscale x 1 x i8> [[TMP31]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] undef, <vscale x 1 x i8> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP34]], <vscale x 1 x i8> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP36]], <vscale x 1 x i8> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP38]], <vscale x 1 x i8> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP40]], <vscale x 1 x i8> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP42]], <vscale x 1 x i8> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP44]], <vscale x 1 x i8> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP46]], <vscale x 1 x i8> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF8X8_T]] [[TMP48]]
+//
+vint8mf8x8_t test_vlseg8e8_v_i8mf8x8_m (vbool64_t mask, vint8mf8x8_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg8e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_i8mf4x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X2_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X2_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg2.mask.nxv2i8.i32(<vscale x 2 x i8> [[TMP6]], <vscale x 2 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X2_T]] undef, <vscale x 2 x i8> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X2_T]] [[TMP10]], <vscale x 2 x i8> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF4X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_i8mf4x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X2_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X2_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg2.mask.nxv2i8.i64(<vscale x 2 x i8> [[TMP6]], <vscale x 2 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X2_T]] undef, <vscale x 2 x i8> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X2_T]] [[TMP10]], <vscale x 2 x i8> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF4X2_T]] [[TMP12]]
+//
+vint8mf4x2_t test_vlseg2e8_v_i8mf4x2_m (vbool32_t mask, vint8mf4x2_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg2e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e8_v_i8mf4x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg3.mask.nxv2i8.i32(<vscale x 2 x i8> [[TMP9]], <vscale x 2 x i8> [[TMP10]], <vscale x 2 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T]] undef, <vscale x 2 x i8> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP14]], <vscale x 2 x i8> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP16]], <vscale x 2 x i8> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF4X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e8_v_i8mf4x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg3.mask.nxv2i8.i64(<vscale x 2 x i8> [[TMP9]], <vscale x 2 x i8> [[TMP10]], <vscale x 2 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T]] undef, <vscale x 2 x i8> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP14]], <vscale x 2 x i8> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP16]], <vscale x 2 x i8> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF4X3_T]] [[TMP18]]
+//
+vint8mf4x3_t test_vlseg3e8_v_i8mf4x3_m (vbool32_t mask, vint8mf4x3_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg3e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e8_v_i8mf4x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg4.mask.nxv2i8.i32(<vscale x 2 x i8> [[TMP12]], <vscale x 2 x i8> [[TMP13]], <vscale x 2 x i8> [[TMP14]], <vscale x 2 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] undef, <vscale x 2 x i8> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP18]], <vscale x 2 x i8> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP20]], <vscale x 2 x i8> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP22]], <vscale x 2 x i8> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF4X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e8_v_i8mf4x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg4.mask.nxv2i8.i64(<vscale x 2 x i8> [[TMP12]], <vscale x 2 x i8> [[TMP13]], <vscale x 2 x i8> [[TMP14]], <vscale x 2 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] undef, <vscale x 2 x i8> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP18]], <vscale x 2 x i8> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP20]], <vscale x 2 x i8> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP22]], <vscale x 2 x i8> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF4X4_T]] [[TMP24]]
+//
+vint8mf4x4_t test_vlseg4e8_v_i8mf4x4_m (vbool32_t mask, vint8mf4x4_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg4e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e8_v_i8mf4x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP3]], <vscale x 2 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg5.mask.nxv2i8.i32(<vscale x 2 x i8> [[TMP15]], <vscale x 2 x i8> [[TMP16]], <vscale x 2 x i8> [[TMP17]], <vscale x 2 x i8> [[TMP18]], <vscale x 2 x i8> [[TMP19]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] undef, <vscale x 2 x i8> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP22]], <vscale x 2 x i8> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP24]], <vscale x 2 x i8> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP26]], <vscale x 2 x i8> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP28]], <vscale x 2 x i8> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF4X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e8_v_i8mf4x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP3]], <vscale x 2 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg5.mask.nxv2i8.i64(<vscale x 2 x i8> [[TMP15]], <vscale x 2 x i8> [[TMP16]], <vscale x 2 x i8> [[TMP17]], <vscale x 2 x i8> [[TMP18]], <vscale x 2 x i8> [[TMP19]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] undef, <vscale x 2 x i8> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP22]], <vscale x 2 x i8> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP24]], <vscale x 2 x i8> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP26]], <vscale x 2 x i8> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP28]], <vscale x 2 x i8> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF4X5_T]] [[TMP30]]
+//
+vint8mf4x5_t test_vlseg5e8_v_i8mf4x5_m (vbool32_t mask, vint8mf4x5_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg5e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e8_v_i8mf4x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP3]], <vscale x 2 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP4]], <vscale x 2 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg6.mask.nxv2i8.i32(<vscale x 2 x i8> [[TMP18]], <vscale x 2 x i8> [[TMP19]], <vscale x 2 x i8> [[TMP20]], <vscale x 2 x i8> [[TMP21]], <vscale x 2 x i8> [[TMP22]], <vscale x 2 x i8> [[TMP23]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] undef, <vscale x 2 x i8> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP26]], <vscale x 2 x i8> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP28]], <vscale x 2 x i8> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP30]], <vscale x 2 x i8> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP32]], <vscale x 2 x i8> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP34]], <vscale x 2 x i8> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF4X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e8_v_i8mf4x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP3]], <vscale x 2 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP4]], <vscale x 2 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg6.mask.nxv2i8.i64(<vscale x 2 x i8> [[TMP18]], <vscale x 2 x i8> [[TMP19]], <vscale x 2 x i8> [[TMP20]], <vscale x 2 x i8> [[TMP21]], <vscale x 2 x i8> [[TMP22]], <vscale x 2 x i8> [[TMP23]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] undef, <vscale x 2 x i8> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP26]], <vscale x 2 x i8> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP28]], <vscale x 2 x i8> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP30]], <vscale x 2 x i8> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP32]], <vscale x 2 x i8> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP34]], <vscale x 2 x i8> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF4X6_T]] [[TMP36]]
+//
+vint8mf4x6_t test_vlseg6e8_v_i8mf4x6_m (vbool32_t mask, vint8mf4x6_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg6e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e8_v_i8mf4x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP3]], <vscale x 2 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP4]], <vscale x 2 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP5]], <vscale x 2 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg7.mask.nxv2i8.i32(<vscale x 2 x i8> [[TMP21]], <vscale x 2 x i8> [[TMP22]], <vscale x 2 x i8> [[TMP23]], <vscale x 2 x i8> [[TMP24]], <vscale x 2 x i8> [[TMP25]], <vscale x 2 x i8> [[TMP26]], <vscale x 2 x i8> [[TMP27]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] undef, <vscale x 2 x i8> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP30]], <vscale x 2 x i8> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP32]], <vscale x 2 x i8> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP34]], <vscale x 2 x i8> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP36]], <vscale x 2 x i8> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP38]], <vscale x 2 x i8> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP40]], <vscale x 2 x i8> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF4X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e8_v_i8mf4x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP3]], <vscale x 2 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP4]], <vscale x 2 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP5]], <vscale x 2 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg7.mask.nxv2i8.i64(<vscale x 2 x i8> [[TMP21]], <vscale x 2 x i8> [[TMP22]], <vscale x 2 x i8> [[TMP23]], <vscale x 2 x i8> [[TMP24]], <vscale x 2 x i8> [[TMP25]], <vscale x 2 x i8> [[TMP26]], <vscale x 2 x i8> [[TMP27]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] undef, <vscale x 2 x i8> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP30]], <vscale x 2 x i8> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP32]], <vscale x 2 x i8> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP34]], <vscale x 2 x i8> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP36]], <vscale x 2 x i8> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP38]], <vscale x 2 x i8> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP40]], <vscale x 2 x i8> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF4X7_T]] [[TMP42]]
+//
+vint8mf4x7_t test_vlseg7e8_v_i8mf4x7_m (vbool32_t mask, vint8mf4x7_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg7e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e8_v_i8mf4x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP3]], <vscale x 2 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP4]], <vscale x 2 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP5]], <vscale x 2 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP6]], <vscale x 2 x i8> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg8.mask.nxv2i8.i32(<vscale x 2 x i8> [[TMP24]], <vscale x 2 x i8> [[TMP25]], <vscale x 2 x i8> [[TMP26]], <vscale x 2 x i8> [[TMP27]], <vscale x 2 x i8> [[TMP28]], <vscale x 2 x i8> [[TMP29]], <vscale x 2 x i8> [[TMP30]], <vscale x 2 x i8> [[TMP31]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] undef, <vscale x 2 x i8> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP34]], <vscale x 2 x i8> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP36]], <vscale x 2 x i8> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP38]], <vscale x 2 x i8> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP40]], <vscale x 2 x i8> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP42]], <vscale x 2 x i8> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP44]], <vscale x 2 x i8> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP46]], <vscale x 2 x i8> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF4X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e8_v_i8mf4x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP3]], <vscale x 2 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP4]], <vscale x 2 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP5]], <vscale x 2 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP6]], <vscale x 2 x i8> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg8.mask.nxv2i8.i64(<vscale x 2 x i8> [[TMP24]], <vscale x 2 x i8> [[TMP25]], <vscale x 2 x i8> [[TMP26]], <vscale x 2 x i8> [[TMP27]], <vscale x 2 x i8> [[TMP28]], <vscale x 2 x i8> [[TMP29]], <vscale x 2 x i8> [[TMP30]], <vscale x 2 x i8> [[TMP31]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] undef, <vscale x 2 x i8> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP34]], <vscale x 2 x i8> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP36]], <vscale x 2 x i8> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP38]], <vscale x 2 x i8> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP40]], <vscale x 2 x i8> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP42]], <vscale x 2 x i8> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP44]], <vscale x 2 x i8> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP46]], <vscale x 2 x i8> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF4X8_T]] [[TMP48]]
+//
+vint8mf4x8_t test_vlseg8e8_v_i8mf4x8_m (vbool32_t mask, vint8mf4x8_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg8e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_i8mf2x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X2_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X2_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg2.mask.nxv4i8.i32(<vscale x 4 x i8> [[TMP6]], <vscale x 4 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X2_T]] undef, <vscale x 4 x i8> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X2_T]] [[TMP10]], <vscale x 4 x i8> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF2X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_i8mf2x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X2_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X2_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg2.mask.nxv4i8.i64(<vscale x 4 x i8> [[TMP6]], <vscale x 4 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X2_T]] undef, <vscale x 4 x i8> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X2_T]] [[TMP10]], <vscale x 4 x i8> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF2X2_T]] [[TMP12]]
+//
+vint8mf2x2_t test_vlseg2e8_v_i8mf2x2_m (vbool16_t mask, vint8mf2x2_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg2e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e8_v_i8mf2x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg3.mask.nxv4i8.i32(<vscale x 4 x i8> [[TMP9]], <vscale x 4 x i8> [[TMP10]], <vscale x 4 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T]] undef, <vscale x 4 x i8> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP14]], <vscale x 4 x i8> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP16]], <vscale x 4 x i8> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF2X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e8_v_i8mf2x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg3.mask.nxv4i8.i64(<vscale x 4 x i8> [[TMP9]], <vscale x 4 x i8> [[TMP10]], <vscale x 4 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T]] undef, <vscale x 4 x i8> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP14]], <vscale x 4 x i8> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP16]], <vscale x 4 x i8> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF2X3_T]] [[TMP18]]
+//
+vint8mf2x3_t test_vlseg3e8_v_i8mf2x3_m (vbool16_t mask, vint8mf2x3_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg3e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e8_v_i8mf2x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg4.mask.nxv4i8.i32(<vscale x 4 x i8> [[TMP12]], <vscale x 4 x i8> [[TMP13]], <vscale x 4 x i8> [[TMP14]], <vscale x 4 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] undef, <vscale x 4 x i8> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP18]], <vscale x 4 x i8> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP20]], <vscale x 4 x i8> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP22]], <vscale x 4 x i8> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF2X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e8_v_i8mf2x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg4.mask.nxv4i8.i64(<vscale x 4 x i8> [[TMP12]], <vscale x 4 x i8> [[TMP13]], <vscale x 4 x i8> [[TMP14]], <vscale x 4 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] undef, <vscale x 4 x i8> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP18]], <vscale x 4 x i8> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP20]], <vscale x 4 x i8> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP22]], <vscale x 4 x i8> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF2X4_T]] [[TMP24]]
+//
+vint8mf2x4_t test_vlseg4e8_v_i8mf2x4_m (vbool16_t mask, vint8mf2x4_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg4e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e8_v_i8mf2x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP3]], <vscale x 4 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg5.mask.nxv4i8.i32(<vscale x 4 x i8> [[TMP15]], <vscale x 4 x i8> [[TMP16]], <vscale x 4 x i8> [[TMP17]], <vscale x 4 x i8> [[TMP18]], <vscale x 4 x i8> [[TMP19]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] undef, <vscale x 4 x i8> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP22]], <vscale x 4 x i8> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP24]], <vscale x 4 x i8> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP26]], <vscale x 4 x i8> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP28]], <vscale x 4 x i8> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF2X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e8_v_i8mf2x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP3]], <vscale x 4 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg5.mask.nxv4i8.i64(<vscale x 4 x i8> [[TMP15]], <vscale x 4 x i8> [[TMP16]], <vscale x 4 x i8> [[TMP17]], <vscale x 4 x i8> [[TMP18]], <vscale x 4 x i8> [[TMP19]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] undef, <vscale x 4 x i8> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP22]], <vscale x 4 x i8> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP24]], <vscale x 4 x i8> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP26]], <vscale x 4 x i8> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP28]], <vscale x 4 x i8> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF2X5_T]] [[TMP30]]
+//
+vint8mf2x5_t test_vlseg5e8_v_i8mf2x5_m (vbool16_t mask, vint8mf2x5_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg5e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e8_v_i8mf2x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP3]], <vscale x 4 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP4]], <vscale x 4 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg6.mask.nxv4i8.i32(<vscale x 4 x i8> [[TMP18]], <vscale x 4 x i8> [[TMP19]], <vscale x 4 x i8> [[TMP20]], <vscale x 4 x i8> [[TMP21]], <vscale x 4 x i8> [[TMP22]], <vscale x 4 x i8> [[TMP23]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] undef, <vscale x 4 x i8> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP26]], <vscale x 4 x i8> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP28]], <vscale x 4 x i8> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP30]], <vscale x 4 x i8> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP32]], <vscale x 4 x i8> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP34]], <vscale x 4 x i8> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF2X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e8_v_i8mf2x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP3]], <vscale x 4 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP4]], <vscale x 4 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg6.mask.nxv4i8.i64(<vscale x 4 x i8> [[TMP18]], <vscale x 4 x i8> [[TMP19]], <vscale x 4 x i8> [[TMP20]], <vscale x 4 x i8> [[TMP21]], <vscale x 4 x i8> [[TMP22]], <vscale x 4 x i8> [[TMP23]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] undef, <vscale x 4 x i8> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP26]], <vscale x 4 x i8> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP28]], <vscale x 4 x i8> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP30]], <vscale x 4 x i8> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP32]], <vscale x 4 x i8> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP34]], <vscale x 4 x i8> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF2X6_T]] [[TMP36]]
+//
+vint8mf2x6_t test_vlseg6e8_v_i8mf2x6_m (vbool16_t mask, vint8mf2x6_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg6e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e8_v_i8mf2x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP3]], <vscale x 4 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP4]], <vscale x 4 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP5]], <vscale x 4 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg7.mask.nxv4i8.i32(<vscale x 4 x i8> [[TMP21]], <vscale x 4 x i8> [[TMP22]], <vscale x 4 x i8> [[TMP23]], <vscale x 4 x i8> [[TMP24]], <vscale x 4 x i8> [[TMP25]], <vscale x 4 x i8> [[TMP26]], <vscale x 4 x i8> [[TMP27]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] undef, <vscale x 4 x i8> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP30]], <vscale x 4 x i8> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP32]], <vscale x 4 x i8> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP34]], <vscale x 4 x i8> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP36]], <vscale x 4 x i8> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP38]], <vscale x 4 x i8> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP40]], <vscale x 4 x i8> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF2X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e8_v_i8mf2x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP3]], <vscale x 4 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP4]], <vscale x 4 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP5]], <vscale x 4 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg7.mask.nxv4i8.i64(<vscale x 4 x i8> [[TMP21]], <vscale x 4 x i8> [[TMP22]], <vscale x 4 x i8> [[TMP23]], <vscale x 4 x i8> [[TMP24]], <vscale x 4 x i8> [[TMP25]], <vscale x 4 x i8> [[TMP26]], <vscale x 4 x i8> [[TMP27]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] undef, <vscale x 4 x i8> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP30]], <vscale x 4 x i8> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP32]], <vscale x 4 x i8> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP34]], <vscale x 4 x i8> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP36]], <vscale x 4 x i8> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP38]], <vscale x 4 x i8> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP40]], <vscale x 4 x i8> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF2X7_T]] [[TMP42]]
+//
+vint8mf2x7_t test_vlseg7e8_v_i8mf2x7_m (vbool16_t mask, vint8mf2x7_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg7e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e8_v_i8mf2x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP3]], <vscale x 4 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP4]], <vscale x 4 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP5]], <vscale x 4 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP6]], <vscale x 4 x i8> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg8.mask.nxv4i8.i32(<vscale x 4 x i8> [[TMP24]], <vscale x 4 x i8> [[TMP25]], <vscale x 4 x i8> [[TMP26]], <vscale x 4 x i8> [[TMP27]], <vscale x 4 x i8> [[TMP28]], <vscale x 4 x i8> [[TMP29]], <vscale x 4 x i8> [[TMP30]], <vscale x 4 x i8> [[TMP31]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] undef, <vscale x 4 x i8> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP34]], <vscale x 4 x i8> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP36]], <vscale x 4 x i8> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP38]], <vscale x 4 x i8> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP40]], <vscale x 4 x i8> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP42]], <vscale x 4 x i8> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP44]], <vscale x 4 x i8> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP46]], <vscale x 4 x i8> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF2X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e8_v_i8mf2x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP3]], <vscale x 4 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP4]], <vscale x 4 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP5]], <vscale x 4 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP6]], <vscale x 4 x i8> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg8.mask.nxv4i8.i64(<vscale x 4 x i8> [[TMP24]], <vscale x 4 x i8> [[TMP25]], <vscale x 4 x i8> [[TMP26]], <vscale x 4 x i8> [[TMP27]], <vscale x 4 x i8> [[TMP28]], <vscale x 4 x i8> [[TMP29]], <vscale x 4 x i8> [[TMP30]], <vscale x 4 x i8> [[TMP31]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] undef, <vscale x 4 x i8> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP34]], <vscale x 4 x i8> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP36]], <vscale x 4 x i8> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP38]], <vscale x 4 x i8> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP40]], <vscale x 4 x i8> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP42]], <vscale x 4 x i8> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP44]], <vscale x 4 x i8> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP46]], <vscale x 4 x i8> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF2X8_T]] [[TMP48]]
+//
+vint8mf2x8_t test_vlseg8e8_v_i8mf2x8_m (vbool16_t mask, vint8mf2x8_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg8e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_i8m1x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X2_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X2_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg2.mask.nxv8i8.i32(<vscale x 8 x i8> [[TMP6]], <vscale x 8 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X2_T]] undef, <vscale x 8 x i8> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X2_T]] [[TMP10]], <vscale x 8 x i8> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8M1X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_i8m1x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X2_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X2_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg2.mask.nxv8i8.i64(<vscale x 8 x i8> [[TMP6]], <vscale x 8 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X2_T]] undef, <vscale x 8 x i8> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X2_T]] [[TMP10]], <vscale x 8 x i8> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8M1X2_T]] [[TMP12]]
+//
+vint8m1x2_t test_vlseg2e8_v_i8m1x2_m (vbool8_t mask, vint8m1x2_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg2e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e8_v_i8m1x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg3.mask.nxv8i8.i32(<vscale x 8 x i8> [[TMP9]], <vscale x 8 x i8> [[TMP10]], <vscale x 8 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T]] undef, <vscale x 8 x i8> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP14]], <vscale x 8 x i8> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP16]], <vscale x 8 x i8> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8M1X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e8_v_i8m1x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg3.mask.nxv8i8.i64(<vscale x 8 x i8> [[TMP9]], <vscale x 8 x i8> [[TMP10]], <vscale x 8 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T]] undef, <vscale x 8 x i8> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP14]], <vscale x 8 x i8> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP16]], <vscale x 8 x i8> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8M1X3_T]] [[TMP18]]
+//
+vint8m1x3_t test_vlseg3e8_v_i8m1x3_m (vbool8_t mask, vint8m1x3_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg3e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e8_v_i8m1x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg4.mask.nxv8i8.i32(<vscale x 8 x i8> [[TMP12]], <vscale x 8 x i8> [[TMP13]], <vscale x 8 x i8> [[TMP14]], <vscale x 8 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] undef, <vscale x 8 x i8> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP18]], <vscale x 8 x i8> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP20]], <vscale x 8 x i8> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP22]], <vscale x 8 x i8> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8M1X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e8_v_i8m1x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg4.mask.nxv8i8.i64(<vscale x 8 x i8> [[TMP12]], <vscale x 8 x i8> [[TMP13]], <vscale x 8 x i8> [[TMP14]], <vscale x 8 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] undef, <vscale x 8 x i8> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP18]], <vscale x 8 x i8> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP20]], <vscale x 8 x i8> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP22]], <vscale x 8 x i8> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8M1X4_T]] [[TMP24]]
+//
+vint8m1x4_t test_vlseg4e8_v_i8m1x4_m (vbool8_t mask, vint8m1x4_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg4e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e8_v_i8m1x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP3]], <vscale x 8 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg5.mask.nxv8i8.i32(<vscale x 8 x i8> [[TMP15]], <vscale x 8 x i8> [[TMP16]], <vscale x 8 x i8> [[TMP17]], <vscale x 8 x i8> [[TMP18]], <vscale x 8 x i8> [[TMP19]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] undef, <vscale x 8 x i8> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP22]], <vscale x 8 x i8> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP24]], <vscale x 8 x i8> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP26]], <vscale x 8 x i8> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP28]], <vscale x 8 x i8> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8M1X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e8_v_i8m1x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP3]], <vscale x 8 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg5.mask.nxv8i8.i64(<vscale x 8 x i8> [[TMP15]], <vscale x 8 x i8> [[TMP16]], <vscale x 8 x i8> [[TMP17]], <vscale x 8 x i8> [[TMP18]], <vscale x 8 x i8> [[TMP19]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] undef, <vscale x 8 x i8> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP22]], <vscale x 8 x i8> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP24]], <vscale x 8 x i8> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP26]], <vscale x 8 x i8> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP28]], <vscale x 8 x i8> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8M1X5_T]] [[TMP30]]
+//
+vint8m1x5_t test_vlseg5e8_v_i8m1x5_m (vbool8_t mask, vint8m1x5_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg5e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e8_v_i8m1x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP3]], <vscale x 8 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP4]], <vscale x 8 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg6.mask.nxv8i8.i32(<vscale x 8 x i8> [[TMP18]], <vscale x 8 x i8> [[TMP19]], <vscale x 8 x i8> [[TMP20]], <vscale x 8 x i8> [[TMP21]], <vscale x 8 x i8> [[TMP22]], <vscale x 8 x i8> [[TMP23]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] undef, <vscale x 8 x i8> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP26]], <vscale x 8 x i8> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP28]], <vscale x 8 x i8> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP30]], <vscale x 8 x i8> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP32]], <vscale x 8 x i8> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP34]], <vscale x 8 x i8> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8M1X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e8_v_i8m1x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP3]], <vscale x 8 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP4]], <vscale x 8 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg6.mask.nxv8i8.i64(<vscale x 8 x i8> [[TMP18]], <vscale x 8 x i8> [[TMP19]], <vscale x 8 x i8> [[TMP20]], <vscale x 8 x i8> [[TMP21]], <vscale x 8 x i8> [[TMP22]], <vscale x 8 x i8> [[TMP23]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] undef, <vscale x 8 x i8> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP26]], <vscale x 8 x i8> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP28]], <vscale x 8 x i8> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP30]], <vscale x 8 x i8> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP32]], <vscale x 8 x i8> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP34]], <vscale x 8 x i8> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8M1X6_T]] [[TMP36]]
+//
+vint8m1x6_t test_vlseg6e8_v_i8m1x6_m (vbool8_t mask, vint8m1x6_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg6e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e8_v_i8m1x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP3]], <vscale x 8 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP4]], <vscale x 8 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP5]], <vscale x 8 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg7.mask.nxv8i8.i32(<vscale x 8 x i8> [[TMP21]], <vscale x 8 x i8> [[TMP22]], <vscale x 8 x i8> [[TMP23]], <vscale x 8 x i8> [[TMP24]], <vscale x 8 x i8> [[TMP25]], <vscale x 8 x i8> [[TMP26]], <vscale x 8 x i8> [[TMP27]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] undef, <vscale x 8 x i8> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP30]], <vscale x 8 x i8> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP32]], <vscale x 8 x i8> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP34]], <vscale x 8 x i8> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP36]], <vscale x 8 x i8> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP38]], <vscale x 8 x i8> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP40]], <vscale x 8 x i8> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8M1X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e8_v_i8m1x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP3]], <vscale x 8 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP4]], <vscale x 8 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP5]], <vscale x 8 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg7.mask.nxv8i8.i64(<vscale x 8 x i8> [[TMP21]], <vscale x 8 x i8> [[TMP22]], <vscale x 8 x i8> [[TMP23]], <vscale x 8 x i8> [[TMP24]], <vscale x 8 x i8> [[TMP25]], <vscale x 8 x i8> [[TMP26]], <vscale x 8 x i8> [[TMP27]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] undef, <vscale x 8 x i8> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP30]], <vscale x 8 x i8> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP32]], <vscale x 8 x i8> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP34]], <vscale x 8 x i8> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP36]], <vscale x 8 x i8> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP38]], <vscale x 8 x i8> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP40]], <vscale x 8 x i8> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8M1X7_T]] [[TMP42]]
+//
+vint8m1x7_t test_vlseg7e8_v_i8m1x7_m (vbool8_t mask, vint8m1x7_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg7e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e8_v_i8m1x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP3]], <vscale x 8 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP4]], <vscale x 8 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP5]], <vscale x 8 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP6]], <vscale x 8 x i8> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg8.mask.nxv8i8.i32(<vscale x 8 x i8> [[TMP24]], <vscale x 8 x i8> [[TMP25]], <vscale x 8 x i8> [[TMP26]], <vscale x 8 x i8> [[TMP27]], <vscale x 8 x i8> [[TMP28]], <vscale x 8 x i8> [[TMP29]], <vscale x 8 x i8> [[TMP30]], <vscale x 8 x i8> [[TMP31]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] undef, <vscale x 8 x i8> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP34]], <vscale x 8 x i8> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP36]], <vscale x 8 x i8> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP38]], <vscale x 8 x i8> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP40]], <vscale x 8 x i8> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP42]], <vscale x 8 x i8> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP44]], <vscale x 8 x i8> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP46]], <vscale x 8 x i8> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8M1X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e8_v_i8m1x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP3]], <vscale x 8 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP4]], <vscale x 8 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP5]], <vscale x 8 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP6]], <vscale x 8 x i8> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg8.mask.nxv8i8.i64(<vscale x 8 x i8> [[TMP24]], <vscale x 8 x i8> [[TMP25]], <vscale x 8 x i8> [[TMP26]], <vscale x 8 x i8> [[TMP27]], <vscale x 8 x i8> [[TMP28]], <vscale x 8 x i8> [[TMP29]], <vscale x 8 x i8> [[TMP30]], <vscale x 8 x i8> [[TMP31]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] undef, <vscale x 8 x i8> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP34]], <vscale x 8 x i8> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP36]], <vscale x 8 x i8> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP38]], <vscale x 8 x i8> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP40]], <vscale x 8 x i8> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP42]], <vscale x 8 x i8> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP44]], <vscale x 8 x i8> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP46]], <vscale x 8 x i8> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8M1X8_T]] [[TMP48]]
+//
+vint8m1x8_t test_vlseg8e8_v_i8m1x8_m (vbool8_t mask, vint8m1x8_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg8e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_i8m2x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X2_T:%.*]] undef, <vscale x 16 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X2_T]] [[TMP0]], <vscale x 16 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg2.mask.nxv16i8.i32(<vscale x 16 x i8> [[TMP6]], <vscale x 16 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X2_T]] undef, <vscale x 16 x i8> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X2_T]] [[TMP10]], <vscale x 16 x i8> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8M2X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_i8m2x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X2_T:%.*]] undef, <vscale x 16 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X2_T]] [[TMP0]], <vscale x 16 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg2.mask.nxv16i8.i64(<vscale x 16 x i8> [[TMP6]], <vscale x 16 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X2_T]] undef, <vscale x 16 x i8> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X2_T]] [[TMP10]], <vscale x 16 x i8> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8M2X2_T]] [[TMP12]]
+//
+vint8m2x2_t test_vlseg2e8_v_i8m2x2_m (vbool4_t mask, vint8m2x2_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg2e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e8_v_i8m2x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T:%.*]] undef, <vscale x 16 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP0]], <vscale x 16 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP1]], <vscale x 16 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg3.mask.nxv16i8.i32(<vscale x 16 x i8> [[TMP9]], <vscale x 16 x i8> [[TMP10]], <vscale x 16 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T]] undef, <vscale x 16 x i8> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP14]], <vscale x 16 x i8> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP16]], <vscale x 16 x i8> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8M2X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e8_v_i8m2x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T:%.*]] undef, <vscale x 16 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP0]], <vscale x 16 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP1]], <vscale x 16 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg3.mask.nxv16i8.i64(<vscale x 16 x i8> [[TMP9]], <vscale x 16 x i8> [[TMP10]], <vscale x 16 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T]] undef, <vscale x 16 x i8> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP14]], <vscale x 16 x i8> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP16]], <vscale x 16 x i8> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8M2X3_T]] [[TMP18]]
+//
+vint8m2x3_t test_vlseg3e8_v_i8m2x3_m (vbool4_t mask, vint8m2x3_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg3e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e8_v_i8m2x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T:%.*]] undef, <vscale x 16 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP0]], <vscale x 16 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP1]], <vscale x 16 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP2]], <vscale x 16 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg4.mask.nxv16i8.i32(<vscale x 16 x i8> [[TMP12]], <vscale x 16 x i8> [[TMP13]], <vscale x 16 x i8> [[TMP14]], <vscale x 16 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] undef, <vscale x 16 x i8> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP18]], <vscale x 16 x i8> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP20]], <vscale x 16 x i8> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP22]], <vscale x 16 x i8> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8M2X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e8_v_i8m2x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T:%.*]] undef, <vscale x 16 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP0]], <vscale x 16 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP1]], <vscale x 16 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP2]], <vscale x 16 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg4.mask.nxv16i8.i64(<vscale x 16 x i8> [[TMP12]], <vscale x 16 x i8> [[TMP13]], <vscale x 16 x i8> [[TMP14]], <vscale x 16 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] undef, <vscale x 16 x i8> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP18]], <vscale x 16 x i8> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP20]], <vscale x 16 x i8> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP22]], <vscale x 16 x i8> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8M2X4_T]] [[TMP24]]
+//
+vint8m2x4_t test_vlseg4e8_v_i8m2x4_m (vbool4_t mask, vint8m2x4_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg4e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_i8m4x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M4X2_T:%.*]] undef, <vscale x 32 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M4X2_T]] [[TMP0]], <vscale x 32 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT8M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT8M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 32 x i8>, <vscale x 32 x i8> } @llvm.riscv.vlseg2.mask.nxv32i8.i32(<vscale x 32 x i8> [[TMP6]], <vscale x 32 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8M4X2_T]] undef, <vscale x 32 x i8> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8M4X2_T]] [[TMP10]], <vscale x 32 x i8> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8M4X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_i8m4x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M4X2_T:%.*]] undef, <vscale x 32 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M4X2_T]] [[TMP0]], <vscale x 32 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT8M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT8M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 32 x i8>, <vscale x 32 x i8> } @llvm.riscv.vlseg2.mask.nxv32i8.i64(<vscale x 32 x i8> [[TMP6]], <vscale x 32 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8M4X2_T]] undef, <vscale x 32 x i8> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8M4X2_T]] [[TMP10]], <vscale x 32 x i8> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8M4X2_T]] [[TMP12]]
+//
+vint8m4x2_t test_vlseg2e8_v_i8m4x2_m (vbool2_t mask, vint8m4x2_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg2e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e16_v_i16mf4x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X2_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X2_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg2.mask.nxv1i16.i32(<vscale x 1 x i16> [[TMP6]], <vscale x 1 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X2_T]] undef, <vscale x 1 x i16> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X2_T]] [[TMP10]], <vscale x 1 x i16> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF4X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e16_v_i16mf4x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X2_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X2_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg2.mask.nxv1i16.i64(<vscale x 1 x i16> [[TMP6]], <vscale x 1 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X2_T]] undef, <vscale x 1 x i16> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X2_T]] [[TMP10]], <vscale x 1 x i16> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF4X2_T]] [[TMP12]]
+//
+vint16mf4x2_t test_vlseg2e16_v_i16mf4x2_m (vbool64_t mask, vint16mf4x2_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg2e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e16_v_i16mf4x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg3.mask.nxv1i16.i32(<vscale x 1 x i16> [[TMP9]], <vscale x 1 x i16> [[TMP10]], <vscale x 1 x i16> [[TMP11]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T]] undef, <vscale x 1 x i16> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP14]], <vscale x 1 x i16> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP16]], <vscale x 1 x i16> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF4X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e16_v_i16mf4x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg3.mask.nxv1i16.i64(<vscale x 1 x i16> [[TMP9]], <vscale x 1 x i16> [[TMP10]], <vscale x 1 x i16> [[TMP11]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T]] undef, <vscale x 1 x i16> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP14]], <vscale x 1 x i16> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP16]], <vscale x 1 x i16> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF4X3_T]] [[TMP18]]
+//
+vint16mf4x3_t test_vlseg3e16_v_i16mf4x3_m (vbool64_t mask, vint16mf4x3_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg3e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e16_v_i16mf4x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg4.mask.nxv1i16.i32(<vscale x 1 x i16> [[TMP12]], <vscale x 1 x i16> [[TMP13]], <vscale x 1 x i16> [[TMP14]], <vscale x 1 x i16> [[TMP15]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] undef, <vscale x 1 x i16> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP18]], <vscale x 1 x i16> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP20]], <vscale x 1 x i16> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP22]], <vscale x 1 x i16> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF4X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e16_v_i16mf4x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg4.mask.nxv1i16.i64(<vscale x 1 x i16> [[TMP12]], <vscale x 1 x i16> [[TMP13]], <vscale x 1 x i16> [[TMP14]], <vscale x 1 x i16> [[TMP15]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] undef, <vscale x 1 x i16> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP18]], <vscale x 1 x i16> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP20]], <vscale x 1 x i16> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP22]], <vscale x 1 x i16> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF4X4_T]] [[TMP24]]
+//
+vint16mf4x4_t test_vlseg4e16_v_i16mf4x4_m (vbool64_t mask, vint16mf4x4_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg4e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e16_v_i16mf4x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP3]], <vscale x 1 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg5.mask.nxv1i16.i32(<vscale x 1 x i16> [[TMP15]], <vscale x 1 x i16> [[TMP16]], <vscale x 1 x i16> [[TMP17]], <vscale x 1 x i16> [[TMP18]], <vscale x 1 x i16> [[TMP19]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] undef, <vscale x 1 x i16> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP22]], <vscale x 1 x i16> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP24]], <vscale x 1 x i16> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP26]], <vscale x 1 x i16> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP28]], <vscale x 1 x i16> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF4X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e16_v_i16mf4x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP3]], <vscale x 1 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg5.mask.nxv1i16.i64(<vscale x 1 x i16> [[TMP15]], <vscale x 1 x i16> [[TMP16]], <vscale x 1 x i16> [[TMP17]], <vscale x 1 x i16> [[TMP18]], <vscale x 1 x i16> [[TMP19]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] undef, <vscale x 1 x i16> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP22]], <vscale x 1 x i16> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP24]], <vscale x 1 x i16> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP26]], <vscale x 1 x i16> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP28]], <vscale x 1 x i16> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF4X5_T]] [[TMP30]]
+//
+vint16mf4x5_t test_vlseg5e16_v_i16mf4x5_m (vbool64_t mask, vint16mf4x5_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg5e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e16_v_i16mf4x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP3]], <vscale x 1 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP4]], <vscale x 1 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg6.mask.nxv1i16.i32(<vscale x 1 x i16> [[TMP18]], <vscale x 1 x i16> [[TMP19]], <vscale x 1 x i16> [[TMP20]], <vscale x 1 x i16> [[TMP21]], <vscale x 1 x i16> [[TMP22]], <vscale x 1 x i16> [[TMP23]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] undef, <vscale x 1 x i16> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP26]], <vscale x 1 x i16> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP28]], <vscale x 1 x i16> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP30]], <vscale x 1 x i16> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP32]], <vscale x 1 x i16> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP34]], <vscale x 1 x i16> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF4X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e16_v_i16mf4x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP3]], <vscale x 1 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP4]], <vscale x 1 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg6.mask.nxv1i16.i64(<vscale x 1 x i16> [[TMP18]], <vscale x 1 x i16> [[TMP19]], <vscale x 1 x i16> [[TMP20]], <vscale x 1 x i16> [[TMP21]], <vscale x 1 x i16> [[TMP22]], <vscale x 1 x i16> [[TMP23]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] undef, <vscale x 1 x i16> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP26]], <vscale x 1 x i16> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP28]], <vscale x 1 x i16> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP30]], <vscale x 1 x i16> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP32]], <vscale x 1 x i16> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP34]], <vscale x 1 x i16> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF4X6_T]] [[TMP36]]
+//
+vint16mf4x6_t test_vlseg6e16_v_i16mf4x6_m (vbool64_t mask, vint16mf4x6_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg6e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e16_v_i16mf4x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP3]], <vscale x 1 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP4]], <vscale x 1 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP5]], <vscale x 1 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg7.mask.nxv1i16.i32(<vscale x 1 x i16> [[TMP21]], <vscale x 1 x i16> [[TMP22]], <vscale x 1 x i16> [[TMP23]], <vscale x 1 x i16> [[TMP24]], <vscale x 1 x i16> [[TMP25]], <vscale x 1 x i16> [[TMP26]], <vscale x 1 x i16> [[TMP27]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] undef, <vscale x 1 x i16> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP30]], <vscale x 1 x i16> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP32]], <vscale x 1 x i16> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP34]], <vscale x 1 x i16> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP36]], <vscale x 1 x i16> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP38]], <vscale x 1 x i16> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP40]], <vscale x 1 x i16> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF4X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e16_v_i16mf4x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP3]], <vscale x 1 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP4]], <vscale x 1 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP5]], <vscale x 1 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg7.mask.nxv1i16.i64(<vscale x 1 x i16> [[TMP21]], <vscale x 1 x i16> [[TMP22]], <vscale x 1 x i16> [[TMP23]], <vscale x 1 x i16> [[TMP24]], <vscale x 1 x i16> [[TMP25]], <vscale x 1 x i16> [[TMP26]], <vscale x 1 x i16> [[TMP27]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] undef, <vscale x 1 x i16> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP30]], <vscale x 1 x i16> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP32]], <vscale x 1 x i16> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP34]], <vscale x 1 x i16> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP36]], <vscale x 1 x i16> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP38]], <vscale x 1 x i16> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP40]], <vscale x 1 x i16> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF4X7_T]] [[TMP42]]
+//
+vint16mf4x7_t test_vlseg7e16_v_i16mf4x7_m (vbool64_t mask, vint16mf4x7_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg7e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e16_v_i16mf4x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP3]], <vscale x 1 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP4]], <vscale x 1 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP5]], <vscale x 1 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP6]], <vscale x 1 x i16> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg8.mask.nxv1i16.i32(<vscale x 1 x i16> [[TMP24]], <vscale x 1 x i16> [[TMP25]], <vscale x 1 x i16> [[TMP26]], <vscale x 1 x i16> [[TMP27]], <vscale x 1 x i16> [[TMP28]], <vscale x 1 x i16> [[TMP29]], <vscale x 1 x i16> [[TMP30]], <vscale x 1 x i16> [[TMP31]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] undef, <vscale x 1 x i16> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP34]], <vscale x 1 x i16> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP36]], <vscale x 1 x i16> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP38]], <vscale x 1 x i16> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP40]], <vscale x 1 x i16> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP42]], <vscale x 1 x i16> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP44]], <vscale x 1 x i16> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP46]], <vscale x 1 x i16> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF4X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e16_v_i16mf4x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP3]], <vscale x 1 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP4]], <vscale x 1 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP5]], <vscale x 1 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP6]], <vscale x 1 x i16> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg8.mask.nxv1i16.i64(<vscale x 1 x i16> [[TMP24]], <vscale x 1 x i16> [[TMP25]], <vscale x 1 x i16> [[TMP26]], <vscale x 1 x i16> [[TMP27]], <vscale x 1 x i16> [[TMP28]], <vscale x 1 x i16> [[TMP29]], <vscale x 1 x i16> [[TMP30]], <vscale x 1 x i16> [[TMP31]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] undef, <vscale x 1 x i16> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP34]], <vscale x 1 x i16> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP36]], <vscale x 1 x i16> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP38]], <vscale x 1 x i16> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP40]], <vscale x 1 x i16> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP42]], <vscale x 1 x i16> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP44]], <vscale x 1 x i16> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP46]], <vscale x 1 x i16> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF4X8_T]] [[TMP48]]
+//
+vint16mf4x8_t test_vlseg8e16_v_i16mf4x8_m (vbool64_t mask, vint16mf4x8_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg8e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e16_v_i16mf2x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X2_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X2_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg2.mask.nxv2i16.i32(<vscale x 2 x i16> [[TMP6]], <vscale x 2 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X2_T]] undef, <vscale x 2 x i16> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X2_T]] [[TMP10]], <vscale x 2 x i16> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF2X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e16_v_i16mf2x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X2_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X2_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg2.mask.nxv2i16.i64(<vscale x 2 x i16> [[TMP6]], <vscale x 2 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X2_T]] undef, <vscale x 2 x i16> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X2_T]] [[TMP10]], <vscale x 2 x i16> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF2X2_T]] [[TMP12]]
+//
+vint16mf2x2_t test_vlseg2e16_v_i16mf2x2_m (vbool32_t mask, vint16mf2x2_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg2e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e16_v_i16mf2x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg3.mask.nxv2i16.i32(<vscale x 2 x i16> [[TMP9]], <vscale x 2 x i16> [[TMP10]], <vscale x 2 x i16> [[TMP11]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T]] undef, <vscale x 2 x i16> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP14]], <vscale x 2 x i16> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP16]], <vscale x 2 x i16> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF2X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e16_v_i16mf2x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg3.mask.nxv2i16.i64(<vscale x 2 x i16> [[TMP9]], <vscale x 2 x i16> [[TMP10]], <vscale x 2 x i16> [[TMP11]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T]] undef, <vscale x 2 x i16> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP14]], <vscale x 2 x i16> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP16]], <vscale x 2 x i16> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF2X3_T]] [[TMP18]]
+//
+vint16mf2x3_t test_vlseg3e16_v_i16mf2x3_m (vbool32_t mask, vint16mf2x3_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg3e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e16_v_i16mf2x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg4.mask.nxv2i16.i32(<vscale x 2 x i16> [[TMP12]], <vscale x 2 x i16> [[TMP13]], <vscale x 2 x i16> [[TMP14]], <vscale x 2 x i16> [[TMP15]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] undef, <vscale x 2 x i16> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP18]], <vscale x 2 x i16> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP20]], <vscale x 2 x i16> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP22]], <vscale x 2 x i16> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF2X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e16_v_i16mf2x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg4.mask.nxv2i16.i64(<vscale x 2 x i16> [[TMP12]], <vscale x 2 x i16> [[TMP13]], <vscale x 2 x i16> [[TMP14]], <vscale x 2 x i16> [[TMP15]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] undef, <vscale x 2 x i16> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP18]], <vscale x 2 x i16> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP20]], <vscale x 2 x i16> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP22]], <vscale x 2 x i16> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF2X4_T]] [[TMP24]]
+//
+vint16mf2x4_t test_vlseg4e16_v_i16mf2x4_m (vbool32_t mask, vint16mf2x4_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg4e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e16_v_i16mf2x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP3]], <vscale x 2 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg5.mask.nxv2i16.i32(<vscale x 2 x i16> [[TMP15]], <vscale x 2 x i16> [[TMP16]], <vscale x 2 x i16> [[TMP17]], <vscale x 2 x i16> [[TMP18]], <vscale x 2 x i16> [[TMP19]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] undef, <vscale x 2 x i16> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP22]], <vscale x 2 x i16> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP24]], <vscale x 2 x i16> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP26]], <vscale x 2 x i16> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP28]], <vscale x 2 x i16> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF2X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e16_v_i16mf2x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP3]], <vscale x 2 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg5.mask.nxv2i16.i64(<vscale x 2 x i16> [[TMP15]], <vscale x 2 x i16> [[TMP16]], <vscale x 2 x i16> [[TMP17]], <vscale x 2 x i16> [[TMP18]], <vscale x 2 x i16> [[TMP19]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] undef, <vscale x 2 x i16> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP22]], <vscale x 2 x i16> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP24]], <vscale x 2 x i16> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP26]], <vscale x 2 x i16> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP28]], <vscale x 2 x i16> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF2X5_T]] [[TMP30]]
+//
+vint16mf2x5_t test_vlseg5e16_v_i16mf2x5_m (vbool32_t mask, vint16mf2x5_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg5e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e16_v_i16mf2x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP3]], <vscale x 2 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP4]], <vscale x 2 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg6.mask.nxv2i16.i32(<vscale x 2 x i16> [[TMP18]], <vscale x 2 x i16> [[TMP19]], <vscale x 2 x i16> [[TMP20]], <vscale x 2 x i16> [[TMP21]], <vscale x 2 x i16> [[TMP22]], <vscale x 2 x i16> [[TMP23]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] undef, <vscale x 2 x i16> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP26]], <vscale x 2 x i16> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP28]], <vscale x 2 x i16> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP30]], <vscale x 2 x i16> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP32]], <vscale x 2 x i16> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP34]], <vscale x 2 x i16> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF2X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e16_v_i16mf2x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP3]], <vscale x 2 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP4]], <vscale x 2 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg6.mask.nxv2i16.i64(<vscale x 2 x i16> [[TMP18]], <vscale x 2 x i16> [[TMP19]], <vscale x 2 x i16> [[TMP20]], <vscale x 2 x i16> [[TMP21]], <vscale x 2 x i16> [[TMP22]], <vscale x 2 x i16> [[TMP23]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] undef, <vscale x 2 x i16> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP26]], <vscale x 2 x i16> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP28]], <vscale x 2 x i16> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP30]], <vscale x 2 x i16> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP32]], <vscale x 2 x i16> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP34]], <vscale x 2 x i16> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF2X6_T]] [[TMP36]]
+//
+vint16mf2x6_t test_vlseg6e16_v_i16mf2x6_m (vbool32_t mask, vint16mf2x6_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg6e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e16_v_i16mf2x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP3]], <vscale x 2 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP4]], <vscale x 2 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP5]], <vscale x 2 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg7.mask.nxv2i16.i32(<vscale x 2 x i16> [[TMP21]], <vscale x 2 x i16> [[TMP22]], <vscale x 2 x i16> [[TMP23]], <vscale x 2 x i16> [[TMP24]], <vscale x 2 x i16> [[TMP25]], <vscale x 2 x i16> [[TMP26]], <vscale x 2 x i16> [[TMP27]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] undef, <vscale x 2 x i16> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP30]], <vscale x 2 x i16> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP32]], <vscale x 2 x i16> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP34]], <vscale x 2 x i16> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP36]], <vscale x 2 x i16> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP38]], <vscale x 2 x i16> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP40]], <vscale x 2 x i16> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF2X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e16_v_i16mf2x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP3]], <vscale x 2 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP4]], <vscale x 2 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP5]], <vscale x 2 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg7.mask.nxv2i16.i64(<vscale x 2 x i16> [[TMP21]], <vscale x 2 x i16> [[TMP22]], <vscale x 2 x i16> [[TMP23]], <vscale x 2 x i16> [[TMP24]], <vscale x 2 x i16> [[TMP25]], <vscale x 2 x i16> [[TMP26]], <vscale x 2 x i16> [[TMP27]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] undef, <vscale x 2 x i16> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP30]], <vscale x 2 x i16> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP32]], <vscale x 2 x i16> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP34]], <vscale x 2 x i16> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP36]], <vscale x 2 x i16> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP38]], <vscale x 2 x i16> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP40]], <vscale x 2 x i16> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF2X7_T]] [[TMP42]]
+//
+vint16mf2x7_t test_vlseg7e16_v_i16mf2x7_m (vbool32_t mask, vint16mf2x7_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg7e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e16_v_i16mf2x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP3]], <vscale x 2 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP4]], <vscale x 2 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP5]], <vscale x 2 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP6]], <vscale x 2 x i16> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg8.mask.nxv2i16.i32(<vscale x 2 x i16> [[TMP24]], <vscale x 2 x i16> [[TMP25]], <vscale x 2 x i16> [[TMP26]], <vscale x 2 x i16> [[TMP27]], <vscale x 2 x i16> [[TMP28]], <vscale x 2 x i16> [[TMP29]], <vscale x 2 x i16> [[TMP30]], <vscale x 2 x i16> [[TMP31]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] undef, <vscale x 2 x i16> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP34]], <vscale x 2 x i16> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP36]], <vscale x 2 x i16> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP38]], <vscale x 2 x i16> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP40]], <vscale x 2 x i16> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP42]], <vscale x 2 x i16> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP44]], <vscale x 2 x i16> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP46]], <vscale x 2 x i16> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF2X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e16_v_i16mf2x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP3]], <vscale x 2 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP4]], <vscale x 2 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP5]], <vscale x 2 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP6]], <vscale x 2 x i16> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg8.mask.nxv2i16.i64(<vscale x 2 x i16> [[TMP24]], <vscale x 2 x i16> [[TMP25]], <vscale x 2 x i16> [[TMP26]], <vscale x 2 x i16> [[TMP27]], <vscale x 2 x i16> [[TMP28]], <vscale x 2 x i16> [[TMP29]], <vscale x 2 x i16> [[TMP30]], <vscale x 2 x i16> [[TMP31]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] undef, <vscale x 2 x i16> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP34]], <vscale x 2 x i16> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP36]], <vscale x 2 x i16> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP38]], <vscale x 2 x i16> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP40]], <vscale x 2 x i16> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP42]], <vscale x 2 x i16> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP44]], <vscale x 2 x i16> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP46]], <vscale x 2 x i16> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF2X8_T]] [[TMP48]]
+//
+vint16mf2x8_t test_vlseg8e16_v_i16mf2x8_m (vbool32_t mask, vint16mf2x8_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg8e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e16_v_i16m1x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X2_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X2_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg2.mask.nxv4i16.i32(<vscale x 4 x i16> [[TMP6]], <vscale x 4 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X2_T]] undef, <vscale x 4 x i16> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X2_T]] [[TMP10]], <vscale x 4 x i16> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16M1X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e16_v_i16m1x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X2_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X2_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg2.mask.nxv4i16.i64(<vscale x 4 x i16> [[TMP6]], <vscale x 4 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X2_T]] undef, <vscale x 4 x i16> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X2_T]] [[TMP10]], <vscale x 4 x i16> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16M1X2_T]] [[TMP12]]
+//
+vint16m1x2_t test_vlseg2e16_v_i16m1x2_m (vbool16_t mask, vint16m1x2_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg2e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e16_v_i16m1x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg3.mask.nxv4i16.i32(<vscale x 4 x i16> [[TMP9]], <vscale x 4 x i16> [[TMP10]], <vscale x 4 x i16> [[TMP11]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T]] undef, <vscale x 4 x i16> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP14]], <vscale x 4 x i16> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP16]], <vscale x 4 x i16> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16M1X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e16_v_i16m1x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg3.mask.nxv4i16.i64(<vscale x 4 x i16> [[TMP9]], <vscale x 4 x i16> [[TMP10]], <vscale x 4 x i16> [[TMP11]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T]] undef, <vscale x 4 x i16> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP14]], <vscale x 4 x i16> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP16]], <vscale x 4 x i16> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16M1X3_T]] [[TMP18]]
+//
+vint16m1x3_t test_vlseg3e16_v_i16m1x3_m (vbool16_t mask, vint16m1x3_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg3e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e16_v_i16m1x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg4.mask.nxv4i16.i32(<vscale x 4 x i16> [[TMP12]], <vscale x 4 x i16> [[TMP13]], <vscale x 4 x i16> [[TMP14]], <vscale x 4 x i16> [[TMP15]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] undef, <vscale x 4 x i16> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP18]], <vscale x 4 x i16> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP20]], <vscale x 4 x i16> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP22]], <vscale x 4 x i16> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16M1X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e16_v_i16m1x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg4.mask.nxv4i16.i64(<vscale x 4 x i16> [[TMP12]], <vscale x 4 x i16> [[TMP13]], <vscale x 4 x i16> [[TMP14]], <vscale x 4 x i16> [[TMP15]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] undef, <vscale x 4 x i16> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP18]], <vscale x 4 x i16> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP20]], <vscale x 4 x i16> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP22]], <vscale x 4 x i16> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16M1X4_T]] [[TMP24]]
+//
+vint16m1x4_t test_vlseg4e16_v_i16m1x4_m (vbool16_t mask, vint16m1x4_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg4e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e16_v_i16m1x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP3]], <vscale x 4 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg5.mask.nxv4i16.i32(<vscale x 4 x i16> [[TMP15]], <vscale x 4 x i16> [[TMP16]], <vscale x 4 x i16> [[TMP17]], <vscale x 4 x i16> [[TMP18]], <vscale x 4 x i16> [[TMP19]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] undef, <vscale x 4 x i16> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP22]], <vscale x 4 x i16> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP24]], <vscale x 4 x i16> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP26]], <vscale x 4 x i16> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP28]], <vscale x 4 x i16> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16M1X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e16_v_i16m1x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP3]], <vscale x 4 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg5.mask.nxv4i16.i64(<vscale x 4 x i16> [[TMP15]], <vscale x 4 x i16> [[TMP16]], <vscale x 4 x i16> [[TMP17]], <vscale x 4 x i16> [[TMP18]], <vscale x 4 x i16> [[TMP19]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] undef, <vscale x 4 x i16> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP22]], <vscale x 4 x i16> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP24]], <vscale x 4 x i16> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP26]], <vscale x 4 x i16> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP28]], <vscale x 4 x i16> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16M1X5_T]] [[TMP30]]
+//
+vint16m1x5_t test_vlseg5e16_v_i16m1x5_m (vbool16_t mask, vint16m1x5_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg5e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e16_v_i16m1x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP3]], <vscale x 4 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP4]], <vscale x 4 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg6.mask.nxv4i16.i32(<vscale x 4 x i16> [[TMP18]], <vscale x 4 x i16> [[TMP19]], <vscale x 4 x i16> [[TMP20]], <vscale x 4 x i16> [[TMP21]], <vscale x 4 x i16> [[TMP22]], <vscale x 4 x i16> [[TMP23]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] undef, <vscale x 4 x i16> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP26]], <vscale x 4 x i16> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP28]], <vscale x 4 x i16> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP30]], <vscale x 4 x i16> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP32]], <vscale x 4 x i16> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP34]], <vscale x 4 x i16> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16M1X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e16_v_i16m1x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP3]], <vscale x 4 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP4]], <vscale x 4 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg6.mask.nxv4i16.i64(<vscale x 4 x i16> [[TMP18]], <vscale x 4 x i16> [[TMP19]], <vscale x 4 x i16> [[TMP20]], <vscale x 4 x i16> [[TMP21]], <vscale x 4 x i16> [[TMP22]], <vscale x 4 x i16> [[TMP23]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] undef, <vscale x 4 x i16> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP26]], <vscale x 4 x i16> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP28]], <vscale x 4 x i16> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP30]], <vscale x 4 x i16> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP32]], <vscale x 4 x i16> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP34]], <vscale x 4 x i16> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16M1X6_T]] [[TMP36]]
+//
+vint16m1x6_t test_vlseg6e16_v_i16m1x6_m (vbool16_t mask, vint16m1x6_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg6e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e16_v_i16m1x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP3]], <vscale x 4 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP4]], <vscale x 4 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP5]], <vscale x 4 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg7.mask.nxv4i16.i32(<vscale x 4 x i16> [[TMP21]], <vscale x 4 x i16> [[TMP22]], <vscale x 4 x i16> [[TMP23]], <vscale x 4 x i16> [[TMP24]], <vscale x 4 x i16> [[TMP25]], <vscale x 4 x i16> [[TMP26]], <vscale x 4 x i16> [[TMP27]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] undef, <vscale x 4 x i16> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP30]], <vscale x 4 x i16> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP32]], <vscale x 4 x i16> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP34]], <vscale x 4 x i16> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP36]], <vscale x 4 x i16> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP38]], <vscale x 4 x i16> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP40]], <vscale x 4 x i16> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16M1X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e16_v_i16m1x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP3]], <vscale x 4 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP4]], <vscale x 4 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP5]], <vscale x 4 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg7.mask.nxv4i16.i64(<vscale x 4 x i16> [[TMP21]], <vscale x 4 x i16> [[TMP22]], <vscale x 4 x i16> [[TMP23]], <vscale x 4 x i16> [[TMP24]], <vscale x 4 x i16> [[TMP25]], <vscale x 4 x i16> [[TMP26]], <vscale x 4 x i16> [[TMP27]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] undef, <vscale x 4 x i16> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP30]], <vscale x 4 x i16> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP32]], <vscale x 4 x i16> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP34]], <vscale x 4 x i16> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP36]], <vscale x 4 x i16> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP38]], <vscale x 4 x i16> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP40]], <vscale x 4 x i16> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16M1X7_T]] [[TMP42]]
+//
+vint16m1x7_t test_vlseg7e16_v_i16m1x7_m (vbool16_t mask, vint16m1x7_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg7e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e16_v_i16m1x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP3]], <vscale x 4 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP4]], <vscale x 4 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP5]], <vscale x 4 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP6]], <vscale x 4 x i16> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg8.mask.nxv4i16.i32(<vscale x 4 x i16> [[TMP24]], <vscale x 4 x i16> [[TMP25]], <vscale x 4 x i16> [[TMP26]], <vscale x 4 x i16> [[TMP27]], <vscale x 4 x i16> [[TMP28]], <vscale x 4 x i16> [[TMP29]], <vscale x 4 x i16> [[TMP30]], <vscale x 4 x i16> [[TMP31]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] undef, <vscale x 4 x i16> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP34]], <vscale x 4 x i16> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP36]], <vscale x 4 x i16> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP38]], <vscale x 4 x i16> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP40]], <vscale x 4 x i16> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP42]], <vscale x 4 x i16> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP44]], <vscale x 4 x i16> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP46]], <vscale x 4 x i16> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16M1X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e16_v_i16m1x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP3]], <vscale x 4 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP4]], <vscale x 4 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP5]], <vscale x 4 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP6]], <vscale x 4 x i16> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg8.mask.nxv4i16.i64(<vscale x 4 x i16> [[TMP24]], <vscale x 4 x i16> [[TMP25]], <vscale x 4 x i16> [[TMP26]], <vscale x 4 x i16> [[TMP27]], <vscale x 4 x i16> [[TMP28]], <vscale x 4 x i16> [[TMP29]], <vscale x 4 x i16> [[TMP30]], <vscale x 4 x i16> [[TMP31]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] undef, <vscale x 4 x i16> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP34]], <vscale x 4 x i16> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP36]], <vscale x 4 x i16> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP38]], <vscale x 4 x i16> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP40]], <vscale x 4 x i16> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP42]], <vscale x 4 x i16> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP44]], <vscale x 4 x i16> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP46]], <vscale x 4 x i16> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16M1X8_T]] [[TMP48]]
+//
+vint16m1x8_t test_vlseg8e16_v_i16m1x8_m (vbool16_t mask, vint16m1x8_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg8e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e16_v_i16m2x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X2_T:%.*]] undef, <vscale x 8 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X2_T]] [[TMP0]], <vscale x 8 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg2.mask.nxv8i16.i32(<vscale x 8 x i16> [[TMP6]], <vscale x 8 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X2_T]] undef, <vscale x 8 x i16> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X2_T]] [[TMP10]], <vscale x 8 x i16> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16M2X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e16_v_i16m2x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X2_T:%.*]] undef, <vscale x 8 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X2_T]] [[TMP0]], <vscale x 8 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg2.mask.nxv8i16.i64(<vscale x 8 x i16> [[TMP6]], <vscale x 8 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X2_T]] undef, <vscale x 8 x i16> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X2_T]] [[TMP10]], <vscale x 8 x i16> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16M2X2_T]] [[TMP12]]
+//
+vint16m2x2_t test_vlseg2e16_v_i16m2x2_m (vbool8_t mask, vint16m2x2_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg2e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e16_v_i16m2x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T:%.*]] undef, <vscale x 8 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP0]], <vscale x 8 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP1]], <vscale x 8 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg3.mask.nxv8i16.i32(<vscale x 8 x i16> [[TMP9]], <vscale x 8 x i16> [[TMP10]], <vscale x 8 x i16> [[TMP11]], i16* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T]] undef, <vscale x 8 x i16> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP14]], <vscale x 8 x i16> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP16]], <vscale x 8 x i16> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16M2X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e16_v_i16m2x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T:%.*]] undef, <vscale x 8 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP0]], <vscale x 8 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP1]], <vscale x 8 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg3.mask.nxv8i16.i64(<vscale x 8 x i16> [[TMP9]], <vscale x 8 x i16> [[TMP10]], <vscale x 8 x i16> [[TMP11]], i16* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T]] undef, <vscale x 8 x i16> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP14]], <vscale x 8 x i16> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP16]], <vscale x 8 x i16> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16M2X3_T]] [[TMP18]]
+//
+vint16m2x3_t test_vlseg3e16_v_i16m2x3_m (vbool8_t mask, vint16m2x3_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg3e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e16_v_i16m2x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T:%.*]] undef, <vscale x 8 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP0]], <vscale x 8 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP1]], <vscale x 8 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP2]], <vscale x 8 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg4.mask.nxv8i16.i32(<vscale x 8 x i16> [[TMP12]], <vscale x 8 x i16> [[TMP13]], <vscale x 8 x i16> [[TMP14]], <vscale x 8 x i16> [[TMP15]], i16* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] undef, <vscale x 8 x i16> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP18]], <vscale x 8 x i16> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP20]], <vscale x 8 x i16> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP22]], <vscale x 8 x i16> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16M2X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e16_v_i16m2x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T:%.*]] undef, <vscale x 8 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP0]], <vscale x 8 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP1]], <vscale x 8 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP2]], <vscale x 8 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg4.mask.nxv8i16.i64(<vscale x 8 x i16> [[TMP12]], <vscale x 8 x i16> [[TMP13]], <vscale x 8 x i16> [[TMP14]], <vscale x 8 x i16> [[TMP15]], i16* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] undef, <vscale x 8 x i16> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP18]], <vscale x 8 x i16> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP20]], <vscale x 8 x i16> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP22]], <vscale x 8 x i16> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16M2X4_T]] [[TMP24]]
+//
+vint16m2x4_t test_vlseg4e16_v_i16m2x4_m (vbool8_t mask, vint16m2x4_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg4e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e16_v_i16m4x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M4X2_T:%.*]] undef, <vscale x 16 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M4X2_T]] [[TMP0]], <vscale x 16 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT16M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT16M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 16 x i16>, <vscale x 16 x i16> } @llvm.riscv.vlseg2.mask.nxv16i16.i32(<vscale x 16 x i16> [[TMP6]], <vscale x 16 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i16> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16M4X2_T]] undef, <vscale x 16 x i16> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i16> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16M4X2_T]] [[TMP10]], <vscale x 16 x i16> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16M4X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e16_v_i16m4x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M4X2_T:%.*]] undef, <vscale x 16 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M4X2_T]] [[TMP0]], <vscale x 16 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT16M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT16M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 16 x i16>, <vscale x 16 x i16> } @llvm.riscv.vlseg2.mask.nxv16i16.i64(<vscale x 16 x i16> [[TMP6]], <vscale x 16 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i16> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16M4X2_T]] undef, <vscale x 16 x i16> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i16> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16M4X2_T]] [[TMP10]], <vscale x 16 x i16> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16M4X2_T]] [[TMP12]]
+//
+vint16m4x2_t test_vlseg2e16_v_i16m4x2_m (vbool4_t mask, vint16m4x2_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg2e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_i32mf2x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X2_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X2_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg2.mask.nxv1i32.i32(<vscale x 1 x i32> [[TMP6]], <vscale x 1 x i32> [[TMP7]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X2_T]] undef, <vscale x 1 x i32> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X2_T]] [[TMP10]], <vscale x 1 x i32> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32MF2X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_i32mf2x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X2_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X2_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg2.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP6]], <vscale x 1 x i32> [[TMP7]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X2_T]] undef, <vscale x 1 x i32> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X2_T]] [[TMP10]], <vscale x 1 x i32> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32MF2X2_T]] [[TMP12]]
+//
+vint32mf2x2_t test_vlseg2e32_v_i32mf2x2_m (vbool64_t mask, vint32mf2x2_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg2e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e32_v_i32mf2x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg3.mask.nxv1i32.i32(<vscale x 1 x i32> [[TMP9]], <vscale x 1 x i32> [[TMP10]], <vscale x 1 x i32> [[TMP11]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T]] undef, <vscale x 1 x i32> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP14]], <vscale x 1 x i32> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP16]], <vscale x 1 x i32> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32MF2X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e32_v_i32mf2x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg3.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP9]], <vscale x 1 x i32> [[TMP10]], <vscale x 1 x i32> [[TMP11]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T]] undef, <vscale x 1 x i32> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP14]], <vscale x 1 x i32> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP16]], <vscale x 1 x i32> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32MF2X3_T]] [[TMP18]]
+//
+vint32mf2x3_t test_vlseg3e32_v_i32mf2x3_m (vbool64_t mask, vint32mf2x3_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg3e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e32_v_i32mf2x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg4.mask.nxv1i32.i32(<vscale x 1 x i32> [[TMP12]], <vscale x 1 x i32> [[TMP13]], <vscale x 1 x i32> [[TMP14]], <vscale x 1 x i32> [[TMP15]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] undef, <vscale x 1 x i32> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP18]], <vscale x 1 x i32> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP20]], <vscale x 1 x i32> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP22]], <vscale x 1 x i32> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32MF2X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e32_v_i32mf2x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg4.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP12]], <vscale x 1 x i32> [[TMP13]], <vscale x 1 x i32> [[TMP14]], <vscale x 1 x i32> [[TMP15]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] undef, <vscale x 1 x i32> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP18]], <vscale x 1 x i32> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP20]], <vscale x 1 x i32> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP22]], <vscale x 1 x i32> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32MF2X4_T]] [[TMP24]]
+//
+vint32mf2x4_t test_vlseg4e32_v_i32mf2x4_m (vbool64_t mask, vint32mf2x4_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg4e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e32_v_i32mf2x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP3]], <vscale x 1 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg5.mask.nxv1i32.i32(<vscale x 1 x i32> [[TMP15]], <vscale x 1 x i32> [[TMP16]], <vscale x 1 x i32> [[TMP17]], <vscale x 1 x i32> [[TMP18]], <vscale x 1 x i32> [[TMP19]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] undef, <vscale x 1 x i32> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP22]], <vscale x 1 x i32> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP24]], <vscale x 1 x i32> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP26]], <vscale x 1 x i32> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP28]], <vscale x 1 x i32> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32MF2X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e32_v_i32mf2x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP3]], <vscale x 1 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg5.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP15]], <vscale x 1 x i32> [[TMP16]], <vscale x 1 x i32> [[TMP17]], <vscale x 1 x i32> [[TMP18]], <vscale x 1 x i32> [[TMP19]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] undef, <vscale x 1 x i32> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP22]], <vscale x 1 x i32> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP24]], <vscale x 1 x i32> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP26]], <vscale x 1 x i32> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP28]], <vscale x 1 x i32> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32MF2X5_T]] [[TMP30]]
+//
+vint32mf2x5_t test_vlseg5e32_v_i32mf2x5_m (vbool64_t mask, vint32mf2x5_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg5e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e32_v_i32mf2x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP3]], <vscale x 1 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP4]], <vscale x 1 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg6.mask.nxv1i32.i32(<vscale x 1 x i32> [[TMP18]], <vscale x 1 x i32> [[TMP19]], <vscale x 1 x i32> [[TMP20]], <vscale x 1 x i32> [[TMP21]], <vscale x 1 x i32> [[TMP22]], <vscale x 1 x i32> [[TMP23]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] undef, <vscale x 1 x i32> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP26]], <vscale x 1 x i32> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP28]], <vscale x 1 x i32> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP30]], <vscale x 1 x i32> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP32]], <vscale x 1 x i32> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP34]], <vscale x 1 x i32> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32MF2X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e32_v_i32mf2x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP3]], <vscale x 1 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP4]], <vscale x 1 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg6.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP18]], <vscale x 1 x i32> [[TMP19]], <vscale x 1 x i32> [[TMP20]], <vscale x 1 x i32> [[TMP21]], <vscale x 1 x i32> [[TMP22]], <vscale x 1 x i32> [[TMP23]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] undef, <vscale x 1 x i32> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP26]], <vscale x 1 x i32> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP28]], <vscale x 1 x i32> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP30]], <vscale x 1 x i32> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP32]], <vscale x 1 x i32> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP34]], <vscale x 1 x i32> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32MF2X6_T]] [[TMP36]]
+//
+vint32mf2x6_t test_vlseg6e32_v_i32mf2x6_m (vbool64_t mask, vint32mf2x6_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg6e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e32_v_i32mf2x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP3]], <vscale x 1 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP4]], <vscale x 1 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP5]], <vscale x 1 x i32> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg7.mask.nxv1i32.i32(<vscale x 1 x i32> [[TMP21]], <vscale x 1 x i32> [[TMP22]], <vscale x 1 x i32> [[TMP23]], <vscale x 1 x i32> [[TMP24]], <vscale x 1 x i32> [[TMP25]], <vscale x 1 x i32> [[TMP26]], <vscale x 1 x i32> [[TMP27]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] undef, <vscale x 1 x i32> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP30]], <vscale x 1 x i32> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP32]], <vscale x 1 x i32> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP34]], <vscale x 1 x i32> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP36]], <vscale x 1 x i32> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP38]], <vscale x 1 x i32> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP40]], <vscale x 1 x i32> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32MF2X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e32_v_i32mf2x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP3]], <vscale x 1 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP4]], <vscale x 1 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP5]], <vscale x 1 x i32> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg7.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP21]], <vscale x 1 x i32> [[TMP22]], <vscale x 1 x i32> [[TMP23]], <vscale x 1 x i32> [[TMP24]], <vscale x 1 x i32> [[TMP25]], <vscale x 1 x i32> [[TMP26]], <vscale x 1 x i32> [[TMP27]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] undef, <vscale x 1 x i32> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP30]], <vscale x 1 x i32> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP32]], <vscale x 1 x i32> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP34]], <vscale x 1 x i32> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP36]], <vscale x 1 x i32> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP38]], <vscale x 1 x i32> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP40]], <vscale x 1 x i32> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32MF2X7_T]] [[TMP42]]
+//
+vint32mf2x7_t test_vlseg7e32_v_i32mf2x7_m (vbool64_t mask, vint32mf2x7_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg7e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e32_v_i32mf2x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP3]], <vscale x 1 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP4]], <vscale x 1 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP5]], <vscale x 1 x i32> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP6]], <vscale x 1 x i32> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg8.mask.nxv1i32.i32(<vscale x 1 x i32> [[TMP24]], <vscale x 1 x i32> [[TMP25]], <vscale x 1 x i32> [[TMP26]], <vscale x 1 x i32> [[TMP27]], <vscale x 1 x i32> [[TMP28]], <vscale x 1 x i32> [[TMP29]], <vscale x 1 x i32> [[TMP30]], <vscale x 1 x i32> [[TMP31]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] undef, <vscale x 1 x i32> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP34]], <vscale x 1 x i32> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP36]], <vscale x 1 x i32> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP38]], <vscale x 1 x i32> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP40]], <vscale x 1 x i32> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP42]], <vscale x 1 x i32> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP44]], <vscale x 1 x i32> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP46]], <vscale x 1 x i32> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32MF2X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e32_v_i32mf2x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP3]], <vscale x 1 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP4]], <vscale x 1 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP5]], <vscale x 1 x i32> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP6]], <vscale x 1 x i32> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg8.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP24]], <vscale x 1 x i32> [[TMP25]], <vscale x 1 x i32> [[TMP26]], <vscale x 1 x i32> [[TMP27]], <vscale x 1 x i32> [[TMP28]], <vscale x 1 x i32> [[TMP29]], <vscale x 1 x i32> [[TMP30]], <vscale x 1 x i32> [[TMP31]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] undef, <vscale x 1 x i32> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP34]], <vscale x 1 x i32> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP36]], <vscale x 1 x i32> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP38]], <vscale x 1 x i32> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP40]], <vscale x 1 x i32> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP42]], <vscale x 1 x i32> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP44]], <vscale x 1 x i32> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP46]], <vscale x 1 x i32> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32MF2X8_T]] [[TMP48]]
+//
+vint32mf2x8_t test_vlseg8e32_v_i32mf2x8_m (vbool64_t mask, vint32mf2x8_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg8e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_i32m1x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X2_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X2_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg2.mask.nxv2i32.i32(<vscale x 2 x i32> [[TMP6]], <vscale x 2 x i32> [[TMP7]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X2_T]] undef, <vscale x 2 x i32> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X2_T]] [[TMP10]], <vscale x 2 x i32> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32M1X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_i32m1x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X2_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X2_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg2.mask.nxv2i32.i64(<vscale x 2 x i32> [[TMP6]], <vscale x 2 x i32> [[TMP7]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X2_T]] undef, <vscale x 2 x i32> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X2_T]] [[TMP10]], <vscale x 2 x i32> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32M1X2_T]] [[TMP12]]
+//
+vint32m1x2_t test_vlseg2e32_v_i32m1x2_m (vbool32_t mask, vint32m1x2_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg2e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e32_v_i32m1x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg3.mask.nxv2i32.i32(<vscale x 2 x i32> [[TMP9]], <vscale x 2 x i32> [[TMP10]], <vscale x 2 x i32> [[TMP11]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T]] undef, <vscale x 2 x i32> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP14]], <vscale x 2 x i32> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP16]], <vscale x 2 x i32> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32M1X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e32_v_i32m1x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg3.mask.nxv2i32.i64(<vscale x 2 x i32> [[TMP9]], <vscale x 2 x i32> [[TMP10]], <vscale x 2 x i32> [[TMP11]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T]] undef, <vscale x 2 x i32> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP14]], <vscale x 2 x i32> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP16]], <vscale x 2 x i32> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32M1X3_T]] [[TMP18]]
+//
+vint32m1x3_t test_vlseg3e32_v_i32m1x3_m (vbool32_t mask, vint32m1x3_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg3e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e32_v_i32m1x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg4.mask.nxv2i32.i32(<vscale x 2 x i32> [[TMP12]], <vscale x 2 x i32> [[TMP13]], <vscale x 2 x i32> [[TMP14]], <vscale x 2 x i32> [[TMP15]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] undef, <vscale x 2 x i32> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP18]], <vscale x 2 x i32> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP20]], <vscale x 2 x i32> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP22]], <vscale x 2 x i32> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32M1X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e32_v_i32m1x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg4.mask.nxv2i32.i64(<vscale x 2 x i32> [[TMP12]], <vscale x 2 x i32> [[TMP13]], <vscale x 2 x i32> [[TMP14]], <vscale x 2 x i32> [[TMP15]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] undef, <vscale x 2 x i32> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP18]], <vscale x 2 x i32> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP20]], <vscale x 2 x i32> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP22]], <vscale x 2 x i32> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32M1X4_T]] [[TMP24]]
+//
+vint32m1x4_t test_vlseg4e32_v_i32m1x4_m (vbool32_t mask, vint32m1x4_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg4e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e32_v_i32m1x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP3]], <vscale x 2 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg5.mask.nxv2i32.i32(<vscale x 2 x i32> [[TMP15]], <vscale x 2 x i32> [[TMP16]], <vscale x 2 x i32> [[TMP17]], <vscale x 2 x i32> [[TMP18]], <vscale x 2 x i32> [[TMP19]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] undef, <vscale x 2 x i32> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP22]], <vscale x 2 x i32> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP24]], <vscale x 2 x i32> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP26]], <vscale x 2 x i32> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP28]], <vscale x 2 x i32> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32M1X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e32_v_i32m1x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP3]], <vscale x 2 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg5.mask.nxv2i32.i64(<vscale x 2 x i32> [[TMP15]], <vscale x 2 x i32> [[TMP16]], <vscale x 2 x i32> [[TMP17]], <vscale x 2 x i32> [[TMP18]], <vscale x 2 x i32> [[TMP19]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] undef, <vscale x 2 x i32> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP22]], <vscale x 2 x i32> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP24]], <vscale x 2 x i32> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP26]], <vscale x 2 x i32> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP28]], <vscale x 2 x i32> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32M1X5_T]] [[TMP30]]
+//
+vint32m1x5_t test_vlseg5e32_v_i32m1x5_m (vbool32_t mask, vint32m1x5_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg5e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e32_v_i32m1x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP3]], <vscale x 2 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP4]], <vscale x 2 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg6.mask.nxv2i32.i32(<vscale x 2 x i32> [[TMP18]], <vscale x 2 x i32> [[TMP19]], <vscale x 2 x i32> [[TMP20]], <vscale x 2 x i32> [[TMP21]], <vscale x 2 x i32> [[TMP22]], <vscale x 2 x i32> [[TMP23]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] undef, <vscale x 2 x i32> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP26]], <vscale x 2 x i32> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP28]], <vscale x 2 x i32> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP30]], <vscale x 2 x i32> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP32]], <vscale x 2 x i32> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP34]], <vscale x 2 x i32> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32M1X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e32_v_i32m1x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP3]], <vscale x 2 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP4]], <vscale x 2 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg6.mask.nxv2i32.i64(<vscale x 2 x i32> [[TMP18]], <vscale x 2 x i32> [[TMP19]], <vscale x 2 x i32> [[TMP20]], <vscale x 2 x i32> [[TMP21]], <vscale x 2 x i32> [[TMP22]], <vscale x 2 x i32> [[TMP23]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] undef, <vscale x 2 x i32> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP26]], <vscale x 2 x i32> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP28]], <vscale x 2 x i32> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP30]], <vscale x 2 x i32> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP32]], <vscale x 2 x i32> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP34]], <vscale x 2 x i32> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32M1X6_T]] [[TMP36]]
+//
+vint32m1x6_t test_vlseg6e32_v_i32m1x6_m (vbool32_t mask, vint32m1x6_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg6e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e32_v_i32m1x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP3]], <vscale x 2 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP4]], <vscale x 2 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP5]], <vscale x 2 x i32> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg7.mask.nxv2i32.i32(<vscale x 2 x i32> [[TMP21]], <vscale x 2 x i32> [[TMP22]], <vscale x 2 x i32> [[TMP23]], <vscale x 2 x i32> [[TMP24]], <vscale x 2 x i32> [[TMP25]], <vscale x 2 x i32> [[TMP26]], <vscale x 2 x i32> [[TMP27]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] undef, <vscale x 2 x i32> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP30]], <vscale x 2 x i32> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP32]], <vscale x 2 x i32> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP34]], <vscale x 2 x i32> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP36]], <vscale x 2 x i32> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP38]], <vscale x 2 x i32> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP40]], <vscale x 2 x i32> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32M1X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e32_v_i32m1x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP3]], <vscale x 2 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP4]], <vscale x 2 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP5]], <vscale x 2 x i32> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg7.mask.nxv2i32.i64(<vscale x 2 x i32> [[TMP21]], <vscale x 2 x i32> [[TMP22]], <vscale x 2 x i32> [[TMP23]], <vscale x 2 x i32> [[TMP24]], <vscale x 2 x i32> [[TMP25]], <vscale x 2 x i32> [[TMP26]], <vscale x 2 x i32> [[TMP27]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] undef, <vscale x 2 x i32> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP30]], <vscale x 2 x i32> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP32]], <vscale x 2 x i32> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP34]], <vscale x 2 x i32> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP36]], <vscale x 2 x i32> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP38]], <vscale x 2 x i32> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP40]], <vscale x 2 x i32> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32M1X7_T]] [[TMP42]]
+//
+vint32m1x7_t test_vlseg7e32_v_i32m1x7_m (vbool32_t mask, vint32m1x7_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg7e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e32_v_i32m1x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP3]], <vscale x 2 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP4]], <vscale x 2 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP5]], <vscale x 2 x i32> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP6]], <vscale x 2 x i32> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg8.mask.nxv2i32.i32(<vscale x 2 x i32> [[TMP24]], <vscale x 2 x i32> [[TMP25]], <vscale x 2 x i32> [[TMP26]], <vscale x 2 x i32> [[TMP27]], <vscale x 2 x i32> [[TMP28]], <vscale x 2 x i32> [[TMP29]], <vscale x 2 x i32> [[TMP30]], <vscale x 2 x i32> [[TMP31]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] undef, <vscale x 2 x i32> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP34]], <vscale x 2 x i32> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP36]], <vscale x 2 x i32> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP38]], <vscale x 2 x i32> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP40]], <vscale x 2 x i32> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP42]], <vscale x 2 x i32> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP44]], <vscale x 2 x i32> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP46]], <vscale x 2 x i32> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32M1X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e32_v_i32m1x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP3]], <vscale x 2 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP4]], <vscale x 2 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP5]], <vscale x 2 x i32> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP6]], <vscale x 2 x i32> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg8.mask.nxv2i32.i64(<vscale x 2 x i32> [[TMP24]], <vscale x 2 x i32> [[TMP25]], <vscale x 2 x i32> [[TMP26]], <vscale x 2 x i32> [[TMP27]], <vscale x 2 x i32> [[TMP28]], <vscale x 2 x i32> [[TMP29]], <vscale x 2 x i32> [[TMP30]], <vscale x 2 x i32> [[TMP31]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] undef, <vscale x 2 x i32> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP34]], <vscale x 2 x i32> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP36]], <vscale x 2 x i32> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP38]], <vscale x 2 x i32> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP40]], <vscale x 2 x i32> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP42]], <vscale x 2 x i32> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP44]], <vscale x 2 x i32> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP46]], <vscale x 2 x i32> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32M1X8_T]] [[TMP48]]
+//
+vint32m1x8_t test_vlseg8e32_v_i32m1x8_m (vbool32_t mask, vint32m1x8_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg8e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_i32m2x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X2_T:%.*]] undef, <vscale x 4 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X2_T]] [[TMP0]], <vscale x 4 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg2.mask.nxv4i32.i32(<vscale x 4 x i32> [[TMP6]], <vscale x 4 x i32> [[TMP7]], i32* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X2_T]] undef, <vscale x 4 x i32> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X2_T]] [[TMP10]], <vscale x 4 x i32> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32M2X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_i32m2x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X2_T:%.*]] undef, <vscale x 4 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X2_T]] [[TMP0]], <vscale x 4 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg2.mask.nxv4i32.i64(<vscale x 4 x i32> [[TMP6]], <vscale x 4 x i32> [[TMP7]], i32* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X2_T]] undef, <vscale x 4 x i32> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X2_T]] [[TMP10]], <vscale x 4 x i32> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32M2X2_T]] [[TMP12]]
+//
+vint32m2x2_t test_vlseg2e32_v_i32m2x2_m (vbool16_t mask, vint32m2x2_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg2e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e32_v_i32m2x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T:%.*]] undef, <vscale x 4 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP0]], <vscale x 4 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP1]], <vscale x 4 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg3.mask.nxv4i32.i32(<vscale x 4 x i32> [[TMP9]], <vscale x 4 x i32> [[TMP10]], <vscale x 4 x i32> [[TMP11]], i32* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T]] undef, <vscale x 4 x i32> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP14]], <vscale x 4 x i32> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP16]], <vscale x 4 x i32> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32M2X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e32_v_i32m2x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T:%.*]] undef, <vscale x 4 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP0]], <vscale x 4 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP1]], <vscale x 4 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg3.mask.nxv4i32.i64(<vscale x 4 x i32> [[TMP9]], <vscale x 4 x i32> [[TMP10]], <vscale x 4 x i32> [[TMP11]], i32* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T]] undef, <vscale x 4 x i32> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP14]], <vscale x 4 x i32> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP16]], <vscale x 4 x i32> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32M2X3_T]] [[TMP18]]
+//
+vint32m2x3_t test_vlseg3e32_v_i32m2x3_m (vbool16_t mask, vint32m2x3_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg3e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e32_v_i32m2x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T:%.*]] undef, <vscale x 4 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP0]], <vscale x 4 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP1]], <vscale x 4 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP2]], <vscale x 4 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg4.mask.nxv4i32.i32(<vscale x 4 x i32> [[TMP12]], <vscale x 4 x i32> [[TMP13]], <vscale x 4 x i32> [[TMP14]], <vscale x 4 x i32> [[TMP15]], i32* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] undef, <vscale x 4 x i32> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP18]], <vscale x 4 x i32> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP20]], <vscale x 4 x i32> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP22]], <vscale x 4 x i32> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32M2X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e32_v_i32m2x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T:%.*]] undef, <vscale x 4 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP0]], <vscale x 4 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP1]], <vscale x 4 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP2]], <vscale x 4 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg4.mask.nxv4i32.i64(<vscale x 4 x i32> [[TMP12]], <vscale x 4 x i32> [[TMP13]], <vscale x 4 x i32> [[TMP14]], <vscale x 4 x i32> [[TMP15]], i32* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] undef, <vscale x 4 x i32> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP18]], <vscale x 4 x i32> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP20]], <vscale x 4 x i32> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP22]], <vscale x 4 x i32> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32M2X4_T]] [[TMP24]]
+//
+vint32m2x4_t test_vlseg4e32_v_i32m2x4_m (vbool16_t mask, vint32m2x4_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg4e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_i32m4x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M4X2_T:%.*]] undef, <vscale x 8 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M4X2_T]] [[TMP0]], <vscale x 8 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT32M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT32M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT32M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT32M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 8 x i32>, <vscale x 8 x i32> } @llvm.riscv.vlseg2.mask.nxv8i32.i32(<vscale x 8 x i32> [[TMP6]], <vscale x 8 x i32> [[TMP7]], i32* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32M4X2_T]] undef, <vscale x 8 x i32> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32M4X2_T]] [[TMP10]], <vscale x 8 x i32> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32M4X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_i32m4x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M4X2_T:%.*]] undef, <vscale x 8 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M4X2_T]] [[TMP0]], <vscale x 8 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT32M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT32M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT32M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT32M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 8 x i32>, <vscale x 8 x i32> } @llvm.riscv.vlseg2.mask.nxv8i32.i64(<vscale x 8 x i32> [[TMP6]], <vscale x 8 x i32> [[TMP7]], i32* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32M4X2_T]] undef, <vscale x 8 x i32> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32M4X2_T]] [[TMP10]], <vscale x 8 x i32> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32M4X2_T]] [[TMP12]]
+//
+vint32m4x2_t test_vlseg2e32_v_i32m4x2_m (vbool8_t mask, vint32m4x2_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg2e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e64_v_i64m1x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X2_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X2_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg2.mask.nxv1i64.i32(<vscale x 1 x i64> [[TMP6]], <vscale x 1 x i64> [[TMP7]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X2_T]] undef, <vscale x 1 x i64> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X2_T]] [[TMP10]], <vscale x 1 x i64> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT64M1X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e64_v_i64m1x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X2_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X2_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg2.mask.nxv1i64.i64(<vscale x 1 x i64> [[TMP6]], <vscale x 1 x i64> [[TMP7]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X2_T]] undef, <vscale x 1 x i64> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X2_T]] [[TMP10]], <vscale x 1 x i64> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT64M1X2_T]] [[TMP12]]
+//
+vint64m1x2_t test_vlseg2e64_v_i64m1x2_m (vbool64_t mask, vint64m1x2_t maskedoff, const int64_t *base, size_t vl) {
+  return vlseg2e64(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e64_v_i64m1x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg3.mask.nxv1i64.i32(<vscale x 1 x i64> [[TMP9]], <vscale x 1 x i64> [[TMP10]], <vscale x 1 x i64> [[TMP11]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T]] undef, <vscale x 1 x i64> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP14]], <vscale x 1 x i64> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP16]], <vscale x 1 x i64> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT64M1X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e64_v_i64m1x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg3.mask.nxv1i64.i64(<vscale x 1 x i64> [[TMP9]], <vscale x 1 x i64> [[TMP10]], <vscale x 1 x i64> [[TMP11]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T]] undef, <vscale x 1 x i64> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP14]], <vscale x 1 x i64> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP16]], <vscale x 1 x i64> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT64M1X3_T]] [[TMP18]]
+//
+vint64m1x3_t test_vlseg3e64_v_i64m1x3_m (vbool64_t mask, vint64m1x3_t maskedoff, const int64_t *base, size_t vl) {
+  return vlseg3e64(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e64_v_i64m1x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg4.mask.nxv1i64.i32(<vscale x 1 x i64> [[TMP12]], <vscale x 1 x i64> [[TMP13]], <vscale x 1 x i64> [[TMP14]], <vscale x 1 x i64> [[TMP15]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] undef, <vscale x 1 x i64> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP18]], <vscale x 1 x i64> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP20]], <vscale x 1 x i64> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP22]], <vscale x 1 x i64> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT64M1X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e64_v_i64m1x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg4.mask.nxv1i64.i64(<vscale x 1 x i64> [[TMP12]], <vscale x 1 x i64> [[TMP13]], <vscale x 1 x i64> [[TMP14]], <vscale x 1 x i64> [[TMP15]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] undef, <vscale x 1 x i64> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP18]], <vscale x 1 x i64> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP20]], <vscale x 1 x i64> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP22]], <vscale x 1 x i64> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT64M1X4_T]] [[TMP24]]
+//
+vint64m1x4_t test_vlseg4e64_v_i64m1x4_m (vbool64_t mask, vint64m1x4_t maskedoff, const int64_t *base, size_t vl) {
+  return vlseg4e64(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e64_v_i64m1x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP3]], <vscale x 1 x i64> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg5.mask.nxv1i64.i32(<vscale x 1 x i64> [[TMP15]], <vscale x 1 x i64> [[TMP16]], <vscale x 1 x i64> [[TMP17]], <vscale x 1 x i64> [[TMP18]], <vscale x 1 x i64> [[TMP19]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] undef, <vscale x 1 x i64> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP22]], <vscale x 1 x i64> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP24]], <vscale x 1 x i64> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP26]], <vscale x 1 x i64> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP28]], <vscale x 1 x i64> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT64M1X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e64_v_i64m1x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP3]], <vscale x 1 x i64> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg5.mask.nxv1i64.i64(<vscale x 1 x i64> [[TMP15]], <vscale x 1 x i64> [[TMP16]], <vscale x 1 x i64> [[TMP17]], <vscale x 1 x i64> [[TMP18]], <vscale x 1 x i64> [[TMP19]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] undef, <vscale x 1 x i64> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP22]], <vscale x 1 x i64> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP24]], <vscale x 1 x i64> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP26]], <vscale x 1 x i64> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP28]], <vscale x 1 x i64> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT64M1X5_T]] [[TMP30]]
+//
+vint64m1x5_t test_vlseg5e64_v_i64m1x5_m (vbool64_t mask, vint64m1x5_t maskedoff, const int64_t *base, size_t vl) {
+  return vlseg5e64(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e64_v_i64m1x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP3]], <vscale x 1 x i64> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP4]], <vscale x 1 x i64> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg6.mask.nxv1i64.i32(<vscale x 1 x i64> [[TMP18]], <vscale x 1 x i64> [[TMP19]], <vscale x 1 x i64> [[TMP20]], <vscale x 1 x i64> [[TMP21]], <vscale x 1 x i64> [[TMP22]], <vscale x 1 x i64> [[TMP23]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] undef, <vscale x 1 x i64> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP26]], <vscale x 1 x i64> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP28]], <vscale x 1 x i64> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP30]], <vscale x 1 x i64> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP32]], <vscale x 1 x i64> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP34]], <vscale x 1 x i64> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT64M1X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e64_v_i64m1x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP3]], <vscale x 1 x i64> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP4]], <vscale x 1 x i64> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg6.mask.nxv1i64.i64(<vscale x 1 x i64> [[TMP18]], <vscale x 1 x i64> [[TMP19]], <vscale x 1 x i64> [[TMP20]], <vscale x 1 x i64> [[TMP21]], <vscale x 1 x i64> [[TMP22]], <vscale x 1 x i64> [[TMP23]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] undef, <vscale x 1 x i64> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP26]], <vscale x 1 x i64> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP28]], <vscale x 1 x i64> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP30]], <vscale x 1 x i64> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP32]], <vscale x 1 x i64> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP34]], <vscale x 1 x i64> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT64M1X6_T]] [[TMP36]]
+//
+vint64m1x6_t test_vlseg6e64_v_i64m1x6_m (vbool64_t mask, vint64m1x6_t maskedoff, const int64_t *base, size_t vl) {
+  return vlseg6e64(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e64_v_i64m1x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP3]], <vscale x 1 x i64> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP4]], <vscale x 1 x i64> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP5]], <vscale x 1 x i64> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg7.mask.nxv1i64.i32(<vscale x 1 x i64> [[TMP21]], <vscale x 1 x i64> [[TMP22]], <vscale x 1 x i64> [[TMP23]], <vscale x 1 x i64> [[TMP24]], <vscale x 1 x i64> [[TMP25]], <vscale x 1 x i64> [[TMP26]], <vscale x 1 x i64> [[TMP27]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] undef, <vscale x 1 x i64> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP30]], <vscale x 1 x i64> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP32]], <vscale x 1 x i64> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP34]], <vscale x 1 x i64> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP36]], <vscale x 1 x i64> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP38]], <vscale x 1 x i64> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP40]], <vscale x 1 x i64> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT64M1X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e64_v_i64m1x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP3]], <vscale x 1 x i64> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP4]], <vscale x 1 x i64> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP5]], <vscale x 1 x i64> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg7.mask.nxv1i64.i64(<vscale x 1 x i64> [[TMP21]], <vscale x 1 x i64> [[TMP22]], <vscale x 1 x i64> [[TMP23]], <vscale x 1 x i64> [[TMP24]], <vscale x 1 x i64> [[TMP25]], <vscale x 1 x i64> [[TMP26]], <vscale x 1 x i64> [[TMP27]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] undef, <vscale x 1 x i64> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP30]], <vscale x 1 x i64> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP32]], <vscale x 1 x i64> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP34]], <vscale x 1 x i64> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP36]], <vscale x 1 x i64> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP38]], <vscale x 1 x i64> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP40]], <vscale x 1 x i64> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT64M1X7_T]] [[TMP42]]
+//
+vint64m1x7_t test_vlseg7e64_v_i64m1x7_m (vbool64_t mask, vint64m1x7_t maskedoff, const int64_t *base, size_t vl) {
+  return vlseg7e64(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e64_v_i64m1x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP3]], <vscale x 1 x i64> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP4]], <vscale x 1 x i64> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP5]], <vscale x 1 x i64> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP6]], <vscale x 1 x i64> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg8.mask.nxv1i64.i32(<vscale x 1 x i64> [[TMP24]], <vscale x 1 x i64> [[TMP25]], <vscale x 1 x i64> [[TMP26]], <vscale x 1 x i64> [[TMP27]], <vscale x 1 x i64> [[TMP28]], <vscale x 1 x i64> [[TMP29]], <vscale x 1 x i64> [[TMP30]], <vscale x 1 x i64> [[TMP31]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] undef, <vscale x 1 x i64> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP34]], <vscale x 1 x i64> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP36]], <vscale x 1 x i64> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP38]], <vscale x 1 x i64> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP40]], <vscale x 1 x i64> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP42]], <vscale x 1 x i64> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP44]], <vscale x 1 x i64> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP46]], <vscale x 1 x i64> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT64M1X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e64_v_i64m1x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP3]], <vscale x 1 x i64> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP4]], <vscale x 1 x i64> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP5]], <vscale x 1 x i64> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP6]], <vscale x 1 x i64> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg8.mask.nxv1i64.i64(<vscale x 1 x i64> [[TMP24]], <vscale x 1 x i64> [[TMP25]], <vscale x 1 x i64> [[TMP26]], <vscale x 1 x i64> [[TMP27]], <vscale x 1 x i64> [[TMP28]], <vscale x 1 x i64> [[TMP29]], <vscale x 1 x i64> [[TMP30]], <vscale x 1 x i64> [[TMP31]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] undef, <vscale x 1 x i64> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP34]], <vscale x 1 x i64> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP36]], <vscale x 1 x i64> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP38]], <vscale x 1 x i64> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP40]], <vscale x 1 x i64> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP42]], <vscale x 1 x i64> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP44]], <vscale x 1 x i64> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP46]], <vscale x 1 x i64> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT64M1X8_T]] [[TMP48]]
+//
+vint64m1x8_t test_vlseg8e64_v_i64m1x8_m (vbool64_t mask, vint64m1x8_t maskedoff, const int64_t *base, size_t vl) {
+  return vlseg8e64(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e64_v_i64m2x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X2_T:%.*]] undef, <vscale x 2 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X2_T]] [[TMP0]], <vscale x 2 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg2.mask.nxv2i64.i32(<vscale x 2 x i64> [[TMP6]], <vscale x 2 x i64> [[TMP7]], i64* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X2_T]] undef, <vscale x 2 x i64> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X2_T]] [[TMP10]], <vscale x 2 x i64> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT64M2X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e64_v_i64m2x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X2_T:%.*]] undef, <vscale x 2 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X2_T]] [[TMP0]], <vscale x 2 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg2.mask.nxv2i64.i64(<vscale x 2 x i64> [[TMP6]], <vscale x 2 x i64> [[TMP7]], i64* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X2_T]] undef, <vscale x 2 x i64> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X2_T]] [[TMP10]], <vscale x 2 x i64> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT64M2X2_T]] [[TMP12]]
+//
+vint64m2x2_t test_vlseg2e64_v_i64m2x2_m (vbool32_t mask, vint64m2x2_t maskedoff, const int64_t *base, size_t vl) {
+  return vlseg2e64(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e64_v_i64m2x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T:%.*]] undef, <vscale x 2 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP0]], <vscale x 2 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP1]], <vscale x 2 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg3.mask.nxv2i64.i32(<vscale x 2 x i64> [[TMP9]], <vscale x 2 x i64> [[TMP10]], <vscale x 2 x i64> [[TMP11]], i64* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T]] undef, <vscale x 2 x i64> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP14]], <vscale x 2 x i64> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP16]], <vscale x 2 x i64> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT64M2X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e64_v_i64m2x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T:%.*]] undef, <vscale x 2 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP0]], <vscale x 2 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP1]], <vscale x 2 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg3.mask.nxv2i64.i64(<vscale x 2 x i64> [[TMP9]], <vscale x 2 x i64> [[TMP10]], <vscale x 2 x i64> [[TMP11]], i64* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T]] undef, <vscale x 2 x i64> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP14]], <vscale x 2 x i64> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP16]], <vscale x 2 x i64> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT64M2X3_T]] [[TMP18]]
+//
+vint64m2x3_t test_vlseg3e64_v_i64m2x3_m (vbool32_t mask, vint64m2x3_t maskedoff, const int64_t *base, size_t vl) {
+  return vlseg3e64(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e64_v_i64m2x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T:%.*]] undef, <vscale x 2 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP0]], <vscale x 2 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP1]], <vscale x 2 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP2]], <vscale x 2 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg4.mask.nxv2i64.i32(<vscale x 2 x i64> [[TMP12]], <vscale x 2 x i64> [[TMP13]], <vscale x 2 x i64> [[TMP14]], <vscale x 2 x i64> [[TMP15]], i64* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] undef, <vscale x 2 x i64> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP18]], <vscale x 2 x i64> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP20]], <vscale x 2 x i64> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP22]], <vscale x 2 x i64> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT64M2X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e64_v_i64m2x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T:%.*]] undef, <vscale x 2 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP0]], <vscale x 2 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP1]], <vscale x 2 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP2]], <vscale x 2 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg4.mask.nxv2i64.i64(<vscale x 2 x i64> [[TMP12]], <vscale x 2 x i64> [[TMP13]], <vscale x 2 x i64> [[TMP14]], <vscale x 2 x i64> [[TMP15]], i64* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] undef, <vscale x 2 x i64> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP18]], <vscale x 2 x i64> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP20]], <vscale x 2 x i64> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP22]], <vscale x 2 x i64> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT64M2X4_T]] [[TMP24]]
+//
+vint64m2x4_t test_vlseg4e64_v_i64m2x4_m (vbool32_t mask, vint64m2x4_t maskedoff, const int64_t *base, size_t vl) {
+  return vlseg4e64(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e64_v_i64m4x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M4X2_T:%.*]] undef, <vscale x 4 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M4X2_T]] [[TMP0]], <vscale x 4 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT64M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT64M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT64M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT64M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT64M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT64M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x i64>, <vscale x 4 x i64> } @llvm.riscv.vlseg2.mask.nxv4i64.i32(<vscale x 4 x i64> [[TMP6]], <vscale x 4 x i64> [[TMP7]], i64* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT64M4X2_T]] undef, <vscale x 4 x i64> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT64M4X2_T]] [[TMP10]], <vscale x 4 x i64> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT64M4X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e64_v_i64m4x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M4X2_T:%.*]] undef, <vscale x 4 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M4X2_T]] [[TMP0]], <vscale x 4 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT64M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT64M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT64M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT64M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT64M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT64M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x i64>, <vscale x 4 x i64> } @llvm.riscv.vlseg2.mask.nxv4i64.i64(<vscale x 4 x i64> [[TMP6]], <vscale x 4 x i64> [[TMP7]], i64* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT64M4X2_T]] undef, <vscale x 4 x i64> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT64M4X2_T]] [[TMP10]], <vscale x 4 x i64> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT64M4X2_T]] [[TMP12]]
+//
+vint64m4x2_t test_vlseg2e64_v_i64m4x2_m (vbool16_t mask, vint64m4x2_t maskedoff, const int64_t *base, size_t vl) {
+  return vlseg2e64(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_u8mf8x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X2_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg2.mask.nxv1i8.i32(<vscale x 1 x i8> [[TMP6]], <vscale x 1 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X2_T]] undef, <vscale x 1 x i8> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP10]], <vscale x 1 x i8> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_u8mf8x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X2_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg2.mask.nxv1i8.i64(<vscale x 1 x i8> [[TMP6]], <vscale x 1 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X2_T]] undef, <vscale x 1 x i8> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP10]], <vscale x 1 x i8> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP12]]
+//
+vuint8mf8x2_t test_vlseg2e8_v_u8mf8x2_m (vbool64_t mask, vuint8mf8x2_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg2e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e8_v_u8mf8x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg3.mask.nxv1i8.i32(<vscale x 1 x i8> [[TMP9]], <vscale x 1 x i8> [[TMP10]], <vscale x 1 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T]] undef, <vscale x 1 x i8> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP14]], <vscale x 1 x i8> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP16]], <vscale x 1 x i8> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e8_v_u8mf8x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg3.mask.nxv1i8.i64(<vscale x 1 x i8> [[TMP9]], <vscale x 1 x i8> [[TMP10]], <vscale x 1 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T]] undef, <vscale x 1 x i8> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP14]], <vscale x 1 x i8> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP16]], <vscale x 1 x i8> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP18]]
+//
+vuint8mf8x3_t test_vlseg3e8_v_u8mf8x3_m (vbool64_t mask, vuint8mf8x3_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg3e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e8_v_u8mf8x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg4.mask.nxv1i8.i32(<vscale x 1 x i8> [[TMP12]], <vscale x 1 x i8> [[TMP13]], <vscale x 1 x i8> [[TMP14]], <vscale x 1 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] undef, <vscale x 1 x i8> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP18]], <vscale x 1 x i8> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP20]], <vscale x 1 x i8> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP22]], <vscale x 1 x i8> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e8_v_u8mf8x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg4.mask.nxv1i8.i64(<vscale x 1 x i8> [[TMP12]], <vscale x 1 x i8> [[TMP13]], <vscale x 1 x i8> [[TMP14]], <vscale x 1 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] undef, <vscale x 1 x i8> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP18]], <vscale x 1 x i8> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP20]], <vscale x 1 x i8> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP22]], <vscale x 1 x i8> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP24]]
+//
+vuint8mf8x4_t test_vlseg4e8_v_u8mf8x4_m (vbool64_t mask, vuint8mf8x4_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg4e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e8_v_u8mf8x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP3]], <vscale x 1 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg5.mask.nxv1i8.i32(<vscale x 1 x i8> [[TMP15]], <vscale x 1 x i8> [[TMP16]], <vscale x 1 x i8> [[TMP17]], <vscale x 1 x i8> [[TMP18]], <vscale x 1 x i8> [[TMP19]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] undef, <vscale x 1 x i8> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP22]], <vscale x 1 x i8> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP24]], <vscale x 1 x i8> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP26]], <vscale x 1 x i8> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP28]], <vscale x 1 x i8> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e8_v_u8mf8x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP3]], <vscale x 1 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg5.mask.nxv1i8.i64(<vscale x 1 x i8> [[TMP15]], <vscale x 1 x i8> [[TMP16]], <vscale x 1 x i8> [[TMP17]], <vscale x 1 x i8> [[TMP18]], <vscale x 1 x i8> [[TMP19]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] undef, <vscale x 1 x i8> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP22]], <vscale x 1 x i8> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP24]], <vscale x 1 x i8> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP26]], <vscale x 1 x i8> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP28]], <vscale x 1 x i8> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP30]]
+//
+vuint8mf8x5_t test_vlseg5e8_v_u8mf8x5_m (vbool64_t mask, vuint8mf8x5_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg5e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e8_v_u8mf8x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP3]], <vscale x 1 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP4]], <vscale x 1 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg6.mask.nxv1i8.i32(<vscale x 1 x i8> [[TMP18]], <vscale x 1 x i8> [[TMP19]], <vscale x 1 x i8> [[TMP20]], <vscale x 1 x i8> [[TMP21]], <vscale x 1 x i8> [[TMP22]], <vscale x 1 x i8> [[TMP23]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] undef, <vscale x 1 x i8> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP26]], <vscale x 1 x i8> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP28]], <vscale x 1 x i8> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP30]], <vscale x 1 x i8> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP32]], <vscale x 1 x i8> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP34]], <vscale x 1 x i8> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e8_v_u8mf8x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP3]], <vscale x 1 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP4]], <vscale x 1 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg6.mask.nxv1i8.i64(<vscale x 1 x i8> [[TMP18]], <vscale x 1 x i8> [[TMP19]], <vscale x 1 x i8> [[TMP20]], <vscale x 1 x i8> [[TMP21]], <vscale x 1 x i8> [[TMP22]], <vscale x 1 x i8> [[TMP23]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] undef, <vscale x 1 x i8> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP26]], <vscale x 1 x i8> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP28]], <vscale x 1 x i8> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP30]], <vscale x 1 x i8> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP32]], <vscale x 1 x i8> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP34]], <vscale x 1 x i8> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP36]]
+//
+vuint8mf8x6_t test_vlseg6e8_v_u8mf8x6_m (vbool64_t mask, vuint8mf8x6_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg6e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e8_v_u8mf8x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP3]], <vscale x 1 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP4]], <vscale x 1 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP5]], <vscale x 1 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg7.mask.nxv1i8.i32(<vscale x 1 x i8> [[TMP21]], <vscale x 1 x i8> [[TMP22]], <vscale x 1 x i8> [[TMP23]], <vscale x 1 x i8> [[TMP24]], <vscale x 1 x i8> [[TMP25]], <vscale x 1 x i8> [[TMP26]], <vscale x 1 x i8> [[TMP27]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] undef, <vscale x 1 x i8> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP30]], <vscale x 1 x i8> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP32]], <vscale x 1 x i8> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP34]], <vscale x 1 x i8> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP36]], <vscale x 1 x i8> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP38]], <vscale x 1 x i8> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP40]], <vscale x 1 x i8> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e8_v_u8mf8x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP3]], <vscale x 1 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP4]], <vscale x 1 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP5]], <vscale x 1 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg7.mask.nxv1i8.i64(<vscale x 1 x i8> [[TMP21]], <vscale x 1 x i8> [[TMP22]], <vscale x 1 x i8> [[TMP23]], <vscale x 1 x i8> [[TMP24]], <vscale x 1 x i8> [[TMP25]], <vscale x 1 x i8> [[TMP26]], <vscale x 1 x i8> [[TMP27]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] undef, <vscale x 1 x i8> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP30]], <vscale x 1 x i8> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP32]], <vscale x 1 x i8> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP34]], <vscale x 1 x i8> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP36]], <vscale x 1 x i8> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP38]], <vscale x 1 x i8> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP40]], <vscale x 1 x i8> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP42]]
+//
+vuint8mf8x7_t test_vlseg7e8_v_u8mf8x7_m (vbool64_t mask, vuint8mf8x7_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg7e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e8_v_u8mf8x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP3]], <vscale x 1 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP4]], <vscale x 1 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP5]], <vscale x 1 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP6]], <vscale x 1 x i8> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg8.mask.nxv1i8.i32(<vscale x 1 x i8> [[TMP24]], <vscale x 1 x i8> [[TMP25]], <vscale x 1 x i8> [[TMP26]], <vscale x 1 x i8> [[TMP27]], <vscale x 1 x i8> [[TMP28]], <vscale x 1 x i8> [[TMP29]], <vscale x 1 x i8> [[TMP30]], <vscale x 1 x i8> [[TMP31]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] undef, <vscale x 1 x i8> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP34]], <vscale x 1 x i8> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP36]], <vscale x 1 x i8> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP38]], <vscale x 1 x i8> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP40]], <vscale x 1 x i8> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP42]], <vscale x 1 x i8> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP44]], <vscale x 1 x i8> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP46]], <vscale x 1 x i8> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e8_v_u8mf8x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP3]], <vscale x 1 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP4]], <vscale x 1 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP5]], <vscale x 1 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP6]], <vscale x 1 x i8> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg8.mask.nxv1i8.i64(<vscale x 1 x i8> [[TMP24]], <vscale x 1 x i8> [[TMP25]], <vscale x 1 x i8> [[TMP26]], <vscale x 1 x i8> [[TMP27]], <vscale x 1 x i8> [[TMP28]], <vscale x 1 x i8> [[TMP29]], <vscale x 1 x i8> [[TMP30]], <vscale x 1 x i8> [[TMP31]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] undef, <vscale x 1 x i8> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP34]], <vscale x 1 x i8> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP36]], <vscale x 1 x i8> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP38]], <vscale x 1 x i8> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP40]], <vscale x 1 x i8> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP42]], <vscale x 1 x i8> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP44]], <vscale x 1 x i8> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP46]], <vscale x 1 x i8> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP48]]
+//
+vuint8mf8x8_t test_vlseg8e8_v_u8mf8x8_m (vbool64_t mask, vuint8mf8x8_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg8e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_u8mf4x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X2_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg2.mask.nxv2i8.i32(<vscale x 2 x i8> [[TMP6]], <vscale x 2 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X2_T]] undef, <vscale x 2 x i8> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP10]], <vscale x 2 x i8> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_u8mf4x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X2_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg2.mask.nxv2i8.i64(<vscale x 2 x i8> [[TMP6]], <vscale x 2 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X2_T]] undef, <vscale x 2 x i8> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP10]], <vscale x 2 x i8> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP12]]
+//
+vuint8mf4x2_t test_vlseg2e8_v_u8mf4x2_m (vbool32_t mask, vuint8mf4x2_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg2e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e8_v_u8mf4x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg3.mask.nxv2i8.i32(<vscale x 2 x i8> [[TMP9]], <vscale x 2 x i8> [[TMP10]], <vscale x 2 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T]] undef, <vscale x 2 x i8> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP14]], <vscale x 2 x i8> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP16]], <vscale x 2 x i8> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e8_v_u8mf4x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg3.mask.nxv2i8.i64(<vscale x 2 x i8> [[TMP9]], <vscale x 2 x i8> [[TMP10]], <vscale x 2 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T]] undef, <vscale x 2 x i8> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP14]], <vscale x 2 x i8> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP16]], <vscale x 2 x i8> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP18]]
+//
+vuint8mf4x3_t test_vlseg3e8_v_u8mf4x3_m (vbool32_t mask, vuint8mf4x3_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg3e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e8_v_u8mf4x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg4.mask.nxv2i8.i32(<vscale x 2 x i8> [[TMP12]], <vscale x 2 x i8> [[TMP13]], <vscale x 2 x i8> [[TMP14]], <vscale x 2 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] undef, <vscale x 2 x i8> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP18]], <vscale x 2 x i8> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP20]], <vscale x 2 x i8> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP22]], <vscale x 2 x i8> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e8_v_u8mf4x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg4.mask.nxv2i8.i64(<vscale x 2 x i8> [[TMP12]], <vscale x 2 x i8> [[TMP13]], <vscale x 2 x i8> [[TMP14]], <vscale x 2 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] undef, <vscale x 2 x i8> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP18]], <vscale x 2 x i8> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP20]], <vscale x 2 x i8> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP22]], <vscale x 2 x i8> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP24]]
+//
+vuint8mf4x4_t test_vlseg4e8_v_u8mf4x4_m (vbool32_t mask, vuint8mf4x4_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg4e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e8_v_u8mf4x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP3]], <vscale x 2 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg5.mask.nxv2i8.i32(<vscale x 2 x i8> [[TMP15]], <vscale x 2 x i8> [[TMP16]], <vscale x 2 x i8> [[TMP17]], <vscale x 2 x i8> [[TMP18]], <vscale x 2 x i8> [[TMP19]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] undef, <vscale x 2 x i8> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP22]], <vscale x 2 x i8> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP24]], <vscale x 2 x i8> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP26]], <vscale x 2 x i8> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP28]], <vscale x 2 x i8> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e8_v_u8mf4x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP3]], <vscale x 2 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg5.mask.nxv2i8.i64(<vscale x 2 x i8> [[TMP15]], <vscale x 2 x i8> [[TMP16]], <vscale x 2 x i8> [[TMP17]], <vscale x 2 x i8> [[TMP18]], <vscale x 2 x i8> [[TMP19]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] undef, <vscale x 2 x i8> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP22]], <vscale x 2 x i8> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP24]], <vscale x 2 x i8> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP26]], <vscale x 2 x i8> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP28]], <vscale x 2 x i8> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP30]]
+//
+vuint8mf4x5_t test_vlseg5e8_v_u8mf4x5_m (vbool32_t mask, vuint8mf4x5_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg5e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e8_v_u8mf4x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP3]], <vscale x 2 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP4]], <vscale x 2 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg6.mask.nxv2i8.i32(<vscale x 2 x i8> [[TMP18]], <vscale x 2 x i8> [[TMP19]], <vscale x 2 x i8> [[TMP20]], <vscale x 2 x i8> [[TMP21]], <vscale x 2 x i8> [[TMP22]], <vscale x 2 x i8> [[TMP23]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] undef, <vscale x 2 x i8> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP26]], <vscale x 2 x i8> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP28]], <vscale x 2 x i8> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP30]], <vscale x 2 x i8> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP32]], <vscale x 2 x i8> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP34]], <vscale x 2 x i8> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e8_v_u8mf4x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP3]], <vscale x 2 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP4]], <vscale x 2 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg6.mask.nxv2i8.i64(<vscale x 2 x i8> [[TMP18]], <vscale x 2 x i8> [[TMP19]], <vscale x 2 x i8> [[TMP20]], <vscale x 2 x i8> [[TMP21]], <vscale x 2 x i8> [[TMP22]], <vscale x 2 x i8> [[TMP23]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] undef, <vscale x 2 x i8> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP26]], <vscale x 2 x i8> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP28]], <vscale x 2 x i8> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP30]], <vscale x 2 x i8> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP32]], <vscale x 2 x i8> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP34]], <vscale x 2 x i8> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP36]]
+//
+vuint8mf4x6_t test_vlseg6e8_v_u8mf4x6_m (vbool32_t mask, vuint8mf4x6_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg6e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e8_v_u8mf4x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP3]], <vscale x 2 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP4]], <vscale x 2 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP5]], <vscale x 2 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg7.mask.nxv2i8.i32(<vscale x 2 x i8> [[TMP21]], <vscale x 2 x i8> [[TMP22]], <vscale x 2 x i8> [[TMP23]], <vscale x 2 x i8> [[TMP24]], <vscale x 2 x i8> [[TMP25]], <vscale x 2 x i8> [[TMP26]], <vscale x 2 x i8> [[TMP27]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] undef, <vscale x 2 x i8> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP30]], <vscale x 2 x i8> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP32]], <vscale x 2 x i8> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP34]], <vscale x 2 x i8> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP36]], <vscale x 2 x i8> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP38]], <vscale x 2 x i8> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP40]], <vscale x 2 x i8> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e8_v_u8mf4x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP3]], <vscale x 2 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP4]], <vscale x 2 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP5]], <vscale x 2 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg7.mask.nxv2i8.i64(<vscale x 2 x i8> [[TMP21]], <vscale x 2 x i8> [[TMP22]], <vscale x 2 x i8> [[TMP23]], <vscale x 2 x i8> [[TMP24]], <vscale x 2 x i8> [[TMP25]], <vscale x 2 x i8> [[TMP26]], <vscale x 2 x i8> [[TMP27]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] undef, <vscale x 2 x i8> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP30]], <vscale x 2 x i8> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP32]], <vscale x 2 x i8> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP34]], <vscale x 2 x i8> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP36]], <vscale x 2 x i8> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP38]], <vscale x 2 x i8> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP40]], <vscale x 2 x i8> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP42]]
+//
+vuint8mf4x7_t test_vlseg7e8_v_u8mf4x7_m (vbool32_t mask, vuint8mf4x7_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg7e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e8_v_u8mf4x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP3]], <vscale x 2 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP4]], <vscale x 2 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP5]], <vscale x 2 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP6]], <vscale x 2 x i8> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg8.mask.nxv2i8.i32(<vscale x 2 x i8> [[TMP24]], <vscale x 2 x i8> [[TMP25]], <vscale x 2 x i8> [[TMP26]], <vscale x 2 x i8> [[TMP27]], <vscale x 2 x i8> [[TMP28]], <vscale x 2 x i8> [[TMP29]], <vscale x 2 x i8> [[TMP30]], <vscale x 2 x i8> [[TMP31]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] undef, <vscale x 2 x i8> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP34]], <vscale x 2 x i8> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP36]], <vscale x 2 x i8> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP38]], <vscale x 2 x i8> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP40]], <vscale x 2 x i8> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP42]], <vscale x 2 x i8> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP44]], <vscale x 2 x i8> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP46]], <vscale x 2 x i8> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e8_v_u8mf4x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP3]], <vscale x 2 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP4]], <vscale x 2 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP5]], <vscale x 2 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP6]], <vscale x 2 x i8> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg8.mask.nxv2i8.i64(<vscale x 2 x i8> [[TMP24]], <vscale x 2 x i8> [[TMP25]], <vscale x 2 x i8> [[TMP26]], <vscale x 2 x i8> [[TMP27]], <vscale x 2 x i8> [[TMP28]], <vscale x 2 x i8> [[TMP29]], <vscale x 2 x i8> [[TMP30]], <vscale x 2 x i8> [[TMP31]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] undef, <vscale x 2 x i8> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP34]], <vscale x 2 x i8> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP36]], <vscale x 2 x i8> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP38]], <vscale x 2 x i8> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP40]], <vscale x 2 x i8> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP42]], <vscale x 2 x i8> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP44]], <vscale x 2 x i8> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP46]], <vscale x 2 x i8> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP48]]
+//
+vuint8mf4x8_t test_vlseg8e8_v_u8mf4x8_m (vbool32_t mask, vuint8mf4x8_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg8e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_u8mf2x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X2_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg2.mask.nxv4i8.i32(<vscale x 4 x i8> [[TMP6]], <vscale x 4 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X2_T]] undef, <vscale x 4 x i8> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP10]], <vscale x 4 x i8> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_u8mf2x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X2_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg2.mask.nxv4i8.i64(<vscale x 4 x i8> [[TMP6]], <vscale x 4 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X2_T]] undef, <vscale x 4 x i8> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP10]], <vscale x 4 x i8> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP12]]
+//
+vuint8mf2x2_t test_vlseg2e8_v_u8mf2x2_m (vbool16_t mask, vuint8mf2x2_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg2e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e8_v_u8mf2x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg3.mask.nxv4i8.i32(<vscale x 4 x i8> [[TMP9]], <vscale x 4 x i8> [[TMP10]], <vscale x 4 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T]] undef, <vscale x 4 x i8> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP14]], <vscale x 4 x i8> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP16]], <vscale x 4 x i8> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e8_v_u8mf2x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg3.mask.nxv4i8.i64(<vscale x 4 x i8> [[TMP9]], <vscale x 4 x i8> [[TMP10]], <vscale x 4 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T]] undef, <vscale x 4 x i8> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP14]], <vscale x 4 x i8> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP16]], <vscale x 4 x i8> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP18]]
+//
+vuint8mf2x3_t test_vlseg3e8_v_u8mf2x3_m (vbool16_t mask, vuint8mf2x3_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg3e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e8_v_u8mf2x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg4.mask.nxv4i8.i32(<vscale x 4 x i8> [[TMP12]], <vscale x 4 x i8> [[TMP13]], <vscale x 4 x i8> [[TMP14]], <vscale x 4 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] undef, <vscale x 4 x i8> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP18]], <vscale x 4 x i8> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP20]], <vscale x 4 x i8> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP22]], <vscale x 4 x i8> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e8_v_u8mf2x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg4.mask.nxv4i8.i64(<vscale x 4 x i8> [[TMP12]], <vscale x 4 x i8> [[TMP13]], <vscale x 4 x i8> [[TMP14]], <vscale x 4 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] undef, <vscale x 4 x i8> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP18]], <vscale x 4 x i8> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP20]], <vscale x 4 x i8> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP22]], <vscale x 4 x i8> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP24]]
+//
+vuint8mf2x4_t test_vlseg4e8_v_u8mf2x4_m (vbool16_t mask, vuint8mf2x4_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg4e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e8_v_u8mf2x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP3]], <vscale x 4 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg5.mask.nxv4i8.i32(<vscale x 4 x i8> [[TMP15]], <vscale x 4 x i8> [[TMP16]], <vscale x 4 x i8> [[TMP17]], <vscale x 4 x i8> [[TMP18]], <vscale x 4 x i8> [[TMP19]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] undef, <vscale x 4 x i8> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP22]], <vscale x 4 x i8> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP24]], <vscale x 4 x i8> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP26]], <vscale x 4 x i8> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP28]], <vscale x 4 x i8> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e8_v_u8mf2x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP3]], <vscale x 4 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg5.mask.nxv4i8.i64(<vscale x 4 x i8> [[TMP15]], <vscale x 4 x i8> [[TMP16]], <vscale x 4 x i8> [[TMP17]], <vscale x 4 x i8> [[TMP18]], <vscale x 4 x i8> [[TMP19]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] undef, <vscale x 4 x i8> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP22]], <vscale x 4 x i8> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP24]], <vscale x 4 x i8> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP26]], <vscale x 4 x i8> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP28]], <vscale x 4 x i8> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP30]]
+//
+vuint8mf2x5_t test_vlseg5e8_v_u8mf2x5_m (vbool16_t mask, vuint8mf2x5_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg5e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e8_v_u8mf2x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP3]], <vscale x 4 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP4]], <vscale x 4 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg6.mask.nxv4i8.i32(<vscale x 4 x i8> [[TMP18]], <vscale x 4 x i8> [[TMP19]], <vscale x 4 x i8> [[TMP20]], <vscale x 4 x i8> [[TMP21]], <vscale x 4 x i8> [[TMP22]], <vscale x 4 x i8> [[TMP23]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] undef, <vscale x 4 x i8> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP26]], <vscale x 4 x i8> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP28]], <vscale x 4 x i8> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP30]], <vscale x 4 x i8> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP32]], <vscale x 4 x i8> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP34]], <vscale x 4 x i8> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e8_v_u8mf2x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP3]], <vscale x 4 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP4]], <vscale x 4 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg6.mask.nxv4i8.i64(<vscale x 4 x i8> [[TMP18]], <vscale x 4 x i8> [[TMP19]], <vscale x 4 x i8> [[TMP20]], <vscale x 4 x i8> [[TMP21]], <vscale x 4 x i8> [[TMP22]], <vscale x 4 x i8> [[TMP23]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] undef, <vscale x 4 x i8> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP26]], <vscale x 4 x i8> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP28]], <vscale x 4 x i8> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP30]], <vscale x 4 x i8> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP32]], <vscale x 4 x i8> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP34]], <vscale x 4 x i8> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP36]]
+//
+vuint8mf2x6_t test_vlseg6e8_v_u8mf2x6_m (vbool16_t mask, vuint8mf2x6_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg6e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e8_v_u8mf2x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP3]], <vscale x 4 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP4]], <vscale x 4 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP5]], <vscale x 4 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg7.mask.nxv4i8.i32(<vscale x 4 x i8> [[TMP21]], <vscale x 4 x i8> [[TMP22]], <vscale x 4 x i8> [[TMP23]], <vscale x 4 x i8> [[TMP24]], <vscale x 4 x i8> [[TMP25]], <vscale x 4 x i8> [[TMP26]], <vscale x 4 x i8> [[TMP27]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] undef, <vscale x 4 x i8> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP30]], <vscale x 4 x i8> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP32]], <vscale x 4 x i8> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP34]], <vscale x 4 x i8> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP36]], <vscale x 4 x i8> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP38]], <vscale x 4 x i8> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP40]], <vscale x 4 x i8> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e8_v_u8mf2x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP3]], <vscale x 4 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP4]], <vscale x 4 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP5]], <vscale x 4 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg7.mask.nxv4i8.i64(<vscale x 4 x i8> [[TMP21]], <vscale x 4 x i8> [[TMP22]], <vscale x 4 x i8> [[TMP23]], <vscale x 4 x i8> [[TMP24]], <vscale x 4 x i8> [[TMP25]], <vscale x 4 x i8> [[TMP26]], <vscale x 4 x i8> [[TMP27]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] undef, <vscale x 4 x i8> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP30]], <vscale x 4 x i8> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP32]], <vscale x 4 x i8> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP34]], <vscale x 4 x i8> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP36]], <vscale x 4 x i8> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP38]], <vscale x 4 x i8> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP40]], <vscale x 4 x i8> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP42]]
+//
+vuint8mf2x7_t test_vlseg7e8_v_u8mf2x7_m (vbool16_t mask, vuint8mf2x7_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg7e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e8_v_u8mf2x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP3]], <vscale x 4 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP4]], <vscale x 4 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP5]], <vscale x 4 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP6]], <vscale x 4 x i8> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg8.mask.nxv4i8.i32(<vscale x 4 x i8> [[TMP24]], <vscale x 4 x i8> [[TMP25]], <vscale x 4 x i8> [[TMP26]], <vscale x 4 x i8> [[TMP27]], <vscale x 4 x i8> [[TMP28]], <vscale x 4 x i8> [[TMP29]], <vscale x 4 x i8> [[TMP30]], <vscale x 4 x i8> [[TMP31]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] undef, <vscale x 4 x i8> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP34]], <vscale x 4 x i8> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP36]], <vscale x 4 x i8> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP38]], <vscale x 4 x i8> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP40]], <vscale x 4 x i8> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP42]], <vscale x 4 x i8> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP44]], <vscale x 4 x i8> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP46]], <vscale x 4 x i8> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e8_v_u8mf2x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP3]], <vscale x 4 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP4]], <vscale x 4 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP5]], <vscale x 4 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP6]], <vscale x 4 x i8> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg8.mask.nxv4i8.i64(<vscale x 4 x i8> [[TMP24]], <vscale x 4 x i8> [[TMP25]], <vscale x 4 x i8> [[TMP26]], <vscale x 4 x i8> [[TMP27]], <vscale x 4 x i8> [[TMP28]], <vscale x 4 x i8> [[TMP29]], <vscale x 4 x i8> [[TMP30]], <vscale x 4 x i8> [[TMP31]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] undef, <vscale x 4 x i8> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP34]], <vscale x 4 x i8> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP36]], <vscale x 4 x i8> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP38]], <vscale x 4 x i8> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP40]], <vscale x 4 x i8> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP42]], <vscale x 4 x i8> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP44]], <vscale x 4 x i8> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP46]], <vscale x 4 x i8> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP48]]
+//
+vuint8mf2x8_t test_vlseg8e8_v_u8mf2x8_m (vbool16_t mask, vuint8mf2x8_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg8e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_u8m1x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X2_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X2_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg2.mask.nxv8i8.i32(<vscale x 8 x i8> [[TMP6]], <vscale x 8 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X2_T]] undef, <vscale x 8 x i8> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X2_T]] [[TMP10]], <vscale x 8 x i8> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8M1X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_u8m1x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X2_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X2_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg2.mask.nxv8i8.i64(<vscale x 8 x i8> [[TMP6]], <vscale x 8 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X2_T]] undef, <vscale x 8 x i8> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X2_T]] [[TMP10]], <vscale x 8 x i8> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8M1X2_T]] [[TMP12]]
+//
+vuint8m1x2_t test_vlseg2e8_v_u8m1x2_m (vbool8_t mask, vuint8m1x2_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg2e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e8_v_u8m1x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg3.mask.nxv8i8.i32(<vscale x 8 x i8> [[TMP9]], <vscale x 8 x i8> [[TMP10]], <vscale x 8 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T]] undef, <vscale x 8 x i8> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP14]], <vscale x 8 x i8> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP16]], <vscale x 8 x i8> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8M1X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e8_v_u8m1x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg3.mask.nxv8i8.i64(<vscale x 8 x i8> [[TMP9]], <vscale x 8 x i8> [[TMP10]], <vscale x 8 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T]] undef, <vscale x 8 x i8> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP14]], <vscale x 8 x i8> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP16]], <vscale x 8 x i8> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8M1X3_T]] [[TMP18]]
+//
+vuint8m1x3_t test_vlseg3e8_v_u8m1x3_m (vbool8_t mask, vuint8m1x3_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg3e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e8_v_u8m1x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg4.mask.nxv8i8.i32(<vscale x 8 x i8> [[TMP12]], <vscale x 8 x i8> [[TMP13]], <vscale x 8 x i8> [[TMP14]], <vscale x 8 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] undef, <vscale x 8 x i8> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP18]], <vscale x 8 x i8> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP20]], <vscale x 8 x i8> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP22]], <vscale x 8 x i8> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8M1X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e8_v_u8m1x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg4.mask.nxv8i8.i64(<vscale x 8 x i8> [[TMP12]], <vscale x 8 x i8> [[TMP13]], <vscale x 8 x i8> [[TMP14]], <vscale x 8 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] undef, <vscale x 8 x i8> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP18]], <vscale x 8 x i8> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP20]], <vscale x 8 x i8> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP22]], <vscale x 8 x i8> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8M1X4_T]] [[TMP24]]
+//
+vuint8m1x4_t test_vlseg4e8_v_u8m1x4_m (vbool8_t mask, vuint8m1x4_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg4e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e8_v_u8m1x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP3]], <vscale x 8 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg5.mask.nxv8i8.i32(<vscale x 8 x i8> [[TMP15]], <vscale x 8 x i8> [[TMP16]], <vscale x 8 x i8> [[TMP17]], <vscale x 8 x i8> [[TMP18]], <vscale x 8 x i8> [[TMP19]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] undef, <vscale x 8 x i8> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP22]], <vscale x 8 x i8> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP24]], <vscale x 8 x i8> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP26]], <vscale x 8 x i8> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP28]], <vscale x 8 x i8> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8M1X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e8_v_u8m1x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP3]], <vscale x 8 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg5.mask.nxv8i8.i64(<vscale x 8 x i8> [[TMP15]], <vscale x 8 x i8> [[TMP16]], <vscale x 8 x i8> [[TMP17]], <vscale x 8 x i8> [[TMP18]], <vscale x 8 x i8> [[TMP19]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] undef, <vscale x 8 x i8> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP22]], <vscale x 8 x i8> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP24]], <vscale x 8 x i8> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP26]], <vscale x 8 x i8> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP28]], <vscale x 8 x i8> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8M1X5_T]] [[TMP30]]
+//
+vuint8m1x5_t test_vlseg5e8_v_u8m1x5_m (vbool8_t mask, vuint8m1x5_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg5e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e8_v_u8m1x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP3]], <vscale x 8 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP4]], <vscale x 8 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg6.mask.nxv8i8.i32(<vscale x 8 x i8> [[TMP18]], <vscale x 8 x i8> [[TMP19]], <vscale x 8 x i8> [[TMP20]], <vscale x 8 x i8> [[TMP21]], <vscale x 8 x i8> [[TMP22]], <vscale x 8 x i8> [[TMP23]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] undef, <vscale x 8 x i8> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP26]], <vscale x 8 x i8> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP28]], <vscale x 8 x i8> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP30]], <vscale x 8 x i8> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP32]], <vscale x 8 x i8> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP34]], <vscale x 8 x i8> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8M1X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e8_v_u8m1x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP3]], <vscale x 8 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP4]], <vscale x 8 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg6.mask.nxv8i8.i64(<vscale x 8 x i8> [[TMP18]], <vscale x 8 x i8> [[TMP19]], <vscale x 8 x i8> [[TMP20]], <vscale x 8 x i8> [[TMP21]], <vscale x 8 x i8> [[TMP22]], <vscale x 8 x i8> [[TMP23]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] undef, <vscale x 8 x i8> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP26]], <vscale x 8 x i8> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP28]], <vscale x 8 x i8> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP30]], <vscale x 8 x i8> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP32]], <vscale x 8 x i8> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP34]], <vscale x 8 x i8> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8M1X6_T]] [[TMP36]]
+//
+vuint8m1x6_t test_vlseg6e8_v_u8m1x6_m (vbool8_t mask, vuint8m1x6_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg6e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e8_v_u8m1x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP3]], <vscale x 8 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP4]], <vscale x 8 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP5]], <vscale x 8 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg7.mask.nxv8i8.i32(<vscale x 8 x i8> [[TMP21]], <vscale x 8 x i8> [[TMP22]], <vscale x 8 x i8> [[TMP23]], <vscale x 8 x i8> [[TMP24]], <vscale x 8 x i8> [[TMP25]], <vscale x 8 x i8> [[TMP26]], <vscale x 8 x i8> [[TMP27]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] undef, <vscale x 8 x i8> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP30]], <vscale x 8 x i8> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP32]], <vscale x 8 x i8> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP34]], <vscale x 8 x i8> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP36]], <vscale x 8 x i8> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP38]], <vscale x 8 x i8> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP40]], <vscale x 8 x i8> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8M1X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e8_v_u8m1x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP3]], <vscale x 8 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP4]], <vscale x 8 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP5]], <vscale x 8 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg7.mask.nxv8i8.i64(<vscale x 8 x i8> [[TMP21]], <vscale x 8 x i8> [[TMP22]], <vscale x 8 x i8> [[TMP23]], <vscale x 8 x i8> [[TMP24]], <vscale x 8 x i8> [[TMP25]], <vscale x 8 x i8> [[TMP26]], <vscale x 8 x i8> [[TMP27]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] undef, <vscale x 8 x i8> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP30]], <vscale x 8 x i8> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP32]], <vscale x 8 x i8> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP34]], <vscale x 8 x i8> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP36]], <vscale x 8 x i8> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP38]], <vscale x 8 x i8> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP40]], <vscale x 8 x i8> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8M1X7_T]] [[TMP42]]
+//
+vuint8m1x7_t test_vlseg7e8_v_u8m1x7_m (vbool8_t mask, vuint8m1x7_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg7e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e8_v_u8m1x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP3]], <vscale x 8 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP4]], <vscale x 8 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP5]], <vscale x 8 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP6]], <vscale x 8 x i8> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg8.mask.nxv8i8.i32(<vscale x 8 x i8> [[TMP24]], <vscale x 8 x i8> [[TMP25]], <vscale x 8 x i8> [[TMP26]], <vscale x 8 x i8> [[TMP27]], <vscale x 8 x i8> [[TMP28]], <vscale x 8 x i8> [[TMP29]], <vscale x 8 x i8> [[TMP30]], <vscale x 8 x i8> [[TMP31]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] undef, <vscale x 8 x i8> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP34]], <vscale x 8 x i8> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP36]], <vscale x 8 x i8> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP38]], <vscale x 8 x i8> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP40]], <vscale x 8 x i8> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP42]], <vscale x 8 x i8> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP44]], <vscale x 8 x i8> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP46]], <vscale x 8 x i8> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8M1X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e8_v_u8m1x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP3]], <vscale x 8 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP4]], <vscale x 8 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP5]], <vscale x 8 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP6]], <vscale x 8 x i8> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg8.mask.nxv8i8.i64(<vscale x 8 x i8> [[TMP24]], <vscale x 8 x i8> [[TMP25]], <vscale x 8 x i8> [[TMP26]], <vscale x 8 x i8> [[TMP27]], <vscale x 8 x i8> [[TMP28]], <vscale x 8 x i8> [[TMP29]], <vscale x 8 x i8> [[TMP30]], <vscale x 8 x i8> [[TMP31]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] undef, <vscale x 8 x i8> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP34]], <vscale x 8 x i8> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP36]], <vscale x 8 x i8> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP38]], <vscale x 8 x i8> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP40]], <vscale x 8 x i8> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP42]], <vscale x 8 x i8> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP44]], <vscale x 8 x i8> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP46]], <vscale x 8 x i8> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8M1X8_T]] [[TMP48]]
+//
+vuint8m1x8_t test_vlseg8e8_v_u8m1x8_m (vbool8_t mask, vuint8m1x8_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg8e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_u8m2x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X2_T:%.*]] undef, <vscale x 16 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X2_T]] [[TMP0]], <vscale x 16 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg2.mask.nxv16i8.i32(<vscale x 16 x i8> [[TMP6]], <vscale x 16 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X2_T]] undef, <vscale x 16 x i8> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X2_T]] [[TMP10]], <vscale x 16 x i8> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8M2X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_u8m2x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X2_T:%.*]] undef, <vscale x 16 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X2_T]] [[TMP0]], <vscale x 16 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg2.mask.nxv16i8.i64(<vscale x 16 x i8> [[TMP6]], <vscale x 16 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X2_T]] undef, <vscale x 16 x i8> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X2_T]] [[TMP10]], <vscale x 16 x i8> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8M2X2_T]] [[TMP12]]
+//
+vuint8m2x2_t test_vlseg2e8_v_u8m2x2_m (vbool4_t mask, vuint8m2x2_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg2e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e8_v_u8m2x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T:%.*]] undef, <vscale x 16 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP0]], <vscale x 16 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP1]], <vscale x 16 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg3.mask.nxv16i8.i32(<vscale x 16 x i8> [[TMP9]], <vscale x 16 x i8> [[TMP10]], <vscale x 16 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T]] undef, <vscale x 16 x i8> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP14]], <vscale x 16 x i8> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP16]], <vscale x 16 x i8> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8M2X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e8_v_u8m2x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T:%.*]] undef, <vscale x 16 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP0]], <vscale x 16 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP1]], <vscale x 16 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg3.mask.nxv16i8.i64(<vscale x 16 x i8> [[TMP9]], <vscale x 16 x i8> [[TMP10]], <vscale x 16 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T]] undef, <vscale x 16 x i8> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP14]], <vscale x 16 x i8> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP16]], <vscale x 16 x i8> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8M2X3_T]] [[TMP18]]
+//
+vuint8m2x3_t test_vlseg3e8_v_u8m2x3_m (vbool4_t mask, vuint8m2x3_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg3e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e8_v_u8m2x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T:%.*]] undef, <vscale x 16 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP0]], <vscale x 16 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP1]], <vscale x 16 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP2]], <vscale x 16 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg4.mask.nxv16i8.i32(<vscale x 16 x i8> [[TMP12]], <vscale x 16 x i8> [[TMP13]], <vscale x 16 x i8> [[TMP14]], <vscale x 16 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] undef, <vscale x 16 x i8> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP18]], <vscale x 16 x i8> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP20]], <vscale x 16 x i8> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP22]], <vscale x 16 x i8> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8M2X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e8_v_u8m2x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T:%.*]] undef, <vscale x 16 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP0]], <vscale x 16 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP1]], <vscale x 16 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP2]], <vscale x 16 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg4.mask.nxv16i8.i64(<vscale x 16 x i8> [[TMP12]], <vscale x 16 x i8> [[TMP13]], <vscale x 16 x i8> [[TMP14]], <vscale x 16 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] undef, <vscale x 16 x i8> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP18]], <vscale x 16 x i8> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP20]], <vscale x 16 x i8> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP22]], <vscale x 16 x i8> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8M2X4_T]] [[TMP24]]
+//
+vuint8m2x4_t test_vlseg4e8_v_u8m2x4_m (vbool4_t mask, vuint8m2x4_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg4e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_u8m4x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M4X2_T:%.*]] undef, <vscale x 32 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M4X2_T]] [[TMP0]], <vscale x 32 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT8M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT8M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 32 x i8>, <vscale x 32 x i8> } @llvm.riscv.vlseg2.mask.nxv32i8.i32(<vscale x 32 x i8> [[TMP6]], <vscale x 32 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8M4X2_T]] undef, <vscale x 32 x i8> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8M4X2_T]] [[TMP10]], <vscale x 32 x i8> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8M4X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_u8m4x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M4X2_T:%.*]] undef, <vscale x 32 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M4X2_T]] [[TMP0]], <vscale x 32 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT8M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT8M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 32 x i8>, <vscale x 32 x i8> } @llvm.riscv.vlseg2.mask.nxv32i8.i64(<vscale x 32 x i8> [[TMP6]], <vscale x 32 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8M4X2_T]] undef, <vscale x 32 x i8> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8M4X2_T]] [[TMP10]], <vscale x 32 x i8> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8M4X2_T]] [[TMP12]]
+//
+vuint8m4x2_t test_vlseg2e8_v_u8m4x2_m (vbool2_t mask, vuint8m4x2_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg2e8(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e16_v_u16mf4x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X2_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg2.mask.nxv1i16.i32(<vscale x 1 x i16> [[TMP6]], <vscale x 1 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X2_T]] undef, <vscale x 1 x i16> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP10]], <vscale x 1 x i16> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e16_v_u16mf4x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X2_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg2.mask.nxv1i16.i64(<vscale x 1 x i16> [[TMP6]], <vscale x 1 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X2_T]] undef, <vscale x 1 x i16> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP10]], <vscale x 1 x i16> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP12]]
+//
+vuint16mf4x2_t test_vlseg2e16_v_u16mf4x2_m (vbool64_t mask, vuint16mf4x2_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg2e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e16_v_u16mf4x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg3.mask.nxv1i16.i32(<vscale x 1 x i16> [[TMP9]], <vscale x 1 x i16> [[TMP10]], <vscale x 1 x i16> [[TMP11]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T]] undef, <vscale x 1 x i16> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP14]], <vscale x 1 x i16> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP16]], <vscale x 1 x i16> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e16_v_u16mf4x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg3.mask.nxv1i16.i64(<vscale x 1 x i16> [[TMP9]], <vscale x 1 x i16> [[TMP10]], <vscale x 1 x i16> [[TMP11]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T]] undef, <vscale x 1 x i16> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP14]], <vscale x 1 x i16> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP16]], <vscale x 1 x i16> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP18]]
+//
+vuint16mf4x3_t test_vlseg3e16_v_u16mf4x3_m (vbool64_t mask, vuint16mf4x3_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg3e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e16_v_u16mf4x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg4.mask.nxv1i16.i32(<vscale x 1 x i16> [[TMP12]], <vscale x 1 x i16> [[TMP13]], <vscale x 1 x i16> [[TMP14]], <vscale x 1 x i16> [[TMP15]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] undef, <vscale x 1 x i16> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP18]], <vscale x 1 x i16> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP20]], <vscale x 1 x i16> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP22]], <vscale x 1 x i16> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e16_v_u16mf4x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg4.mask.nxv1i16.i64(<vscale x 1 x i16> [[TMP12]], <vscale x 1 x i16> [[TMP13]], <vscale x 1 x i16> [[TMP14]], <vscale x 1 x i16> [[TMP15]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] undef, <vscale x 1 x i16> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP18]], <vscale x 1 x i16> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP20]], <vscale x 1 x i16> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP22]], <vscale x 1 x i16> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP24]]
+//
+vuint16mf4x4_t test_vlseg4e16_v_u16mf4x4_m (vbool64_t mask, vuint16mf4x4_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg4e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e16_v_u16mf4x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP3]], <vscale x 1 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg5.mask.nxv1i16.i32(<vscale x 1 x i16> [[TMP15]], <vscale x 1 x i16> [[TMP16]], <vscale x 1 x i16> [[TMP17]], <vscale x 1 x i16> [[TMP18]], <vscale x 1 x i16> [[TMP19]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] undef, <vscale x 1 x i16> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP22]], <vscale x 1 x i16> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP24]], <vscale x 1 x i16> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP26]], <vscale x 1 x i16> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP28]], <vscale x 1 x i16> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e16_v_u16mf4x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP3]], <vscale x 1 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg5.mask.nxv1i16.i64(<vscale x 1 x i16> [[TMP15]], <vscale x 1 x i16> [[TMP16]], <vscale x 1 x i16> [[TMP17]], <vscale x 1 x i16> [[TMP18]], <vscale x 1 x i16> [[TMP19]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] undef, <vscale x 1 x i16> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP22]], <vscale x 1 x i16> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP24]], <vscale x 1 x i16> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP26]], <vscale x 1 x i16> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP28]], <vscale x 1 x i16> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP30]]
+//
+vuint16mf4x5_t test_vlseg5e16_v_u16mf4x5_m (vbool64_t mask, vuint16mf4x5_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg5e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e16_v_u16mf4x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP3]], <vscale x 1 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP4]], <vscale x 1 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg6.mask.nxv1i16.i32(<vscale x 1 x i16> [[TMP18]], <vscale x 1 x i16> [[TMP19]], <vscale x 1 x i16> [[TMP20]], <vscale x 1 x i16> [[TMP21]], <vscale x 1 x i16> [[TMP22]], <vscale x 1 x i16> [[TMP23]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] undef, <vscale x 1 x i16> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP26]], <vscale x 1 x i16> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP28]], <vscale x 1 x i16> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP30]], <vscale x 1 x i16> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP32]], <vscale x 1 x i16> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP34]], <vscale x 1 x i16> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e16_v_u16mf4x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP3]], <vscale x 1 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP4]], <vscale x 1 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg6.mask.nxv1i16.i64(<vscale x 1 x i16> [[TMP18]], <vscale x 1 x i16> [[TMP19]], <vscale x 1 x i16> [[TMP20]], <vscale x 1 x i16> [[TMP21]], <vscale x 1 x i16> [[TMP22]], <vscale x 1 x i16> [[TMP23]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] undef, <vscale x 1 x i16> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP26]], <vscale x 1 x i16> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP28]], <vscale x 1 x i16> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP30]], <vscale x 1 x i16> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP32]], <vscale x 1 x i16> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP34]], <vscale x 1 x i16> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP36]]
+//
+vuint16mf4x6_t test_vlseg6e16_v_u16mf4x6_m (vbool64_t mask, vuint16mf4x6_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg6e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e16_v_u16mf4x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP3]], <vscale x 1 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP4]], <vscale x 1 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP5]], <vscale x 1 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg7.mask.nxv1i16.i32(<vscale x 1 x i16> [[TMP21]], <vscale x 1 x i16> [[TMP22]], <vscale x 1 x i16> [[TMP23]], <vscale x 1 x i16> [[TMP24]], <vscale x 1 x i16> [[TMP25]], <vscale x 1 x i16> [[TMP26]], <vscale x 1 x i16> [[TMP27]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] undef, <vscale x 1 x i16> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP30]], <vscale x 1 x i16> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP32]], <vscale x 1 x i16> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP34]], <vscale x 1 x i16> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP36]], <vscale x 1 x i16> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP38]], <vscale x 1 x i16> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP40]], <vscale x 1 x i16> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e16_v_u16mf4x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP3]], <vscale x 1 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP4]], <vscale x 1 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP5]], <vscale x 1 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg7.mask.nxv1i16.i64(<vscale x 1 x i16> [[TMP21]], <vscale x 1 x i16> [[TMP22]], <vscale x 1 x i16> [[TMP23]], <vscale x 1 x i16> [[TMP24]], <vscale x 1 x i16> [[TMP25]], <vscale x 1 x i16> [[TMP26]], <vscale x 1 x i16> [[TMP27]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] undef, <vscale x 1 x i16> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP30]], <vscale x 1 x i16> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP32]], <vscale x 1 x i16> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP34]], <vscale x 1 x i16> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP36]], <vscale x 1 x i16> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP38]], <vscale x 1 x i16> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP40]], <vscale x 1 x i16> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP42]]
+//
+vuint16mf4x7_t test_vlseg7e16_v_u16mf4x7_m (vbool64_t mask, vuint16mf4x7_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg7e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e16_v_u16mf4x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP3]], <vscale x 1 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP4]], <vscale x 1 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP5]], <vscale x 1 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP6]], <vscale x 1 x i16> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg8.mask.nxv1i16.i32(<vscale x 1 x i16> [[TMP24]], <vscale x 1 x i16> [[TMP25]], <vscale x 1 x i16> [[TMP26]], <vscale x 1 x i16> [[TMP27]], <vscale x 1 x i16> [[TMP28]], <vscale x 1 x i16> [[TMP29]], <vscale x 1 x i16> [[TMP30]], <vscale x 1 x i16> [[TMP31]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] undef, <vscale x 1 x i16> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP34]], <vscale x 1 x i16> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP36]], <vscale x 1 x i16> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP38]], <vscale x 1 x i16> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP40]], <vscale x 1 x i16> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP42]], <vscale x 1 x i16> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP44]], <vscale x 1 x i16> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP46]], <vscale x 1 x i16> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e16_v_u16mf4x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP3]], <vscale x 1 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP4]], <vscale x 1 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP5]], <vscale x 1 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP6]], <vscale x 1 x i16> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg8.mask.nxv1i16.i64(<vscale x 1 x i16> [[TMP24]], <vscale x 1 x i16> [[TMP25]], <vscale x 1 x i16> [[TMP26]], <vscale x 1 x i16> [[TMP27]], <vscale x 1 x i16> [[TMP28]], <vscale x 1 x i16> [[TMP29]], <vscale x 1 x i16> [[TMP30]], <vscale x 1 x i16> [[TMP31]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] undef, <vscale x 1 x i16> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP34]], <vscale x 1 x i16> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP36]], <vscale x 1 x i16> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP38]], <vscale x 1 x i16> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP40]], <vscale x 1 x i16> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP42]], <vscale x 1 x i16> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP44]], <vscale x 1 x i16> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP46]], <vscale x 1 x i16> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP48]]
+//
+vuint16mf4x8_t test_vlseg8e16_v_u16mf4x8_m (vbool64_t mask, vuint16mf4x8_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg8e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e16_v_u16mf2x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X2_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg2.mask.nxv2i16.i32(<vscale x 2 x i16> [[TMP6]], <vscale x 2 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X2_T]] undef, <vscale x 2 x i16> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP10]], <vscale x 2 x i16> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e16_v_u16mf2x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X2_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg2.mask.nxv2i16.i64(<vscale x 2 x i16> [[TMP6]], <vscale x 2 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X2_T]] undef, <vscale x 2 x i16> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP10]], <vscale x 2 x i16> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP12]]
+//
+vuint16mf2x2_t test_vlseg2e16_v_u16mf2x2_m (vbool32_t mask, vuint16mf2x2_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg2e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e16_v_u16mf2x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg3.mask.nxv2i16.i32(<vscale x 2 x i16> [[TMP9]], <vscale x 2 x i16> [[TMP10]], <vscale x 2 x i16> [[TMP11]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T]] undef, <vscale x 2 x i16> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP14]], <vscale x 2 x i16> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP16]], <vscale x 2 x i16> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e16_v_u16mf2x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg3.mask.nxv2i16.i64(<vscale x 2 x i16> [[TMP9]], <vscale x 2 x i16> [[TMP10]], <vscale x 2 x i16> [[TMP11]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T]] undef, <vscale x 2 x i16> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP14]], <vscale x 2 x i16> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP16]], <vscale x 2 x i16> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP18]]
+//
+vuint16mf2x3_t test_vlseg3e16_v_u16mf2x3_m (vbool32_t mask, vuint16mf2x3_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg3e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e16_v_u16mf2x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg4.mask.nxv2i16.i32(<vscale x 2 x i16> [[TMP12]], <vscale x 2 x i16> [[TMP13]], <vscale x 2 x i16> [[TMP14]], <vscale x 2 x i16> [[TMP15]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] undef, <vscale x 2 x i16> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP18]], <vscale x 2 x i16> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP20]], <vscale x 2 x i16> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP22]], <vscale x 2 x i16> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e16_v_u16mf2x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg4.mask.nxv2i16.i64(<vscale x 2 x i16> [[TMP12]], <vscale x 2 x i16> [[TMP13]], <vscale x 2 x i16> [[TMP14]], <vscale x 2 x i16> [[TMP15]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] undef, <vscale x 2 x i16> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP18]], <vscale x 2 x i16> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP20]], <vscale x 2 x i16> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP22]], <vscale x 2 x i16> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP24]]
+//
+vuint16mf2x4_t test_vlseg4e16_v_u16mf2x4_m (vbool32_t mask, vuint16mf2x4_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg4e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e16_v_u16mf2x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP3]], <vscale x 2 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg5.mask.nxv2i16.i32(<vscale x 2 x i16> [[TMP15]], <vscale x 2 x i16> [[TMP16]], <vscale x 2 x i16> [[TMP17]], <vscale x 2 x i16> [[TMP18]], <vscale x 2 x i16> [[TMP19]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] undef, <vscale x 2 x i16> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP22]], <vscale x 2 x i16> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP24]], <vscale x 2 x i16> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP26]], <vscale x 2 x i16> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP28]], <vscale x 2 x i16> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e16_v_u16mf2x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP3]], <vscale x 2 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg5.mask.nxv2i16.i64(<vscale x 2 x i16> [[TMP15]], <vscale x 2 x i16> [[TMP16]], <vscale x 2 x i16> [[TMP17]], <vscale x 2 x i16> [[TMP18]], <vscale x 2 x i16> [[TMP19]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] undef, <vscale x 2 x i16> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP22]], <vscale x 2 x i16> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP24]], <vscale x 2 x i16> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP26]], <vscale x 2 x i16> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP28]], <vscale x 2 x i16> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP30]]
+//
+vuint16mf2x5_t test_vlseg5e16_v_u16mf2x5_m (vbool32_t mask, vuint16mf2x5_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg5e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e16_v_u16mf2x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP3]], <vscale x 2 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP4]], <vscale x 2 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg6.mask.nxv2i16.i32(<vscale x 2 x i16> [[TMP18]], <vscale x 2 x i16> [[TMP19]], <vscale x 2 x i16> [[TMP20]], <vscale x 2 x i16> [[TMP21]], <vscale x 2 x i16> [[TMP22]], <vscale x 2 x i16> [[TMP23]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] undef, <vscale x 2 x i16> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP26]], <vscale x 2 x i16> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP28]], <vscale x 2 x i16> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP30]], <vscale x 2 x i16> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP32]], <vscale x 2 x i16> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP34]], <vscale x 2 x i16> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e16_v_u16mf2x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP3]], <vscale x 2 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP4]], <vscale x 2 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg6.mask.nxv2i16.i64(<vscale x 2 x i16> [[TMP18]], <vscale x 2 x i16> [[TMP19]], <vscale x 2 x i16> [[TMP20]], <vscale x 2 x i16> [[TMP21]], <vscale x 2 x i16> [[TMP22]], <vscale x 2 x i16> [[TMP23]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] undef, <vscale x 2 x i16> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP26]], <vscale x 2 x i16> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP28]], <vscale x 2 x i16> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP30]], <vscale x 2 x i16> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP32]], <vscale x 2 x i16> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP34]], <vscale x 2 x i16> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP36]]
+//
+vuint16mf2x6_t test_vlseg6e16_v_u16mf2x6_m (vbool32_t mask, vuint16mf2x6_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg6e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e16_v_u16mf2x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP3]], <vscale x 2 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP4]], <vscale x 2 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP5]], <vscale x 2 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg7.mask.nxv2i16.i32(<vscale x 2 x i16> [[TMP21]], <vscale x 2 x i16> [[TMP22]], <vscale x 2 x i16> [[TMP23]], <vscale x 2 x i16> [[TMP24]], <vscale x 2 x i16> [[TMP25]], <vscale x 2 x i16> [[TMP26]], <vscale x 2 x i16> [[TMP27]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] undef, <vscale x 2 x i16> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP30]], <vscale x 2 x i16> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP32]], <vscale x 2 x i16> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP34]], <vscale x 2 x i16> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP36]], <vscale x 2 x i16> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP38]], <vscale x 2 x i16> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP40]], <vscale x 2 x i16> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e16_v_u16mf2x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP3]], <vscale x 2 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP4]], <vscale x 2 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP5]], <vscale x 2 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg7.mask.nxv2i16.i64(<vscale x 2 x i16> [[TMP21]], <vscale x 2 x i16> [[TMP22]], <vscale x 2 x i16> [[TMP23]], <vscale x 2 x i16> [[TMP24]], <vscale x 2 x i16> [[TMP25]], <vscale x 2 x i16> [[TMP26]], <vscale x 2 x i16> [[TMP27]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] undef, <vscale x 2 x i16> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP30]], <vscale x 2 x i16> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP32]], <vscale x 2 x i16> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP34]], <vscale x 2 x i16> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP36]], <vscale x 2 x i16> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP38]], <vscale x 2 x i16> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP40]], <vscale x 2 x i16> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP42]]
+//
+vuint16mf2x7_t test_vlseg7e16_v_u16mf2x7_m (vbool32_t mask, vuint16mf2x7_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg7e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e16_v_u16mf2x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP3]], <vscale x 2 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP4]], <vscale x 2 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP5]], <vscale x 2 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP6]], <vscale x 2 x i16> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg8.mask.nxv2i16.i32(<vscale x 2 x i16> [[TMP24]], <vscale x 2 x i16> [[TMP25]], <vscale x 2 x i16> [[TMP26]], <vscale x 2 x i16> [[TMP27]], <vscale x 2 x i16> [[TMP28]], <vscale x 2 x i16> [[TMP29]], <vscale x 2 x i16> [[TMP30]], <vscale x 2 x i16> [[TMP31]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] undef, <vscale x 2 x i16> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP34]], <vscale x 2 x i16> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP36]], <vscale x 2 x i16> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP38]], <vscale x 2 x i16> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP40]], <vscale x 2 x i16> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP42]], <vscale x 2 x i16> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP44]], <vscale x 2 x i16> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP46]], <vscale x 2 x i16> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e16_v_u16mf2x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP3]], <vscale x 2 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP4]], <vscale x 2 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP5]], <vscale x 2 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP6]], <vscale x 2 x i16> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg8.mask.nxv2i16.i64(<vscale x 2 x i16> [[TMP24]], <vscale x 2 x i16> [[TMP25]], <vscale x 2 x i16> [[TMP26]], <vscale x 2 x i16> [[TMP27]], <vscale x 2 x i16> [[TMP28]], <vscale x 2 x i16> [[TMP29]], <vscale x 2 x i16> [[TMP30]], <vscale x 2 x i16> [[TMP31]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] undef, <vscale x 2 x i16> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP34]], <vscale x 2 x i16> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP36]], <vscale x 2 x i16> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP38]], <vscale x 2 x i16> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP40]], <vscale x 2 x i16> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP42]], <vscale x 2 x i16> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP44]], <vscale x 2 x i16> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP46]], <vscale x 2 x i16> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP48]]
+//
+vuint16mf2x8_t test_vlseg8e16_v_u16mf2x8_m (vbool32_t mask, vuint16mf2x8_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg8e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e16_v_u16m1x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X2_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X2_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg2.mask.nxv4i16.i32(<vscale x 4 x i16> [[TMP6]], <vscale x 4 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X2_T]] undef, <vscale x 4 x i16> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X2_T]] [[TMP10]], <vscale x 4 x i16> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16M1X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e16_v_u16m1x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X2_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X2_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg2.mask.nxv4i16.i64(<vscale x 4 x i16> [[TMP6]], <vscale x 4 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X2_T]] undef, <vscale x 4 x i16> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X2_T]] [[TMP10]], <vscale x 4 x i16> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16M1X2_T]] [[TMP12]]
+//
+vuint16m1x2_t test_vlseg2e16_v_u16m1x2_m (vbool16_t mask, vuint16m1x2_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg2e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e16_v_u16m1x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg3.mask.nxv4i16.i32(<vscale x 4 x i16> [[TMP9]], <vscale x 4 x i16> [[TMP10]], <vscale x 4 x i16> [[TMP11]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T]] undef, <vscale x 4 x i16> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP14]], <vscale x 4 x i16> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP16]], <vscale x 4 x i16> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16M1X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e16_v_u16m1x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg3.mask.nxv4i16.i64(<vscale x 4 x i16> [[TMP9]], <vscale x 4 x i16> [[TMP10]], <vscale x 4 x i16> [[TMP11]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T]] undef, <vscale x 4 x i16> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP14]], <vscale x 4 x i16> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP16]], <vscale x 4 x i16> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16M1X3_T]] [[TMP18]]
+//
+vuint16m1x3_t test_vlseg3e16_v_u16m1x3_m (vbool16_t mask, vuint16m1x3_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg3e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e16_v_u16m1x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg4.mask.nxv4i16.i32(<vscale x 4 x i16> [[TMP12]], <vscale x 4 x i16> [[TMP13]], <vscale x 4 x i16> [[TMP14]], <vscale x 4 x i16> [[TMP15]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] undef, <vscale x 4 x i16> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP18]], <vscale x 4 x i16> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP20]], <vscale x 4 x i16> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP22]], <vscale x 4 x i16> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16M1X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e16_v_u16m1x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg4.mask.nxv4i16.i64(<vscale x 4 x i16> [[TMP12]], <vscale x 4 x i16> [[TMP13]], <vscale x 4 x i16> [[TMP14]], <vscale x 4 x i16> [[TMP15]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] undef, <vscale x 4 x i16> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP18]], <vscale x 4 x i16> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP20]], <vscale x 4 x i16> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP22]], <vscale x 4 x i16> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16M1X4_T]] [[TMP24]]
+//
+vuint16m1x4_t test_vlseg4e16_v_u16m1x4_m (vbool16_t mask, vuint16m1x4_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg4e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e16_v_u16m1x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP3]], <vscale x 4 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg5.mask.nxv4i16.i32(<vscale x 4 x i16> [[TMP15]], <vscale x 4 x i16> [[TMP16]], <vscale x 4 x i16> [[TMP17]], <vscale x 4 x i16> [[TMP18]], <vscale x 4 x i16> [[TMP19]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] undef, <vscale x 4 x i16> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP22]], <vscale x 4 x i16> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP24]], <vscale x 4 x i16> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP26]], <vscale x 4 x i16> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP28]], <vscale x 4 x i16> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16M1X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e16_v_u16m1x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP3]], <vscale x 4 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg5.mask.nxv4i16.i64(<vscale x 4 x i16> [[TMP15]], <vscale x 4 x i16> [[TMP16]], <vscale x 4 x i16> [[TMP17]], <vscale x 4 x i16> [[TMP18]], <vscale x 4 x i16> [[TMP19]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] undef, <vscale x 4 x i16> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP22]], <vscale x 4 x i16> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP24]], <vscale x 4 x i16> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP26]], <vscale x 4 x i16> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP28]], <vscale x 4 x i16> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16M1X5_T]] [[TMP30]]
+//
+vuint16m1x5_t test_vlseg5e16_v_u16m1x5_m (vbool16_t mask, vuint16m1x5_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg5e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e16_v_u16m1x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP3]], <vscale x 4 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP4]], <vscale x 4 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg6.mask.nxv4i16.i32(<vscale x 4 x i16> [[TMP18]], <vscale x 4 x i16> [[TMP19]], <vscale x 4 x i16> [[TMP20]], <vscale x 4 x i16> [[TMP21]], <vscale x 4 x i16> [[TMP22]], <vscale x 4 x i16> [[TMP23]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] undef, <vscale x 4 x i16> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP26]], <vscale x 4 x i16> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP28]], <vscale x 4 x i16> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP30]], <vscale x 4 x i16> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP32]], <vscale x 4 x i16> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP34]], <vscale x 4 x i16> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16M1X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e16_v_u16m1x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP3]], <vscale x 4 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP4]], <vscale x 4 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg6.mask.nxv4i16.i64(<vscale x 4 x i16> [[TMP18]], <vscale x 4 x i16> [[TMP19]], <vscale x 4 x i16> [[TMP20]], <vscale x 4 x i16> [[TMP21]], <vscale x 4 x i16> [[TMP22]], <vscale x 4 x i16> [[TMP23]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] undef, <vscale x 4 x i16> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP26]], <vscale x 4 x i16> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP28]], <vscale x 4 x i16> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP30]], <vscale x 4 x i16> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP32]], <vscale x 4 x i16> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP34]], <vscale x 4 x i16> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16M1X6_T]] [[TMP36]]
+//
+vuint16m1x6_t test_vlseg6e16_v_u16m1x6_m (vbool16_t mask, vuint16m1x6_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg6e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e16_v_u16m1x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP3]], <vscale x 4 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP4]], <vscale x 4 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP5]], <vscale x 4 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg7.mask.nxv4i16.i32(<vscale x 4 x i16> [[TMP21]], <vscale x 4 x i16> [[TMP22]], <vscale x 4 x i16> [[TMP23]], <vscale x 4 x i16> [[TMP24]], <vscale x 4 x i16> [[TMP25]], <vscale x 4 x i16> [[TMP26]], <vscale x 4 x i16> [[TMP27]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] undef, <vscale x 4 x i16> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP30]], <vscale x 4 x i16> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP32]], <vscale x 4 x i16> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP34]], <vscale x 4 x i16> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP36]], <vscale x 4 x i16> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP38]], <vscale x 4 x i16> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP40]], <vscale x 4 x i16> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16M1X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e16_v_u16m1x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP3]], <vscale x 4 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP4]], <vscale x 4 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP5]], <vscale x 4 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg7.mask.nxv4i16.i64(<vscale x 4 x i16> [[TMP21]], <vscale x 4 x i16> [[TMP22]], <vscale x 4 x i16> [[TMP23]], <vscale x 4 x i16> [[TMP24]], <vscale x 4 x i16> [[TMP25]], <vscale x 4 x i16> [[TMP26]], <vscale x 4 x i16> [[TMP27]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] undef, <vscale x 4 x i16> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP30]], <vscale x 4 x i16> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP32]], <vscale x 4 x i16> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP34]], <vscale x 4 x i16> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP36]], <vscale x 4 x i16> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP38]], <vscale x 4 x i16> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP40]], <vscale x 4 x i16> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16M1X7_T]] [[TMP42]]
+//
+vuint16m1x7_t test_vlseg7e16_v_u16m1x7_m (vbool16_t mask, vuint16m1x7_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg7e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e16_v_u16m1x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP3]], <vscale x 4 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP4]], <vscale x 4 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP5]], <vscale x 4 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP6]], <vscale x 4 x i16> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg8.mask.nxv4i16.i32(<vscale x 4 x i16> [[TMP24]], <vscale x 4 x i16> [[TMP25]], <vscale x 4 x i16> [[TMP26]], <vscale x 4 x i16> [[TMP27]], <vscale x 4 x i16> [[TMP28]], <vscale x 4 x i16> [[TMP29]], <vscale x 4 x i16> [[TMP30]], <vscale x 4 x i16> [[TMP31]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] undef, <vscale x 4 x i16> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP34]], <vscale x 4 x i16> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP36]], <vscale x 4 x i16> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP38]], <vscale x 4 x i16> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP40]], <vscale x 4 x i16> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP42]], <vscale x 4 x i16> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP44]], <vscale x 4 x i16> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP46]], <vscale x 4 x i16> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16M1X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e16_v_u16m1x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP3]], <vscale x 4 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP4]], <vscale x 4 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP5]], <vscale x 4 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP6]], <vscale x 4 x i16> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg8.mask.nxv4i16.i64(<vscale x 4 x i16> [[TMP24]], <vscale x 4 x i16> [[TMP25]], <vscale x 4 x i16> [[TMP26]], <vscale x 4 x i16> [[TMP27]], <vscale x 4 x i16> [[TMP28]], <vscale x 4 x i16> [[TMP29]], <vscale x 4 x i16> [[TMP30]], <vscale x 4 x i16> [[TMP31]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] undef, <vscale x 4 x i16> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP34]], <vscale x 4 x i16> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP36]], <vscale x 4 x i16> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP38]], <vscale x 4 x i16> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP40]], <vscale x 4 x i16> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP42]], <vscale x 4 x i16> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP44]], <vscale x 4 x i16> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP46]], <vscale x 4 x i16> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16M1X8_T]] [[TMP48]]
+//
+vuint16m1x8_t test_vlseg8e16_v_u16m1x8_m (vbool16_t mask, vuint16m1x8_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg8e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e16_v_u16m2x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X2_T:%.*]] undef, <vscale x 8 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X2_T]] [[TMP0]], <vscale x 8 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg2.mask.nxv8i16.i32(<vscale x 8 x i16> [[TMP6]], <vscale x 8 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X2_T]] undef, <vscale x 8 x i16> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X2_T]] [[TMP10]], <vscale x 8 x i16> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16M2X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e16_v_u16m2x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X2_T:%.*]] undef, <vscale x 8 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X2_T]] [[TMP0]], <vscale x 8 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg2.mask.nxv8i16.i64(<vscale x 8 x i16> [[TMP6]], <vscale x 8 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X2_T]] undef, <vscale x 8 x i16> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X2_T]] [[TMP10]], <vscale x 8 x i16> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16M2X2_T]] [[TMP12]]
+//
+vuint16m2x2_t test_vlseg2e16_v_u16m2x2_m (vbool8_t mask, vuint16m2x2_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg2e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e16_v_u16m2x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T:%.*]] undef, <vscale x 8 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP0]], <vscale x 8 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP1]], <vscale x 8 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg3.mask.nxv8i16.i32(<vscale x 8 x i16> [[TMP9]], <vscale x 8 x i16> [[TMP10]], <vscale x 8 x i16> [[TMP11]], i16* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T]] undef, <vscale x 8 x i16> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP14]], <vscale x 8 x i16> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP16]], <vscale x 8 x i16> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16M2X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e16_v_u16m2x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T:%.*]] undef, <vscale x 8 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP0]], <vscale x 8 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP1]], <vscale x 8 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg3.mask.nxv8i16.i64(<vscale x 8 x i16> [[TMP9]], <vscale x 8 x i16> [[TMP10]], <vscale x 8 x i16> [[TMP11]], i16* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T]] undef, <vscale x 8 x i16> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP14]], <vscale x 8 x i16> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP16]], <vscale x 8 x i16> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16M2X3_T]] [[TMP18]]
+//
+vuint16m2x3_t test_vlseg3e16_v_u16m2x3_m (vbool8_t mask, vuint16m2x3_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg3e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e16_v_u16m2x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T:%.*]] undef, <vscale x 8 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP0]], <vscale x 8 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP1]], <vscale x 8 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP2]], <vscale x 8 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg4.mask.nxv8i16.i32(<vscale x 8 x i16> [[TMP12]], <vscale x 8 x i16> [[TMP13]], <vscale x 8 x i16> [[TMP14]], <vscale x 8 x i16> [[TMP15]], i16* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] undef, <vscale x 8 x i16> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP18]], <vscale x 8 x i16> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP20]], <vscale x 8 x i16> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP22]], <vscale x 8 x i16> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16M2X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e16_v_u16m2x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T:%.*]] undef, <vscale x 8 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP0]], <vscale x 8 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP1]], <vscale x 8 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP2]], <vscale x 8 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg4.mask.nxv8i16.i64(<vscale x 8 x i16> [[TMP12]], <vscale x 8 x i16> [[TMP13]], <vscale x 8 x i16> [[TMP14]], <vscale x 8 x i16> [[TMP15]], i16* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] undef, <vscale x 8 x i16> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP18]], <vscale x 8 x i16> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP20]], <vscale x 8 x i16> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP22]], <vscale x 8 x i16> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16M2X4_T]] [[TMP24]]
+//
+vuint16m2x4_t test_vlseg4e16_v_u16m2x4_m (vbool8_t mask, vuint16m2x4_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg4e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e16_v_u16m4x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M4X2_T:%.*]] undef, <vscale x 16 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M4X2_T]] [[TMP0]], <vscale x 16 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT16M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT16M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 16 x i16>, <vscale x 16 x i16> } @llvm.riscv.vlseg2.mask.nxv16i16.i32(<vscale x 16 x i16> [[TMP6]], <vscale x 16 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i16> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16M4X2_T]] undef, <vscale x 16 x i16> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i16> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16M4X2_T]] [[TMP10]], <vscale x 16 x i16> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16M4X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e16_v_u16m4x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M4X2_T:%.*]] undef, <vscale x 16 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M4X2_T]] [[TMP0]], <vscale x 16 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT16M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT16M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 16 x i16>, <vscale x 16 x i16> } @llvm.riscv.vlseg2.mask.nxv16i16.i64(<vscale x 16 x i16> [[TMP6]], <vscale x 16 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i16> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16M4X2_T]] undef, <vscale x 16 x i16> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i16> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16M4X2_T]] [[TMP10]], <vscale x 16 x i16> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16M4X2_T]] [[TMP12]]
+//
+vuint16m4x2_t test_vlseg2e16_v_u16m4x2_m (vbool4_t mask, vuint16m4x2_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg2e16(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_u32mf2x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X2_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg2.mask.nxv1i32.i32(<vscale x 1 x i32> [[TMP6]], <vscale x 1 x i32> [[TMP7]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X2_T]] undef, <vscale x 1 x i32> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP10]], <vscale x 1 x i32> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_u32mf2x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X2_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg2.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP6]], <vscale x 1 x i32> [[TMP7]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X2_T]] undef, <vscale x 1 x i32> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP10]], <vscale x 1 x i32> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP12]]
+//
+vuint32mf2x2_t test_vlseg2e32_v_u32mf2x2_m (vbool64_t mask, vuint32mf2x2_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg2e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e32_v_u32mf2x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg3.mask.nxv1i32.i32(<vscale x 1 x i32> [[TMP9]], <vscale x 1 x i32> [[TMP10]], <vscale x 1 x i32> [[TMP11]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T]] undef, <vscale x 1 x i32> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP14]], <vscale x 1 x i32> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP16]], <vscale x 1 x i32> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e32_v_u32mf2x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg3.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP9]], <vscale x 1 x i32> [[TMP10]], <vscale x 1 x i32> [[TMP11]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T]] undef, <vscale x 1 x i32> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP14]], <vscale x 1 x i32> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP16]], <vscale x 1 x i32> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP18]]
+//
+vuint32mf2x3_t test_vlseg3e32_v_u32mf2x3_m (vbool64_t mask, vuint32mf2x3_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg3e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e32_v_u32mf2x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg4.mask.nxv1i32.i32(<vscale x 1 x i32> [[TMP12]], <vscale x 1 x i32> [[TMP13]], <vscale x 1 x i32> [[TMP14]], <vscale x 1 x i32> [[TMP15]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] undef, <vscale x 1 x i32> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP18]], <vscale x 1 x i32> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP20]], <vscale x 1 x i32> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP22]], <vscale x 1 x i32> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e32_v_u32mf2x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg4.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP12]], <vscale x 1 x i32> [[TMP13]], <vscale x 1 x i32> [[TMP14]], <vscale x 1 x i32> [[TMP15]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] undef, <vscale x 1 x i32> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP18]], <vscale x 1 x i32> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP20]], <vscale x 1 x i32> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP22]], <vscale x 1 x i32> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP24]]
+//
+vuint32mf2x4_t test_vlseg4e32_v_u32mf2x4_m (vbool64_t mask, vuint32mf2x4_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg4e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e32_v_u32mf2x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP3]], <vscale x 1 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg5.mask.nxv1i32.i32(<vscale x 1 x i32> [[TMP15]], <vscale x 1 x i32> [[TMP16]], <vscale x 1 x i32> [[TMP17]], <vscale x 1 x i32> [[TMP18]], <vscale x 1 x i32> [[TMP19]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] undef, <vscale x 1 x i32> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP22]], <vscale x 1 x i32> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP24]], <vscale x 1 x i32> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP26]], <vscale x 1 x i32> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP28]], <vscale x 1 x i32> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e32_v_u32mf2x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP3]], <vscale x 1 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg5.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP15]], <vscale x 1 x i32> [[TMP16]], <vscale x 1 x i32> [[TMP17]], <vscale x 1 x i32> [[TMP18]], <vscale x 1 x i32> [[TMP19]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] undef, <vscale x 1 x i32> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP22]], <vscale x 1 x i32> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP24]], <vscale x 1 x i32> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP26]], <vscale x 1 x i32> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP28]], <vscale x 1 x i32> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP30]]
+//
+vuint32mf2x5_t test_vlseg5e32_v_u32mf2x5_m (vbool64_t mask, vuint32mf2x5_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg5e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e32_v_u32mf2x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP3]], <vscale x 1 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP4]], <vscale x 1 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg6.mask.nxv1i32.i32(<vscale x 1 x i32> [[TMP18]], <vscale x 1 x i32> [[TMP19]], <vscale x 1 x i32> [[TMP20]], <vscale x 1 x i32> [[TMP21]], <vscale x 1 x i32> [[TMP22]], <vscale x 1 x i32> [[TMP23]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] undef, <vscale x 1 x i32> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP26]], <vscale x 1 x i32> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP28]], <vscale x 1 x i32> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP30]], <vscale x 1 x i32> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP32]], <vscale x 1 x i32> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP34]], <vscale x 1 x i32> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e32_v_u32mf2x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP3]], <vscale x 1 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP4]], <vscale x 1 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg6.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP18]], <vscale x 1 x i32> [[TMP19]], <vscale x 1 x i32> [[TMP20]], <vscale x 1 x i32> [[TMP21]], <vscale x 1 x i32> [[TMP22]], <vscale x 1 x i32> [[TMP23]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] undef, <vscale x 1 x i32> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP26]], <vscale x 1 x i32> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP28]], <vscale x 1 x i32> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP30]], <vscale x 1 x i32> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP32]], <vscale x 1 x i32> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP34]], <vscale x 1 x i32> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP36]]
+//
+vuint32mf2x6_t test_vlseg6e32_v_u32mf2x6_m (vbool64_t mask, vuint32mf2x6_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg6e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e32_v_u32mf2x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP3]], <vscale x 1 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP4]], <vscale x 1 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP5]], <vscale x 1 x i32> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg7.mask.nxv1i32.i32(<vscale x 1 x i32> [[TMP21]], <vscale x 1 x i32> [[TMP22]], <vscale x 1 x i32> [[TMP23]], <vscale x 1 x i32> [[TMP24]], <vscale x 1 x i32> [[TMP25]], <vscale x 1 x i32> [[TMP26]], <vscale x 1 x i32> [[TMP27]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] undef, <vscale x 1 x i32> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP30]], <vscale x 1 x i32> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP32]], <vscale x 1 x i32> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP34]], <vscale x 1 x i32> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP36]], <vscale x 1 x i32> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP38]], <vscale x 1 x i32> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP40]], <vscale x 1 x i32> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e32_v_u32mf2x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP3]], <vscale x 1 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP4]], <vscale x 1 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP5]], <vscale x 1 x i32> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg7.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP21]], <vscale x 1 x i32> [[TMP22]], <vscale x 1 x i32> [[TMP23]], <vscale x 1 x i32> [[TMP24]], <vscale x 1 x i32> [[TMP25]], <vscale x 1 x i32> [[TMP26]], <vscale x 1 x i32> [[TMP27]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] undef, <vscale x 1 x i32> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP30]], <vscale x 1 x i32> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP32]], <vscale x 1 x i32> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP34]], <vscale x 1 x i32> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP36]], <vscale x 1 x i32> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP38]], <vscale x 1 x i32> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP40]], <vscale x 1 x i32> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP42]]
+//
+vuint32mf2x7_t test_vlseg7e32_v_u32mf2x7_m (vbool64_t mask, vuint32mf2x7_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg7e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e32_v_u32mf2x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP3]], <vscale x 1 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP4]], <vscale x 1 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP5]], <vscale x 1 x i32> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP6]], <vscale x 1 x i32> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg8.mask.nxv1i32.i32(<vscale x 1 x i32> [[TMP24]], <vscale x 1 x i32> [[TMP25]], <vscale x 1 x i32> [[TMP26]], <vscale x 1 x i32> [[TMP27]], <vscale x 1 x i32> [[TMP28]], <vscale x 1 x i32> [[TMP29]], <vscale x 1 x i32> [[TMP30]], <vscale x 1 x i32> [[TMP31]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] undef, <vscale x 1 x i32> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP34]], <vscale x 1 x i32> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP36]], <vscale x 1 x i32> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP38]], <vscale x 1 x i32> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP40]], <vscale x 1 x i32> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP42]], <vscale x 1 x i32> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP44]], <vscale x 1 x i32> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP46]], <vscale x 1 x i32> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e32_v_u32mf2x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP3]], <vscale x 1 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP4]], <vscale x 1 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP5]], <vscale x 1 x i32> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP6]], <vscale x 1 x i32> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg8.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP24]], <vscale x 1 x i32> [[TMP25]], <vscale x 1 x i32> [[TMP26]], <vscale x 1 x i32> [[TMP27]], <vscale x 1 x i32> [[TMP28]], <vscale x 1 x i32> [[TMP29]], <vscale x 1 x i32> [[TMP30]], <vscale x 1 x i32> [[TMP31]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] undef, <vscale x 1 x i32> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP34]], <vscale x 1 x i32> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP36]], <vscale x 1 x i32> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP38]], <vscale x 1 x i32> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP40]], <vscale x 1 x i32> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP42]], <vscale x 1 x i32> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP44]], <vscale x 1 x i32> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP46]], <vscale x 1 x i32> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP48]]
+//
+vuint32mf2x8_t test_vlseg8e32_v_u32mf2x8_m (vbool64_t mask, vuint32mf2x8_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg8e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_u32m1x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X2_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X2_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg2.mask.nxv2i32.i32(<vscale x 2 x i32> [[TMP6]], <vscale x 2 x i32> [[TMP7]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X2_T]] undef, <vscale x 2 x i32> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X2_T]] [[TMP10]], <vscale x 2 x i32> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32M1X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_u32m1x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X2_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X2_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg2.mask.nxv2i32.i64(<vscale x 2 x i32> [[TMP6]], <vscale x 2 x i32> [[TMP7]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X2_T]] undef, <vscale x 2 x i32> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X2_T]] [[TMP10]], <vscale x 2 x i32> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32M1X2_T]] [[TMP12]]
+//
+vuint32m1x2_t test_vlseg2e32_v_u32m1x2_m (vbool32_t mask, vuint32m1x2_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg2e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e32_v_u32m1x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg3.mask.nxv2i32.i32(<vscale x 2 x i32> [[TMP9]], <vscale x 2 x i32> [[TMP10]], <vscale x 2 x i32> [[TMP11]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T]] undef, <vscale x 2 x i32> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP14]], <vscale x 2 x i32> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP16]], <vscale x 2 x i32> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32M1X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e32_v_u32m1x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg3.mask.nxv2i32.i64(<vscale x 2 x i32> [[TMP9]], <vscale x 2 x i32> [[TMP10]], <vscale x 2 x i32> [[TMP11]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T]] undef, <vscale x 2 x i32> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP14]], <vscale x 2 x i32> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP16]], <vscale x 2 x i32> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32M1X3_T]] [[TMP18]]
+//
+vuint32m1x3_t test_vlseg3e32_v_u32m1x3_m (vbool32_t mask, vuint32m1x3_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg3e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e32_v_u32m1x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg4.mask.nxv2i32.i32(<vscale x 2 x i32> [[TMP12]], <vscale x 2 x i32> [[TMP13]], <vscale x 2 x i32> [[TMP14]], <vscale x 2 x i32> [[TMP15]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] undef, <vscale x 2 x i32> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP18]], <vscale x 2 x i32> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP20]], <vscale x 2 x i32> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP22]], <vscale x 2 x i32> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32M1X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e32_v_u32m1x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg4.mask.nxv2i32.i64(<vscale x 2 x i32> [[TMP12]], <vscale x 2 x i32> [[TMP13]], <vscale x 2 x i32> [[TMP14]], <vscale x 2 x i32> [[TMP15]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] undef, <vscale x 2 x i32> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP18]], <vscale x 2 x i32> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP20]], <vscale x 2 x i32> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP22]], <vscale x 2 x i32> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32M1X4_T]] [[TMP24]]
+//
+vuint32m1x4_t test_vlseg4e32_v_u32m1x4_m (vbool32_t mask, vuint32m1x4_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg4e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e32_v_u32m1x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP3]], <vscale x 2 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg5.mask.nxv2i32.i32(<vscale x 2 x i32> [[TMP15]], <vscale x 2 x i32> [[TMP16]], <vscale x 2 x i32> [[TMP17]], <vscale x 2 x i32> [[TMP18]], <vscale x 2 x i32> [[TMP19]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] undef, <vscale x 2 x i32> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP22]], <vscale x 2 x i32> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP24]], <vscale x 2 x i32> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP26]], <vscale x 2 x i32> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP28]], <vscale x 2 x i32> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32M1X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e32_v_u32m1x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP3]], <vscale x 2 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg5.mask.nxv2i32.i64(<vscale x 2 x i32> [[TMP15]], <vscale x 2 x i32> [[TMP16]], <vscale x 2 x i32> [[TMP17]], <vscale x 2 x i32> [[TMP18]], <vscale x 2 x i32> [[TMP19]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] undef, <vscale x 2 x i32> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP22]], <vscale x 2 x i32> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP24]], <vscale x 2 x i32> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP26]], <vscale x 2 x i32> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP28]], <vscale x 2 x i32> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32M1X5_T]] [[TMP30]]
+//
+vuint32m1x5_t test_vlseg5e32_v_u32m1x5_m (vbool32_t mask, vuint32m1x5_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg5e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e32_v_u32m1x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP3]], <vscale x 2 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP4]], <vscale x 2 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg6.mask.nxv2i32.i32(<vscale x 2 x i32> [[TMP18]], <vscale x 2 x i32> [[TMP19]], <vscale x 2 x i32> [[TMP20]], <vscale x 2 x i32> [[TMP21]], <vscale x 2 x i32> [[TMP22]], <vscale x 2 x i32> [[TMP23]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] undef, <vscale x 2 x i32> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP26]], <vscale x 2 x i32> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP28]], <vscale x 2 x i32> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP30]], <vscale x 2 x i32> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP32]], <vscale x 2 x i32> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP34]], <vscale x 2 x i32> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32M1X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e32_v_u32m1x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP3]], <vscale x 2 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP4]], <vscale x 2 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg6.mask.nxv2i32.i64(<vscale x 2 x i32> [[TMP18]], <vscale x 2 x i32> [[TMP19]], <vscale x 2 x i32> [[TMP20]], <vscale x 2 x i32> [[TMP21]], <vscale x 2 x i32> [[TMP22]], <vscale x 2 x i32> [[TMP23]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] undef, <vscale x 2 x i32> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP26]], <vscale x 2 x i32> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP28]], <vscale x 2 x i32> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP30]], <vscale x 2 x i32> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP32]], <vscale x 2 x i32> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP34]], <vscale x 2 x i32> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32M1X6_T]] [[TMP36]]
+//
+vuint32m1x6_t test_vlseg6e32_v_u32m1x6_m (vbool32_t mask, vuint32m1x6_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg6e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e32_v_u32m1x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP3]], <vscale x 2 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP4]], <vscale x 2 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP5]], <vscale x 2 x i32> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg7.mask.nxv2i32.i32(<vscale x 2 x i32> [[TMP21]], <vscale x 2 x i32> [[TMP22]], <vscale x 2 x i32> [[TMP23]], <vscale x 2 x i32> [[TMP24]], <vscale x 2 x i32> [[TMP25]], <vscale x 2 x i32> [[TMP26]], <vscale x 2 x i32> [[TMP27]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] undef, <vscale x 2 x i32> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP30]], <vscale x 2 x i32> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP32]], <vscale x 2 x i32> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP34]], <vscale x 2 x i32> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP36]], <vscale x 2 x i32> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP38]], <vscale x 2 x i32> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP40]], <vscale x 2 x i32> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32M1X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e32_v_u32m1x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP3]], <vscale x 2 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP4]], <vscale x 2 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP5]], <vscale x 2 x i32> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg7.mask.nxv2i32.i64(<vscale x 2 x i32> [[TMP21]], <vscale x 2 x i32> [[TMP22]], <vscale x 2 x i32> [[TMP23]], <vscale x 2 x i32> [[TMP24]], <vscale x 2 x i32> [[TMP25]], <vscale x 2 x i32> [[TMP26]], <vscale x 2 x i32> [[TMP27]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] undef, <vscale x 2 x i32> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP30]], <vscale x 2 x i32> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP32]], <vscale x 2 x i32> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP34]], <vscale x 2 x i32> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP36]], <vscale x 2 x i32> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP38]], <vscale x 2 x i32> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP40]], <vscale x 2 x i32> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32M1X7_T]] [[TMP42]]
+//
+vuint32m1x7_t test_vlseg7e32_v_u32m1x7_m (vbool32_t mask, vuint32m1x7_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg7e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e32_v_u32m1x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP3]], <vscale x 2 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP4]], <vscale x 2 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP5]], <vscale x 2 x i32> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP6]], <vscale x 2 x i32> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg8.mask.nxv2i32.i32(<vscale x 2 x i32> [[TMP24]], <vscale x 2 x i32> [[TMP25]], <vscale x 2 x i32> [[TMP26]], <vscale x 2 x i32> [[TMP27]], <vscale x 2 x i32> [[TMP28]], <vscale x 2 x i32> [[TMP29]], <vscale x 2 x i32> [[TMP30]], <vscale x 2 x i32> [[TMP31]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] undef, <vscale x 2 x i32> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP34]], <vscale x 2 x i32> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP36]], <vscale x 2 x i32> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP38]], <vscale x 2 x i32> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP40]], <vscale x 2 x i32> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP42]], <vscale x 2 x i32> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP44]], <vscale x 2 x i32> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP46]], <vscale x 2 x i32> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32M1X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e32_v_u32m1x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP3]], <vscale x 2 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP4]], <vscale x 2 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP5]], <vscale x 2 x i32> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP6]], <vscale x 2 x i32> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg8.mask.nxv2i32.i64(<vscale x 2 x i32> [[TMP24]], <vscale x 2 x i32> [[TMP25]], <vscale x 2 x i32> [[TMP26]], <vscale x 2 x i32> [[TMP27]], <vscale x 2 x i32> [[TMP28]], <vscale x 2 x i32> [[TMP29]], <vscale x 2 x i32> [[TMP30]], <vscale x 2 x i32> [[TMP31]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] undef, <vscale x 2 x i32> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP34]], <vscale x 2 x i32> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP36]], <vscale x 2 x i32> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP38]], <vscale x 2 x i32> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP40]], <vscale x 2 x i32> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP42]], <vscale x 2 x i32> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP44]], <vscale x 2 x i32> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP46]], <vscale x 2 x i32> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32M1X8_T]] [[TMP48]]
+//
+vuint32m1x8_t test_vlseg8e32_v_u32m1x8_m (vbool32_t mask, vuint32m1x8_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg8e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_u32m2x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X2_T:%.*]] undef, <vscale x 4 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X2_T]] [[TMP0]], <vscale x 4 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg2.mask.nxv4i32.i32(<vscale x 4 x i32> [[TMP6]], <vscale x 4 x i32> [[TMP7]], i32* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X2_T]] undef, <vscale x 4 x i32> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X2_T]] [[TMP10]], <vscale x 4 x i32> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32M2X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_u32m2x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X2_T:%.*]] undef, <vscale x 4 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X2_T]] [[TMP0]], <vscale x 4 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg2.mask.nxv4i32.i64(<vscale x 4 x i32> [[TMP6]], <vscale x 4 x i32> [[TMP7]], i32* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X2_T]] undef, <vscale x 4 x i32> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X2_T]] [[TMP10]], <vscale x 4 x i32> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32M2X2_T]] [[TMP12]]
+//
+vuint32m2x2_t test_vlseg2e32_v_u32m2x2_m (vbool16_t mask, vuint32m2x2_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg2e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e32_v_u32m2x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T:%.*]] undef, <vscale x 4 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP0]], <vscale x 4 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP1]], <vscale x 4 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg3.mask.nxv4i32.i32(<vscale x 4 x i32> [[TMP9]], <vscale x 4 x i32> [[TMP10]], <vscale x 4 x i32> [[TMP11]], i32* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T]] undef, <vscale x 4 x i32> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP14]], <vscale x 4 x i32> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP16]], <vscale x 4 x i32> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32M2X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e32_v_u32m2x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T:%.*]] undef, <vscale x 4 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP0]], <vscale x 4 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP1]], <vscale x 4 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg3.mask.nxv4i32.i64(<vscale x 4 x i32> [[TMP9]], <vscale x 4 x i32> [[TMP10]], <vscale x 4 x i32> [[TMP11]], i32* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T]] undef, <vscale x 4 x i32> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP14]], <vscale x 4 x i32> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP16]], <vscale x 4 x i32> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32M2X3_T]] [[TMP18]]
+//
+vuint32m2x3_t test_vlseg3e32_v_u32m2x3_m (vbool16_t mask, vuint32m2x3_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg3e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e32_v_u32m2x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T:%.*]] undef, <vscale x 4 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP0]], <vscale x 4 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP1]], <vscale x 4 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP2]], <vscale x 4 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg4.mask.nxv4i32.i32(<vscale x 4 x i32> [[TMP12]], <vscale x 4 x i32> [[TMP13]], <vscale x 4 x i32> [[TMP14]], <vscale x 4 x i32> [[TMP15]], i32* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] undef, <vscale x 4 x i32> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP18]], <vscale x 4 x i32> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP20]], <vscale x 4 x i32> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP22]], <vscale x 4 x i32> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32M2X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e32_v_u32m2x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T:%.*]] undef, <vscale x 4 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP0]], <vscale x 4 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP1]], <vscale x 4 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP2]], <vscale x 4 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg4.mask.nxv4i32.i64(<vscale x 4 x i32> [[TMP12]], <vscale x 4 x i32> [[TMP13]], <vscale x 4 x i32> [[TMP14]], <vscale x 4 x i32> [[TMP15]], i32* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] undef, <vscale x 4 x i32> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP18]], <vscale x 4 x i32> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP20]], <vscale x 4 x i32> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP22]], <vscale x 4 x i32> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32M2X4_T]] [[TMP24]]
+//
+vuint32m2x4_t test_vlseg4e32_v_u32m2x4_m (vbool16_t mask, vuint32m2x4_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg4e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_u32m4x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M4X2_T:%.*]] undef, <vscale x 8 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M4X2_T]] [[TMP0]], <vscale x 8 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT32M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT32M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT32M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT32M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 8 x i32>, <vscale x 8 x i32> } @llvm.riscv.vlseg2.mask.nxv8i32.i32(<vscale x 8 x i32> [[TMP6]], <vscale x 8 x i32> [[TMP7]], i32* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32M4X2_T]] undef, <vscale x 8 x i32> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32M4X2_T]] [[TMP10]], <vscale x 8 x i32> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32M4X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_u32m4x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M4X2_T:%.*]] undef, <vscale x 8 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M4X2_T]] [[TMP0]], <vscale x 8 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT32M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT32M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT32M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT32M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 8 x i32>, <vscale x 8 x i32> } @llvm.riscv.vlseg2.mask.nxv8i32.i64(<vscale x 8 x i32> [[TMP6]], <vscale x 8 x i32> [[TMP7]], i32* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32M4X2_T]] undef, <vscale x 8 x i32> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32M4X2_T]] [[TMP10]], <vscale x 8 x i32> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32M4X2_T]] [[TMP12]]
+//
+vuint32m4x2_t test_vlseg2e32_v_u32m4x2_m (vbool8_t mask, vuint32m4x2_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg2e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e64_v_u64m1x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X2_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X2_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg2.mask.nxv1i64.i32(<vscale x 1 x i64> [[TMP6]], <vscale x 1 x i64> [[TMP7]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X2_T]] undef, <vscale x 1 x i64> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X2_T]] [[TMP10]], <vscale x 1 x i64> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT64M1X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e64_v_u64m1x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X2_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X2_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg2.mask.nxv1i64.i64(<vscale x 1 x i64> [[TMP6]], <vscale x 1 x i64> [[TMP7]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X2_T]] undef, <vscale x 1 x i64> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X2_T]] [[TMP10]], <vscale x 1 x i64> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT64M1X2_T]] [[TMP12]]
+//
+vuint64m1x2_t test_vlseg2e64_v_u64m1x2_m (vbool64_t mask, vuint64m1x2_t maskedoff, const uint64_t *base, size_t vl) {
+  return vlseg2e64(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e64_v_u64m1x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg3.mask.nxv1i64.i32(<vscale x 1 x i64> [[TMP9]], <vscale x 1 x i64> [[TMP10]], <vscale x 1 x i64> [[TMP11]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T]] undef, <vscale x 1 x i64> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP14]], <vscale x 1 x i64> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP16]], <vscale x 1 x i64> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT64M1X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e64_v_u64m1x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg3.mask.nxv1i64.i64(<vscale x 1 x i64> [[TMP9]], <vscale x 1 x i64> [[TMP10]], <vscale x 1 x i64> [[TMP11]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T]] undef, <vscale x 1 x i64> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP14]], <vscale x 1 x i64> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP16]], <vscale x 1 x i64> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT64M1X3_T]] [[TMP18]]
+//
+vuint64m1x3_t test_vlseg3e64_v_u64m1x3_m (vbool64_t mask, vuint64m1x3_t maskedoff, const uint64_t *base, size_t vl) {
+  return vlseg3e64(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e64_v_u64m1x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg4.mask.nxv1i64.i32(<vscale x 1 x i64> [[TMP12]], <vscale x 1 x i64> [[TMP13]], <vscale x 1 x i64> [[TMP14]], <vscale x 1 x i64> [[TMP15]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] undef, <vscale x 1 x i64> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP18]], <vscale x 1 x i64> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP20]], <vscale x 1 x i64> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP22]], <vscale x 1 x i64> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT64M1X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e64_v_u64m1x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg4.mask.nxv1i64.i64(<vscale x 1 x i64> [[TMP12]], <vscale x 1 x i64> [[TMP13]], <vscale x 1 x i64> [[TMP14]], <vscale x 1 x i64> [[TMP15]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] undef, <vscale x 1 x i64> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP18]], <vscale x 1 x i64> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP20]], <vscale x 1 x i64> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP22]], <vscale x 1 x i64> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT64M1X4_T]] [[TMP24]]
+//
+vuint64m1x4_t test_vlseg4e64_v_u64m1x4_m (vbool64_t mask, vuint64m1x4_t maskedoff, const uint64_t *base, size_t vl) {
+  return vlseg4e64(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e64_v_u64m1x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP3]], <vscale x 1 x i64> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg5.mask.nxv1i64.i32(<vscale x 1 x i64> [[TMP15]], <vscale x 1 x i64> [[TMP16]], <vscale x 1 x i64> [[TMP17]], <vscale x 1 x i64> [[TMP18]], <vscale x 1 x i64> [[TMP19]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] undef, <vscale x 1 x i64> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP22]], <vscale x 1 x i64> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP24]], <vscale x 1 x i64> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP26]], <vscale x 1 x i64> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP28]], <vscale x 1 x i64> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT64M1X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e64_v_u64m1x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP3]], <vscale x 1 x i64> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg5.mask.nxv1i64.i64(<vscale x 1 x i64> [[TMP15]], <vscale x 1 x i64> [[TMP16]], <vscale x 1 x i64> [[TMP17]], <vscale x 1 x i64> [[TMP18]], <vscale x 1 x i64> [[TMP19]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] undef, <vscale x 1 x i64> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP22]], <vscale x 1 x i64> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP24]], <vscale x 1 x i64> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP26]], <vscale x 1 x i64> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP28]], <vscale x 1 x i64> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT64M1X5_T]] [[TMP30]]
+//
+vuint64m1x5_t test_vlseg5e64_v_u64m1x5_m (vbool64_t mask, vuint64m1x5_t maskedoff, const uint64_t *base, size_t vl) {
+  return vlseg5e64(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e64_v_u64m1x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP3]], <vscale x 1 x i64> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP4]], <vscale x 1 x i64> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg6.mask.nxv1i64.i32(<vscale x 1 x i64> [[TMP18]], <vscale x 1 x i64> [[TMP19]], <vscale x 1 x i64> [[TMP20]], <vscale x 1 x i64> [[TMP21]], <vscale x 1 x i64> [[TMP22]], <vscale x 1 x i64> [[TMP23]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] undef, <vscale x 1 x i64> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP26]], <vscale x 1 x i64> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP28]], <vscale x 1 x i64> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP30]], <vscale x 1 x i64> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP32]], <vscale x 1 x i64> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP34]], <vscale x 1 x i64> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT64M1X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e64_v_u64m1x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP3]], <vscale x 1 x i64> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP4]], <vscale x 1 x i64> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg6.mask.nxv1i64.i64(<vscale x 1 x i64> [[TMP18]], <vscale x 1 x i64> [[TMP19]], <vscale x 1 x i64> [[TMP20]], <vscale x 1 x i64> [[TMP21]], <vscale x 1 x i64> [[TMP22]], <vscale x 1 x i64> [[TMP23]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] undef, <vscale x 1 x i64> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP26]], <vscale x 1 x i64> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP28]], <vscale x 1 x i64> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP30]], <vscale x 1 x i64> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP32]], <vscale x 1 x i64> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP34]], <vscale x 1 x i64> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT64M1X6_T]] [[TMP36]]
+//
+vuint64m1x6_t test_vlseg6e64_v_u64m1x6_m (vbool64_t mask, vuint64m1x6_t maskedoff, const uint64_t *base, size_t vl) {
+  return vlseg6e64(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e64_v_u64m1x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP3]], <vscale x 1 x i64> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP4]], <vscale x 1 x i64> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP5]], <vscale x 1 x i64> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg7.mask.nxv1i64.i32(<vscale x 1 x i64> [[TMP21]], <vscale x 1 x i64> [[TMP22]], <vscale x 1 x i64> [[TMP23]], <vscale x 1 x i64> [[TMP24]], <vscale x 1 x i64> [[TMP25]], <vscale x 1 x i64> [[TMP26]], <vscale x 1 x i64> [[TMP27]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] undef, <vscale x 1 x i64> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP30]], <vscale x 1 x i64> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP32]], <vscale x 1 x i64> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP34]], <vscale x 1 x i64> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP36]], <vscale x 1 x i64> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP38]], <vscale x 1 x i64> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP40]], <vscale x 1 x i64> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT64M1X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e64_v_u64m1x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP3]], <vscale x 1 x i64> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP4]], <vscale x 1 x i64> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP5]], <vscale x 1 x i64> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg7.mask.nxv1i64.i64(<vscale x 1 x i64> [[TMP21]], <vscale x 1 x i64> [[TMP22]], <vscale x 1 x i64> [[TMP23]], <vscale x 1 x i64> [[TMP24]], <vscale x 1 x i64> [[TMP25]], <vscale x 1 x i64> [[TMP26]], <vscale x 1 x i64> [[TMP27]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] undef, <vscale x 1 x i64> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP30]], <vscale x 1 x i64> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP32]], <vscale x 1 x i64> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP34]], <vscale x 1 x i64> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP36]], <vscale x 1 x i64> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP38]], <vscale x 1 x i64> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP40]], <vscale x 1 x i64> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT64M1X7_T]] [[TMP42]]
+//
+vuint64m1x7_t test_vlseg7e64_v_u64m1x7_m (vbool64_t mask, vuint64m1x7_t maskedoff, const uint64_t *base, size_t vl) {
+  return vlseg7e64(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e64_v_u64m1x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP3]], <vscale x 1 x i64> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP4]], <vscale x 1 x i64> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP5]], <vscale x 1 x i64> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP6]], <vscale x 1 x i64> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg8.mask.nxv1i64.i32(<vscale x 1 x i64> [[TMP24]], <vscale x 1 x i64> [[TMP25]], <vscale x 1 x i64> [[TMP26]], <vscale x 1 x i64> [[TMP27]], <vscale x 1 x i64> [[TMP28]], <vscale x 1 x i64> [[TMP29]], <vscale x 1 x i64> [[TMP30]], <vscale x 1 x i64> [[TMP31]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] undef, <vscale x 1 x i64> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP34]], <vscale x 1 x i64> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP36]], <vscale x 1 x i64> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP38]], <vscale x 1 x i64> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP40]], <vscale x 1 x i64> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP42]], <vscale x 1 x i64> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP44]], <vscale x 1 x i64> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP46]], <vscale x 1 x i64> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT64M1X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e64_v_u64m1x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP3]], <vscale x 1 x i64> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP4]], <vscale x 1 x i64> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP5]], <vscale x 1 x i64> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP6]], <vscale x 1 x i64> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg8.mask.nxv1i64.i64(<vscale x 1 x i64> [[TMP24]], <vscale x 1 x i64> [[TMP25]], <vscale x 1 x i64> [[TMP26]], <vscale x 1 x i64> [[TMP27]], <vscale x 1 x i64> [[TMP28]], <vscale x 1 x i64> [[TMP29]], <vscale x 1 x i64> [[TMP30]], <vscale x 1 x i64> [[TMP31]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] undef, <vscale x 1 x i64> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP34]], <vscale x 1 x i64> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP36]], <vscale x 1 x i64> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP38]], <vscale x 1 x i64> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP40]], <vscale x 1 x i64> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP42]], <vscale x 1 x i64> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP44]], <vscale x 1 x i64> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP46]], <vscale x 1 x i64> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT64M1X8_T]] [[TMP48]]
+//
+vuint64m1x8_t test_vlseg8e64_v_u64m1x8_m (vbool64_t mask, vuint64m1x8_t maskedoff, const uint64_t *base, size_t vl) {
+  return vlseg8e64(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e64_v_u64m2x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X2_T:%.*]] undef, <vscale x 2 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X2_T]] [[TMP0]], <vscale x 2 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg2.mask.nxv2i64.i32(<vscale x 2 x i64> [[TMP6]], <vscale x 2 x i64> [[TMP7]], i64* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X2_T]] undef, <vscale x 2 x i64> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X2_T]] [[TMP10]], <vscale x 2 x i64> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT64M2X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e64_v_u64m2x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X2_T:%.*]] undef, <vscale x 2 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X2_T]] [[TMP0]], <vscale x 2 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg2.mask.nxv2i64.i64(<vscale x 2 x i64> [[TMP6]], <vscale x 2 x i64> [[TMP7]], i64* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X2_T]] undef, <vscale x 2 x i64> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X2_T]] [[TMP10]], <vscale x 2 x i64> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT64M2X2_T]] [[TMP12]]
+//
+vuint64m2x2_t test_vlseg2e64_v_u64m2x2_m (vbool32_t mask, vuint64m2x2_t maskedoff, const uint64_t *base, size_t vl) {
+  return vlseg2e64(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e64_v_u64m2x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T:%.*]] undef, <vscale x 2 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP0]], <vscale x 2 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP1]], <vscale x 2 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg3.mask.nxv2i64.i32(<vscale x 2 x i64> [[TMP9]], <vscale x 2 x i64> [[TMP10]], <vscale x 2 x i64> [[TMP11]], i64* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T]] undef, <vscale x 2 x i64> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP14]], <vscale x 2 x i64> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP16]], <vscale x 2 x i64> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT64M2X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e64_v_u64m2x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T:%.*]] undef, <vscale x 2 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP0]], <vscale x 2 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP1]], <vscale x 2 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg3.mask.nxv2i64.i64(<vscale x 2 x i64> [[TMP9]], <vscale x 2 x i64> [[TMP10]], <vscale x 2 x i64> [[TMP11]], i64* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T]] undef, <vscale x 2 x i64> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP14]], <vscale x 2 x i64> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP16]], <vscale x 2 x i64> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT64M2X3_T]] [[TMP18]]
+//
+vuint64m2x3_t test_vlseg3e64_v_u64m2x3_m (vbool32_t mask, vuint64m2x3_t maskedoff, const uint64_t *base, size_t vl) {
+  return vlseg3e64(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e64_v_u64m2x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T:%.*]] undef, <vscale x 2 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP0]], <vscale x 2 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP1]], <vscale x 2 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP2]], <vscale x 2 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg4.mask.nxv2i64.i32(<vscale x 2 x i64> [[TMP12]], <vscale x 2 x i64> [[TMP13]], <vscale x 2 x i64> [[TMP14]], <vscale x 2 x i64> [[TMP15]], i64* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] undef, <vscale x 2 x i64> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP18]], <vscale x 2 x i64> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP20]], <vscale x 2 x i64> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP22]], <vscale x 2 x i64> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT64M2X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e64_v_u64m2x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T:%.*]] undef, <vscale x 2 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP0]], <vscale x 2 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP1]], <vscale x 2 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP2]], <vscale x 2 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg4.mask.nxv2i64.i64(<vscale x 2 x i64> [[TMP12]], <vscale x 2 x i64> [[TMP13]], <vscale x 2 x i64> [[TMP14]], <vscale x 2 x i64> [[TMP15]], i64* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] undef, <vscale x 2 x i64> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP18]], <vscale x 2 x i64> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP20]], <vscale x 2 x i64> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP22]], <vscale x 2 x i64> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT64M2X4_T]] [[TMP24]]
+//
+vuint64m2x4_t test_vlseg4e64_v_u64m2x4_m (vbool32_t mask, vuint64m2x4_t maskedoff, const uint64_t *base, size_t vl) {
+  return vlseg4e64(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e64_v_u64m4x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M4X2_T:%.*]] undef, <vscale x 4 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M4X2_T]] [[TMP0]], <vscale x 4 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT64M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT64M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT64M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT64M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT64M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT64M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x i64>, <vscale x 4 x i64> } @llvm.riscv.vlseg2.mask.nxv4i64.i32(<vscale x 4 x i64> [[TMP6]], <vscale x 4 x i64> [[TMP7]], i64* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT64M4X2_T]] undef, <vscale x 4 x i64> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT64M4X2_T]] [[TMP10]], <vscale x 4 x i64> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT64M4X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e64_v_u64m4x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M4X2_T:%.*]] undef, <vscale x 4 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M4X2_T]] [[TMP0]], <vscale x 4 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT64M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT64M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT64M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT64M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT64M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT64M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x i64>, <vscale x 4 x i64> } @llvm.riscv.vlseg2.mask.nxv4i64.i64(<vscale x 4 x i64> [[TMP6]], <vscale x 4 x i64> [[TMP7]], i64* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT64M4X2_T]] undef, <vscale x 4 x i64> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT64M4X2_T]] [[TMP10]], <vscale x 4 x i64> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT64M4X2_T]] [[TMP12]]
+//
+vuint64m4x2_t test_vlseg2e64_v_u64m4x2_m (vbool16_t mask, vuint64m4x2_t maskedoff, const uint64_t *base, size_t vl) {
+  return vlseg2e64(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_f32mf2x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X2_T:%.*]] undef, <vscale x 1 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP0]], <vscale x 1 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg2.mask.nxv1f32.i32(<vscale x 1 x float> [[TMP6]], <vscale x 1 x float> [[TMP7]], float* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] undef, <vscale x 1 x float> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP10]], <vscale x 1 x float> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_f32mf2x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X2_T:%.*]] undef, <vscale x 1 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP0]], <vscale x 1 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg2.mask.nxv1f32.i64(<vscale x 1 x float> [[TMP6]], <vscale x 1 x float> [[TMP7]], float* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] undef, <vscale x 1 x float> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP10]], <vscale x 1 x float> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP12]]
+//
+vfloat32mf2x2_t test_vlseg2e32_v_f32mf2x2_m (vbool64_t mask, vfloat32mf2x2_t maskedoff, const float *base, size_t vl) {
+  return vlseg2e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e32_v_f32mf2x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T:%.*]] undef, <vscale x 1 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP0]], <vscale x 1 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP1]], <vscale x 1 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg3.mask.nxv1f32.i32(<vscale x 1 x float> [[TMP9]], <vscale x 1 x float> [[TMP10]], <vscale x 1 x float> [[TMP11]], float* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] undef, <vscale x 1 x float> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP14]], <vscale x 1 x float> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP16]], <vscale x 1 x float> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e32_v_f32mf2x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T:%.*]] undef, <vscale x 1 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP0]], <vscale x 1 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP1]], <vscale x 1 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg3.mask.nxv1f32.i64(<vscale x 1 x float> [[TMP9]], <vscale x 1 x float> [[TMP10]], <vscale x 1 x float> [[TMP11]], float* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] undef, <vscale x 1 x float> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP14]], <vscale x 1 x float> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP16]], <vscale x 1 x float> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP18]]
+//
+vfloat32mf2x3_t test_vlseg3e32_v_f32mf2x3_m (vbool64_t mask, vfloat32mf2x3_t maskedoff, const float *base, size_t vl) {
+  return vlseg3e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e32_v_f32mf2x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T:%.*]] undef, <vscale x 1 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP0]], <vscale x 1 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP1]], <vscale x 1 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP2]], <vscale x 1 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg4.mask.nxv1f32.i32(<vscale x 1 x float> [[TMP12]], <vscale x 1 x float> [[TMP13]], <vscale x 1 x float> [[TMP14]], <vscale x 1 x float> [[TMP15]], float* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] undef, <vscale x 1 x float> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP18]], <vscale x 1 x float> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP20]], <vscale x 1 x float> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP22]], <vscale x 1 x float> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e32_v_f32mf2x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T:%.*]] undef, <vscale x 1 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP0]], <vscale x 1 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP1]], <vscale x 1 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP2]], <vscale x 1 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg4.mask.nxv1f32.i64(<vscale x 1 x float> [[TMP12]], <vscale x 1 x float> [[TMP13]], <vscale x 1 x float> [[TMP14]], <vscale x 1 x float> [[TMP15]], float* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] undef, <vscale x 1 x float> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP18]], <vscale x 1 x float> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP20]], <vscale x 1 x float> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP22]], <vscale x 1 x float> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP24]]
+//
+vfloat32mf2x4_t test_vlseg4e32_v_f32mf2x4_m (vbool64_t mask, vfloat32mf2x4_t maskedoff, const float *base, size_t vl) {
+  return vlseg4e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e32_v_f32mf2x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T:%.*]] undef, <vscale x 1 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP0]], <vscale x 1 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP1]], <vscale x 1 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP2]], <vscale x 1 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP3]], <vscale x 1 x float> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg5.mask.nxv1f32.i32(<vscale x 1 x float> [[TMP15]], <vscale x 1 x float> [[TMP16]], <vscale x 1 x float> [[TMP17]], <vscale x 1 x float> [[TMP18]], <vscale x 1 x float> [[TMP19]], float* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] undef, <vscale x 1 x float> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP22]], <vscale x 1 x float> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP24]], <vscale x 1 x float> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP26]], <vscale x 1 x float> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP28]], <vscale x 1 x float> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e32_v_f32mf2x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T:%.*]] undef, <vscale x 1 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP0]], <vscale x 1 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP1]], <vscale x 1 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP2]], <vscale x 1 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP3]], <vscale x 1 x float> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg5.mask.nxv1f32.i64(<vscale x 1 x float> [[TMP15]], <vscale x 1 x float> [[TMP16]], <vscale x 1 x float> [[TMP17]], <vscale x 1 x float> [[TMP18]], <vscale x 1 x float> [[TMP19]], float* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] undef, <vscale x 1 x float> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP22]], <vscale x 1 x float> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP24]], <vscale x 1 x float> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP26]], <vscale x 1 x float> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP28]], <vscale x 1 x float> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP30]]
+//
+vfloat32mf2x5_t test_vlseg5e32_v_f32mf2x5_m (vbool64_t mask, vfloat32mf2x5_t maskedoff, const float *base, size_t vl) {
+  return vlseg5e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e32_v_f32mf2x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T:%.*]] undef, <vscale x 1 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP0]], <vscale x 1 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP1]], <vscale x 1 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP2]], <vscale x 1 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP3]], <vscale x 1 x float> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP4]], <vscale x 1 x float> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg6.mask.nxv1f32.i32(<vscale x 1 x float> [[TMP18]], <vscale x 1 x float> [[TMP19]], <vscale x 1 x float> [[TMP20]], <vscale x 1 x float> [[TMP21]], <vscale x 1 x float> [[TMP22]], <vscale x 1 x float> [[TMP23]], float* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] undef, <vscale x 1 x float> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP26]], <vscale x 1 x float> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP28]], <vscale x 1 x float> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP30]], <vscale x 1 x float> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP32]], <vscale x 1 x float> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP34]], <vscale x 1 x float> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e32_v_f32mf2x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T:%.*]] undef, <vscale x 1 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP0]], <vscale x 1 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP1]], <vscale x 1 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP2]], <vscale x 1 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP3]], <vscale x 1 x float> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP4]], <vscale x 1 x float> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg6.mask.nxv1f32.i64(<vscale x 1 x float> [[TMP18]], <vscale x 1 x float> [[TMP19]], <vscale x 1 x float> [[TMP20]], <vscale x 1 x float> [[TMP21]], <vscale x 1 x float> [[TMP22]], <vscale x 1 x float> [[TMP23]], float* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] undef, <vscale x 1 x float> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP26]], <vscale x 1 x float> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP28]], <vscale x 1 x float> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP30]], <vscale x 1 x float> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP32]], <vscale x 1 x float> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP34]], <vscale x 1 x float> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP36]]
+//
+vfloat32mf2x6_t test_vlseg6e32_v_f32mf2x6_m (vbool64_t mask, vfloat32mf2x6_t maskedoff, const float *base, size_t vl) {
+  return vlseg6e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e32_v_f32mf2x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T:%.*]] undef, <vscale x 1 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP0]], <vscale x 1 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP1]], <vscale x 1 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP2]], <vscale x 1 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP3]], <vscale x 1 x float> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP4]], <vscale x 1 x float> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP5]], <vscale x 1 x float> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg7.mask.nxv1f32.i32(<vscale x 1 x float> [[TMP21]], <vscale x 1 x float> [[TMP22]], <vscale x 1 x float> [[TMP23]], <vscale x 1 x float> [[TMP24]], <vscale x 1 x float> [[TMP25]], <vscale x 1 x float> [[TMP26]], <vscale x 1 x float> [[TMP27]], float* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] undef, <vscale x 1 x float> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP30]], <vscale x 1 x float> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP32]], <vscale x 1 x float> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP34]], <vscale x 1 x float> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP36]], <vscale x 1 x float> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP38]], <vscale x 1 x float> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP40]], <vscale x 1 x float> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e32_v_f32mf2x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T:%.*]] undef, <vscale x 1 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP0]], <vscale x 1 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP1]], <vscale x 1 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP2]], <vscale x 1 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP3]], <vscale x 1 x float> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP4]], <vscale x 1 x float> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP5]], <vscale x 1 x float> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg7.mask.nxv1f32.i64(<vscale x 1 x float> [[TMP21]], <vscale x 1 x float> [[TMP22]], <vscale x 1 x float> [[TMP23]], <vscale x 1 x float> [[TMP24]], <vscale x 1 x float> [[TMP25]], <vscale x 1 x float> [[TMP26]], <vscale x 1 x float> [[TMP27]], float* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] undef, <vscale x 1 x float> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP30]], <vscale x 1 x float> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP32]], <vscale x 1 x float> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP34]], <vscale x 1 x float> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP36]], <vscale x 1 x float> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP38]], <vscale x 1 x float> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP40]], <vscale x 1 x float> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP42]]
+//
+vfloat32mf2x7_t test_vlseg7e32_v_f32mf2x7_m (vbool64_t mask, vfloat32mf2x7_t maskedoff, const float *base, size_t vl) {
+  return vlseg7e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e32_v_f32mf2x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T:%.*]] undef, <vscale x 1 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP0]], <vscale x 1 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP1]], <vscale x 1 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP2]], <vscale x 1 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP3]], <vscale x 1 x float> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP4]], <vscale x 1 x float> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP5]], <vscale x 1 x float> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP6]], <vscale x 1 x float> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg8.mask.nxv1f32.i32(<vscale x 1 x float> [[TMP24]], <vscale x 1 x float> [[TMP25]], <vscale x 1 x float> [[TMP26]], <vscale x 1 x float> [[TMP27]], <vscale x 1 x float> [[TMP28]], <vscale x 1 x float> [[TMP29]], <vscale x 1 x float> [[TMP30]], <vscale x 1 x float> [[TMP31]], float* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] undef, <vscale x 1 x float> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP34]], <vscale x 1 x float> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP36]], <vscale x 1 x float> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP38]], <vscale x 1 x float> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP40]], <vscale x 1 x float> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP42]], <vscale x 1 x float> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP44]], <vscale x 1 x float> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP46]], <vscale x 1 x float> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e32_v_f32mf2x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T:%.*]] undef, <vscale x 1 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP0]], <vscale x 1 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP1]], <vscale x 1 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP2]], <vscale x 1 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP3]], <vscale x 1 x float> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP4]], <vscale x 1 x float> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP5]], <vscale x 1 x float> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP6]], <vscale x 1 x float> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg8.mask.nxv1f32.i64(<vscale x 1 x float> [[TMP24]], <vscale x 1 x float> [[TMP25]], <vscale x 1 x float> [[TMP26]], <vscale x 1 x float> [[TMP27]], <vscale x 1 x float> [[TMP28]], <vscale x 1 x float> [[TMP29]], <vscale x 1 x float> [[TMP30]], <vscale x 1 x float> [[TMP31]], float* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] undef, <vscale x 1 x float> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP34]], <vscale x 1 x float> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP36]], <vscale x 1 x float> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP38]], <vscale x 1 x float> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP40]], <vscale x 1 x float> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP42]], <vscale x 1 x float> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP44]], <vscale x 1 x float> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP46]], <vscale x 1 x float> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP48]]
+//
+vfloat32mf2x8_t test_vlseg8e32_v_f32mf2x8_m (vbool64_t mask, vfloat32mf2x8_t maskedoff, const float *base, size_t vl) {
+  return vlseg8e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_f32m1x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X2_T:%.*]] undef, <vscale x 2 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP0]], <vscale x 2 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg2.mask.nxv2f32.i32(<vscale x 2 x float> [[TMP6]], <vscale x 2 x float> [[TMP7]], float* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X2_T]] undef, <vscale x 2 x float> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP10]], <vscale x 2 x float> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_f32m1x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X2_T:%.*]] undef, <vscale x 2 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP0]], <vscale x 2 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg2.mask.nxv2f32.i64(<vscale x 2 x float> [[TMP6]], <vscale x 2 x float> [[TMP7]], float* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X2_T]] undef, <vscale x 2 x float> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP10]], <vscale x 2 x float> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP12]]
+//
+vfloat32m1x2_t test_vlseg2e32_v_f32m1x2_m (vbool32_t mask, vfloat32m1x2_t maskedoff, const float *base, size_t vl) {
+  return vlseg2e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e32_v_f32m1x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T:%.*]] undef, <vscale x 2 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP0]], <vscale x 2 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP1]], <vscale x 2 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg3.mask.nxv2f32.i32(<vscale x 2 x float> [[TMP9]], <vscale x 2 x float> [[TMP10]], <vscale x 2 x float> [[TMP11]], float* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T]] undef, <vscale x 2 x float> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP14]], <vscale x 2 x float> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP16]], <vscale x 2 x float> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e32_v_f32m1x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T:%.*]] undef, <vscale x 2 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP0]], <vscale x 2 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP1]], <vscale x 2 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg3.mask.nxv2f32.i64(<vscale x 2 x float> [[TMP9]], <vscale x 2 x float> [[TMP10]], <vscale x 2 x float> [[TMP11]], float* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T]] undef, <vscale x 2 x float> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP14]], <vscale x 2 x float> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP16]], <vscale x 2 x float> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP18]]
+//
+vfloat32m1x3_t test_vlseg3e32_v_f32m1x3_m (vbool32_t mask, vfloat32m1x3_t maskedoff, const float *base, size_t vl) {
+  return vlseg3e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e32_v_f32m1x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T:%.*]] undef, <vscale x 2 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP0]], <vscale x 2 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP1]], <vscale x 2 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP2]], <vscale x 2 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg4.mask.nxv2f32.i32(<vscale x 2 x float> [[TMP12]], <vscale x 2 x float> [[TMP13]], <vscale x 2 x float> [[TMP14]], <vscale x 2 x float> [[TMP15]], float* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] undef, <vscale x 2 x float> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP18]], <vscale x 2 x float> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP20]], <vscale x 2 x float> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP22]], <vscale x 2 x float> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e32_v_f32m1x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T:%.*]] undef, <vscale x 2 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP0]], <vscale x 2 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP1]], <vscale x 2 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP2]], <vscale x 2 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg4.mask.nxv2f32.i64(<vscale x 2 x float> [[TMP12]], <vscale x 2 x float> [[TMP13]], <vscale x 2 x float> [[TMP14]], <vscale x 2 x float> [[TMP15]], float* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] undef, <vscale x 2 x float> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP18]], <vscale x 2 x float> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP20]], <vscale x 2 x float> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP22]], <vscale x 2 x float> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP24]]
+//
+vfloat32m1x4_t test_vlseg4e32_v_f32m1x4_m (vbool32_t mask, vfloat32m1x4_t maskedoff, const float *base, size_t vl) {
+  return vlseg4e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e32_v_f32m1x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T:%.*]] undef, <vscale x 2 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP0]], <vscale x 2 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP1]], <vscale x 2 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP2]], <vscale x 2 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP3]], <vscale x 2 x float> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg5.mask.nxv2f32.i32(<vscale x 2 x float> [[TMP15]], <vscale x 2 x float> [[TMP16]], <vscale x 2 x float> [[TMP17]], <vscale x 2 x float> [[TMP18]], <vscale x 2 x float> [[TMP19]], float* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] undef, <vscale x 2 x float> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP22]], <vscale x 2 x float> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP24]], <vscale x 2 x float> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP26]], <vscale x 2 x float> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP28]], <vscale x 2 x float> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e32_v_f32m1x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T:%.*]] undef, <vscale x 2 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP0]], <vscale x 2 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP1]], <vscale x 2 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP2]], <vscale x 2 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP3]], <vscale x 2 x float> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg5.mask.nxv2f32.i64(<vscale x 2 x float> [[TMP15]], <vscale x 2 x float> [[TMP16]], <vscale x 2 x float> [[TMP17]], <vscale x 2 x float> [[TMP18]], <vscale x 2 x float> [[TMP19]], float* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] undef, <vscale x 2 x float> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP22]], <vscale x 2 x float> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP24]], <vscale x 2 x float> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP26]], <vscale x 2 x float> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP28]], <vscale x 2 x float> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP30]]
+//
+vfloat32m1x5_t test_vlseg5e32_v_f32m1x5_m (vbool32_t mask, vfloat32m1x5_t maskedoff, const float *base, size_t vl) {
+  return vlseg5e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e32_v_f32m1x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T:%.*]] undef, <vscale x 2 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP0]], <vscale x 2 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP1]], <vscale x 2 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP2]], <vscale x 2 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP3]], <vscale x 2 x float> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP4]], <vscale x 2 x float> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg6.mask.nxv2f32.i32(<vscale x 2 x float> [[TMP18]], <vscale x 2 x float> [[TMP19]], <vscale x 2 x float> [[TMP20]], <vscale x 2 x float> [[TMP21]], <vscale x 2 x float> [[TMP22]], <vscale x 2 x float> [[TMP23]], float* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] undef, <vscale x 2 x float> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP26]], <vscale x 2 x float> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP28]], <vscale x 2 x float> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP30]], <vscale x 2 x float> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP32]], <vscale x 2 x float> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP34]], <vscale x 2 x float> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e32_v_f32m1x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T:%.*]] undef, <vscale x 2 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP0]], <vscale x 2 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP1]], <vscale x 2 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP2]], <vscale x 2 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP3]], <vscale x 2 x float> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP4]], <vscale x 2 x float> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg6.mask.nxv2f32.i64(<vscale x 2 x float> [[TMP18]], <vscale x 2 x float> [[TMP19]], <vscale x 2 x float> [[TMP20]], <vscale x 2 x float> [[TMP21]], <vscale x 2 x float> [[TMP22]], <vscale x 2 x float> [[TMP23]], float* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] undef, <vscale x 2 x float> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP26]], <vscale x 2 x float> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP28]], <vscale x 2 x float> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP30]], <vscale x 2 x float> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP32]], <vscale x 2 x float> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP34]], <vscale x 2 x float> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP36]]
+//
+vfloat32m1x6_t test_vlseg6e32_v_f32m1x6_m (vbool32_t mask, vfloat32m1x6_t maskedoff, const float *base, size_t vl) {
+  return vlseg6e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e32_v_f32m1x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T:%.*]] undef, <vscale x 2 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP0]], <vscale x 2 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP1]], <vscale x 2 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP2]], <vscale x 2 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP3]], <vscale x 2 x float> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP4]], <vscale x 2 x float> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP5]], <vscale x 2 x float> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg7.mask.nxv2f32.i32(<vscale x 2 x float> [[TMP21]], <vscale x 2 x float> [[TMP22]], <vscale x 2 x float> [[TMP23]], <vscale x 2 x float> [[TMP24]], <vscale x 2 x float> [[TMP25]], <vscale x 2 x float> [[TMP26]], <vscale x 2 x float> [[TMP27]], float* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] undef, <vscale x 2 x float> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP30]], <vscale x 2 x float> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP32]], <vscale x 2 x float> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP34]], <vscale x 2 x float> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP36]], <vscale x 2 x float> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP38]], <vscale x 2 x float> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP40]], <vscale x 2 x float> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e32_v_f32m1x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T:%.*]] undef, <vscale x 2 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP0]], <vscale x 2 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP1]], <vscale x 2 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP2]], <vscale x 2 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP3]], <vscale x 2 x float> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP4]], <vscale x 2 x float> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP5]], <vscale x 2 x float> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg7.mask.nxv2f32.i64(<vscale x 2 x float> [[TMP21]], <vscale x 2 x float> [[TMP22]], <vscale x 2 x float> [[TMP23]], <vscale x 2 x float> [[TMP24]], <vscale x 2 x float> [[TMP25]], <vscale x 2 x float> [[TMP26]], <vscale x 2 x float> [[TMP27]], float* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] undef, <vscale x 2 x float> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP30]], <vscale x 2 x float> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP32]], <vscale x 2 x float> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP34]], <vscale x 2 x float> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP36]], <vscale x 2 x float> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP38]], <vscale x 2 x float> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP40]], <vscale x 2 x float> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP42]]
+//
+vfloat32m1x7_t test_vlseg7e32_v_f32m1x7_m (vbool32_t mask, vfloat32m1x7_t maskedoff, const float *base, size_t vl) {
+  return vlseg7e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e32_v_f32m1x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T:%.*]] undef, <vscale x 2 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP0]], <vscale x 2 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP1]], <vscale x 2 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP2]], <vscale x 2 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP3]], <vscale x 2 x float> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP4]], <vscale x 2 x float> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP5]], <vscale x 2 x float> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP6]], <vscale x 2 x float> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg8.mask.nxv2f32.i32(<vscale x 2 x float> [[TMP24]], <vscale x 2 x float> [[TMP25]], <vscale x 2 x float> [[TMP26]], <vscale x 2 x float> [[TMP27]], <vscale x 2 x float> [[TMP28]], <vscale x 2 x float> [[TMP29]], <vscale x 2 x float> [[TMP30]], <vscale x 2 x float> [[TMP31]], float* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] undef, <vscale x 2 x float> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP34]], <vscale x 2 x float> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP36]], <vscale x 2 x float> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP38]], <vscale x 2 x float> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP40]], <vscale x 2 x float> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP42]], <vscale x 2 x float> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP44]], <vscale x 2 x float> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP46]], <vscale x 2 x float> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e32_v_f32m1x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T:%.*]] undef, <vscale x 2 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP0]], <vscale x 2 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP1]], <vscale x 2 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP2]], <vscale x 2 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP3]], <vscale x 2 x float> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP4]], <vscale x 2 x float> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP5]], <vscale x 2 x float> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP6]], <vscale x 2 x float> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg8.mask.nxv2f32.i64(<vscale x 2 x float> [[TMP24]], <vscale x 2 x float> [[TMP25]], <vscale x 2 x float> [[TMP26]], <vscale x 2 x float> [[TMP27]], <vscale x 2 x float> [[TMP28]], <vscale x 2 x float> [[TMP29]], <vscale x 2 x float> [[TMP30]], <vscale x 2 x float> [[TMP31]], float* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] undef, <vscale x 2 x float> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP34]], <vscale x 2 x float> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP36]], <vscale x 2 x float> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP38]], <vscale x 2 x float> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP40]], <vscale x 2 x float> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP42]], <vscale x 2 x float> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP44]], <vscale x 2 x float> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP46]], <vscale x 2 x float> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP48]]
+//
+vfloat32m1x8_t test_vlseg8e32_v_f32m1x8_m (vbool32_t mask, vfloat32m1x8_t maskedoff, const float *base, size_t vl) {
+  return vlseg8e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_f32m2x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X2_T:%.*]] undef, <vscale x 4 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP0]], <vscale x 4 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.riscv.vlseg2.mask.nxv4f32.i32(<vscale x 4 x float> [[TMP6]], <vscale x 4 x float> [[TMP7]], float* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X2_T]] undef, <vscale x 4 x float> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP10]], <vscale x 4 x float> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_f32m2x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X2_T:%.*]] undef, <vscale x 4 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP0]], <vscale x 4 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.riscv.vlseg2.mask.nxv4f32.i64(<vscale x 4 x float> [[TMP6]], <vscale x 4 x float> [[TMP7]], float* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X2_T]] undef, <vscale x 4 x float> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP10]], <vscale x 4 x float> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP12]]
+//
+vfloat32m2x2_t test_vlseg2e32_v_f32m2x2_m (vbool16_t mask, vfloat32m2x2_t maskedoff, const float *base, size_t vl) {
+  return vlseg2e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e32_v_f32m2x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T:%.*]] undef, <vscale x 4 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP0]], <vscale x 4 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP1]], <vscale x 4 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.riscv.vlseg3.mask.nxv4f32.i32(<vscale x 4 x float> [[TMP9]], <vscale x 4 x float> [[TMP10]], <vscale x 4 x float> [[TMP11]], float* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T]] undef, <vscale x 4 x float> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP14]], <vscale x 4 x float> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP16]], <vscale x 4 x float> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e32_v_f32m2x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T:%.*]] undef, <vscale x 4 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP0]], <vscale x 4 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP1]], <vscale x 4 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.riscv.vlseg3.mask.nxv4f32.i64(<vscale x 4 x float> [[TMP9]], <vscale x 4 x float> [[TMP10]], <vscale x 4 x float> [[TMP11]], float* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T]] undef, <vscale x 4 x float> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP14]], <vscale x 4 x float> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP16]], <vscale x 4 x float> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP18]]
+//
+vfloat32m2x3_t test_vlseg3e32_v_f32m2x3_m (vbool16_t mask, vfloat32m2x3_t maskedoff, const float *base, size_t vl) {
+  return vlseg3e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e32_v_f32m2x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T:%.*]] undef, <vscale x 4 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP0]], <vscale x 4 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP1]], <vscale x 4 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP2]], <vscale x 4 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.riscv.vlseg4.mask.nxv4f32.i32(<vscale x 4 x float> [[TMP12]], <vscale x 4 x float> [[TMP13]], <vscale x 4 x float> [[TMP14]], <vscale x 4 x float> [[TMP15]], float* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] undef, <vscale x 4 x float> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP18]], <vscale x 4 x float> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP20]], <vscale x 4 x float> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP22]], <vscale x 4 x float> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e32_v_f32m2x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T:%.*]] undef, <vscale x 4 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP0]], <vscale x 4 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP1]], <vscale x 4 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP2]], <vscale x 4 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.riscv.vlseg4.mask.nxv4f32.i64(<vscale x 4 x float> [[TMP12]], <vscale x 4 x float> [[TMP13]], <vscale x 4 x float> [[TMP14]], <vscale x 4 x float> [[TMP15]], float* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] undef, <vscale x 4 x float> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP18]], <vscale x 4 x float> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP20]], <vscale x 4 x float> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP22]], <vscale x 4 x float> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP24]]
+//
+vfloat32m2x4_t test_vlseg4e32_v_f32m2x4_m (vbool16_t mask, vfloat32m2x4_t maskedoff, const float *base, size_t vl) {
+  return vlseg4e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_f32m4x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M4X2_T:%.*]] undef, <vscale x 8 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP0]], <vscale x 8 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 8 x float>, <vscale x 8 x float> } @llvm.riscv.vlseg2.mask.nxv8f32.i32(<vscale x 8 x float> [[TMP6]], <vscale x 8 x float> [[TMP7]], float* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x float>, <vscale x 8 x float> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M4X2_T]] undef, <vscale x 8 x float> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x float>, <vscale x 8 x float> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP10]], <vscale x 8 x float> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_f32m4x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M4X2_T:%.*]] undef, <vscale x 8 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP0]], <vscale x 8 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 8 x float>, <vscale x 8 x float> } @llvm.riscv.vlseg2.mask.nxv8f32.i64(<vscale x 8 x float> [[TMP6]], <vscale x 8 x float> [[TMP7]], float* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x float>, <vscale x 8 x float> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M4X2_T]] undef, <vscale x 8 x float> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x float>, <vscale x 8 x float> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP10]], <vscale x 8 x float> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP12]]
+//
+vfloat32m4x2_t test_vlseg2e32_v_f32m4x2_m (vbool8_t mask, vfloat32m4x2_t maskedoff, const float *base, size_t vl) {
+  return vlseg2e32(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e64_v_f64m1x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X2_T:%.*]] undef, <vscale x 1 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP0]], <vscale x 1 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg2.mask.nxv1f64.i32(<vscale x 1 x double> [[TMP6]], <vscale x 1 x double> [[TMP7]], double* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X2_T]] undef, <vscale x 1 x double> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP10]], <vscale x 1 x double> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e64_v_f64m1x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X2_T:%.*]] undef, <vscale x 1 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP0]], <vscale x 1 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg2.mask.nxv1f64.i64(<vscale x 1 x double> [[TMP6]], <vscale x 1 x double> [[TMP7]], double* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X2_T]] undef, <vscale x 1 x double> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP10]], <vscale x 1 x double> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP12]]
+//
+vfloat64m1x2_t test_vlseg2e64_v_f64m1x2_m (vbool64_t mask, vfloat64m1x2_t maskedoff, const double *base, size_t vl) {
+  return vlseg2e64(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e64_v_f64m1x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T:%.*]] undef, <vscale x 1 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP0]], <vscale x 1 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP1]], <vscale x 1 x double> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg3.mask.nxv1f64.i32(<vscale x 1 x double> [[TMP9]], <vscale x 1 x double> [[TMP10]], <vscale x 1 x double> [[TMP11]], double* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T]] undef, <vscale x 1 x double> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP14]], <vscale x 1 x double> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP16]], <vscale x 1 x double> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e64_v_f64m1x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T:%.*]] undef, <vscale x 1 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP0]], <vscale x 1 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP1]], <vscale x 1 x double> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg3.mask.nxv1f64.i64(<vscale x 1 x double> [[TMP9]], <vscale x 1 x double> [[TMP10]], <vscale x 1 x double> [[TMP11]], double* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T]] undef, <vscale x 1 x double> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP14]], <vscale x 1 x double> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP16]], <vscale x 1 x double> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP18]]
+//
+vfloat64m1x3_t test_vlseg3e64_v_f64m1x3_m (vbool64_t mask, vfloat64m1x3_t maskedoff, const double *base, size_t vl) {
+  return vlseg3e64(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e64_v_f64m1x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T:%.*]] undef, <vscale x 1 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP0]], <vscale x 1 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP1]], <vscale x 1 x double> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP2]], <vscale x 1 x double> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg4.mask.nxv1f64.i32(<vscale x 1 x double> [[TMP12]], <vscale x 1 x double> [[TMP13]], <vscale x 1 x double> [[TMP14]], <vscale x 1 x double> [[TMP15]], double* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] undef, <vscale x 1 x double> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP18]], <vscale x 1 x double> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP20]], <vscale x 1 x double> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP22]], <vscale x 1 x double> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e64_v_f64m1x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T:%.*]] undef, <vscale x 1 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP0]], <vscale x 1 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP1]], <vscale x 1 x double> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP2]], <vscale x 1 x double> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg4.mask.nxv1f64.i64(<vscale x 1 x double> [[TMP12]], <vscale x 1 x double> [[TMP13]], <vscale x 1 x double> [[TMP14]], <vscale x 1 x double> [[TMP15]], double* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] undef, <vscale x 1 x double> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP18]], <vscale x 1 x double> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP20]], <vscale x 1 x double> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP22]], <vscale x 1 x double> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP24]]
+//
+vfloat64m1x4_t test_vlseg4e64_v_f64m1x4_m (vbool64_t mask, vfloat64m1x4_t maskedoff, const double *base, size_t vl) {
+  return vlseg4e64(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e64_v_f64m1x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T:%.*]] undef, <vscale x 1 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP0]], <vscale x 1 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP1]], <vscale x 1 x double> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP2]], <vscale x 1 x double> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP3]], <vscale x 1 x double> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg5.mask.nxv1f64.i32(<vscale x 1 x double> [[TMP15]], <vscale x 1 x double> [[TMP16]], <vscale x 1 x double> [[TMP17]], <vscale x 1 x double> [[TMP18]], <vscale x 1 x double> [[TMP19]], double* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] undef, <vscale x 1 x double> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP22]], <vscale x 1 x double> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP24]], <vscale x 1 x double> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP26]], <vscale x 1 x double> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP28]], <vscale x 1 x double> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e64_v_f64m1x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T:%.*]] undef, <vscale x 1 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP0]], <vscale x 1 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP1]], <vscale x 1 x double> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP2]], <vscale x 1 x double> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP3]], <vscale x 1 x double> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg5.mask.nxv1f64.i64(<vscale x 1 x double> [[TMP15]], <vscale x 1 x double> [[TMP16]], <vscale x 1 x double> [[TMP17]], <vscale x 1 x double> [[TMP18]], <vscale x 1 x double> [[TMP19]], double* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] undef, <vscale x 1 x double> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP22]], <vscale x 1 x double> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP24]], <vscale x 1 x double> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP26]], <vscale x 1 x double> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP28]], <vscale x 1 x double> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP30]]
+//
+vfloat64m1x5_t test_vlseg5e64_v_f64m1x5_m (vbool64_t mask, vfloat64m1x5_t maskedoff, const double *base, size_t vl) {
+  return vlseg5e64(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e64_v_f64m1x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T:%.*]] undef, <vscale x 1 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP0]], <vscale x 1 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP1]], <vscale x 1 x double> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP2]], <vscale x 1 x double> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP3]], <vscale x 1 x double> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP4]], <vscale x 1 x double> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg6.mask.nxv1f64.i32(<vscale x 1 x double> [[TMP18]], <vscale x 1 x double> [[TMP19]], <vscale x 1 x double> [[TMP20]], <vscale x 1 x double> [[TMP21]], <vscale x 1 x double> [[TMP22]], <vscale x 1 x double> [[TMP23]], double* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] undef, <vscale x 1 x double> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP26]], <vscale x 1 x double> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP28]], <vscale x 1 x double> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP30]], <vscale x 1 x double> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP32]], <vscale x 1 x double> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP34]], <vscale x 1 x double> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e64_v_f64m1x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T:%.*]] undef, <vscale x 1 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP0]], <vscale x 1 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP1]], <vscale x 1 x double> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP2]], <vscale x 1 x double> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP3]], <vscale x 1 x double> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP4]], <vscale x 1 x double> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg6.mask.nxv1f64.i64(<vscale x 1 x double> [[TMP18]], <vscale x 1 x double> [[TMP19]], <vscale x 1 x double> [[TMP20]], <vscale x 1 x double> [[TMP21]], <vscale x 1 x double> [[TMP22]], <vscale x 1 x double> [[TMP23]], double* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] undef, <vscale x 1 x double> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP26]], <vscale x 1 x double> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP28]], <vscale x 1 x double> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP30]], <vscale x 1 x double> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP32]], <vscale x 1 x double> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP34]], <vscale x 1 x double> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP36]]
+//
+vfloat64m1x6_t test_vlseg6e64_v_f64m1x6_m (vbool64_t mask, vfloat64m1x6_t maskedoff, const double *base, size_t vl) {
+  return vlseg6e64(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e64_v_f64m1x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T:%.*]] undef, <vscale x 1 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP0]], <vscale x 1 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP1]], <vscale x 1 x double> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP2]], <vscale x 1 x double> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP3]], <vscale x 1 x double> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP4]], <vscale x 1 x double> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP5]], <vscale x 1 x double> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg7.mask.nxv1f64.i32(<vscale x 1 x double> [[TMP21]], <vscale x 1 x double> [[TMP22]], <vscale x 1 x double> [[TMP23]], <vscale x 1 x double> [[TMP24]], <vscale x 1 x double> [[TMP25]], <vscale x 1 x double> [[TMP26]], <vscale x 1 x double> [[TMP27]], double* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] undef, <vscale x 1 x double> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP30]], <vscale x 1 x double> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP32]], <vscale x 1 x double> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP34]], <vscale x 1 x double> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP36]], <vscale x 1 x double> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP38]], <vscale x 1 x double> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP40]], <vscale x 1 x double> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e64_v_f64m1x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T:%.*]] undef, <vscale x 1 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP0]], <vscale x 1 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP1]], <vscale x 1 x double> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP2]], <vscale x 1 x double> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP3]], <vscale x 1 x double> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP4]], <vscale x 1 x double> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP5]], <vscale x 1 x double> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg7.mask.nxv1f64.i64(<vscale x 1 x double> [[TMP21]], <vscale x 1 x double> [[TMP22]], <vscale x 1 x double> [[TMP23]], <vscale x 1 x double> [[TMP24]], <vscale x 1 x double> [[TMP25]], <vscale x 1 x double> [[TMP26]], <vscale x 1 x double> [[TMP27]], double* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] undef, <vscale x 1 x double> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP30]], <vscale x 1 x double> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP32]], <vscale x 1 x double> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP34]], <vscale x 1 x double> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP36]], <vscale x 1 x double> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP38]], <vscale x 1 x double> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP40]], <vscale x 1 x double> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP42]]
+//
+vfloat64m1x7_t test_vlseg7e64_v_f64m1x7_m (vbool64_t mask, vfloat64m1x7_t maskedoff, const double *base, size_t vl) {
+  return vlseg7e64(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e64_v_f64m1x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T:%.*]] undef, <vscale x 1 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP0]], <vscale x 1 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP1]], <vscale x 1 x double> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP2]], <vscale x 1 x double> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP3]], <vscale x 1 x double> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP4]], <vscale x 1 x double> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP5]], <vscale x 1 x double> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP6]], <vscale x 1 x double> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg8.mask.nxv1f64.i32(<vscale x 1 x double> [[TMP24]], <vscale x 1 x double> [[TMP25]], <vscale x 1 x double> [[TMP26]], <vscale x 1 x double> [[TMP27]], <vscale x 1 x double> [[TMP28]], <vscale x 1 x double> [[TMP29]], <vscale x 1 x double> [[TMP30]], <vscale x 1 x double> [[TMP31]], double* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] undef, <vscale x 1 x double> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP34]], <vscale x 1 x double> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP36]], <vscale x 1 x double> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP38]], <vscale x 1 x double> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP40]], <vscale x 1 x double> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP42]], <vscale x 1 x double> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP44]], <vscale x 1 x double> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP46]], <vscale x 1 x double> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e64_v_f64m1x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T:%.*]] undef, <vscale x 1 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP0]], <vscale x 1 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP1]], <vscale x 1 x double> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP2]], <vscale x 1 x double> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP3]], <vscale x 1 x double> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP4]], <vscale x 1 x double> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP5]], <vscale x 1 x double> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP6]], <vscale x 1 x double> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg8.mask.nxv1f64.i64(<vscale x 1 x double> [[TMP24]], <vscale x 1 x double> [[TMP25]], <vscale x 1 x double> [[TMP26]], <vscale x 1 x double> [[TMP27]], <vscale x 1 x double> [[TMP28]], <vscale x 1 x double> [[TMP29]], <vscale x 1 x double> [[TMP30]], <vscale x 1 x double> [[TMP31]], double* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] undef, <vscale x 1 x double> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP34]], <vscale x 1 x double> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP36]], <vscale x 1 x double> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP38]], <vscale x 1 x double> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP40]], <vscale x 1 x double> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP42]], <vscale x 1 x double> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP44]], <vscale x 1 x double> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP46]], <vscale x 1 x double> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP48]]
+//
+vfloat64m1x8_t test_vlseg8e64_v_f64m1x8_m (vbool64_t mask, vfloat64m1x8_t maskedoff, const double *base, size_t vl) {
+  return vlseg8e64(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e64_v_f64m2x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X2_T:%.*]] undef, <vscale x 2 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP0]], <vscale x 2 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.riscv.vlseg2.mask.nxv2f64.i32(<vscale x 2 x double> [[TMP6]], <vscale x 2 x double> [[TMP7]], double* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X2_T]] undef, <vscale x 2 x double> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP10]], <vscale x 2 x double> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e64_v_f64m2x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X2_T:%.*]] undef, <vscale x 2 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP0]], <vscale x 2 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.riscv.vlseg2.mask.nxv2f64.i64(<vscale x 2 x double> [[TMP6]], <vscale x 2 x double> [[TMP7]], double* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X2_T]] undef, <vscale x 2 x double> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP10]], <vscale x 2 x double> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP12]]
+//
+vfloat64m2x2_t test_vlseg2e64_v_f64m2x2_m (vbool32_t mask, vfloat64m2x2_t maskedoff, const double *base, size_t vl) {
+  return vlseg2e64(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e64_v_f64m2x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T:%.*]] undef, <vscale x 2 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP0]], <vscale x 2 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP1]], <vscale x 2 x double> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @llvm.riscv.vlseg3.mask.nxv2f64.i32(<vscale x 2 x double> [[TMP9]], <vscale x 2 x double> [[TMP10]], <vscale x 2 x double> [[TMP11]], double* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T]] undef, <vscale x 2 x double> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP14]], <vscale x 2 x double> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP16]], <vscale x 2 x double> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e64_v_f64m2x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T:%.*]] undef, <vscale x 2 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP0]], <vscale x 2 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP1]], <vscale x 2 x double> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @llvm.riscv.vlseg3.mask.nxv2f64.i64(<vscale x 2 x double> [[TMP9]], <vscale x 2 x double> [[TMP10]], <vscale x 2 x double> [[TMP11]], double* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T]] undef, <vscale x 2 x double> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP14]], <vscale x 2 x double> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP16]], <vscale x 2 x double> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP18]]
+//
+vfloat64m2x3_t test_vlseg3e64_v_f64m2x3_m (vbool32_t mask, vfloat64m2x3_t maskedoff, const double *base, size_t vl) {
+  return vlseg3e64(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e64_v_f64m2x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T:%.*]] undef, <vscale x 2 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP0]], <vscale x 2 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP1]], <vscale x 2 x double> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP2]], <vscale x 2 x double> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @llvm.riscv.vlseg4.mask.nxv2f64.i32(<vscale x 2 x double> [[TMP12]], <vscale x 2 x double> [[TMP13]], <vscale x 2 x double> [[TMP14]], <vscale x 2 x double> [[TMP15]], double* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] undef, <vscale x 2 x double> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP18]], <vscale x 2 x double> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP20]], <vscale x 2 x double> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP22]], <vscale x 2 x double> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e64_v_f64m2x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T:%.*]] undef, <vscale x 2 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP0]], <vscale x 2 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP1]], <vscale x 2 x double> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP2]], <vscale x 2 x double> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @llvm.riscv.vlseg4.mask.nxv2f64.i64(<vscale x 2 x double> [[TMP12]], <vscale x 2 x double> [[TMP13]], <vscale x 2 x double> [[TMP14]], <vscale x 2 x double> [[TMP15]], double* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] undef, <vscale x 2 x double> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP18]], <vscale x 2 x double> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP20]], <vscale x 2 x double> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP22]], <vscale x 2 x double> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP24]]
+//
+vfloat64m2x4_t test_vlseg4e64_v_f64m2x4_m (vbool32_t mask, vfloat64m2x4_t maskedoff, const double *base, size_t vl) {
+  return vlseg4e64(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e64_v_f64m4x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M4X2_T:%.*]] undef, <vscale x 4 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP0]], <vscale x 4 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x double>, <vscale x 4 x double> } @llvm.riscv.vlseg2.mask.nxv4f64.i32(<vscale x 4 x double> [[TMP6]], <vscale x 4 x double> [[TMP7]], double* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x double>, <vscale x 4 x double> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M4X2_T]] undef, <vscale x 4 x double> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x double>, <vscale x 4 x double> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP10]], <vscale x 4 x double> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e64_v_f64m4x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M4X2_T:%.*]] undef, <vscale x 4 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP0]], <vscale x 4 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x double>, <vscale x 4 x double> } @llvm.riscv.vlseg2.mask.nxv4f64.i64(<vscale x 4 x double> [[TMP6]], <vscale x 4 x double> [[TMP7]], double* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR7]]
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x double>, <vscale x 4 x double> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M4X2_T]] undef, <vscale x 4 x double> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x double>, <vscale x 4 x double> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP10]], <vscale x 4 x double> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP12]]
+//
+vfloat64m4x2_t test_vlseg2e64_v_f64m4x2_m (vbool16_t mask, vfloat64m4x2_t maskedoff, const double *base, size_t vl) {
+  return vlseg2e64(mask, maskedoff, base, vl);
+}

clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
+// RUN:   -target-feature +experimental-v \
+// RUN:   -target-feature +experimental-zfh -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
+// RUN:   -target-feature +experimental-zfh -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
+// RUN:   -target-feature +experimental-zfh -target-feature +m -fallow-half-arguments-and-returns -Werror -Wall -S -o - %s >/dev/null 2>%t
+// RUN: FileCheck --check-prefix=ASM --allow-empty %s <%t
+
+// ASM-NOT: warning
+#include <riscv_vector.h>
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_i8mf8x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg2.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X2_T:%.*]] undef, <vscale x 1 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X2_T]] [[TMP2]], <vscale x 1 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF8X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_i8mf8x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg2.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X2_T:%.*]] undef, <vscale x 1 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X2_T]] [[TMP2]], <vscale x 1 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF8X2_T]] [[TMP4]]
+//
+vint8mf8x2_t test_vlseg2e8_v_i8mf8x2 (const int8_t *base, size_t vl) {
+  return vlseg2e8_v_i8mf8x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e8_v_i8mf8x3(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg3.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T:%.*]] undef, <vscale x 1 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP2]], <vscale x 1 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP4]], <vscale x 1 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF8X3_T]] [[TMP6]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e8_v_i8mf8x3(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg3.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T:%.*]] undef, <vscale x 1 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP2]], <vscale x 1 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP4]], <vscale x 1 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF8X3_T]] [[TMP6]]
+//
+vint8mf8x3_t test_vlseg3e8_v_i8mf8x3 (const int8_t *base, size_t vl) {
+  return vlseg3e8_v_i8mf8x3(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e8_v_i8mf8x4(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg4.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T:%.*]] undef, <vscale x 1 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP2]], <vscale x 1 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP4]], <vscale x 1 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP6]], <vscale x 1 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF8X4_T]] [[TMP8]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e8_v_i8mf8x4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg4.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T:%.*]] undef, <vscale x 1 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP2]], <vscale x 1 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP4]], <vscale x 1 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP6]], <vscale x 1 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF8X4_T]] [[TMP8]]
+//
+vint8mf8x4_t test_vlseg4e8_v_i8mf8x4 (const int8_t *base, size_t vl) {
+  return vlseg4e8_v_i8mf8x4(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e8_v_i8mf8x5(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg5.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T:%.*]] undef, <vscale x 1 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP2]], <vscale x 1 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], <vscale x 1 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP6]], <vscale x 1 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP8]], <vscale x 1 x i8> [[TMP9]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF8X5_T]] [[TMP10]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e8_v_i8mf8x5(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg5.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T:%.*]] undef, <vscale x 1 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP2]], <vscale x 1 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], <vscale x 1 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP6]], <vscale x 1 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP8]], <vscale x 1 x i8> [[TMP9]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF8X5_T]] [[TMP10]]
+//
+vint8mf8x5_t test_vlseg5e8_v_i8mf8x5 (const int8_t *base, size_t vl) {
+  return vlseg5e8_v_i8mf8x5(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e8_v_i8mf8x6(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg6.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T:%.*]] undef, <vscale x 1 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP2]], <vscale x 1 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP4]], <vscale x 1 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP6]], <vscale x 1 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP8]], <vscale x 1 x i8> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP10]], <vscale x 1 x i8> [[TMP11]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF8X6_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e8_v_i8mf8x6(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg6.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T:%.*]] undef, <vscale x 1 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP2]], <vscale x 1 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP4]], <vscale x 1 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP6]], <vscale x 1 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP8]], <vscale x 1 x i8> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP10]], <vscale x 1 x i8> [[TMP11]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF8X6_T]] [[TMP12]]
+//
+vint8mf8x6_t test_vlseg6e8_v_i8mf8x6 (const int8_t *base, size_t vl) {
+  return vlseg6e8_v_i8mf8x6(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e8_v_i8mf8x7(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg7.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T:%.*]] undef, <vscale x 1 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP2]], <vscale x 1 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP4]], <vscale x 1 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], <vscale x 1 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP8]], <vscale x 1 x i8> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP10]], <vscale x 1 x i8> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP12]], <vscale x 1 x i8> [[TMP13]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF8X7_T]] [[TMP14]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e8_v_i8mf8x7(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg7.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T:%.*]] undef, <vscale x 1 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP2]], <vscale x 1 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP4]], <vscale x 1 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], <vscale x 1 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP8]], <vscale x 1 x i8> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP10]], <vscale x 1 x i8> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP12]], <vscale x 1 x i8> [[TMP13]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF8X7_T]] [[TMP14]]
+//
+vint8mf8x7_t test_vlseg7e8_v_i8mf8x7 (const int8_t *base, size_t vl) {
+  return vlseg7e8_v_i8mf8x7(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e8_v_i8mf8x8(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg8.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T:%.*]] undef, <vscale x 1 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP2]], <vscale x 1 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP4]], <vscale x 1 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP6]], <vscale x 1 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP8]], <vscale x 1 x i8> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP10]], <vscale x 1 x i8> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP12]], <vscale x 1 x i8> [[TMP13]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP14]], <vscale x 1 x i8> [[TMP15]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF8X8_T]] [[TMP16]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e8_v_i8mf8x8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg8.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T:%.*]] undef, <vscale x 1 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP2]], <vscale x 1 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP4]], <vscale x 1 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP6]], <vscale x 1 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP8]], <vscale x 1 x i8> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP10]], <vscale x 1 x i8> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP12]], <vscale x 1 x i8> [[TMP13]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP14]], <vscale x 1 x i8> [[TMP15]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF8X8_T]] [[TMP16]]
+//
+vint8mf8x8_t test_vlseg8e8_v_i8mf8x8 (const int8_t *base, size_t vl) {
+  return vlseg8e8_v_i8mf8x8(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_i8mf4x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg2.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X2_T:%.*]] undef, <vscale x 2 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X2_T]] [[TMP2]], <vscale x 2 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF4X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_i8mf4x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg2.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X2_T:%.*]] undef, <vscale x 2 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X2_T]] [[TMP2]], <vscale x 2 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF4X2_T]] [[TMP4]]
+//
+vint8mf4x2_t test_vlseg2e8_v_i8mf4x2 (const int8_t *base, size_t vl) {
+  return vlseg2e8_v_i8mf4x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e8_v_i8mf4x3(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg3.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T:%.*]] undef, <vscale x 2 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP2]], <vscale x 2 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP4]], <vscale x 2 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF4X3_T]] [[TMP6]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e8_v_i8mf4x3(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg3.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T:%.*]] undef, <vscale x 2 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP2]], <vscale x 2 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP4]], <vscale x 2 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF4X3_T]] [[TMP6]]
+//
+vint8mf4x3_t test_vlseg3e8_v_i8mf4x3 (const int8_t *base, size_t vl) {
+  return vlseg3e8_v_i8mf4x3(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e8_v_i8mf4x4(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg4.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T:%.*]] undef, <vscale x 2 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP2]], <vscale x 2 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP4]], <vscale x 2 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP6]], <vscale x 2 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF4X4_T]] [[TMP8]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e8_v_i8mf4x4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg4.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T:%.*]] undef, <vscale x 2 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP2]], <vscale x 2 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP4]], <vscale x 2 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP6]], <vscale x 2 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF4X4_T]] [[TMP8]]
+//
+vint8mf4x4_t test_vlseg4e8_v_i8mf4x4 (const int8_t *base, size_t vl) {
+  return vlseg4e8_v_i8mf4x4(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e8_v_i8mf4x5(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg5.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T:%.*]] undef, <vscale x 2 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP2]], <vscale x 2 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], <vscale x 2 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP6]], <vscale x 2 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP8]], <vscale x 2 x i8> [[TMP9]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF4X5_T]] [[TMP10]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e8_v_i8mf4x5(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg5.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T:%.*]] undef, <vscale x 2 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP2]], <vscale x 2 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], <vscale x 2 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP6]], <vscale x 2 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP8]], <vscale x 2 x i8> [[TMP9]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF4X5_T]] [[TMP10]]
+//
+vint8mf4x5_t test_vlseg5e8_v_i8mf4x5 (const int8_t *base, size_t vl) {
+  return vlseg5e8_v_i8mf4x5(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e8_v_i8mf4x6(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg6.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T:%.*]] undef, <vscale x 2 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP2]], <vscale x 2 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP4]], <vscale x 2 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP6]], <vscale x 2 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP8]], <vscale x 2 x i8> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP10]], <vscale x 2 x i8> [[TMP11]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF4X6_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e8_v_i8mf4x6(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg6.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T:%.*]] undef, <vscale x 2 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP2]], <vscale x 2 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP4]], <vscale x 2 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP6]], <vscale x 2 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP8]], <vscale x 2 x i8> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP10]], <vscale x 2 x i8> [[TMP11]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF4X6_T]] [[TMP12]]
+//
+vint8mf4x6_t test_vlseg6e8_v_i8mf4x6 (const int8_t *base, size_t vl) {
+  return vlseg6e8_v_i8mf4x6(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e8_v_i8mf4x7(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg7.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T:%.*]] undef, <vscale x 2 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP2]], <vscale x 2 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP4]], <vscale x 2 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], <vscale x 2 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP8]], <vscale x 2 x i8> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP10]], <vscale x 2 x i8> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP12]], <vscale x 2 x i8> [[TMP13]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF4X7_T]] [[TMP14]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e8_v_i8mf4x7(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg7.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T:%.*]] undef, <vscale x 2 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP2]], <vscale x 2 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP4]], <vscale x 2 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], <vscale x 2 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP8]], <vscale x 2 x i8> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP10]], <vscale x 2 x i8> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP12]], <vscale x 2 x i8> [[TMP13]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF4X7_T]] [[TMP14]]
+//
+vint8mf4x7_t test_vlseg7e8_v_i8mf4x7 (const int8_t *base, size_t vl) {
+  return vlseg7e8_v_i8mf4x7(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e8_v_i8mf4x8(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg8.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T:%.*]] undef, <vscale x 2 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP2]], <vscale x 2 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP4]], <vscale x 2 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP6]], <vscale x 2 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP8]], <vscale x 2 x i8> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP10]], <vscale x 2 x i8> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP12]], <vscale x 2 x i8> [[TMP13]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP14]], <vscale x 2 x i8> [[TMP15]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF4X8_T]] [[TMP16]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e8_v_i8mf4x8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg8.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T:%.*]] undef, <vscale x 2 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP2]], <vscale x 2 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP4]], <vscale x 2 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP6]], <vscale x 2 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP8]], <vscale x 2 x i8> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP10]], <vscale x 2 x i8> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP12]], <vscale x 2 x i8> [[TMP13]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP14]], <vscale x 2 x i8> [[TMP15]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF4X8_T]] [[TMP16]]
+//
+vint8mf4x8_t test_vlseg8e8_v_i8mf4x8 (const int8_t *base, size_t vl) {
+  return vlseg8e8_v_i8mf4x8(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_i8mf2x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg2.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X2_T:%.*]] undef, <vscale x 4 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X2_T]] [[TMP2]], <vscale x 4 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF2X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_i8mf2x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg2.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X2_T:%.*]] undef, <vscale x 4 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X2_T]] [[TMP2]], <vscale x 4 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF2X2_T]] [[TMP4]]
+//
+vint8mf2x2_t test_vlseg2e8_v_i8mf2x2 (const int8_t *base, size_t vl) {
+  return vlseg2e8_v_i8mf2x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e8_v_i8mf2x3(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg3.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T:%.*]] undef, <vscale x 4 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP2]], <vscale x 4 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP4]], <vscale x 4 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF2X3_T]] [[TMP6]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e8_v_i8mf2x3(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg3.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T:%.*]] undef, <vscale x 4 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP2]], <vscale x 4 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP4]], <vscale x 4 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF2X3_T]] [[TMP6]]
+//
+vint8mf2x3_t test_vlseg3e8_v_i8mf2x3 (const int8_t *base, size_t vl) {
+  return vlseg3e8_v_i8mf2x3(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e8_v_i8mf2x4(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg4.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T:%.*]] undef, <vscale x 4 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP2]], <vscale x 4 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP4]], <vscale x 4 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP6]], <vscale x 4 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF2X4_T]] [[TMP8]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e8_v_i8mf2x4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg4.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T:%.*]] undef, <vscale x 4 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP2]], <vscale x 4 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP4]], <vscale x 4 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP6]], <vscale x 4 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF2X4_T]] [[TMP8]]
+//
+vint8mf2x4_t test_vlseg4e8_v_i8mf2x4 (const int8_t *base, size_t vl) {
+  return vlseg4e8_v_i8mf2x4(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e8_v_i8mf2x5(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg5.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T:%.*]] undef, <vscale x 4 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP2]], <vscale x 4 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], <vscale x 4 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP6]], <vscale x 4 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP8]], <vscale x 4 x i8> [[TMP9]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF2X5_T]] [[TMP10]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e8_v_i8mf2x5(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg5.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T:%.*]] undef, <vscale x 4 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP2]], <vscale x 4 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], <vscale x 4 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP6]], <vscale x 4 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP8]], <vscale x 4 x i8> [[TMP9]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF2X5_T]] [[TMP10]]
+//
+vint8mf2x5_t test_vlseg5e8_v_i8mf2x5 (const int8_t *base, size_t vl) {
+  return vlseg5e8_v_i8mf2x5(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e8_v_i8mf2x6(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg6.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T:%.*]] undef, <vscale x 4 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP2]], <vscale x 4 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP4]], <vscale x 4 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP6]], <vscale x 4 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP8]], <vscale x 4 x i8> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP10]], <vscale x 4 x i8> [[TMP11]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF2X6_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e8_v_i8mf2x6(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg6.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T:%.*]] undef, <vscale x 4 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP2]], <vscale x 4 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP4]], <vscale x 4 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP6]], <vscale x 4 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP8]], <vscale x 4 x i8> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP10]], <vscale x 4 x i8> [[TMP11]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF2X6_T]] [[TMP12]]
+//
+vint8mf2x6_t test_vlseg6e8_v_i8mf2x6 (const int8_t *base, size_t vl) {
+  return vlseg6e8_v_i8mf2x6(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e8_v_i8mf2x7(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg7.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T:%.*]] undef, <vscale x 4 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP2]], <vscale x 4 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP4]], <vscale x 4 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], <vscale x 4 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP8]], <vscale x 4 x i8> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP10]], <vscale x 4 x i8> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP12]], <vscale x 4 x i8> [[TMP13]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF2X7_T]] [[TMP14]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e8_v_i8mf2x7(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg7.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T:%.*]] undef, <vscale x 4 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP2]], <vscale x 4 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP4]], <vscale x 4 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], <vscale x 4 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP8]], <vscale x 4 x i8> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP10]], <vscale x 4 x i8> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP12]], <vscale x 4 x i8> [[TMP13]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF2X7_T]] [[TMP14]]
+//
+vint8mf2x7_t test_vlseg7e8_v_i8mf2x7 (const int8_t *base, size_t vl) {
+  return vlseg7e8_v_i8mf2x7(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e8_v_i8mf2x8(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg8.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T:%.*]] undef, <vscale x 4 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP2]], <vscale x 4 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP4]], <vscale x 4 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP6]], <vscale x 4 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP8]], <vscale x 4 x i8> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP10]], <vscale x 4 x i8> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP12]], <vscale x 4 x i8> [[TMP13]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP14]], <vscale x 4 x i8> [[TMP15]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF2X8_T]] [[TMP16]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e8_v_i8mf2x8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg8.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T:%.*]] undef, <vscale x 4 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP2]], <vscale x 4 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP4]], <vscale x 4 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP6]], <vscale x 4 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP8]], <vscale x 4 x i8> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP10]], <vscale x 4 x i8> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP12]], <vscale x 4 x i8> [[TMP13]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP14]], <vscale x 4 x i8> [[TMP15]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF2X8_T]] [[TMP16]]
+//
+vint8mf2x8_t test_vlseg8e8_v_i8mf2x8 (const int8_t *base, size_t vl) {
+  return vlseg8e8_v_i8mf2x8(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_i8m1x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg2.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X2_T:%.*]] undef, <vscale x 8 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X2_T]] [[TMP2]], <vscale x 8 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8M1X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_i8m1x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg2.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X2_T:%.*]] undef, <vscale x 8 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X2_T]] [[TMP2]], <vscale x 8 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8M1X2_T]] [[TMP4]]
+//
+vint8m1x2_t test_vlseg2e8_v_i8m1x2 (const int8_t *base, size_t vl) {
+  return vlseg2e8_v_i8m1x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e8_v_i8m1x3(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg3.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T:%.*]] undef, <vscale x 8 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP2]], <vscale x 8 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP4]], <vscale x 8 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8M1X3_T]] [[TMP6]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e8_v_i8m1x3(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg3.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T:%.*]] undef, <vscale x 8 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP2]], <vscale x 8 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP4]], <vscale x 8 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8M1X3_T]] [[TMP6]]
+//
+vint8m1x3_t test_vlseg3e8_v_i8m1x3 (const int8_t *base, size_t vl) {
+  return vlseg3e8_v_i8m1x3(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e8_v_i8m1x4(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg4.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T:%.*]] undef, <vscale x 8 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP2]], <vscale x 8 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP4]], <vscale x 8 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP6]], <vscale x 8 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8M1X4_T]] [[TMP8]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e8_v_i8m1x4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg4.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T:%.*]] undef, <vscale x 8 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP2]], <vscale x 8 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP4]], <vscale x 8 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP6]], <vscale x 8 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8M1X4_T]] [[TMP8]]
+//
+vint8m1x4_t test_vlseg4e8_v_i8m1x4 (const int8_t *base, size_t vl) {
+  return vlseg4e8_v_i8m1x4(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e8_v_i8m1x5(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg5.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T:%.*]] undef, <vscale x 8 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP2]], <vscale x 8 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], <vscale x 8 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP6]], <vscale x 8 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP8]], <vscale x 8 x i8> [[TMP9]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8M1X5_T]] [[TMP10]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e8_v_i8m1x5(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg5.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T:%.*]] undef, <vscale x 8 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP2]], <vscale x 8 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], <vscale x 8 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP6]], <vscale x 8 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP8]], <vscale x 8 x i8> [[TMP9]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8M1X5_T]] [[TMP10]]
+//
+vint8m1x5_t test_vlseg5e8_v_i8m1x5 (const int8_t *base, size_t vl) {
+  return vlseg5e8_v_i8m1x5(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e8_v_i8m1x6(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg6.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T:%.*]] undef, <vscale x 8 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP2]], <vscale x 8 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP4]], <vscale x 8 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP6]], <vscale x 8 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP8]], <vscale x 8 x i8> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP10]], <vscale x 8 x i8> [[TMP11]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8M1X6_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e8_v_i8m1x6(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg6.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T:%.*]] undef, <vscale x 8 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP2]], <vscale x 8 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP4]], <vscale x 8 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP6]], <vscale x 8 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP8]], <vscale x 8 x i8> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP10]], <vscale x 8 x i8> [[TMP11]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8M1X6_T]] [[TMP12]]
+//
+vint8m1x6_t test_vlseg6e8_v_i8m1x6 (const int8_t *base, size_t vl) {
+  return vlseg6e8_v_i8m1x6(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e8_v_i8m1x7(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg7.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T:%.*]] undef, <vscale x 8 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP2]], <vscale x 8 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP4]], <vscale x 8 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], <vscale x 8 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP8]], <vscale x 8 x i8> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP10]], <vscale x 8 x i8> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP12]], <vscale x 8 x i8> [[TMP13]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8M1X7_T]] [[TMP14]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e8_v_i8m1x7(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg7.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T:%.*]] undef, <vscale x 8 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP2]], <vscale x 8 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP4]], <vscale x 8 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], <vscale x 8 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP8]], <vscale x 8 x i8> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP10]], <vscale x 8 x i8> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP12]], <vscale x 8 x i8> [[TMP13]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8M1X7_T]] [[TMP14]]
+//
+vint8m1x7_t test_vlseg7e8_v_i8m1x7 (const int8_t *base, size_t vl) {
+  return vlseg7e8_v_i8m1x7(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e8_v_i8m1x8(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg8.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T:%.*]] undef, <vscale x 8 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP2]], <vscale x 8 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP4]], <vscale x 8 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP6]], <vscale x 8 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP8]], <vscale x 8 x i8> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP10]], <vscale x 8 x i8> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP12]], <vscale x 8 x i8> [[TMP13]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP14]], <vscale x 8 x i8> [[TMP15]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8M1X8_T]] [[TMP16]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e8_v_i8m1x8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg8.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T:%.*]] undef, <vscale x 8 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP2]], <vscale x 8 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP4]], <vscale x 8 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP6]], <vscale x 8 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP8]], <vscale x 8 x i8> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP10]], <vscale x 8 x i8> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP12]], <vscale x 8 x i8> [[TMP13]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP14]], <vscale x 8 x i8> [[TMP15]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8M1X8_T]] [[TMP16]]
+//
+vint8m1x8_t test_vlseg8e8_v_i8m1x8 (const int8_t *base, size_t vl) {
+  return vlseg8e8_v_i8m1x8(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_i8m2x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg2.nxv16i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X2_T:%.*]] undef, <vscale x 16 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X2_T]] [[TMP2]], <vscale x 16 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8M2X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_i8m2x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg2.nxv16i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X2_T:%.*]] undef, <vscale x 16 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X2_T]] [[TMP2]], <vscale x 16 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8M2X2_T]] [[TMP4]]
+//
+vint8m2x2_t test_vlseg2e8_v_i8m2x2 (const int8_t *base, size_t vl) {
+  return vlseg2e8_v_i8m2x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e8_v_i8m2x3(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg3.nxv16i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T:%.*]] undef, <vscale x 16 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP2]], <vscale x 16 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP4]], <vscale x 16 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8M2X3_T]] [[TMP6]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e8_v_i8m2x3(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg3.nxv16i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T:%.*]] undef, <vscale x 16 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP2]], <vscale x 16 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP4]], <vscale x 16 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8M2X3_T]] [[TMP6]]
+//
+vint8m2x3_t test_vlseg3e8_v_i8m2x3 (const int8_t *base, size_t vl) {
+  return vlseg3e8_v_i8m2x3(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e8_v_i8m2x4(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg4.nxv16i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T:%.*]] undef, <vscale x 16 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP2]], <vscale x 16 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP4]], <vscale x 16 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP6]], <vscale x 16 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8M2X4_T]] [[TMP8]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e8_v_i8m2x4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg4.nxv16i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T:%.*]] undef, <vscale x 16 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP2]], <vscale x 16 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP4]], <vscale x 16 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP6]], <vscale x 16 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8M2X4_T]] [[TMP8]]
+//
+vint8m2x4_t test_vlseg4e8_v_i8m2x4 (const int8_t *base, size_t vl) {
+  return vlseg4e8_v_i8m2x4(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_i8m4x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 32 x i8>, <vscale x 32 x i8> } @llvm.riscv.vlseg2.nxv32i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M4X2_T:%.*]] undef, <vscale x 32 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M4X2_T]] [[TMP2]], <vscale x 32 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8M4X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_i8m4x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 32 x i8>, <vscale x 32 x i8> } @llvm.riscv.vlseg2.nxv32i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M4X2_T:%.*]] undef, <vscale x 32 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M4X2_T]] [[TMP2]], <vscale x 32 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8M4X2_T]] [[TMP4]]
+//
+vint8m4x2_t test_vlseg2e8_v_i8m4x2 (const int8_t *base, size_t vl) {
+  return vlseg2e8_v_i8m4x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e16_v_i16mf4x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg2.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X2_T:%.*]] undef, <vscale x 1 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X2_T]] [[TMP2]], <vscale x 1 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF4X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e16_v_i16mf4x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg2.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X2_T:%.*]] undef, <vscale x 1 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X2_T]] [[TMP2]], <vscale x 1 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF4X2_T]] [[TMP4]]
+//
+vint16mf4x2_t test_vlseg2e16_v_i16mf4x2 (const int16_t *base, size_t vl) {
+  return vlseg2e16_v_i16mf4x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e16_v_i16mf4x3(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg3.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T:%.*]] undef, <vscale x 1 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP2]], <vscale x 1 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP4]], <vscale x 1 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF4X3_T]] [[TMP6]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e16_v_i16mf4x3(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg3.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T:%.*]] undef, <vscale x 1 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP2]], <vscale x 1 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP4]], <vscale x 1 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF4X3_T]] [[TMP6]]
+//
+vint16mf4x3_t test_vlseg3e16_v_i16mf4x3 (const int16_t *base, size_t vl) {
+  return vlseg3e16_v_i16mf4x3(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e16_v_i16mf4x4(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg4.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T:%.*]] undef, <vscale x 1 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP2]], <vscale x 1 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP4]], <vscale x 1 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP6]], <vscale x 1 x i16> [[TMP7]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF4X4_T]] [[TMP8]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e16_v_i16mf4x4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg4.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T:%.*]] undef, <vscale x 1 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP2]], <vscale x 1 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP4]], <vscale x 1 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP6]], <vscale x 1 x i16> [[TMP7]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF4X4_T]] [[TMP8]]
+//
+vint16mf4x4_t test_vlseg4e16_v_i16mf4x4 (const int16_t *base, size_t vl) {
+  return vlseg4e16_v_i16mf4x4(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e16_v_i16mf4x5(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg5.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T:%.*]] undef, <vscale x 1 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP2]], <vscale x 1 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], <vscale x 1 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP6]], <vscale x 1 x i16> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP8]], <vscale x 1 x i16> [[TMP9]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF4X5_T]] [[TMP10]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e16_v_i16mf4x5(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg5.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T:%.*]] undef, <vscale x 1 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP2]], <vscale x 1 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], <vscale x 1 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP6]], <vscale x 1 x i16> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP8]], <vscale x 1 x i16> [[TMP9]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF4X5_T]] [[TMP10]]
+//
+vint16mf4x5_t test_vlseg5e16_v_i16mf4x5 (const int16_t *base, size_t vl) {
+  return vlseg5e16_v_i16mf4x5(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e16_v_i16mf4x6(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg6.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T:%.*]] undef, <vscale x 1 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP2]], <vscale x 1 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP4]], <vscale x 1 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP6]], <vscale x 1 x i16> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP8]], <vscale x 1 x i16> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP10]], <vscale x 1 x i16> [[TMP11]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF4X6_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e16_v_i16mf4x6(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg6.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T:%.*]] undef, <vscale x 1 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP2]], <vscale x 1 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP4]], <vscale x 1 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP6]], <vscale x 1 x i16> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP8]], <vscale x 1 x i16> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP10]], <vscale x 1 x i16> [[TMP11]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF4X6_T]] [[TMP12]]
+//
+vint16mf4x6_t test_vlseg6e16_v_i16mf4x6 (const int16_t *base, size_t vl) {
+  return vlseg6e16_v_i16mf4x6(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e16_v_i16mf4x7(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg7.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T:%.*]] undef, <vscale x 1 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP2]], <vscale x 1 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP4]], <vscale x 1 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], <vscale x 1 x i16> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP8]], <vscale x 1 x i16> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP10]], <vscale x 1 x i16> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP12]], <vscale x 1 x i16> [[TMP13]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF4X7_T]] [[TMP14]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e16_v_i16mf4x7(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg7.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T:%.*]] undef, <vscale x 1 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP2]], <vscale x 1 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP4]], <vscale x 1 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], <vscale x 1 x i16> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP8]], <vscale x 1 x i16> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP10]], <vscale x 1 x i16> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP12]], <vscale x 1 x i16> [[TMP13]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF4X7_T]] [[TMP14]]
+//
+vint16mf4x7_t test_vlseg7e16_v_i16mf4x7 (const int16_t *base, size_t vl) {
+  return vlseg7e16_v_i16mf4x7(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e16_v_i16mf4x8(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg8.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T:%.*]] undef, <vscale x 1 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP2]], <vscale x 1 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP4]], <vscale x 1 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP6]], <vscale x 1 x i16> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP8]], <vscale x 1 x i16> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP10]], <vscale x 1 x i16> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP12]], <vscale x 1 x i16> [[TMP13]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP14]], <vscale x 1 x i16> [[TMP15]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF4X8_T]] [[TMP16]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e16_v_i16mf4x8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg8.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T:%.*]] undef, <vscale x 1 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP2]], <vscale x 1 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP4]], <vscale x 1 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP6]], <vscale x 1 x i16> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP8]], <vscale x 1 x i16> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP10]], <vscale x 1 x i16> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP12]], <vscale x 1 x i16> [[TMP13]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP14]], <vscale x 1 x i16> [[TMP15]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF4X8_T]] [[TMP16]]
+//
+vint16mf4x8_t test_vlseg8e16_v_i16mf4x8 (const int16_t *base, size_t vl) {
+  return vlseg8e16_v_i16mf4x8(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e16_v_i16mf2x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg2.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X2_T:%.*]] undef, <vscale x 2 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X2_T]] [[TMP2]], <vscale x 2 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF2X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e16_v_i16mf2x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg2.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X2_T:%.*]] undef, <vscale x 2 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X2_T]] [[TMP2]], <vscale x 2 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF2X2_T]] [[TMP4]]
+//
+vint16mf2x2_t test_vlseg2e16_v_i16mf2x2 (const int16_t *base, size_t vl) {
+  return vlseg2e16_v_i16mf2x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e16_v_i16mf2x3(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg3.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T:%.*]] undef, <vscale x 2 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP2]], <vscale x 2 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP4]], <vscale x 2 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF2X3_T]] [[TMP6]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e16_v_i16mf2x3(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg3.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T:%.*]] undef, <vscale x 2 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP2]], <vscale x 2 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP4]], <vscale x 2 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF2X3_T]] [[TMP6]]
+//
+vint16mf2x3_t test_vlseg3e16_v_i16mf2x3 (const int16_t *base, size_t vl) {
+  return vlseg3e16_v_i16mf2x3(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e16_v_i16mf2x4(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg4.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T:%.*]] undef, <vscale x 2 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP2]], <vscale x 2 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP4]], <vscale x 2 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP6]], <vscale x 2 x i16> [[TMP7]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF2X4_T]] [[TMP8]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e16_v_i16mf2x4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg4.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T:%.*]] undef, <vscale x 2 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP2]], <vscale x 2 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP4]], <vscale x 2 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP6]], <vscale x 2 x i16> [[TMP7]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF2X4_T]] [[TMP8]]
+//
+vint16mf2x4_t test_vlseg4e16_v_i16mf2x4 (const int16_t *base, size_t vl) {
+  return vlseg4e16_v_i16mf2x4(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e16_v_i16mf2x5(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg5.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T:%.*]] undef, <vscale x 2 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP2]], <vscale x 2 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], <vscale x 2 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP6]], <vscale x 2 x i16> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP8]], <vscale x 2 x i16> [[TMP9]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF2X5_T]] [[TMP10]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e16_v_i16mf2x5(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg5.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T:%.*]] undef, <vscale x 2 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP2]], <vscale x 2 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], <vscale x 2 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP6]], <vscale x 2 x i16> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP8]], <vscale x 2 x i16> [[TMP9]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF2X5_T]] [[TMP10]]
+//
+vint16mf2x5_t test_vlseg5e16_v_i16mf2x5 (const int16_t *base, size_t vl) {
+  return vlseg5e16_v_i16mf2x5(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e16_v_i16mf2x6(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg6.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T:%.*]] undef, <vscale x 2 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP2]], <vscale x 2 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP4]], <vscale x 2 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP6]], <vscale x 2 x i16> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP8]], <vscale x 2 x i16> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP10]], <vscale x 2 x i16> [[TMP11]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF2X6_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e16_v_i16mf2x6(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg6.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T:%.*]] undef, <vscale x 2 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP2]], <vscale x 2 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP4]], <vscale x 2 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP6]], <vscale x 2 x i16> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP8]], <vscale x 2 x i16> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP10]], <vscale x 2 x i16> [[TMP11]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF2X6_T]] [[TMP12]]
+//
+vint16mf2x6_t test_vlseg6e16_v_i16mf2x6 (const int16_t *base, size_t vl) {
+  return vlseg6e16_v_i16mf2x6(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e16_v_i16mf2x7(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg7.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T:%.*]] undef, <vscale x 2 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP2]], <vscale x 2 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP4]], <vscale x 2 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], <vscale x 2 x i16> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP8]], <vscale x 2 x i16> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP10]], <vscale x 2 x i16> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP12]], <vscale x 2 x i16> [[TMP13]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF2X7_T]] [[TMP14]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e16_v_i16mf2x7(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg7.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T:%.*]] undef, <vscale x 2 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP2]], <vscale x 2 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP4]], <vscale x 2 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], <vscale x 2 x i16> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP8]], <vscale x 2 x i16> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP10]], <vscale x 2 x i16> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP12]], <vscale x 2 x i16> [[TMP13]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF2X7_T]] [[TMP14]]
+//
+vint16mf2x7_t test_vlseg7e16_v_i16mf2x7 (const int16_t *base, size_t vl) {
+  return vlseg7e16_v_i16mf2x7(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e16_v_i16mf2x8(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg8.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T:%.*]] undef, <vscale x 2 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP2]], <vscale x 2 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP4]], <vscale x 2 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP6]], <vscale x 2 x i16> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP8]], <vscale x 2 x i16> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP10]], <vscale x 2 x i16> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP12]], <vscale x 2 x i16> [[TMP13]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP14]], <vscale x 2 x i16> [[TMP15]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF2X8_T]] [[TMP16]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e16_v_i16mf2x8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg8.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T:%.*]] undef, <vscale x 2 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP2]], <vscale x 2 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP4]], <vscale x 2 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP6]], <vscale x 2 x i16> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP8]], <vscale x 2 x i16> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP10]], <vscale x 2 x i16> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP12]], <vscale x 2 x i16> [[TMP13]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP14]], <vscale x 2 x i16> [[TMP15]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF2X8_T]] [[TMP16]]
+//
+vint16mf2x8_t test_vlseg8e16_v_i16mf2x8 (const int16_t *base, size_t vl) {
+  return vlseg8e16_v_i16mf2x8(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e16_v_i16m1x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg2.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X2_T:%.*]] undef, <vscale x 4 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X2_T]] [[TMP2]], <vscale x 4 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16M1X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e16_v_i16m1x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg2.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X2_T:%.*]] undef, <vscale x 4 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X2_T]] [[TMP2]], <vscale x 4 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16M1X2_T]] [[TMP4]]
+//
+vint16m1x2_t test_vlseg2e16_v_i16m1x2 (const int16_t *base, size_t vl) {
+  return vlseg2e16_v_i16m1x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e16_v_i16m1x3(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg3.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T:%.*]] undef, <vscale x 4 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP2]], <vscale x 4 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP4]], <vscale x 4 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16M1X3_T]] [[TMP6]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e16_v_i16m1x3(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg3.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T:%.*]] undef, <vscale x 4 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP2]], <vscale x 4 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP4]], <vscale x 4 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16M1X3_T]] [[TMP6]]
+//
+vint16m1x3_t test_vlseg3e16_v_i16m1x3 (const int16_t *base, size_t vl) {
+  return vlseg3e16_v_i16m1x3(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e16_v_i16m1x4(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg4.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T:%.*]] undef, <vscale x 4 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP2]], <vscale x 4 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP4]], <vscale x 4 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP6]], <vscale x 4 x i16> [[TMP7]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16M1X4_T]] [[TMP8]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e16_v_i16m1x4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg4.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T:%.*]] undef, <vscale x 4 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP2]], <vscale x 4 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP4]], <vscale x 4 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP6]], <vscale x 4 x i16> [[TMP7]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16M1X4_T]] [[TMP8]]
+//
+vint16m1x4_t test_vlseg4e16_v_i16m1x4 (const int16_t *base, size_t vl) {
+  return vlseg4e16_v_i16m1x4(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e16_v_i16m1x5(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg5.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T:%.*]] undef, <vscale x 4 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP2]], <vscale x 4 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], <vscale x 4 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP6]], <vscale x 4 x i16> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP8]], <vscale x 4 x i16> [[TMP9]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16M1X5_T]] [[TMP10]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e16_v_i16m1x5(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg5.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T:%.*]] undef, <vscale x 4 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP2]], <vscale x 4 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], <vscale x 4 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP6]], <vscale x 4 x i16> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP8]], <vscale x 4 x i16> [[TMP9]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16M1X5_T]] [[TMP10]]
+//
+vint16m1x5_t test_vlseg5e16_v_i16m1x5 (const int16_t *base, size_t vl) {
+  return vlseg5e16_v_i16m1x5(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e16_v_i16m1x6(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg6.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T:%.*]] undef, <vscale x 4 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP2]], <vscale x 4 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP4]], <vscale x 4 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP6]], <vscale x 4 x i16> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP8]], <vscale x 4 x i16> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP10]], <vscale x 4 x i16> [[TMP11]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16M1X6_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e16_v_i16m1x6(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg6.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T:%.*]] undef, <vscale x 4 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP2]], <vscale x 4 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP4]], <vscale x 4 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP6]], <vscale x 4 x i16> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP8]], <vscale x 4 x i16> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP10]], <vscale x 4 x i16> [[TMP11]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16M1X6_T]] [[TMP12]]
+//
+vint16m1x6_t test_vlseg6e16_v_i16m1x6 (const int16_t *base, size_t vl) {
+  return vlseg6e16_v_i16m1x6(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e16_v_i16m1x7(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg7.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T:%.*]] undef, <vscale x 4 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP2]], <vscale x 4 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP4]], <vscale x 4 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], <vscale x 4 x i16> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP8]], <vscale x 4 x i16> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP10]], <vscale x 4 x i16> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP12]], <vscale x 4 x i16> [[TMP13]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16M1X7_T]] [[TMP14]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e16_v_i16m1x7(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg7.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T:%.*]] undef, <vscale x 4 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP2]], <vscale x 4 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP4]], <vscale x 4 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], <vscale x 4 x i16> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP8]], <vscale x 4 x i16> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP10]], <vscale x 4 x i16> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP12]], <vscale x 4 x i16> [[TMP13]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16M1X7_T]] [[TMP14]]
+//
+vint16m1x7_t test_vlseg7e16_v_i16m1x7 (const int16_t *base, size_t vl) {
+  return vlseg7e16_v_i16m1x7(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e16_v_i16m1x8(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg8.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T:%.*]] undef, <vscale x 4 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP2]], <vscale x 4 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP4]], <vscale x 4 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP6]], <vscale x 4 x i16> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP8]], <vscale x 4 x i16> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP10]], <vscale x 4 x i16> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP12]], <vscale x 4 x i16> [[TMP13]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP14]], <vscale x 4 x i16> [[TMP15]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16M1X8_T]] [[TMP16]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e16_v_i16m1x8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg8.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T:%.*]] undef, <vscale x 4 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP2]], <vscale x 4 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP4]], <vscale x 4 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP6]], <vscale x 4 x i16> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP8]], <vscale x 4 x i16> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP10]], <vscale x 4 x i16> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP12]], <vscale x 4 x i16> [[TMP13]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP14]], <vscale x 4 x i16> [[TMP15]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16M1X8_T]] [[TMP16]]
+//
+vint16m1x8_t test_vlseg8e16_v_i16m1x8 (const int16_t *base, size_t vl) {
+  return vlseg8e16_v_i16m1x8(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e16_v_i16m2x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg2.nxv8i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X2_T:%.*]] undef, <vscale x 8 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X2_T]] [[TMP2]], <vscale x 8 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16M2X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e16_v_i16m2x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg2.nxv8i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X2_T:%.*]] undef, <vscale x 8 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X2_T]] [[TMP2]], <vscale x 8 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16M2X2_T]] [[TMP4]]
+//
+vint16m2x2_t test_vlseg2e16_v_i16m2x2 (const int16_t *base, size_t vl) {
+  return vlseg2e16_v_i16m2x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e16_v_i16m2x3(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg3.nxv8i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T:%.*]] undef, <vscale x 8 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP2]], <vscale x 8 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP4]], <vscale x 8 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16M2X3_T]] [[TMP6]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e16_v_i16m2x3(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg3.nxv8i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T:%.*]] undef, <vscale x 8 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP2]], <vscale x 8 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP4]], <vscale x 8 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16M2X3_T]] [[TMP6]]
+//
+vint16m2x3_t test_vlseg3e16_v_i16m2x3 (const int16_t *base, size_t vl) {
+  return vlseg3e16_v_i16m2x3(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e16_v_i16m2x4(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg4.nxv8i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T:%.*]] undef, <vscale x 8 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP2]], <vscale x 8 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP4]], <vscale x 8 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP6]], <vscale x 8 x i16> [[TMP7]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16M2X4_T]] [[TMP8]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e16_v_i16m2x4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg4.nxv8i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T:%.*]] undef, <vscale x 8 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP2]], <vscale x 8 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP4]], <vscale x 8 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP6]], <vscale x 8 x i16> [[TMP7]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16M2X4_T]] [[TMP8]]
+//
+vint16m2x4_t test_vlseg4e16_v_i16m2x4 (const int16_t *base, size_t vl) {
+  return vlseg4e16_v_i16m2x4(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e16_v_i16m4x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 16 x i16>, <vscale x 16 x i16> } @llvm.riscv.vlseg2.nxv16i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M4X2_T:%.*]] undef, <vscale x 16 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M4X2_T]] [[TMP2]], <vscale x 16 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16M4X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e16_v_i16m4x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 16 x i16>, <vscale x 16 x i16> } @llvm.riscv.vlseg2.nxv16i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M4X2_T:%.*]] undef, <vscale x 16 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M4X2_T]] [[TMP2]], <vscale x 16 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16M4X2_T]] [[TMP4]]
+//
+vint16m4x2_t test_vlseg2e16_v_i16m4x2 (const int16_t *base, size_t vl) {
+  return vlseg2e16_v_i16m4x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_i32mf2x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg2.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X2_T:%.*]] undef, <vscale x 1 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X2_T]] [[TMP2]], <vscale x 1 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32MF2X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_i32mf2x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg2.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X2_T:%.*]] undef, <vscale x 1 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X2_T]] [[TMP2]], <vscale x 1 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32MF2X2_T]] [[TMP4]]
+//
+vint32mf2x2_t test_vlseg2e32_v_i32mf2x2 (const int32_t *base, size_t vl) {
+  return vlseg2e32_v_i32mf2x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e32_v_i32mf2x3(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg3.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T:%.*]] undef, <vscale x 1 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP2]], <vscale x 1 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP4]], <vscale x 1 x i32> [[TMP5]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32MF2X3_T]] [[TMP6]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e32_v_i32mf2x3(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg3.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T:%.*]] undef, <vscale x 1 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP2]], <vscale x 1 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP4]], <vscale x 1 x i32> [[TMP5]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32MF2X3_T]] [[TMP6]]
+//
+vint32mf2x3_t test_vlseg3e32_v_i32mf2x3 (const int32_t *base, size_t vl) {
+  return vlseg3e32_v_i32mf2x3(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e32_v_i32mf2x4(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg4.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T:%.*]] undef, <vscale x 1 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP2]], <vscale x 1 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP4]], <vscale x 1 x i32> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP6]], <vscale x 1 x i32> [[TMP7]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32MF2X4_T]] [[TMP8]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e32_v_i32mf2x4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg4.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T:%.*]] undef, <vscale x 1 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP2]], <vscale x 1 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP4]], <vscale x 1 x i32> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP6]], <vscale x 1 x i32> [[TMP7]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32MF2X4_T]] [[TMP8]]
+//
+vint32mf2x4_t test_vlseg4e32_v_i32mf2x4 (const int32_t *base, size_t vl) {
+  return vlseg4e32_v_i32mf2x4(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e32_v_i32mf2x5(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg5.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T:%.*]] undef, <vscale x 1 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP2]], <vscale x 1 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], <vscale x 1 x i32> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP6]], <vscale x 1 x i32> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP8]], <vscale x 1 x i32> [[TMP9]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32MF2X5_T]] [[TMP10]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e32_v_i32mf2x5(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg5.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T:%.*]] undef, <vscale x 1 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP2]], <vscale x 1 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], <vscale x 1 x i32> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP6]], <vscale x 1 x i32> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP8]], <vscale x 1 x i32> [[TMP9]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32MF2X5_T]] [[TMP10]]
+//
+vint32mf2x5_t test_vlseg5e32_v_i32mf2x5 (const int32_t *base, size_t vl) {
+  return vlseg5e32_v_i32mf2x5(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e32_v_i32mf2x6(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg6.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T:%.*]] undef, <vscale x 1 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP2]], <vscale x 1 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP4]], <vscale x 1 x i32> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP6]], <vscale x 1 x i32> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP8]], <vscale x 1 x i32> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP10]], <vscale x 1 x i32> [[TMP11]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32MF2X6_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e32_v_i32mf2x6(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg6.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T:%.*]] undef, <vscale x 1 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP2]], <vscale x 1 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP4]], <vscale x 1 x i32> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP6]], <vscale x 1 x i32> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP8]], <vscale x 1 x i32> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP10]], <vscale x 1 x i32> [[TMP11]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32MF2X6_T]] [[TMP12]]
+//
+vint32mf2x6_t test_vlseg6e32_v_i32mf2x6 (const int32_t *base, size_t vl) {
+  return vlseg6e32_v_i32mf2x6(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e32_v_i32mf2x7(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg7.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T:%.*]] undef, <vscale x 1 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP2]], <vscale x 1 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP4]], <vscale x 1 x i32> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], <vscale x 1 x i32> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP8]], <vscale x 1 x i32> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP10]], <vscale x 1 x i32> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP12]], <vscale x 1 x i32> [[TMP13]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32MF2X7_T]] [[TMP14]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e32_v_i32mf2x7(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg7.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T:%.*]] undef, <vscale x 1 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP2]], <vscale x 1 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP4]], <vscale x 1 x i32> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], <vscale x 1 x i32> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP8]], <vscale x 1 x i32> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP10]], <vscale x 1 x i32> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP12]], <vscale x 1 x i32> [[TMP13]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32MF2X7_T]] [[TMP14]]
+//
+vint32mf2x7_t test_vlseg7e32_v_i32mf2x7 (const int32_t *base, size_t vl) {
+  return vlseg7e32_v_i32mf2x7(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e32_v_i32mf2x8(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg8.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T:%.*]] undef, <vscale x 1 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP2]], <vscale x 1 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP4]], <vscale x 1 x i32> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP6]], <vscale x 1 x i32> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP8]], <vscale x 1 x i32> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP10]], <vscale x 1 x i32> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP12]], <vscale x 1 x i32> [[TMP13]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP14]], <vscale x 1 x i32> [[TMP15]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32MF2X8_T]] [[TMP16]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e32_v_i32mf2x8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg8.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T:%.*]] undef, <vscale x 1 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP2]], <vscale x 1 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP4]], <vscale x 1 x i32> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP6]], <vscale x 1 x i32> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP8]], <vscale x 1 x i32> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP10]], <vscale x 1 x i32> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP12]], <vscale x 1 x i32> [[TMP13]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP14]], <vscale x 1 x i32> [[TMP15]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32MF2X8_T]] [[TMP16]]
+//
+vint32mf2x8_t test_vlseg8e32_v_i32mf2x8 (const int32_t *base, size_t vl) {
+  return vlseg8e32_v_i32mf2x8(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_i32m1x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg2.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X2_T:%.*]] undef, <vscale x 2 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X2_T]] [[TMP2]], <vscale x 2 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32M1X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_i32m1x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg2.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X2_T:%.*]] undef, <vscale x 2 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X2_T]] [[TMP2]], <vscale x 2 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32M1X2_T]] [[TMP4]]
+//
+vint32m1x2_t test_vlseg2e32_v_i32m1x2 (const int32_t *base, size_t vl) {
+  return vlseg2e32_v_i32m1x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e32_v_i32m1x3(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg3.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T:%.*]] undef, <vscale x 2 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP2]], <vscale x 2 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP4]], <vscale x 2 x i32> [[TMP5]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32M1X3_T]] [[TMP6]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e32_v_i32m1x3(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg3.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T:%.*]] undef, <vscale x 2 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP2]], <vscale x 2 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP4]], <vscale x 2 x i32> [[TMP5]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32M1X3_T]] [[TMP6]]
+//
+vint32m1x3_t test_vlseg3e32_v_i32m1x3 (const int32_t *base, size_t vl) {
+  return vlseg3e32_v_i32m1x3(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e32_v_i32m1x4(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg4.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T:%.*]] undef, <vscale x 2 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP2]], <vscale x 2 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP4]], <vscale x 2 x i32> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP6]], <vscale x 2 x i32> [[TMP7]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32M1X4_T]] [[TMP8]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e32_v_i32m1x4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg4.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T:%.*]] undef, <vscale x 2 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP2]], <vscale x 2 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP4]], <vscale x 2 x i32> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP6]], <vscale x 2 x i32> [[TMP7]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32M1X4_T]] [[TMP8]]
+//
+vint32m1x4_t test_vlseg4e32_v_i32m1x4 (const int32_t *base, size_t vl) {
+  return vlseg4e32_v_i32m1x4(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e32_v_i32m1x5(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg5.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T:%.*]] undef, <vscale x 2 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP2]], <vscale x 2 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], <vscale x 2 x i32> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP6]], <vscale x 2 x i32> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP8]], <vscale x 2 x i32> [[TMP9]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32M1X5_T]] [[TMP10]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e32_v_i32m1x5(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg5.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T:%.*]] undef, <vscale x 2 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP2]], <vscale x 2 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], <vscale x 2 x i32> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP6]], <vscale x 2 x i32> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP8]], <vscale x 2 x i32> [[TMP9]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32M1X5_T]] [[TMP10]]
+//
+vint32m1x5_t test_vlseg5e32_v_i32m1x5 (const int32_t *base, size_t vl) {
+  return vlseg5e32_v_i32m1x5(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e32_v_i32m1x6(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg6.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T:%.*]] undef, <vscale x 2 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP2]], <vscale x 2 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP4]], <vscale x 2 x i32> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP6]], <vscale x 2 x i32> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP8]], <vscale x 2 x i32> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP10]], <vscale x 2 x i32> [[TMP11]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32M1X6_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e32_v_i32m1x6(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg6.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T:%.*]] undef, <vscale x 2 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP2]], <vscale x 2 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP4]], <vscale x 2 x i32> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP6]], <vscale x 2 x i32> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP8]], <vscale x 2 x i32> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP10]], <vscale x 2 x i32> [[TMP11]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32M1X6_T]] [[TMP12]]
+//
+vint32m1x6_t test_vlseg6e32_v_i32m1x6 (const int32_t *base, size_t vl) {
+  return vlseg6e32_v_i32m1x6(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e32_v_i32m1x7(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg7.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T:%.*]] undef, <vscale x 2 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP2]], <vscale x 2 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP4]], <vscale x 2 x i32> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], <vscale x 2 x i32> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP8]], <vscale x 2 x i32> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP10]], <vscale x 2 x i32> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP12]], <vscale x 2 x i32> [[TMP13]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32M1X7_T]] [[TMP14]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e32_v_i32m1x7(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg7.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T:%.*]] undef, <vscale x 2 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP2]], <vscale x 2 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP4]], <vscale x 2 x i32> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], <vscale x 2 x i32> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP8]], <vscale x 2 x i32> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP10]], <vscale x 2 x i32> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP12]], <vscale x 2 x i32> [[TMP13]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32M1X7_T]] [[TMP14]]
+//
+vint32m1x7_t test_vlseg7e32_v_i32m1x7 (const int32_t *base, size_t vl) {
+  return vlseg7e32_v_i32m1x7(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e32_v_i32m1x8(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg8.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T:%.*]] undef, <vscale x 2 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP2]], <vscale x 2 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP4]], <vscale x 2 x i32> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP6]], <vscale x 2 x i32> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP8]], <vscale x 2 x i32> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP10]], <vscale x 2 x i32> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP12]], <vscale x 2 x i32> [[TMP13]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP14]], <vscale x 2 x i32> [[TMP15]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32M1X8_T]] [[TMP16]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e32_v_i32m1x8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg8.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T:%.*]] undef, <vscale x 2 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP2]], <vscale x 2 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP4]], <vscale x 2 x i32> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP6]], <vscale x 2 x i32> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP8]], <vscale x 2 x i32> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP10]], <vscale x 2 x i32> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP12]], <vscale x 2 x i32> [[TMP13]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP14]], <vscale x 2 x i32> [[TMP15]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32M1X8_T]] [[TMP16]]
+//
+vint32m1x8_t test_vlseg8e32_v_i32m1x8 (const int32_t *base, size_t vl) {
+  return vlseg8e32_v_i32m1x8(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_i32m2x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg2.nxv4i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X2_T:%.*]] undef, <vscale x 4 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X2_T]] [[TMP2]], <vscale x 4 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32M2X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_i32m2x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg2.nxv4i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X2_T:%.*]] undef, <vscale x 4 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X2_T]] [[TMP2]], <vscale x 4 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32M2X2_T]] [[TMP4]]
+//
+vint32m2x2_t test_vlseg2e32_v_i32m2x2 (const int32_t *base, size_t vl) {
+  return vlseg2e32_v_i32m2x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e32_v_i32m2x3(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg3.nxv4i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T:%.*]] undef, <vscale x 4 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP2]], <vscale x 4 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP4]], <vscale x 4 x i32> [[TMP5]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32M2X3_T]] [[TMP6]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e32_v_i32m2x3(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg3.nxv4i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T:%.*]] undef, <vscale x 4 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP2]], <vscale x 4 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP4]], <vscale x 4 x i32> [[TMP5]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32M2X3_T]] [[TMP6]]
+//
+vint32m2x3_t test_vlseg3e32_v_i32m2x3 (const int32_t *base, size_t vl) {
+  return vlseg3e32_v_i32m2x3(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e32_v_i32m2x4(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg4.nxv4i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T:%.*]] undef, <vscale x 4 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP2]], <vscale x 4 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP4]], <vscale x 4 x i32> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP6]], <vscale x 4 x i32> [[TMP7]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32M2X4_T]] [[TMP8]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e32_v_i32m2x4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg4.nxv4i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T:%.*]] undef, <vscale x 4 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP2]], <vscale x 4 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP4]], <vscale x 4 x i32> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP6]], <vscale x 4 x i32> [[TMP7]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32M2X4_T]] [[TMP8]]
+//
+vint32m2x4_t test_vlseg4e32_v_i32m2x4 (const int32_t *base, size_t vl) {
+  return vlseg4e32_v_i32m2x4(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_i32m4x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i32>, <vscale x 8 x i32> } @llvm.riscv.vlseg2.nxv8i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M4X2_T:%.*]] undef, <vscale x 8 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M4X2_T]] [[TMP2]], <vscale x 8 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32M4X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_i32m4x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i32>, <vscale x 8 x i32> } @llvm.riscv.vlseg2.nxv8i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M4X2_T:%.*]] undef, <vscale x 8 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M4X2_T]] [[TMP2]], <vscale x 8 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32M4X2_T]] [[TMP4]]
+//
+vint32m4x2_t test_vlseg2e32_v_i32m4x2 (const int32_t *base, size_t vl) {
+  return vlseg2e32_v_i32m4x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e64_v_i64m1x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg2.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X2_T:%.*]] undef, <vscale x 1 x i64> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X2_T]] [[TMP2]], <vscale x 1 x i64> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT64M1X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e64_v_i64m1x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg2.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X2_T:%.*]] undef, <vscale x 1 x i64> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X2_T]] [[TMP2]], <vscale x 1 x i64> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT64M1X2_T]] [[TMP4]]
+//
+vint64m1x2_t test_vlseg2e64_v_i64m1x2 (const int64_t *base, size_t vl) {
+  return vlseg2e64_v_i64m1x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e64_v_i64m1x3(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg3.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T:%.*]] undef, <vscale x 1 x i64> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP2]], <vscale x 1 x i64> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP4]], <vscale x 1 x i64> [[TMP5]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT64M1X3_T]] [[TMP6]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e64_v_i64m1x3(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg3.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T:%.*]] undef, <vscale x 1 x i64> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP2]], <vscale x 1 x i64> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP4]], <vscale x 1 x i64> [[TMP5]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT64M1X3_T]] [[TMP6]]
+//
+vint64m1x3_t test_vlseg3e64_v_i64m1x3 (const int64_t *base, size_t vl) {
+  return vlseg3e64_v_i64m1x3(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e64_v_i64m1x4(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg4.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T:%.*]] undef, <vscale x 1 x i64> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP2]], <vscale x 1 x i64> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP4]], <vscale x 1 x i64> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP6]], <vscale x 1 x i64> [[TMP7]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT64M1X4_T]] [[TMP8]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e64_v_i64m1x4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg4.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T:%.*]] undef, <vscale x 1 x i64> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP2]], <vscale x 1 x i64> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP4]], <vscale x 1 x i64> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP6]], <vscale x 1 x i64> [[TMP7]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT64M1X4_T]] [[TMP8]]
+//
+vint64m1x4_t test_vlseg4e64_v_i64m1x4 (const int64_t *base, size_t vl) {
+  return vlseg4e64_v_i64m1x4(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e64_v_i64m1x5(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg5.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T:%.*]] undef, <vscale x 1 x i64> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP2]], <vscale x 1 x i64> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], <vscale x 1 x i64> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP6]], <vscale x 1 x i64> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP8]], <vscale x 1 x i64> [[TMP9]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT64M1X5_T]] [[TMP10]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e64_v_i64m1x5(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg5.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T:%.*]] undef, <vscale x 1 x i64> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP2]], <vscale x 1 x i64> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], <vscale x 1 x i64> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP6]], <vscale x 1 x i64> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP8]], <vscale x 1 x i64> [[TMP9]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT64M1X5_T]] [[TMP10]]
+//
+vint64m1x5_t test_vlseg5e64_v_i64m1x5 (const int64_t *base, size_t vl) {
+  return vlseg5e64_v_i64m1x5(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e64_v_i64m1x6(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg6.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T:%.*]] undef, <vscale x 1 x i64> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP2]], <vscale x 1 x i64> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP4]], <vscale x 1 x i64> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP6]], <vscale x 1 x i64> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP8]], <vscale x 1 x i64> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP10]], <vscale x 1 x i64> [[TMP11]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT64M1X6_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e64_v_i64m1x6(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg6.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T:%.*]] undef, <vscale x 1 x i64> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP2]], <vscale x 1 x i64> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP4]], <vscale x 1 x i64> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP6]], <vscale x 1 x i64> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP8]], <vscale x 1 x i64> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP10]], <vscale x 1 x i64> [[TMP11]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT64M1X6_T]] [[TMP12]]
+//
+vint64m1x6_t test_vlseg6e64_v_i64m1x6 (const int64_t *base, size_t vl) {
+  return vlseg6e64_v_i64m1x6(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e64_v_i64m1x7(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg7.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T:%.*]] undef, <vscale x 1 x i64> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP2]], <vscale x 1 x i64> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP4]], <vscale x 1 x i64> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], <vscale x 1 x i64> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP8]], <vscale x 1 x i64> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP10]], <vscale x 1 x i64> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP12]], <vscale x 1 x i64> [[TMP13]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT64M1X7_T]] [[TMP14]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e64_v_i64m1x7(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg7.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T:%.*]] undef, <vscale x 1 x i64> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP2]], <vscale x 1 x i64> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP4]], <vscale x 1 x i64> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], <vscale x 1 x i64> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP8]], <vscale x 1 x i64> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP10]], <vscale x 1 x i64> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP12]], <vscale x 1 x i64> [[TMP13]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT64M1X7_T]] [[TMP14]]
+//
+vint64m1x7_t test_vlseg7e64_v_i64m1x7 (const int64_t *base, size_t vl) {
+  return vlseg7e64_v_i64m1x7(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e64_v_i64m1x8(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg8.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T:%.*]] undef, <vscale x 1 x i64> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP2]], <vscale x 1 x i64> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP4]], <vscale x 1 x i64> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP6]], <vscale x 1 x i64> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP8]], <vscale x 1 x i64> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP10]], <vscale x 1 x i64> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP12]], <vscale x 1 x i64> [[TMP13]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP14]], <vscale x 1 x i64> [[TMP15]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT64M1X8_T]] [[TMP16]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e64_v_i64m1x8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg8.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T:%.*]] undef, <vscale x 1 x i64> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP2]], <vscale x 1 x i64> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP4]], <vscale x 1 x i64> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP6]], <vscale x 1 x i64> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP8]], <vscale x 1 x i64> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP10]], <vscale x 1 x i64> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP12]], <vscale x 1 x i64> [[TMP13]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP14]], <vscale x 1 x i64> [[TMP15]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT64M1X8_T]] [[TMP16]]
+//
+vint64m1x8_t test_vlseg8e64_v_i64m1x8 (const int64_t *base, size_t vl) {
+  return vlseg8e64_v_i64m1x8(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e64_v_i64m2x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg2.nxv2i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X2_T:%.*]] undef, <vscale x 2 x i64> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X2_T]] [[TMP2]], <vscale x 2 x i64> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT64M2X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e64_v_i64m2x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg2.nxv2i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X2_T:%.*]] undef, <vscale x 2 x i64> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X2_T]] [[TMP2]], <vscale x 2 x i64> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT64M2X2_T]] [[TMP4]]
+//
+vint64m2x2_t test_vlseg2e64_v_i64m2x2 (const int64_t *base, size_t vl) {
+  return vlseg2e64_v_i64m2x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e64_v_i64m2x3(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg3.nxv2i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T:%.*]] undef, <vscale x 2 x i64> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP2]], <vscale x 2 x i64> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP4]], <vscale x 2 x i64> [[TMP5]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT64M2X3_T]] [[TMP6]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e64_v_i64m2x3(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg3.nxv2i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T:%.*]] undef, <vscale x 2 x i64> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP2]], <vscale x 2 x i64> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP4]], <vscale x 2 x i64> [[TMP5]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT64M2X3_T]] [[TMP6]]
+//
+vint64m2x3_t test_vlseg3e64_v_i64m2x3 (const int64_t *base, size_t vl) {
+  return vlseg3e64_v_i64m2x3(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e64_v_i64m2x4(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg4.nxv2i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T:%.*]] undef, <vscale x 2 x i64> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP2]], <vscale x 2 x i64> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP4]], <vscale x 2 x i64> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP6]], <vscale x 2 x i64> [[TMP7]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT64M2X4_T]] [[TMP8]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e64_v_i64m2x4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg4.nxv2i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T:%.*]] undef, <vscale x 2 x i64> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP2]], <vscale x 2 x i64> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP4]], <vscale x 2 x i64> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP6]], <vscale x 2 x i64> [[TMP7]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT64M2X4_T]] [[TMP8]]
+//
+vint64m2x4_t test_vlseg4e64_v_i64m2x4 (const int64_t *base, size_t vl) {
+  return vlseg4e64_v_i64m2x4(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e64_v_i64m4x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i64>, <vscale x 4 x i64> } @llvm.riscv.vlseg2.nxv4i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M4X2_T:%.*]] undef, <vscale x 4 x i64> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M4X2_T]] [[TMP2]], <vscale x 4 x i64> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT64M4X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e64_v_i64m4x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i64>, <vscale x 4 x i64> } @llvm.riscv.vlseg2.nxv4i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M4X2_T:%.*]] undef, <vscale x 4 x i64> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M4X2_T]] [[TMP2]], <vscale x 4 x i64> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT64M4X2_T]] [[TMP4]]
+//
+vint64m4x2_t test_vlseg2e64_v_i64m4x2 (const int64_t *base, size_t vl) {
+  return vlseg2e64_v_i64m4x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_u8mf8x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg2.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X2_T:%.*]] undef, <vscale x 1 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP2]], <vscale x 1 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_u8mf8x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg2.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X2_T:%.*]] undef, <vscale x 1 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP2]], <vscale x 1 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP4]]
+//
+vuint8mf8x2_t test_vlseg2e8_v_u8mf8x2 (const uint8_t *base, size_t vl) {
+  return vlseg2e8_v_u8mf8x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e8_v_u8mf8x3(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg3.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T:%.*]] undef, <vscale x 1 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP2]], <vscale x 1 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP4]], <vscale x 1 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP6]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e8_v_u8mf8x3(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg3.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T:%.*]] undef, <vscale x 1 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP2]], <vscale x 1 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP4]], <vscale x 1 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP6]]
+//
+vuint8mf8x3_t test_vlseg3e8_v_u8mf8x3 (const uint8_t *base, size_t vl) {
+  return vlseg3e8_v_u8mf8x3(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e8_v_u8mf8x4(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg4.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T:%.*]] undef, <vscale x 1 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP2]], <vscale x 1 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP4]], <vscale x 1 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP6]], <vscale x 1 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP8]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e8_v_u8mf8x4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg4.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T:%.*]] undef, <vscale x 1 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP2]], <vscale x 1 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP4]], <vscale x 1 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP6]], <vscale x 1 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP8]]
+//
+vuint8mf8x4_t test_vlseg4e8_v_u8mf8x4 (const uint8_t *base, size_t vl) {
+  return vlseg4e8_v_u8mf8x4(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e8_v_u8mf8x5(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg5.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T:%.*]] undef, <vscale x 1 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP2]], <vscale x 1 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], <vscale x 1 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP6]], <vscale x 1 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP8]], <vscale x 1 x i8> [[TMP9]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP10]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e8_v_u8mf8x5(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg5.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T:%.*]] undef, <vscale x 1 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP2]], <vscale x 1 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], <vscale x 1 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP6]], <vscale x 1 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP8]], <vscale x 1 x i8> [[TMP9]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP10]]
+//
+vuint8mf8x5_t test_vlseg5e8_v_u8mf8x5 (const uint8_t *base, size_t vl) {
+  return vlseg5e8_v_u8mf8x5(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e8_v_u8mf8x6(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg6.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T:%.*]] undef, <vscale x 1 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP2]], <vscale x 1 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP4]], <vscale x 1 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP6]], <vscale x 1 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP8]], <vscale x 1 x i8> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP10]], <vscale x 1 x i8> [[TMP11]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e8_v_u8mf8x6(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg6.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T:%.*]] undef, <vscale x 1 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP2]], <vscale x 1 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP4]], <vscale x 1 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP6]], <vscale x 1 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP8]], <vscale x 1 x i8> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP10]], <vscale x 1 x i8> [[TMP11]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP12]]
+//
+vuint8mf8x6_t test_vlseg6e8_v_u8mf8x6 (const uint8_t *base, size_t vl) {
+  return vlseg6e8_v_u8mf8x6(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e8_v_u8mf8x7(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg7.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T:%.*]] undef, <vscale x 1 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP2]], <vscale x 1 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP4]], <vscale x 1 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], <vscale x 1 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP8]], <vscale x 1 x i8> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP10]], <vscale x 1 x i8> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP12]], <vscale x 1 x i8> [[TMP13]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP14]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e8_v_u8mf8x7(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg7.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T:%.*]] undef, <vscale x 1 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP2]], <vscale x 1 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP4]], <vscale x 1 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], <vscale x 1 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP8]], <vscale x 1 x i8> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP10]], <vscale x 1 x i8> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP12]], <vscale x 1 x i8> [[TMP13]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP14]]
+//
+vuint8mf8x7_t test_vlseg7e8_v_u8mf8x7 (const uint8_t *base, size_t vl) {
+  return vlseg7e8_v_u8mf8x7(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e8_v_u8mf8x8(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg8.nxv1i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T:%.*]] undef, <vscale x 1 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP2]], <vscale x 1 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP4]], <vscale x 1 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP6]], <vscale x 1 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP8]], <vscale x 1 x i8> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP10]], <vscale x 1 x i8> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP12]], <vscale x 1 x i8> [[TMP13]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP14]], <vscale x 1 x i8> [[TMP15]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP16]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e8_v_u8mf8x8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg8.nxv1i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T:%.*]] undef, <vscale x 1 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP2]], <vscale x 1 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP4]], <vscale x 1 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP6]], <vscale x 1 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP8]], <vscale x 1 x i8> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP10]], <vscale x 1 x i8> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP12]], <vscale x 1 x i8> [[TMP13]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP0]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP14]], <vscale x 1 x i8> [[TMP15]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP16]]
+//
+vuint8mf8x8_t test_vlseg8e8_v_u8mf8x8 (const uint8_t *base, size_t vl) {
+  return vlseg8e8_v_u8mf8x8(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_u8mf4x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg2.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X2_T:%.*]] undef, <vscale x 2 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP2]], <vscale x 2 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_u8mf4x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg2.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X2_T:%.*]] undef, <vscale x 2 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP2]], <vscale x 2 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP4]]
+//
+vuint8mf4x2_t test_vlseg2e8_v_u8mf4x2 (const uint8_t *base, size_t vl) {
+  return vlseg2e8_v_u8mf4x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e8_v_u8mf4x3(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg3.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T:%.*]] undef, <vscale x 2 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP2]], <vscale x 2 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP4]], <vscale x 2 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP6]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e8_v_u8mf4x3(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg3.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T:%.*]] undef, <vscale x 2 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP2]], <vscale x 2 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP4]], <vscale x 2 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP6]]
+//
+vuint8mf4x3_t test_vlseg3e8_v_u8mf4x3 (const uint8_t *base, size_t vl) {
+  return vlseg3e8_v_u8mf4x3(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e8_v_u8mf4x4(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg4.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T:%.*]] undef, <vscale x 2 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP2]], <vscale x 2 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP4]], <vscale x 2 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP6]], <vscale x 2 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP8]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e8_v_u8mf4x4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg4.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T:%.*]] undef, <vscale x 2 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP2]], <vscale x 2 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP4]], <vscale x 2 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP6]], <vscale x 2 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP8]]
+//
+vuint8mf4x4_t test_vlseg4e8_v_u8mf4x4 (const uint8_t *base, size_t vl) {
+  return vlseg4e8_v_u8mf4x4(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e8_v_u8mf4x5(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg5.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T:%.*]] undef, <vscale x 2 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP2]], <vscale x 2 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], <vscale x 2 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP6]], <vscale x 2 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP8]], <vscale x 2 x i8> [[TMP9]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP10]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e8_v_u8mf4x5(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg5.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T:%.*]] undef, <vscale x 2 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP2]], <vscale x 2 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], <vscale x 2 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP6]], <vscale x 2 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP8]], <vscale x 2 x i8> [[TMP9]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP10]]
+//
+vuint8mf4x5_t test_vlseg5e8_v_u8mf4x5 (const uint8_t *base, size_t vl) {
+  return vlseg5e8_v_u8mf4x5(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e8_v_u8mf4x6(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg6.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T:%.*]] undef, <vscale x 2 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP2]], <vscale x 2 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP4]], <vscale x 2 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP6]], <vscale x 2 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP8]], <vscale x 2 x i8> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP10]], <vscale x 2 x i8> [[TMP11]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e8_v_u8mf4x6(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg6.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T:%.*]] undef, <vscale x 2 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP2]], <vscale x 2 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP4]], <vscale x 2 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP6]], <vscale x 2 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP8]], <vscale x 2 x i8> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP10]], <vscale x 2 x i8> [[TMP11]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP12]]
+//
+vuint8mf4x6_t test_vlseg6e8_v_u8mf4x6 (const uint8_t *base, size_t vl) {
+  return vlseg6e8_v_u8mf4x6(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e8_v_u8mf4x7(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg7.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T:%.*]] undef, <vscale x 2 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP2]], <vscale x 2 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP4]], <vscale x 2 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], <vscale x 2 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP8]], <vscale x 2 x i8> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP10]], <vscale x 2 x i8> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP12]], <vscale x 2 x i8> [[TMP13]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP14]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e8_v_u8mf4x7(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg7.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T:%.*]] undef, <vscale x 2 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP2]], <vscale x 2 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP4]], <vscale x 2 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], <vscale x 2 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP8]], <vscale x 2 x i8> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP10]], <vscale x 2 x i8> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP12]], <vscale x 2 x i8> [[TMP13]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP14]]
+//
+vuint8mf4x7_t test_vlseg7e8_v_u8mf4x7 (const uint8_t *base, size_t vl) {
+  return vlseg7e8_v_u8mf4x7(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e8_v_u8mf4x8(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg8.nxv2i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T:%.*]] undef, <vscale x 2 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP2]], <vscale x 2 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP4]], <vscale x 2 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP6]], <vscale x 2 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP8]], <vscale x 2 x i8> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP10]], <vscale x 2 x i8> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP12]], <vscale x 2 x i8> [[TMP13]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP14]], <vscale x 2 x i8> [[TMP15]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP16]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e8_v_u8mf4x8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg8.nxv2i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T:%.*]] undef, <vscale x 2 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP2]], <vscale x 2 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP4]], <vscale x 2 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP6]], <vscale x 2 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP8]], <vscale x 2 x i8> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP10]], <vscale x 2 x i8> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP12]], <vscale x 2 x i8> [[TMP13]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP0]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP14]], <vscale x 2 x i8> [[TMP15]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP16]]
+//
+vuint8mf4x8_t test_vlseg8e8_v_u8mf4x8 (const uint8_t *base, size_t vl) {
+  return vlseg8e8_v_u8mf4x8(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_u8mf2x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg2.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X2_T:%.*]] undef, <vscale x 4 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP2]], <vscale x 4 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_u8mf2x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg2.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X2_T:%.*]] undef, <vscale x 4 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP2]], <vscale x 4 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP4]]
+//
+vuint8mf2x2_t test_vlseg2e8_v_u8mf2x2 (const uint8_t *base, size_t vl) {
+  return vlseg2e8_v_u8mf2x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e8_v_u8mf2x3(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg3.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T:%.*]] undef, <vscale x 4 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP2]], <vscale x 4 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP4]], <vscale x 4 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP6]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e8_v_u8mf2x3(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg3.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T:%.*]] undef, <vscale x 4 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP2]], <vscale x 4 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP4]], <vscale x 4 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP6]]
+//
+vuint8mf2x3_t test_vlseg3e8_v_u8mf2x3 (const uint8_t *base, size_t vl) {
+  return vlseg3e8_v_u8mf2x3(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e8_v_u8mf2x4(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg4.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T:%.*]] undef, <vscale x 4 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP2]], <vscale x 4 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP4]], <vscale x 4 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP6]], <vscale x 4 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP8]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e8_v_u8mf2x4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg4.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T:%.*]] undef, <vscale x 4 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP2]], <vscale x 4 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP4]], <vscale x 4 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP6]], <vscale x 4 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP8]]
+//
+vuint8mf2x4_t test_vlseg4e8_v_u8mf2x4 (const uint8_t *base, size_t vl) {
+  return vlseg4e8_v_u8mf2x4(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e8_v_u8mf2x5(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg5.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T:%.*]] undef, <vscale x 4 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP2]], <vscale x 4 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], <vscale x 4 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP6]], <vscale x 4 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP8]], <vscale x 4 x i8> [[TMP9]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP10]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e8_v_u8mf2x5(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg5.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T:%.*]] undef, <vscale x 4 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP2]], <vscale x 4 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], <vscale x 4 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP6]], <vscale x 4 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP8]], <vscale x 4 x i8> [[TMP9]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP10]]
+//
+vuint8mf2x5_t test_vlseg5e8_v_u8mf2x5 (const uint8_t *base, size_t vl) {
+  return vlseg5e8_v_u8mf2x5(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e8_v_u8mf2x6(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg6.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T:%.*]] undef, <vscale x 4 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP2]], <vscale x 4 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP4]], <vscale x 4 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP6]], <vscale x 4 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP8]], <vscale x 4 x i8> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP10]], <vscale x 4 x i8> [[TMP11]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e8_v_u8mf2x6(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg6.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T:%.*]] undef, <vscale x 4 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP2]], <vscale x 4 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP4]], <vscale x 4 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP6]], <vscale x 4 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP8]], <vscale x 4 x i8> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP10]], <vscale x 4 x i8> [[TMP11]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP12]]
+//
+vuint8mf2x6_t test_vlseg6e8_v_u8mf2x6 (const uint8_t *base, size_t vl) {
+  return vlseg6e8_v_u8mf2x6(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e8_v_u8mf2x7(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg7.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T:%.*]] undef, <vscale x 4 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP2]], <vscale x 4 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP4]], <vscale x 4 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], <vscale x 4 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP8]], <vscale x 4 x i8> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP10]], <vscale x 4 x i8> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP12]], <vscale x 4 x i8> [[TMP13]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP14]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e8_v_u8mf2x7(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg7.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T:%.*]] undef, <vscale x 4 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP2]], <vscale x 4 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP4]], <vscale x 4 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], <vscale x 4 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP8]], <vscale x 4 x i8> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP10]], <vscale x 4 x i8> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP12]], <vscale x 4 x i8> [[TMP13]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP14]]
+//
+vuint8mf2x7_t test_vlseg7e8_v_u8mf2x7 (const uint8_t *base, size_t vl) {
+  return vlseg7e8_v_u8mf2x7(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e8_v_u8mf2x8(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg8.nxv4i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T:%.*]] undef, <vscale x 4 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP2]], <vscale x 4 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP4]], <vscale x 4 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP6]], <vscale x 4 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP8]], <vscale x 4 x i8> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP10]], <vscale x 4 x i8> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP12]], <vscale x 4 x i8> [[TMP13]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP14]], <vscale x 4 x i8> [[TMP15]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP16]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e8_v_u8mf2x8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg8.nxv4i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T:%.*]] undef, <vscale x 4 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP2]], <vscale x 4 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP4]], <vscale x 4 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP6]], <vscale x 4 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP8]], <vscale x 4 x i8> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP10]], <vscale x 4 x i8> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP12]], <vscale x 4 x i8> [[TMP13]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP0]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP14]], <vscale x 4 x i8> [[TMP15]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP16]]
+//
+vuint8mf2x8_t test_vlseg8e8_v_u8mf2x8 (const uint8_t *base, size_t vl) {
+  return vlseg8e8_v_u8mf2x8(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_u8m1x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg2.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X2_T:%.*]] undef, <vscale x 8 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X2_T]] [[TMP2]], <vscale x 8 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8M1X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_u8m1x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg2.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X2_T:%.*]] undef, <vscale x 8 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X2_T]] [[TMP2]], <vscale x 8 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8M1X2_T]] [[TMP4]]
+//
+vuint8m1x2_t test_vlseg2e8_v_u8m1x2 (const uint8_t *base, size_t vl) {
+  return vlseg2e8_v_u8m1x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e8_v_u8m1x3(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg3.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T:%.*]] undef, <vscale x 8 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP2]], <vscale x 8 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP4]], <vscale x 8 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8M1X3_T]] [[TMP6]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e8_v_u8m1x3(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg3.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T:%.*]] undef, <vscale x 8 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP2]], <vscale x 8 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP4]], <vscale x 8 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8M1X3_T]] [[TMP6]]
+//
+vuint8m1x3_t test_vlseg3e8_v_u8m1x3 (const uint8_t *base, size_t vl) {
+  return vlseg3e8_v_u8m1x3(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e8_v_u8m1x4(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg4.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T:%.*]] undef, <vscale x 8 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP2]], <vscale x 8 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP4]], <vscale x 8 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP6]], <vscale x 8 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8M1X4_T]] [[TMP8]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e8_v_u8m1x4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg4.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T:%.*]] undef, <vscale x 8 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP2]], <vscale x 8 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP4]], <vscale x 8 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP6]], <vscale x 8 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8M1X4_T]] [[TMP8]]
+//
+vuint8m1x4_t test_vlseg4e8_v_u8m1x4 (const uint8_t *base, size_t vl) {
+  return vlseg4e8_v_u8m1x4(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e8_v_u8m1x5(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg5.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T:%.*]] undef, <vscale x 8 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP2]], <vscale x 8 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], <vscale x 8 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP6]], <vscale x 8 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP8]], <vscale x 8 x i8> [[TMP9]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8M1X5_T]] [[TMP10]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e8_v_u8m1x5(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg5.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T:%.*]] undef, <vscale x 8 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP2]], <vscale x 8 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], <vscale x 8 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP6]], <vscale x 8 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP8]], <vscale x 8 x i8> [[TMP9]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8M1X5_T]] [[TMP10]]
+//
+vuint8m1x5_t test_vlseg5e8_v_u8m1x5 (const uint8_t *base, size_t vl) {
+  return vlseg5e8_v_u8m1x5(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e8_v_u8m1x6(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg6.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T:%.*]] undef, <vscale x 8 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP2]], <vscale x 8 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP4]], <vscale x 8 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP6]], <vscale x 8 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP8]], <vscale x 8 x i8> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP10]], <vscale x 8 x i8> [[TMP11]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8M1X6_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e8_v_u8m1x6(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg6.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T:%.*]] undef, <vscale x 8 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP2]], <vscale x 8 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP4]], <vscale x 8 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP6]], <vscale x 8 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP8]], <vscale x 8 x i8> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP10]], <vscale x 8 x i8> [[TMP11]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8M1X6_T]] [[TMP12]]
+//
+vuint8m1x6_t test_vlseg6e8_v_u8m1x6 (const uint8_t *base, size_t vl) {
+  return vlseg6e8_v_u8m1x6(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e8_v_u8m1x7(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg7.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T:%.*]] undef, <vscale x 8 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP2]], <vscale x 8 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP4]], <vscale x 8 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], <vscale x 8 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP8]], <vscale x 8 x i8> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP10]], <vscale x 8 x i8> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP12]], <vscale x 8 x i8> [[TMP13]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8M1X7_T]] [[TMP14]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e8_v_u8m1x7(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg7.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T:%.*]] undef, <vscale x 8 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP2]], <vscale x 8 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP4]], <vscale x 8 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], <vscale x 8 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP8]], <vscale x 8 x i8> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP10]], <vscale x 8 x i8> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP12]], <vscale x 8 x i8> [[TMP13]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8M1X7_T]] [[TMP14]]
+//
+vuint8m1x7_t test_vlseg7e8_v_u8m1x7 (const uint8_t *base, size_t vl) {
+  return vlseg7e8_v_u8m1x7(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e8_v_u8m1x8(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg8.nxv8i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T:%.*]] undef, <vscale x 8 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP2]], <vscale x 8 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP4]], <vscale x 8 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP6]], <vscale x 8 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP8]], <vscale x 8 x i8> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP10]], <vscale x 8 x i8> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP12]], <vscale x 8 x i8> [[TMP13]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP14]], <vscale x 8 x i8> [[TMP15]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8M1X8_T]] [[TMP16]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e8_v_u8m1x8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg8.nxv8i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T:%.*]] undef, <vscale x 8 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP2]], <vscale x 8 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP4]], <vscale x 8 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP6]], <vscale x 8 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP8]], <vscale x 8 x i8> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP10]], <vscale x 8 x i8> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP12]], <vscale x 8 x i8> [[TMP13]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP0]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP14]], <vscale x 8 x i8> [[TMP15]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8M1X8_T]] [[TMP16]]
+//
+vuint8m1x8_t test_vlseg8e8_v_u8m1x8 (const uint8_t *base, size_t vl) {
+  return vlseg8e8_v_u8m1x8(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_u8m2x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg2.nxv16i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X2_T:%.*]] undef, <vscale x 16 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X2_T]] [[TMP2]], <vscale x 16 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8M2X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_u8m2x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg2.nxv16i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X2_T:%.*]] undef, <vscale x 16 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X2_T]] [[TMP2]], <vscale x 16 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8M2X2_T]] [[TMP4]]
+//
+vuint8m2x2_t test_vlseg2e8_v_u8m2x2 (const uint8_t *base, size_t vl) {
+  return vlseg2e8_v_u8m2x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e8_v_u8m2x3(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg3.nxv16i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T:%.*]] undef, <vscale x 16 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP2]], <vscale x 16 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP4]], <vscale x 16 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8M2X3_T]] [[TMP6]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e8_v_u8m2x3(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg3.nxv16i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T:%.*]] undef, <vscale x 16 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP2]], <vscale x 16 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP4]], <vscale x 16 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8M2X3_T]] [[TMP6]]
+//
+vuint8m2x3_t test_vlseg3e8_v_u8m2x3 (const uint8_t *base, size_t vl) {
+  return vlseg3e8_v_u8m2x3(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e8_v_u8m2x4(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg4.nxv16i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T:%.*]] undef, <vscale x 16 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP2]], <vscale x 16 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP4]], <vscale x 16 x i8> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP6]], <vscale x 16 x i8> [[TMP7]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8M2X4_T]] [[TMP8]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e8_v_u8m2x4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg4.nxv16i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T:%.*]] undef, <vscale x 16 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP2]], <vscale x 16 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP4]], <vscale x 16 x i8> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP6]], <vscale x 16 x i8> [[TMP7]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8M2X4_T]] [[TMP8]]
+//
+vuint8m2x4_t test_vlseg4e8_v_u8m2x4 (const uint8_t *base, size_t vl) {
+  return vlseg4e8_v_u8m2x4(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_u8m4x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 32 x i8>, <vscale x 32 x i8> } @llvm.riscv.vlseg2.nxv32i8.i32(i8* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M4X2_T:%.*]] undef, <vscale x 32 x i8> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M4X2_T]] [[TMP2]], <vscale x 32 x i8> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8M4X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_u8m4x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 32 x i8>, <vscale x 32 x i8> } @llvm.riscv.vlseg2.nxv32i8.i64(i8* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M4X2_T:%.*]] undef, <vscale x 32 x i8> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M4X2_T]] [[TMP2]], <vscale x 32 x i8> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8M4X2_T]] [[TMP4]]
+//
+vuint8m4x2_t test_vlseg2e8_v_u8m4x2 (const uint8_t *base, size_t vl) {
+  return vlseg2e8_v_u8m4x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e16_v_u16mf4x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg2.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X2_T:%.*]] undef, <vscale x 1 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP2]], <vscale x 1 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e16_v_u16mf4x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg2.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X2_T:%.*]] undef, <vscale x 1 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP2]], <vscale x 1 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP4]]
+//
+vuint16mf4x2_t test_vlseg2e16_v_u16mf4x2 (const uint16_t *base, size_t vl) {
+  return vlseg2e16_v_u16mf4x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e16_v_u16mf4x3(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg3.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T:%.*]] undef, <vscale x 1 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP2]], <vscale x 1 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP4]], <vscale x 1 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP6]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e16_v_u16mf4x3(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg3.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T:%.*]] undef, <vscale x 1 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP2]], <vscale x 1 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP4]], <vscale x 1 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP6]]
+//
+vuint16mf4x3_t test_vlseg3e16_v_u16mf4x3 (const uint16_t *base, size_t vl) {
+  return vlseg3e16_v_u16mf4x3(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e16_v_u16mf4x4(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg4.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T:%.*]] undef, <vscale x 1 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP2]], <vscale x 1 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP4]], <vscale x 1 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP6]], <vscale x 1 x i16> [[TMP7]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP8]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e16_v_u16mf4x4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg4.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T:%.*]] undef, <vscale x 1 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP2]], <vscale x 1 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP4]], <vscale x 1 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP6]], <vscale x 1 x i16> [[TMP7]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP8]]
+//
+vuint16mf4x4_t test_vlseg4e16_v_u16mf4x4 (const uint16_t *base, size_t vl) {
+  return vlseg4e16_v_u16mf4x4(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e16_v_u16mf4x5(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg5.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T:%.*]] undef, <vscale x 1 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP2]], <vscale x 1 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], <vscale x 1 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP6]], <vscale x 1 x i16> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP8]], <vscale x 1 x i16> [[TMP9]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP10]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e16_v_u16mf4x5(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg5.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T:%.*]] undef, <vscale x 1 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP2]], <vscale x 1 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], <vscale x 1 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP6]], <vscale x 1 x i16> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP8]], <vscale x 1 x i16> [[TMP9]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP10]]
+//
+vuint16mf4x5_t test_vlseg5e16_v_u16mf4x5 (const uint16_t *base, size_t vl) {
+  return vlseg5e16_v_u16mf4x5(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e16_v_u16mf4x6(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg6.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T:%.*]] undef, <vscale x 1 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP2]], <vscale x 1 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP4]], <vscale x 1 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP6]], <vscale x 1 x i16> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP8]], <vscale x 1 x i16> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP10]], <vscale x 1 x i16> [[TMP11]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e16_v_u16mf4x6(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg6.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T:%.*]] undef, <vscale x 1 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP2]], <vscale x 1 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP4]], <vscale x 1 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP6]], <vscale x 1 x i16> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP8]], <vscale x 1 x i16> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP10]], <vscale x 1 x i16> [[TMP11]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP12]]
+//
+vuint16mf4x6_t test_vlseg6e16_v_u16mf4x6 (const uint16_t *base, size_t vl) {
+  return vlseg6e16_v_u16mf4x6(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e16_v_u16mf4x7(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg7.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T:%.*]] undef, <vscale x 1 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP2]], <vscale x 1 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP4]], <vscale x 1 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], <vscale x 1 x i16> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP8]], <vscale x 1 x i16> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP10]], <vscale x 1 x i16> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP12]], <vscale x 1 x i16> [[TMP13]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP14]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e16_v_u16mf4x7(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg7.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T:%.*]] undef, <vscale x 1 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP2]], <vscale x 1 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP4]], <vscale x 1 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], <vscale x 1 x i16> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP8]], <vscale x 1 x i16> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP10]], <vscale x 1 x i16> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP12]], <vscale x 1 x i16> [[TMP13]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP14]]
+//
+vuint16mf4x7_t test_vlseg7e16_v_u16mf4x7 (const uint16_t *base, size_t vl) {
+  return vlseg7e16_v_u16mf4x7(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e16_v_u16mf4x8(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg8.nxv1i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T:%.*]] undef, <vscale x 1 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP2]], <vscale x 1 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP4]], <vscale x 1 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP6]], <vscale x 1 x i16> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP8]], <vscale x 1 x i16> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP10]], <vscale x 1 x i16> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP12]], <vscale x 1 x i16> [[TMP13]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP14]], <vscale x 1 x i16> [[TMP15]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP16]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e16_v_u16mf4x8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg8.nxv1i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T:%.*]] undef, <vscale x 1 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP2]], <vscale x 1 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP4]], <vscale x 1 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP6]], <vscale x 1 x i16> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP8]], <vscale x 1 x i16> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP10]], <vscale x 1 x i16> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP12]], <vscale x 1 x i16> [[TMP13]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP0]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP14]], <vscale x 1 x i16> [[TMP15]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP16]]
+//
+vuint16mf4x8_t test_vlseg8e16_v_u16mf4x8 (const uint16_t *base, size_t vl) {
+  return vlseg8e16_v_u16mf4x8(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e16_v_u16mf2x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg2.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X2_T:%.*]] undef, <vscale x 2 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP2]], <vscale x 2 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e16_v_u16mf2x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg2.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X2_T:%.*]] undef, <vscale x 2 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP2]], <vscale x 2 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP4]]
+//
+vuint16mf2x2_t test_vlseg2e16_v_u16mf2x2 (const uint16_t *base, size_t vl) {
+  return vlseg2e16_v_u16mf2x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e16_v_u16mf2x3(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg3.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T:%.*]] undef, <vscale x 2 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP2]], <vscale x 2 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP4]], <vscale x 2 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP6]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e16_v_u16mf2x3(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg3.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T:%.*]] undef, <vscale x 2 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP2]], <vscale x 2 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP4]], <vscale x 2 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP6]]
+//
+vuint16mf2x3_t test_vlseg3e16_v_u16mf2x3 (const uint16_t *base, size_t vl) {
+  return vlseg3e16_v_u16mf2x3(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e16_v_u16mf2x4(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg4.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T:%.*]] undef, <vscale x 2 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP2]], <vscale x 2 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP4]], <vscale x 2 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP6]], <vscale x 2 x i16> [[TMP7]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP8]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e16_v_u16mf2x4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg4.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T:%.*]] undef, <vscale x 2 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP2]], <vscale x 2 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP4]], <vscale x 2 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP6]], <vscale x 2 x i16> [[TMP7]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP8]]
+//
+vuint16mf2x4_t test_vlseg4e16_v_u16mf2x4 (const uint16_t *base, size_t vl) {
+  return vlseg4e16_v_u16mf2x4(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e16_v_u16mf2x5(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg5.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T:%.*]] undef, <vscale x 2 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP2]], <vscale x 2 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], <vscale x 2 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP6]], <vscale x 2 x i16> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP8]], <vscale x 2 x i16> [[TMP9]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP10]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e16_v_u16mf2x5(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg5.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T:%.*]] undef, <vscale x 2 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP2]], <vscale x 2 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], <vscale x 2 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP6]], <vscale x 2 x i16> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP8]], <vscale x 2 x i16> [[TMP9]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP10]]
+//
+vuint16mf2x5_t test_vlseg5e16_v_u16mf2x5 (const uint16_t *base, size_t vl) {
+  return vlseg5e16_v_u16mf2x5(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e16_v_u16mf2x6(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg6.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T:%.*]] undef, <vscale x 2 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP2]], <vscale x 2 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP4]], <vscale x 2 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP6]], <vscale x 2 x i16> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP8]], <vscale x 2 x i16> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP10]], <vscale x 2 x i16> [[TMP11]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e16_v_u16mf2x6(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg6.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T:%.*]] undef, <vscale x 2 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP2]], <vscale x 2 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP4]], <vscale x 2 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP6]], <vscale x 2 x i16> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP8]], <vscale x 2 x i16> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP10]], <vscale x 2 x i16> [[TMP11]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP12]]
+//
+vuint16mf2x6_t test_vlseg6e16_v_u16mf2x6 (const uint16_t *base, size_t vl) {
+  return vlseg6e16_v_u16mf2x6(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e16_v_u16mf2x7(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg7.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T:%.*]] undef, <vscale x 2 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP2]], <vscale x 2 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP4]], <vscale x 2 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], <vscale x 2 x i16> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP8]], <vscale x 2 x i16> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP10]], <vscale x 2 x i16> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP12]], <vscale x 2 x i16> [[TMP13]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP14]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e16_v_u16mf2x7(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg7.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T:%.*]] undef, <vscale x 2 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP2]], <vscale x 2 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP4]], <vscale x 2 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], <vscale x 2 x i16> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP8]], <vscale x 2 x i16> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP10]], <vscale x 2 x i16> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP12]], <vscale x 2 x i16> [[TMP13]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP14]]
+//
+vuint16mf2x7_t test_vlseg7e16_v_u16mf2x7 (const uint16_t *base, size_t vl) {
+  return vlseg7e16_v_u16mf2x7(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e16_v_u16mf2x8(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg8.nxv2i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T:%.*]] undef, <vscale x 2 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP2]], <vscale x 2 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP4]], <vscale x 2 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP6]], <vscale x 2 x i16> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP8]], <vscale x 2 x i16> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP10]], <vscale x 2 x i16> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP12]], <vscale x 2 x i16> [[TMP13]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP14]], <vscale x 2 x i16> [[TMP15]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP16]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e16_v_u16mf2x8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg8.nxv2i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T:%.*]] undef, <vscale x 2 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP2]], <vscale x 2 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP4]], <vscale x 2 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP6]], <vscale x 2 x i16> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP8]], <vscale x 2 x i16> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP10]], <vscale x 2 x i16> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP12]], <vscale x 2 x i16> [[TMP13]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP0]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP14]], <vscale x 2 x i16> [[TMP15]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP16]]
+//
+vuint16mf2x8_t test_vlseg8e16_v_u16mf2x8 (const uint16_t *base, size_t vl) {
+  return vlseg8e16_v_u16mf2x8(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e16_v_u16m1x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg2.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X2_T:%.*]] undef, <vscale x 4 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X2_T]] [[TMP2]], <vscale x 4 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16M1X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e16_v_u16m1x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg2.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X2_T:%.*]] undef, <vscale x 4 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X2_T]] [[TMP2]], <vscale x 4 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16M1X2_T]] [[TMP4]]
+//
+vuint16m1x2_t test_vlseg2e16_v_u16m1x2 (const uint16_t *base, size_t vl) {
+  return vlseg2e16_v_u16m1x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e16_v_u16m1x3(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg3.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T:%.*]] undef, <vscale x 4 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP2]], <vscale x 4 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP4]], <vscale x 4 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16M1X3_T]] [[TMP6]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e16_v_u16m1x3(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg3.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T:%.*]] undef, <vscale x 4 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP2]], <vscale x 4 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP4]], <vscale x 4 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16M1X3_T]] [[TMP6]]
+//
+vuint16m1x3_t test_vlseg3e16_v_u16m1x3 (const uint16_t *base, size_t vl) {
+  return vlseg3e16_v_u16m1x3(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e16_v_u16m1x4(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg4.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T:%.*]] undef, <vscale x 4 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP2]], <vscale x 4 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP4]], <vscale x 4 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP6]], <vscale x 4 x i16> [[TMP7]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16M1X4_T]] [[TMP8]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e16_v_u16m1x4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg4.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T:%.*]] undef, <vscale x 4 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP2]], <vscale x 4 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP4]], <vscale x 4 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP6]], <vscale x 4 x i16> [[TMP7]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16M1X4_T]] [[TMP8]]
+//
+vuint16m1x4_t test_vlseg4e16_v_u16m1x4 (const uint16_t *base, size_t vl) {
+  return vlseg4e16_v_u16m1x4(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e16_v_u16m1x5(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg5.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T:%.*]] undef, <vscale x 4 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP2]], <vscale x 4 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], <vscale x 4 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP6]], <vscale x 4 x i16> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP8]], <vscale x 4 x i16> [[TMP9]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16M1X5_T]] [[TMP10]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e16_v_u16m1x5(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg5.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T:%.*]] undef, <vscale x 4 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP2]], <vscale x 4 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], <vscale x 4 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP6]], <vscale x 4 x i16> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP8]], <vscale x 4 x i16> [[TMP9]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16M1X5_T]] [[TMP10]]
+//
+vuint16m1x5_t test_vlseg5e16_v_u16m1x5 (const uint16_t *base, size_t vl) {
+  return vlseg5e16_v_u16m1x5(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e16_v_u16m1x6(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg6.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T:%.*]] undef, <vscale x 4 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP2]], <vscale x 4 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP4]], <vscale x 4 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP6]], <vscale x 4 x i16> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP8]], <vscale x 4 x i16> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP10]], <vscale x 4 x i16> [[TMP11]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16M1X6_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e16_v_u16m1x6(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg6.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T:%.*]] undef, <vscale x 4 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP2]], <vscale x 4 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP4]], <vscale x 4 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP6]], <vscale x 4 x i16> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP8]], <vscale x 4 x i16> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP10]], <vscale x 4 x i16> [[TMP11]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16M1X6_T]] [[TMP12]]
+//
+vuint16m1x6_t test_vlseg6e16_v_u16m1x6 (const uint16_t *base, size_t vl) {
+  return vlseg6e16_v_u16m1x6(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e16_v_u16m1x7(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg7.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T:%.*]] undef, <vscale x 4 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP2]], <vscale x 4 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP4]], <vscale x 4 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], <vscale x 4 x i16> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP8]], <vscale x 4 x i16> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP10]], <vscale x 4 x i16> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP12]], <vscale x 4 x i16> [[TMP13]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16M1X7_T]] [[TMP14]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e16_v_u16m1x7(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg7.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T:%.*]] undef, <vscale x 4 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP2]], <vscale x 4 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP4]], <vscale x 4 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], <vscale x 4 x i16> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP8]], <vscale x 4 x i16> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP10]], <vscale x 4 x i16> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP12]], <vscale x 4 x i16> [[TMP13]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16M1X7_T]] [[TMP14]]
+//
+vuint16m1x7_t test_vlseg7e16_v_u16m1x7 (const uint16_t *base, size_t vl) {
+  return vlseg7e16_v_u16m1x7(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e16_v_u16m1x8(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg8.nxv4i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T:%.*]] undef, <vscale x 4 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP2]], <vscale x 4 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP4]], <vscale x 4 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP6]], <vscale x 4 x i16> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP8]], <vscale x 4 x i16> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP10]], <vscale x 4 x i16> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP12]], <vscale x 4 x i16> [[TMP13]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP14]], <vscale x 4 x i16> [[TMP15]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16M1X8_T]] [[TMP16]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e16_v_u16m1x8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg8.nxv4i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T:%.*]] undef, <vscale x 4 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP2]], <vscale x 4 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP4]], <vscale x 4 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP6]], <vscale x 4 x i16> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP8]], <vscale x 4 x i16> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP10]], <vscale x 4 x i16> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP12]], <vscale x 4 x i16> [[TMP13]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP0]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP14]], <vscale x 4 x i16> [[TMP15]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16M1X8_T]] [[TMP16]]
+//
+vuint16m1x8_t test_vlseg8e16_v_u16m1x8 (const uint16_t *base, size_t vl) {
+  return vlseg8e16_v_u16m1x8(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e16_v_u16m2x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg2.nxv8i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X2_T:%.*]] undef, <vscale x 8 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X2_T]] [[TMP2]], <vscale x 8 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16M2X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e16_v_u16m2x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg2.nxv8i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X2_T:%.*]] undef, <vscale x 8 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X2_T]] [[TMP2]], <vscale x 8 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16M2X2_T]] [[TMP4]]
+//
+vuint16m2x2_t test_vlseg2e16_v_u16m2x2 (const uint16_t *base, size_t vl) {
+  return vlseg2e16_v_u16m2x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e16_v_u16m2x3(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg3.nxv8i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T:%.*]] undef, <vscale x 8 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP2]], <vscale x 8 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP4]], <vscale x 8 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16M2X3_T]] [[TMP6]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e16_v_u16m2x3(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg3.nxv8i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T:%.*]] undef, <vscale x 8 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP2]], <vscale x 8 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP4]], <vscale x 8 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16M2X3_T]] [[TMP6]]
+//
+vuint16m2x3_t test_vlseg3e16_v_u16m2x3 (const uint16_t *base, size_t vl) {
+  return vlseg3e16_v_u16m2x3(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e16_v_u16m2x4(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg4.nxv8i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T:%.*]] undef, <vscale x 8 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP2]], <vscale x 8 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP4]], <vscale x 8 x i16> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP6]], <vscale x 8 x i16> [[TMP7]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16M2X4_T]] [[TMP8]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e16_v_u16m2x4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg4.nxv8i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T:%.*]] undef, <vscale x 8 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP2]], <vscale x 8 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP4]], <vscale x 8 x i16> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP6]], <vscale x 8 x i16> [[TMP7]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16M2X4_T]] [[TMP8]]
+//
+vuint16m2x4_t test_vlseg4e16_v_u16m2x4 (const uint16_t *base, size_t vl) {
+  return vlseg4e16_v_u16m2x4(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e16_v_u16m4x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 16 x i16>, <vscale x 16 x i16> } @llvm.riscv.vlseg2.nxv16i16.i32(i16* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i16> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M4X2_T:%.*]] undef, <vscale x 16 x i16> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i16> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M4X2_T]] [[TMP2]], <vscale x 16 x i16> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16M4X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e16_v_u16m4x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 16 x i16>, <vscale x 16 x i16> } @llvm.riscv.vlseg2.nxv16i16.i64(i16* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i16> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M4X2_T:%.*]] undef, <vscale x 16 x i16> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i16> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M4X2_T]] [[TMP2]], <vscale x 16 x i16> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16M4X2_T]] [[TMP4]]
+//
+vuint16m4x2_t test_vlseg2e16_v_u16m4x2 (const uint16_t *base, size_t vl) {
+  return vlseg2e16_v_u16m4x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_u32mf2x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg2.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X2_T:%.*]] undef, <vscale x 1 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP2]], <vscale x 1 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_u32mf2x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg2.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X2_T:%.*]] undef, <vscale x 1 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP2]], <vscale x 1 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP4]]
+//
+vuint32mf2x2_t test_vlseg2e32_v_u32mf2x2 (const uint32_t *base, size_t vl) {
+  return vlseg2e32_v_u32mf2x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e32_v_u32mf2x3(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg3.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T:%.*]] undef, <vscale x 1 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP2]], <vscale x 1 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP4]], <vscale x 1 x i32> [[TMP5]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP6]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e32_v_u32mf2x3(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg3.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T:%.*]] undef, <vscale x 1 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP2]], <vscale x 1 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP4]], <vscale x 1 x i32> [[TMP5]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP6]]
+//
+vuint32mf2x3_t test_vlseg3e32_v_u32mf2x3 (const uint32_t *base, size_t vl) {
+  return vlseg3e32_v_u32mf2x3(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e32_v_u32mf2x4(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg4.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T:%.*]] undef, <vscale x 1 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP2]], <vscale x 1 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP4]], <vscale x 1 x i32> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP6]], <vscale x 1 x i32> [[TMP7]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP8]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e32_v_u32mf2x4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg4.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T:%.*]] undef, <vscale x 1 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP2]], <vscale x 1 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP4]], <vscale x 1 x i32> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP6]], <vscale x 1 x i32> [[TMP7]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP8]]
+//
+vuint32mf2x4_t test_vlseg4e32_v_u32mf2x4 (const uint32_t *base, size_t vl) {
+  return vlseg4e32_v_u32mf2x4(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e32_v_u32mf2x5(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg5.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T:%.*]] undef, <vscale x 1 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP2]], <vscale x 1 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], <vscale x 1 x i32> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP6]], <vscale x 1 x i32> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP8]], <vscale x 1 x i32> [[TMP9]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP10]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e32_v_u32mf2x5(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg5.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T:%.*]] undef, <vscale x 1 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP2]], <vscale x 1 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], <vscale x 1 x i32> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP6]], <vscale x 1 x i32> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP8]], <vscale x 1 x i32> [[TMP9]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP10]]
+//
+vuint32mf2x5_t test_vlseg5e32_v_u32mf2x5 (const uint32_t *base, size_t vl) {
+  return vlseg5e32_v_u32mf2x5(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e32_v_u32mf2x6(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg6.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T:%.*]] undef, <vscale x 1 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP2]], <vscale x 1 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP4]], <vscale x 1 x i32> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP6]], <vscale x 1 x i32> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP8]], <vscale x 1 x i32> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP10]], <vscale x 1 x i32> [[TMP11]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e32_v_u32mf2x6(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg6.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T:%.*]] undef, <vscale x 1 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP2]], <vscale x 1 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP4]], <vscale x 1 x i32> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP6]], <vscale x 1 x i32> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP8]], <vscale x 1 x i32> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP10]], <vscale x 1 x i32> [[TMP11]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP12]]
+//
+vuint32mf2x6_t test_vlseg6e32_v_u32mf2x6 (const uint32_t *base, size_t vl) {
+  return vlseg6e32_v_u32mf2x6(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e32_v_u32mf2x7(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg7.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T:%.*]] undef, <vscale x 1 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP2]], <vscale x 1 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP4]], <vscale x 1 x i32> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], <vscale x 1 x i32> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP8]], <vscale x 1 x i32> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP10]], <vscale x 1 x i32> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP12]], <vscale x 1 x i32> [[TMP13]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP14]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e32_v_u32mf2x7(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg7.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T:%.*]] undef, <vscale x 1 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP2]], <vscale x 1 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP4]], <vscale x 1 x i32> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], <vscale x 1 x i32> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP8]], <vscale x 1 x i32> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP10]], <vscale x 1 x i32> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP12]], <vscale x 1 x i32> [[TMP13]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP14]]
+//
+vuint32mf2x7_t test_vlseg7e32_v_u32mf2x7 (const uint32_t *base, size_t vl) {
+  return vlseg7e32_v_u32mf2x7(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e32_v_u32mf2x8(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg8.nxv1i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T:%.*]] undef, <vscale x 1 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP2]], <vscale x 1 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP4]], <vscale x 1 x i32> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP6]], <vscale x 1 x i32> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP8]], <vscale x 1 x i32> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP10]], <vscale x 1 x i32> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP12]], <vscale x 1 x i32> [[TMP13]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP14]], <vscale x 1 x i32> [[TMP15]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP16]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e32_v_u32mf2x8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg8.nxv1i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T:%.*]] undef, <vscale x 1 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP2]], <vscale x 1 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP4]], <vscale x 1 x i32> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP6]], <vscale x 1 x i32> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP8]], <vscale x 1 x i32> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP10]], <vscale x 1 x i32> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP12]], <vscale x 1 x i32> [[TMP13]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP0]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP14]], <vscale x 1 x i32> [[TMP15]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP16]]
+//
+vuint32mf2x8_t test_vlseg8e32_v_u32mf2x8 (const uint32_t *base, size_t vl) {
+  return vlseg8e32_v_u32mf2x8(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_u32m1x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg2.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X2_T:%.*]] undef, <vscale x 2 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X2_T]] [[TMP2]], <vscale x 2 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32M1X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_u32m1x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg2.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X2_T:%.*]] undef, <vscale x 2 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X2_T]] [[TMP2]], <vscale x 2 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32M1X2_T]] [[TMP4]]
+//
+vuint32m1x2_t test_vlseg2e32_v_u32m1x2 (const uint32_t *base, size_t vl) {
+  return vlseg2e32_v_u32m1x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e32_v_u32m1x3(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg3.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T:%.*]] undef, <vscale x 2 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP2]], <vscale x 2 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP4]], <vscale x 2 x i32> [[TMP5]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32M1X3_T]] [[TMP6]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e32_v_u32m1x3(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg3.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T:%.*]] undef, <vscale x 2 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP2]], <vscale x 2 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP4]], <vscale x 2 x i32> [[TMP5]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32M1X3_T]] [[TMP6]]
+//
+vuint32m1x3_t test_vlseg3e32_v_u32m1x3 (const uint32_t *base, size_t vl) {
+  return vlseg3e32_v_u32m1x3(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e32_v_u32m1x4(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg4.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T:%.*]] undef, <vscale x 2 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP2]], <vscale x 2 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP4]], <vscale x 2 x i32> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP6]], <vscale x 2 x i32> [[TMP7]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32M1X4_T]] [[TMP8]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e32_v_u32m1x4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg4.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T:%.*]] undef, <vscale x 2 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP2]], <vscale x 2 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP4]], <vscale x 2 x i32> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP6]], <vscale x 2 x i32> [[TMP7]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32M1X4_T]] [[TMP8]]
+//
+vuint32m1x4_t test_vlseg4e32_v_u32m1x4 (const uint32_t *base, size_t vl) {
+  return vlseg4e32_v_u32m1x4(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e32_v_u32m1x5(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg5.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T:%.*]] undef, <vscale x 2 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP2]], <vscale x 2 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], <vscale x 2 x i32> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP6]], <vscale x 2 x i32> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP8]], <vscale x 2 x i32> [[TMP9]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32M1X5_T]] [[TMP10]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e32_v_u32m1x5(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg5.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T:%.*]] undef, <vscale x 2 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP2]], <vscale x 2 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], <vscale x 2 x i32> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP6]], <vscale x 2 x i32> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP8]], <vscale x 2 x i32> [[TMP9]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32M1X5_T]] [[TMP10]]
+//
+vuint32m1x5_t test_vlseg5e32_v_u32m1x5 (const uint32_t *base, size_t vl) {
+  return vlseg5e32_v_u32m1x5(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e32_v_u32m1x6(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg6.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T:%.*]] undef, <vscale x 2 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP2]], <vscale x 2 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP4]], <vscale x 2 x i32> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP6]], <vscale x 2 x i32> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP8]], <vscale x 2 x i32> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP10]], <vscale x 2 x i32> [[TMP11]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32M1X6_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e32_v_u32m1x6(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg6.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T:%.*]] undef, <vscale x 2 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP2]], <vscale x 2 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP4]], <vscale x 2 x i32> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP6]], <vscale x 2 x i32> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP8]], <vscale x 2 x i32> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP10]], <vscale x 2 x i32> [[TMP11]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32M1X6_T]] [[TMP12]]
+//
+vuint32m1x6_t test_vlseg6e32_v_u32m1x6 (const uint32_t *base, size_t vl) {
+  return vlseg6e32_v_u32m1x6(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e32_v_u32m1x7(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg7.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T:%.*]] undef, <vscale x 2 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP2]], <vscale x 2 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP4]], <vscale x 2 x i32> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], <vscale x 2 x i32> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP8]], <vscale x 2 x i32> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP10]], <vscale x 2 x i32> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP12]], <vscale x 2 x i32> [[TMP13]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32M1X7_T]] [[TMP14]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e32_v_u32m1x7(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg7.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T:%.*]] undef, <vscale x 2 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP2]], <vscale x 2 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP4]], <vscale x 2 x i32> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], <vscale x 2 x i32> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP8]], <vscale x 2 x i32> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP10]], <vscale x 2 x i32> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP12]], <vscale x 2 x i32> [[TMP13]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32M1X7_T]] [[TMP14]]
+//
+vuint32m1x7_t test_vlseg7e32_v_u32m1x7 (const uint32_t *base, size_t vl) {
+  return vlseg7e32_v_u32m1x7(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e32_v_u32m1x8(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg8.nxv2i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T:%.*]] undef, <vscale x 2 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP2]], <vscale x 2 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP4]], <vscale x 2 x i32> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP6]], <vscale x 2 x i32> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP8]], <vscale x 2 x i32> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP10]], <vscale x 2 x i32> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP12]], <vscale x 2 x i32> [[TMP13]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP14]], <vscale x 2 x i32> [[TMP15]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32M1X8_T]] [[TMP16]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e32_v_u32m1x8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg8.nxv2i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T:%.*]] undef, <vscale x 2 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP2]], <vscale x 2 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP4]], <vscale x 2 x i32> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP6]], <vscale x 2 x i32> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP8]], <vscale x 2 x i32> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP10]], <vscale x 2 x i32> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP12]], <vscale x 2 x i32> [[TMP13]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP14]], <vscale x 2 x i32> [[TMP15]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32M1X8_T]] [[TMP16]]
+//
+vuint32m1x8_t test_vlseg8e32_v_u32m1x8 (const uint32_t *base, size_t vl) {
+  return vlseg8e32_v_u32m1x8(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_u32m2x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg2.nxv4i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X2_T:%.*]] undef, <vscale x 4 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X2_T]] [[TMP2]], <vscale x 4 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32M2X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_u32m2x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg2.nxv4i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X2_T:%.*]] undef, <vscale x 4 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X2_T]] [[TMP2]], <vscale x 4 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32M2X2_T]] [[TMP4]]
+//
+vuint32m2x2_t test_vlseg2e32_v_u32m2x2 (const uint32_t *base, size_t vl) {
+  return vlseg2e32_v_u32m2x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e32_v_u32m2x3(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg3.nxv4i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T:%.*]] undef, <vscale x 4 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP2]], <vscale x 4 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP4]], <vscale x 4 x i32> [[TMP5]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32M2X3_T]] [[TMP6]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e32_v_u32m2x3(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg3.nxv4i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T:%.*]] undef, <vscale x 4 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP2]], <vscale x 4 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP4]], <vscale x 4 x i32> [[TMP5]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32M2X3_T]] [[TMP6]]
+//
+vuint32m2x3_t test_vlseg3e32_v_u32m2x3 (const uint32_t *base, size_t vl) {
+  return vlseg3e32_v_u32m2x3(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e32_v_u32m2x4(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg4.nxv4i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T:%.*]] undef, <vscale x 4 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP2]], <vscale x 4 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP4]], <vscale x 4 x i32> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP6]], <vscale x 4 x i32> [[TMP7]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32M2X4_T]] [[TMP8]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e32_v_u32m2x4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg4.nxv4i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T:%.*]] undef, <vscale x 4 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP2]], <vscale x 4 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP4]], <vscale x 4 x i32> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP6]], <vscale x 4 x i32> [[TMP7]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32M2X4_T]] [[TMP8]]
+//
+vuint32m2x4_t test_vlseg4e32_v_u32m2x4 (const uint32_t *base, size_t vl) {
+  return vlseg4e32_v_u32m2x4(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_u32m4x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i32>, <vscale x 8 x i32> } @llvm.riscv.vlseg2.nxv8i32.i32(i32* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M4X2_T:%.*]] undef, <vscale x 8 x i32> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M4X2_T]] [[TMP2]], <vscale x 8 x i32> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32M4X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_u32m4x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x i32>, <vscale x 8 x i32> } @llvm.riscv.vlseg2.nxv8i32.i64(i32* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M4X2_T:%.*]] undef, <vscale x 8 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M4X2_T]] [[TMP2]], <vscale x 8 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32M4X2_T]] [[TMP4]]
+//
+vuint32m4x2_t test_vlseg2e32_v_u32m4x2 (const uint32_t *base, size_t vl) {
+  return vlseg2e32_v_u32m4x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e64_v_u64m1x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg2.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X2_T:%.*]] undef, <vscale x 1 x i64> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X2_T]] [[TMP2]], <vscale x 1 x i64> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT64M1X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e64_v_u64m1x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg2.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X2_T:%.*]] undef, <vscale x 1 x i64> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X2_T]] [[TMP2]], <vscale x 1 x i64> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT64M1X2_T]] [[TMP4]]
+//
+vuint64m1x2_t test_vlseg2e64_v_u64m1x2 (const uint64_t *base, size_t vl) {
+  return vlseg2e64_v_u64m1x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e64_v_u64m1x3(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg3.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T:%.*]] undef, <vscale x 1 x i64> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP2]], <vscale x 1 x i64> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP4]], <vscale x 1 x i64> [[TMP5]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT64M1X3_T]] [[TMP6]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e64_v_u64m1x3(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg3.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T:%.*]] undef, <vscale x 1 x i64> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP2]], <vscale x 1 x i64> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP4]], <vscale x 1 x i64> [[TMP5]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT64M1X3_T]] [[TMP6]]
+//
+vuint64m1x3_t test_vlseg3e64_v_u64m1x3 (const uint64_t *base, size_t vl) {
+  return vlseg3e64_v_u64m1x3(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e64_v_u64m1x4(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg4.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T:%.*]] undef, <vscale x 1 x i64> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP2]], <vscale x 1 x i64> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP4]], <vscale x 1 x i64> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP6]], <vscale x 1 x i64> [[TMP7]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT64M1X4_T]] [[TMP8]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e64_v_u64m1x4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg4.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T:%.*]] undef, <vscale x 1 x i64> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP2]], <vscale x 1 x i64> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP4]], <vscale x 1 x i64> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP6]], <vscale x 1 x i64> [[TMP7]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT64M1X4_T]] [[TMP8]]
+//
+vuint64m1x4_t test_vlseg4e64_v_u64m1x4 (const uint64_t *base, size_t vl) {
+  return vlseg4e64_v_u64m1x4(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e64_v_u64m1x5(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg5.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T:%.*]] undef, <vscale x 1 x i64> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP2]], <vscale x 1 x i64> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], <vscale x 1 x i64> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP6]], <vscale x 1 x i64> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP8]], <vscale x 1 x i64> [[TMP9]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT64M1X5_T]] [[TMP10]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e64_v_u64m1x5(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg5.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T:%.*]] undef, <vscale x 1 x i64> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP2]], <vscale x 1 x i64> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], <vscale x 1 x i64> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP6]], <vscale x 1 x i64> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP8]], <vscale x 1 x i64> [[TMP9]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT64M1X5_T]] [[TMP10]]
+//
+vuint64m1x5_t test_vlseg5e64_v_u64m1x5 (const uint64_t *base, size_t vl) {
+  return vlseg5e64_v_u64m1x5(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e64_v_u64m1x6(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg6.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T:%.*]] undef, <vscale x 1 x i64> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP2]], <vscale x 1 x i64> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP4]], <vscale x 1 x i64> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP6]], <vscale x 1 x i64> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP8]], <vscale x 1 x i64> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP10]], <vscale x 1 x i64> [[TMP11]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT64M1X6_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e64_v_u64m1x6(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg6.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T:%.*]] undef, <vscale x 1 x i64> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP2]], <vscale x 1 x i64> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP4]], <vscale x 1 x i64> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP6]], <vscale x 1 x i64> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP8]], <vscale x 1 x i64> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP10]], <vscale x 1 x i64> [[TMP11]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT64M1X6_T]] [[TMP12]]
+//
+vuint64m1x6_t test_vlseg6e64_v_u64m1x6 (const uint64_t *base, size_t vl) {
+  return vlseg6e64_v_u64m1x6(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e64_v_u64m1x7(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg7.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T:%.*]] undef, <vscale x 1 x i64> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP2]], <vscale x 1 x i64> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP4]], <vscale x 1 x i64> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], <vscale x 1 x i64> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP8]], <vscale x 1 x i64> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP10]], <vscale x 1 x i64> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP12]], <vscale x 1 x i64> [[TMP13]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT64M1X7_T]] [[TMP14]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e64_v_u64m1x7(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg7.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T:%.*]] undef, <vscale x 1 x i64> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP2]], <vscale x 1 x i64> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP4]], <vscale x 1 x i64> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], <vscale x 1 x i64> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP8]], <vscale x 1 x i64> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP10]], <vscale x 1 x i64> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP12]], <vscale x 1 x i64> [[TMP13]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT64M1X7_T]] [[TMP14]]
+//
+vuint64m1x7_t test_vlseg7e64_v_u64m1x7 (const uint64_t *base, size_t vl) {
+  return vlseg7e64_v_u64m1x7(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e64_v_u64m1x8(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg8.nxv1i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T:%.*]] undef, <vscale x 1 x i64> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP2]], <vscale x 1 x i64> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP4]], <vscale x 1 x i64> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP6]], <vscale x 1 x i64> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP8]], <vscale x 1 x i64> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP10]], <vscale x 1 x i64> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP12]], <vscale x 1 x i64> [[TMP13]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP14]], <vscale x 1 x i64> [[TMP15]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT64M1X8_T]] [[TMP16]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e64_v_u64m1x8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg8.nxv1i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T:%.*]] undef, <vscale x 1 x i64> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP2]], <vscale x 1 x i64> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP4]], <vscale x 1 x i64> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP6]], <vscale x 1 x i64> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP8]], <vscale x 1 x i64> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP10]], <vscale x 1 x i64> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP12]], <vscale x 1 x i64> [[TMP13]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP0]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP14]], <vscale x 1 x i64> [[TMP15]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT64M1X8_T]] [[TMP16]]
+//
+vuint64m1x8_t test_vlseg8e64_v_u64m1x8 (const uint64_t *base, size_t vl) {
+  return vlseg8e64_v_u64m1x8(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e64_v_u64m2x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg2.nxv2i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X2_T:%.*]] undef, <vscale x 2 x i64> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X2_T]] [[TMP2]], <vscale x 2 x i64> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT64M2X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e64_v_u64m2x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg2.nxv2i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X2_T:%.*]] undef, <vscale x 2 x i64> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X2_T]] [[TMP2]], <vscale x 2 x i64> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT64M2X2_T]] [[TMP4]]
+//
+vuint64m2x2_t test_vlseg2e64_v_u64m2x2 (const uint64_t *base, size_t vl) {
+  return vlseg2e64_v_u64m2x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e64_v_u64m2x3(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg3.nxv2i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T:%.*]] undef, <vscale x 2 x i64> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP2]], <vscale x 2 x i64> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP4]], <vscale x 2 x i64> [[TMP5]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT64M2X3_T]] [[TMP6]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e64_v_u64m2x3(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg3.nxv2i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T:%.*]] undef, <vscale x 2 x i64> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP2]], <vscale x 2 x i64> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP4]], <vscale x 2 x i64> [[TMP5]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT64M2X3_T]] [[TMP6]]
+//
+vuint64m2x3_t test_vlseg3e64_v_u64m2x3 (const uint64_t *base, size_t vl) {
+  return vlseg3e64_v_u64m2x3(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e64_v_u64m2x4(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg4.nxv2i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T:%.*]] undef, <vscale x 2 x i64> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP2]], <vscale x 2 x i64> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP4]], <vscale x 2 x i64> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP6]], <vscale x 2 x i64> [[TMP7]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT64M2X4_T]] [[TMP8]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e64_v_u64m2x4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg4.nxv2i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T:%.*]] undef, <vscale x 2 x i64> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP2]], <vscale x 2 x i64> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP4]], <vscale x 2 x i64> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP6]], <vscale x 2 x i64> [[TMP7]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT64M2X4_T]] [[TMP8]]
+//
+vuint64m2x4_t test_vlseg4e64_v_u64m2x4 (const uint64_t *base, size_t vl) {
+  return vlseg4e64_v_u64m2x4(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e64_v_u64m4x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i64>, <vscale x 4 x i64> } @llvm.riscv.vlseg2.nxv4i64.i32(i64* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M4X2_T:%.*]] undef, <vscale x 4 x i64> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M4X2_T]] [[TMP2]], <vscale x 4 x i64> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT64M4X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e64_v_u64m4x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x i64>, <vscale x 4 x i64> } @llvm.riscv.vlseg2.nxv4i64.i64(i64* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M4X2_T:%.*]] undef, <vscale x 4 x i64> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M4X2_T]] [[TMP2]], <vscale x 4 x i64> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT64M4X2_T]] [[TMP4]]
+//
+vuint64m4x2_t test_vlseg2e64_v_u64m4x2 (const uint64_t *base, size_t vl) {
+  return vlseg2e64_v_u64m4x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_f32mf2x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg2.nxv1f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X2_T:%.*]] undef, <vscale x 1 x float> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP2]], <vscale x 1 x float> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_f32mf2x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg2.nxv1f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X2_T:%.*]] undef, <vscale x 1 x float> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP2]], <vscale x 1 x float> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP4]]
+//
+vfloat32mf2x2_t test_vlseg2e32_v_f32mf2x2 (const float *base, size_t vl) {
+  return vlseg2e32_v_f32mf2x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e32_v_f32mf2x3(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg3.nxv1f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T:%.*]] undef, <vscale x 1 x float> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP2]], <vscale x 1 x float> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP4]], <vscale x 1 x float> [[TMP5]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP6]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e32_v_f32mf2x3(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg3.nxv1f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T:%.*]] undef, <vscale x 1 x float> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP2]], <vscale x 1 x float> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP4]], <vscale x 1 x float> [[TMP5]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP6]]
+//
+vfloat32mf2x3_t test_vlseg3e32_v_f32mf2x3 (const float *base, size_t vl) {
+  return vlseg3e32_v_f32mf2x3(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e32_v_f32mf2x4(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg4.nxv1f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T:%.*]] undef, <vscale x 1 x float> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP2]], <vscale x 1 x float> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP4]], <vscale x 1 x float> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP6]], <vscale x 1 x float> [[TMP7]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP8]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e32_v_f32mf2x4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg4.nxv1f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T:%.*]] undef, <vscale x 1 x float> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP2]], <vscale x 1 x float> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP4]], <vscale x 1 x float> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP6]], <vscale x 1 x float> [[TMP7]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP8]]
+//
+vfloat32mf2x4_t test_vlseg4e32_v_f32mf2x4 (const float *base, size_t vl) {
+  return vlseg4e32_v_f32mf2x4(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e32_v_f32mf2x5(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg5.nxv1f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T:%.*]] undef, <vscale x 1 x float> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP2]], <vscale x 1 x float> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], <vscale x 1 x float> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP6]], <vscale x 1 x float> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP8]], <vscale x 1 x float> [[TMP9]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP10]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e32_v_f32mf2x5(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg5.nxv1f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T:%.*]] undef, <vscale x 1 x float> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP2]], <vscale x 1 x float> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], <vscale x 1 x float> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP6]], <vscale x 1 x float> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP8]], <vscale x 1 x float> [[TMP9]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP10]]
+//
+vfloat32mf2x5_t test_vlseg5e32_v_f32mf2x5 (const float *base, size_t vl) {
+  return vlseg5e32_v_f32mf2x5(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e32_v_f32mf2x6(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg6.nxv1f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T:%.*]] undef, <vscale x 1 x float> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP2]], <vscale x 1 x float> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP4]], <vscale x 1 x float> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP6]], <vscale x 1 x float> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP8]], <vscale x 1 x float> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP10]], <vscale x 1 x float> [[TMP11]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e32_v_f32mf2x6(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg6.nxv1f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T:%.*]] undef, <vscale x 1 x float> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP2]], <vscale x 1 x float> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP4]], <vscale x 1 x float> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP6]], <vscale x 1 x float> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP8]], <vscale x 1 x float> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP10]], <vscale x 1 x float> [[TMP11]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP12]]
+//
+vfloat32mf2x6_t test_vlseg6e32_v_f32mf2x6 (const float *base, size_t vl) {
+  return vlseg6e32_v_f32mf2x6(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e32_v_f32mf2x7(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg7.nxv1f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T:%.*]] undef, <vscale x 1 x float> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP2]], <vscale x 1 x float> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP4]], <vscale x 1 x float> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], <vscale x 1 x float> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP8]], <vscale x 1 x float> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP10]], <vscale x 1 x float> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP12]], <vscale x 1 x float> [[TMP13]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP14]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e32_v_f32mf2x7(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg7.nxv1f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T:%.*]] undef, <vscale x 1 x float> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP2]], <vscale x 1 x float> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP4]], <vscale x 1 x float> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], <vscale x 1 x float> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP8]], <vscale x 1 x float> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP10]], <vscale x 1 x float> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP12]], <vscale x 1 x float> [[TMP13]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP14]]
+//
+vfloat32mf2x7_t test_vlseg7e32_v_f32mf2x7 (const float *base, size_t vl) {
+  return vlseg7e32_v_f32mf2x7(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e32_v_f32mf2x8(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg8.nxv1f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T:%.*]] undef, <vscale x 1 x float> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP2]], <vscale x 1 x float> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP4]], <vscale x 1 x float> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP6]], <vscale x 1 x float> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP8]], <vscale x 1 x float> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP10]], <vscale x 1 x float> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP12]], <vscale x 1 x float> [[TMP13]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP14]], <vscale x 1 x float> [[TMP15]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP16]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e32_v_f32mf2x8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg8.nxv1f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T:%.*]] undef, <vscale x 1 x float> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP2]], <vscale x 1 x float> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP4]], <vscale x 1 x float> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP6]], <vscale x 1 x float> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP8]], <vscale x 1 x float> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP10]], <vscale x 1 x float> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP12]], <vscale x 1 x float> [[TMP13]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP0]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP14]], <vscale x 1 x float> [[TMP15]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP16]]
+//
+vfloat32mf2x8_t test_vlseg8e32_v_f32mf2x8 (const float *base, size_t vl) {
+  return vlseg8e32_v_f32mf2x8(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_f32m1x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg2.nxv2f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X2_T:%.*]] undef, <vscale x 2 x float> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP2]], <vscale x 2 x float> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_f32m1x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg2.nxv2f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X2_T:%.*]] undef, <vscale x 2 x float> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP2]], <vscale x 2 x float> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP4]]
+//
+vfloat32m1x2_t test_vlseg2e32_v_f32m1x2 (const float *base, size_t vl) {
+  return vlseg2e32_v_f32m1x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e32_v_f32m1x3(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg3.nxv2f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T:%.*]] undef, <vscale x 2 x float> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP2]], <vscale x 2 x float> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP4]], <vscale x 2 x float> [[TMP5]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP6]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e32_v_f32m1x3(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg3.nxv2f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T:%.*]] undef, <vscale x 2 x float> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP2]], <vscale x 2 x float> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP4]], <vscale x 2 x float> [[TMP5]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP6]]
+//
+vfloat32m1x3_t test_vlseg3e32_v_f32m1x3 (const float *base, size_t vl) {
+  return vlseg3e32_v_f32m1x3(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e32_v_f32m1x4(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg4.nxv2f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T:%.*]] undef, <vscale x 2 x float> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP2]], <vscale x 2 x float> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP4]], <vscale x 2 x float> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP6]], <vscale x 2 x float> [[TMP7]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP8]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e32_v_f32m1x4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg4.nxv2f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T:%.*]] undef, <vscale x 2 x float> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP2]], <vscale x 2 x float> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP4]], <vscale x 2 x float> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP6]], <vscale x 2 x float> [[TMP7]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP8]]
+//
+vfloat32m1x4_t test_vlseg4e32_v_f32m1x4 (const float *base, size_t vl) {
+  return vlseg4e32_v_f32m1x4(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e32_v_f32m1x5(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg5.nxv2f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T:%.*]] undef, <vscale x 2 x float> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP2]], <vscale x 2 x float> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], <vscale x 2 x float> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP6]], <vscale x 2 x float> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP8]], <vscale x 2 x float> [[TMP9]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP10]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e32_v_f32m1x5(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg5.nxv2f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T:%.*]] undef, <vscale x 2 x float> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP2]], <vscale x 2 x float> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], <vscale x 2 x float> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP6]], <vscale x 2 x float> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP8]], <vscale x 2 x float> [[TMP9]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP10]]
+//
+vfloat32m1x5_t test_vlseg5e32_v_f32m1x5 (const float *base, size_t vl) {
+  return vlseg5e32_v_f32m1x5(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e32_v_f32m1x6(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg6.nxv2f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T:%.*]] undef, <vscale x 2 x float> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP2]], <vscale x 2 x float> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP4]], <vscale x 2 x float> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP6]], <vscale x 2 x float> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP8]], <vscale x 2 x float> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP10]], <vscale x 2 x float> [[TMP11]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e32_v_f32m1x6(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg6.nxv2f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T:%.*]] undef, <vscale x 2 x float> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP2]], <vscale x 2 x float> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP4]], <vscale x 2 x float> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP6]], <vscale x 2 x float> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP8]], <vscale x 2 x float> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP10]], <vscale x 2 x float> [[TMP11]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP12]]
+//
+vfloat32m1x6_t test_vlseg6e32_v_f32m1x6 (const float *base, size_t vl) {
+  return vlseg6e32_v_f32m1x6(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e32_v_f32m1x7(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg7.nxv2f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T:%.*]] undef, <vscale x 2 x float> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP2]], <vscale x 2 x float> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP4]], <vscale x 2 x float> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], <vscale x 2 x float> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP8]], <vscale x 2 x float> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP10]], <vscale x 2 x float> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP12]], <vscale x 2 x float> [[TMP13]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP14]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e32_v_f32m1x7(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg7.nxv2f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T:%.*]] undef, <vscale x 2 x float> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP2]], <vscale x 2 x float> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP4]], <vscale x 2 x float> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], <vscale x 2 x float> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP8]], <vscale x 2 x float> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP10]], <vscale x 2 x float> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP12]], <vscale x 2 x float> [[TMP13]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP14]]
+//
+vfloat32m1x7_t test_vlseg7e32_v_f32m1x7 (const float *base, size_t vl) {
+  return vlseg7e32_v_f32m1x7(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e32_v_f32m1x8(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg8.nxv2f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T:%.*]] undef, <vscale x 2 x float> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP2]], <vscale x 2 x float> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP4]], <vscale x 2 x float> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP6]], <vscale x 2 x float> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP8]], <vscale x 2 x float> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP10]], <vscale x 2 x float> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP12]], <vscale x 2 x float> [[TMP13]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP14]], <vscale x 2 x float> [[TMP15]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP16]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e32_v_f32m1x8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg8.nxv2f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T:%.*]] undef, <vscale x 2 x float> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP2]], <vscale x 2 x float> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP4]], <vscale x 2 x float> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP6]], <vscale x 2 x float> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP8]], <vscale x 2 x float> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP10]], <vscale x 2 x float> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP12]], <vscale x 2 x float> [[TMP13]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP0]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP14]], <vscale x 2 x float> [[TMP15]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP16]]
+//
+vfloat32m1x8_t test_vlseg8e32_v_f32m1x8 (const float *base, size_t vl) {
+  return vlseg8e32_v_f32m1x8(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_f32m2x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.riscv.vlseg2.nxv4f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X2_T:%.*]] undef, <vscale x 4 x float> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP2]], <vscale x 4 x float> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_f32m2x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.riscv.vlseg2.nxv4f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X2_T:%.*]] undef, <vscale x 4 x float> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP2]], <vscale x 4 x float> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP4]]
+//
+vfloat32m2x2_t test_vlseg2e32_v_f32m2x2 (const float *base, size_t vl) {
+  return vlseg2e32_v_f32m2x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e32_v_f32m2x3(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.riscv.vlseg3.nxv4f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T:%.*]] undef, <vscale x 4 x float> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP2]], <vscale x 4 x float> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP4]], <vscale x 4 x float> [[TMP5]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP6]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e32_v_f32m2x3(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.riscv.vlseg3.nxv4f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T:%.*]] undef, <vscale x 4 x float> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP2]], <vscale x 4 x float> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP4]], <vscale x 4 x float> [[TMP5]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP6]]
+//
+vfloat32m2x3_t test_vlseg3e32_v_f32m2x3 (const float *base, size_t vl) {
+  return vlseg3e32_v_f32m2x3(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e32_v_f32m2x4(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.riscv.vlseg4.nxv4f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T:%.*]] undef, <vscale x 4 x float> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP2]], <vscale x 4 x float> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP4]], <vscale x 4 x float> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP6]], <vscale x 4 x float> [[TMP7]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP8]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e32_v_f32m2x4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.riscv.vlseg4.nxv4f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T:%.*]] undef, <vscale x 4 x float> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP2]], <vscale x 4 x float> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP4]], <vscale x 4 x float> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP6]], <vscale x 4 x float> [[TMP7]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP8]]
+//
+vfloat32m2x4_t test_vlseg4e32_v_f32m2x4 (const float *base, size_t vl) {
+  return vlseg4e32_v_f32m2x4(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_f32m4x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x float>, <vscale x 8 x float> } @llvm.riscv.vlseg2.nxv8f32.i32(float* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x float>, <vscale x 8 x float> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M4X2_T:%.*]] undef, <vscale x 8 x float> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x float>, <vscale x 8 x float> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP2]], <vscale x 8 x float> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_f32m4x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x float>, <vscale x 8 x float> } @llvm.riscv.vlseg2.nxv8f32.i64(float* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 8 x float>, <vscale x 8 x float> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M4X2_T:%.*]] undef, <vscale x 8 x float> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 8 x float>, <vscale x 8 x float> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP2]], <vscale x 8 x float> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP4]]
+//
+vfloat32m4x2_t test_vlseg2e32_v_f32m4x2 (const float *base, size_t vl) {
+  return vlseg2e32_v_f32m4x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e64_v_f64m1x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg2.nxv1f64.i32(double* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X2_T:%.*]] undef, <vscale x 1 x double> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP2]], <vscale x 1 x double> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e64_v_f64m1x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg2.nxv1f64.i64(double* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X2_T:%.*]] undef, <vscale x 1 x double> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP2]], <vscale x 1 x double> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP4]]
+//
+vfloat64m1x2_t test_vlseg2e64_v_f64m1x2 (const double *base, size_t vl) {
+  return vlseg2e64_v_f64m1x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e64_v_f64m1x3(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg3.nxv1f64.i32(double* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T:%.*]] undef, <vscale x 1 x double> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP2]], <vscale x 1 x double> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP4]], <vscale x 1 x double> [[TMP5]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP6]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e64_v_f64m1x3(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg3.nxv1f64.i64(double* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T:%.*]] undef, <vscale x 1 x double> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP2]], <vscale x 1 x double> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP4]], <vscale x 1 x double> [[TMP5]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP6]]
+//
+vfloat64m1x3_t test_vlseg3e64_v_f64m1x3 (const double *base, size_t vl) {
+  return vlseg3e64_v_f64m1x3(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e64_v_f64m1x4(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg4.nxv1f64.i32(double* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T:%.*]] undef, <vscale x 1 x double> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP2]], <vscale x 1 x double> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP4]], <vscale x 1 x double> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP6]], <vscale x 1 x double> [[TMP7]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP8]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e64_v_f64m1x4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg4.nxv1f64.i64(double* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T:%.*]] undef, <vscale x 1 x double> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP2]], <vscale x 1 x double> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP4]], <vscale x 1 x double> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP6]], <vscale x 1 x double> [[TMP7]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP8]]
+//
+vfloat64m1x4_t test_vlseg4e64_v_f64m1x4 (const double *base, size_t vl) {
+  return vlseg4e64_v_f64m1x4(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e64_v_f64m1x5(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg5.nxv1f64.i32(double* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T:%.*]] undef, <vscale x 1 x double> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP2]], <vscale x 1 x double> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], <vscale x 1 x double> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP6]], <vscale x 1 x double> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP8]], <vscale x 1 x double> [[TMP9]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP10]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e64_v_f64m1x5(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg5.nxv1f64.i64(double* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T:%.*]] undef, <vscale x 1 x double> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP2]], <vscale x 1 x double> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], <vscale x 1 x double> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP6]], <vscale x 1 x double> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP8]], <vscale x 1 x double> [[TMP9]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP10]]
+//
+vfloat64m1x5_t test_vlseg5e64_v_f64m1x5 (const double *base, size_t vl) {
+  return vlseg5e64_v_f64m1x5(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e64_v_f64m1x6(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg6.nxv1f64.i32(double* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T:%.*]] undef, <vscale x 1 x double> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP2]], <vscale x 1 x double> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP4]], <vscale x 1 x double> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP6]], <vscale x 1 x double> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP8]], <vscale x 1 x double> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP10]], <vscale x 1 x double> [[TMP11]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e64_v_f64m1x6(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg6.nxv1f64.i64(double* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T:%.*]] undef, <vscale x 1 x double> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP2]], <vscale x 1 x double> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP4]], <vscale x 1 x double> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP6]], <vscale x 1 x double> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP8]], <vscale x 1 x double> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP10]], <vscale x 1 x double> [[TMP11]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP12]]
+//
+vfloat64m1x6_t test_vlseg6e64_v_f64m1x6 (const double *base, size_t vl) {
+  return vlseg6e64_v_f64m1x6(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e64_v_f64m1x7(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg7.nxv1f64.i32(double* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T:%.*]] undef, <vscale x 1 x double> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP2]], <vscale x 1 x double> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP4]], <vscale x 1 x double> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], <vscale x 1 x double> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP8]], <vscale x 1 x double> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP10]], <vscale x 1 x double> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP12]], <vscale x 1 x double> [[TMP13]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP14]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e64_v_f64m1x7(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg7.nxv1f64.i64(double* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T:%.*]] undef, <vscale x 1 x double> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP2]], <vscale x 1 x double> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP4]], <vscale x 1 x double> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], <vscale x 1 x double> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP8]], <vscale x 1 x double> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP10]], <vscale x 1 x double> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP12]], <vscale x 1 x double> [[TMP13]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP14]]
+//
+vfloat64m1x7_t test_vlseg7e64_v_f64m1x7 (const double *base, size_t vl) {
+  return vlseg7e64_v_f64m1x7(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e64_v_f64m1x8(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg8.nxv1f64.i32(double* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T:%.*]] undef, <vscale x 1 x double> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP2]], <vscale x 1 x double> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP4]], <vscale x 1 x double> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP6]], <vscale x 1 x double> [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 4
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP8]], <vscale x 1 x double> [[TMP9]], 4
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 5
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP10]], <vscale x 1 x double> [[TMP11]], 5
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 6
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP12]], <vscale x 1 x double> [[TMP13]], 6
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 7
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP14]], <vscale x 1 x double> [[TMP15]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP16]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e64_v_f64m1x8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg8.nxv1f64.i64(double* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T:%.*]] undef, <vscale x 1 x double> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP2]], <vscale x 1 x double> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP4]], <vscale x 1 x double> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP6]], <vscale x 1 x double> [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 4
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP8]], <vscale x 1 x double> [[TMP9]], 4
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 5
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP10]], <vscale x 1 x double> [[TMP11]], 5
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 6
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP12]], <vscale x 1 x double> [[TMP13]], 6
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP0]], 7
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP14]], <vscale x 1 x double> [[TMP15]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP16]]
+//
+vfloat64m1x8_t test_vlseg8e64_v_f64m1x8 (const double *base, size_t vl) {
+  return vlseg8e64_v_f64m1x8(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e64_v_f64m2x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.riscv.vlseg2.nxv2f64.i32(double* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X2_T:%.*]] undef, <vscale x 2 x double> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP2]], <vscale x 2 x double> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e64_v_f64m2x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.riscv.vlseg2.nxv2f64.i64(double* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X2_T:%.*]] undef, <vscale x 2 x double> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP2]], <vscale x 2 x double> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP4]]
+//
+vfloat64m2x2_t test_vlseg2e64_v_f64m2x2 (const double *base, size_t vl) {
+  return vlseg2e64_v_f64m2x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e64_v_f64m2x3(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @llvm.riscv.vlseg3.nxv2f64.i32(double* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T:%.*]] undef, <vscale x 2 x double> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP2]], <vscale x 2 x double> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP4]], <vscale x 2 x double> [[TMP5]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP6]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e64_v_f64m2x3(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @llvm.riscv.vlseg3.nxv2f64.i64(double* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T:%.*]] undef, <vscale x 2 x double> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP2]], <vscale x 2 x double> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP4]], <vscale x 2 x double> [[TMP5]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP6]]
+//
+vfloat64m2x3_t test_vlseg3e64_v_f64m2x3 (const double *base, size_t vl) {
+  return vlseg3e64_v_f64m2x3(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e64_v_f64m2x4(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @llvm.riscv.vlseg4.nxv2f64.i32(double* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T:%.*]] undef, <vscale x 2 x double> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP2]], <vscale x 2 x double> [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP0]], 2
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP4]], <vscale x 2 x double> [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP0]], 3
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP6]], <vscale x 2 x double> [[TMP7]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP8]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e64_v_f64m2x4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @llvm.riscv.vlseg4.nxv2f64.i64(double* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T:%.*]] undef, <vscale x 2 x double> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP2]], <vscale x 2 x double> [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP0]], 2
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP4]], <vscale x 2 x double> [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP0]], 3
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP6]], <vscale x 2 x double> [[TMP7]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP8]]
+//
+vfloat64m2x4_t test_vlseg4e64_v_f64m2x4 (const double *base, size_t vl) {
+  return vlseg4e64_v_f64m2x4(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e64_v_f64m4x2(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x double>, <vscale x 4 x double> } @llvm.riscv.vlseg2.nxv4f64.i32(double* [[BASE:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x double>, <vscale x 4 x double> } [[TMP0]], 0
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M4X2_T:%.*]] undef, <vscale x 4 x double> [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x double>, <vscale x 4 x double> } [[TMP0]], 1
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP2]], <vscale x 4 x double> [[TMP3]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP4]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e64_v_f64m4x2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x double>, <vscale x 4 x double> } @llvm.riscv.vlseg2.nxv4f64.i64(double* [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = extractvalue { <vscale x 4 x double>, <vscale x 4 x double> } [[TMP0]], 0
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M4X2_T:%.*]] undef, <vscale x 4 x double> [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue { <vscale x 4 x double>, <vscale x 4 x double> } [[TMP0]], 1
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP2]], <vscale x 4 x double> [[TMP3]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP4]]
+//
+vfloat64m4x2_t test_vlseg2e64_v_f64m4x2 (const double *base, size_t vl) {
+  return vlseg2e64_v_f64m4x2(base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_i8mf8x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X2_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X2_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X2_T]] undef, <vscale x 1 x i8> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X2_T]] [[TMP3]], <vscale x 1 x i8> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg2.mask.nxv1i8.i32(<vscale x 1 x i8> [[TMP6]], <vscale x 1 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X2_T]] undef, <vscale x 1 x i8> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X2_T]] [[TMP10]], <vscale x 1 x i8> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF8X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_i8mf8x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X2_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X2_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X2_T]] undef, <vscale x 1 x i8> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X2_T]] [[TMP3]], <vscale x 1 x i8> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg2.mask.nxv1i8.i64(<vscale x 1 x i8> [[TMP6]], <vscale x 1 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X2_T]] undef, <vscale x 1 x i8> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X2_T]] [[TMP10]], <vscale x 1 x i8> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF8X2_T]] [[TMP12]]
+//
+vint8mf8x2_t test_vlseg2e8_v_i8mf8x2_m (vbool64_t mask, vint8mf8x2_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg2e8_v_i8mf8x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e8_v_i8mf8x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T]] undef, <vscale x 1 x i8> [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP4]], <vscale x 1 x i8> [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP6]], <vscale x 1 x i8> [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg3.mask.nxv1i8.i32(<vscale x 1 x i8> [[TMP9]], <vscale x 1 x i8> [[TMP10]], <vscale x 1 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T]] undef, <vscale x 1 x i8> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP14]], <vscale x 1 x i8> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP16]], <vscale x 1 x i8> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF8X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e8_v_i8mf8x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T]] undef, <vscale x 1 x i8> [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP4]], <vscale x 1 x i8> [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP6]], <vscale x 1 x i8> [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg3.mask.nxv1i8.i64(<vscale x 1 x i8> [[TMP9]], <vscale x 1 x i8> [[TMP10]], <vscale x 1 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T]] undef, <vscale x 1 x i8> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP14]], <vscale x 1 x i8> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X3_T]] [[TMP16]], <vscale x 1 x i8> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF8X3_T]] [[TMP18]]
+//
+vint8mf8x3_t test_vlseg3e8_v_i8mf8x3_m (vbool64_t mask, vint8mf8x3_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg3e8_v_i8mf8x3_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e8_v_i8mf8x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] undef, <vscale x 1 x i8> [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP5]], <vscale x 1 x i8> [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP7]], <vscale x 1 x i8> [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP9]], <vscale x 1 x i8> [[TMP10]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP11]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP11]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg4.mask.nxv1i8.i32(<vscale x 1 x i8> [[TMP12]], <vscale x 1 x i8> [[TMP13]], <vscale x 1 x i8> [[TMP14]], <vscale x 1 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] undef, <vscale x 1 x i8> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP18]], <vscale x 1 x i8> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP20]], <vscale x 1 x i8> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP22]], <vscale x 1 x i8> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF8X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e8_v_i8mf8x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] undef, <vscale x 1 x i8> [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP5]], <vscale x 1 x i8> [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP7]], <vscale x 1 x i8> [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP9]], <vscale x 1 x i8> [[TMP10]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP11]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP11]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg4.mask.nxv1i8.i64(<vscale x 1 x i8> [[TMP12]], <vscale x 1 x i8> [[TMP13]], <vscale x 1 x i8> [[TMP14]], <vscale x 1 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] undef, <vscale x 1 x i8> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP18]], <vscale x 1 x i8> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP20]], <vscale x 1 x i8> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X4_T]] [[TMP22]], <vscale x 1 x i8> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF8X4_T]] [[TMP24]]
+//
+vint8mf8x4_t test_vlseg4e8_v_i8mf8x4_m (vbool64_t mask, vint8mf8x4_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg4e8_v_i8mf8x4_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e8_v_i8mf8x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP3]], <vscale x 1 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] undef, <vscale x 1 x i8> [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP6]], <vscale x 1 x i8> [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP8]], <vscale x 1 x i8> [[TMP9]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP10]], <vscale x 1 x i8> [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP12]], <vscale x 1 x i8> [[TMP13]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP14]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP14]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP14]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg5.mask.nxv1i8.i32(<vscale x 1 x i8> [[TMP15]], <vscale x 1 x i8> [[TMP16]], <vscale x 1 x i8> [[TMP17]], <vscale x 1 x i8> [[TMP18]], <vscale x 1 x i8> [[TMP19]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] undef, <vscale x 1 x i8> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP22]], <vscale x 1 x i8> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP24]], <vscale x 1 x i8> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP26]], <vscale x 1 x i8> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP28]], <vscale x 1 x i8> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF8X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e8_v_i8mf8x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP3]], <vscale x 1 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] undef, <vscale x 1 x i8> [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP6]], <vscale x 1 x i8> [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP8]], <vscale x 1 x i8> [[TMP9]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP10]], <vscale x 1 x i8> [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP12]], <vscale x 1 x i8> [[TMP13]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP14]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP14]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP14]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg5.mask.nxv1i8.i64(<vscale x 1 x i8> [[TMP15]], <vscale x 1 x i8> [[TMP16]], <vscale x 1 x i8> [[TMP17]], <vscale x 1 x i8> [[TMP18]], <vscale x 1 x i8> [[TMP19]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] undef, <vscale x 1 x i8> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP22]], <vscale x 1 x i8> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP24]], <vscale x 1 x i8> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP26]], <vscale x 1 x i8> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X5_T]] [[TMP28]], <vscale x 1 x i8> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF8X5_T]] [[TMP30]]
+//
+vint8mf8x5_t test_vlseg5e8_v_i8mf8x5_m (vbool64_t mask, vint8mf8x5_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg5e8_v_i8mf8x5_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e8_v_i8mf8x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP3]], <vscale x 1 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP4]], <vscale x 1 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] undef, <vscale x 1 x i8> [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP7]], <vscale x 1 x i8> [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP9]], <vscale x 1 x i8> [[TMP10]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP11]], <vscale x 1 x i8> [[TMP12]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP13]], <vscale x 1 x i8> [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP15]], <vscale x 1 x i8> [[TMP16]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP17]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP17]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP17]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP17]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg6.mask.nxv1i8.i32(<vscale x 1 x i8> [[TMP18]], <vscale x 1 x i8> [[TMP19]], <vscale x 1 x i8> [[TMP20]], <vscale x 1 x i8> [[TMP21]], <vscale x 1 x i8> [[TMP22]], <vscale x 1 x i8> [[TMP23]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] undef, <vscale x 1 x i8> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP26]], <vscale x 1 x i8> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP28]], <vscale x 1 x i8> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP30]], <vscale x 1 x i8> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP32]], <vscale x 1 x i8> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP34]], <vscale x 1 x i8> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF8X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e8_v_i8mf8x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP3]], <vscale x 1 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP4]], <vscale x 1 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] undef, <vscale x 1 x i8> [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP7]], <vscale x 1 x i8> [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP9]], <vscale x 1 x i8> [[TMP10]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP11]], <vscale x 1 x i8> [[TMP12]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP13]], <vscale x 1 x i8> [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP15]], <vscale x 1 x i8> [[TMP16]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP17]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP17]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP17]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP17]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg6.mask.nxv1i8.i64(<vscale x 1 x i8> [[TMP18]], <vscale x 1 x i8> [[TMP19]], <vscale x 1 x i8> [[TMP20]], <vscale x 1 x i8> [[TMP21]], <vscale x 1 x i8> [[TMP22]], <vscale x 1 x i8> [[TMP23]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] undef, <vscale x 1 x i8> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP26]], <vscale x 1 x i8> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP28]], <vscale x 1 x i8> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP30]], <vscale x 1 x i8> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP32]], <vscale x 1 x i8> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X6_T]] [[TMP34]], <vscale x 1 x i8> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF8X6_T]] [[TMP36]]
+//
+vint8mf8x6_t test_vlseg6e8_v_i8mf8x6_m (vbool64_t mask, vint8mf8x6_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg6e8_v_i8mf8x6_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e8_v_i8mf8x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP3]], <vscale x 1 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP4]], <vscale x 1 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP5]], <vscale x 1 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] undef, <vscale x 1 x i8> [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP8]], <vscale x 1 x i8> [[TMP9]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP10]], <vscale x 1 x i8> [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP12]], <vscale x 1 x i8> [[TMP13]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP14]], <vscale x 1 x i8> [[TMP15]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP16]], <vscale x 1 x i8> [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP18]], <vscale x 1 x i8> [[TMP19]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP20]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg7.mask.nxv1i8.i32(<vscale x 1 x i8> [[TMP21]], <vscale x 1 x i8> [[TMP22]], <vscale x 1 x i8> [[TMP23]], <vscale x 1 x i8> [[TMP24]], <vscale x 1 x i8> [[TMP25]], <vscale x 1 x i8> [[TMP26]], <vscale x 1 x i8> [[TMP27]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] undef, <vscale x 1 x i8> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP30]], <vscale x 1 x i8> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP32]], <vscale x 1 x i8> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP34]], <vscale x 1 x i8> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP36]], <vscale x 1 x i8> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP38]], <vscale x 1 x i8> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP40]], <vscale x 1 x i8> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF8X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e8_v_i8mf8x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP3]], <vscale x 1 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP4]], <vscale x 1 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP5]], <vscale x 1 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] undef, <vscale x 1 x i8> [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP8]], <vscale x 1 x i8> [[TMP9]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP10]], <vscale x 1 x i8> [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP12]], <vscale x 1 x i8> [[TMP13]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP14]], <vscale x 1 x i8> [[TMP15]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP16]], <vscale x 1 x i8> [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP18]], <vscale x 1 x i8> [[TMP19]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP20]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg7.mask.nxv1i8.i64(<vscale x 1 x i8> [[TMP21]], <vscale x 1 x i8> [[TMP22]], <vscale x 1 x i8> [[TMP23]], <vscale x 1 x i8> [[TMP24]], <vscale x 1 x i8> [[TMP25]], <vscale x 1 x i8> [[TMP26]], <vscale x 1 x i8> [[TMP27]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] undef, <vscale x 1 x i8> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP30]], <vscale x 1 x i8> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP32]], <vscale x 1 x i8> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP34]], <vscale x 1 x i8> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP36]], <vscale x 1 x i8> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP38]], <vscale x 1 x i8> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X7_T]] [[TMP40]], <vscale x 1 x i8> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF8X7_T]] [[TMP42]]
+//
+vint8mf8x7_t test_vlseg7e8_v_i8mf8x7_m (vbool64_t mask, vint8mf8x7_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg7e8_v_i8mf8x7_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e8_v_i8mf8x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP3]], <vscale x 1 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP4]], <vscale x 1 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP5]], <vscale x 1 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP6]], <vscale x 1 x i8> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] undef, <vscale x 1 x i8> [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP9]], <vscale x 1 x i8> [[TMP10]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP11]], <vscale x 1 x i8> [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP13]], <vscale x 1 x i8> [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP15]], <vscale x 1 x i8> [[TMP16]], 4
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP17]], <vscale x 1 x i8> [[TMP18]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP19]], <vscale x 1 x i8> [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP21]], <vscale x 1 x i8> [[TMP22]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP23]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP23]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP23]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP23]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP23]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP23]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP23]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg8.mask.nxv1i8.i32(<vscale x 1 x i8> [[TMP24]], <vscale x 1 x i8> [[TMP25]], <vscale x 1 x i8> [[TMP26]], <vscale x 1 x i8> [[TMP27]], <vscale x 1 x i8> [[TMP28]], <vscale x 1 x i8> [[TMP29]], <vscale x 1 x i8> [[TMP30]], <vscale x 1 x i8> [[TMP31]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] undef, <vscale x 1 x i8> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP34]], <vscale x 1 x i8> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP36]], <vscale x 1 x i8> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP38]], <vscale x 1 x i8> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP40]], <vscale x 1 x i8> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP42]], <vscale x 1 x i8> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP44]], <vscale x 1 x i8> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP46]], <vscale x 1 x i8> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF8X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e8_v_i8mf8x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP3]], <vscale x 1 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP4]], <vscale x 1 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP5]], <vscale x 1 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP6]], <vscale x 1 x i8> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] undef, <vscale x 1 x i8> [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP9]], <vscale x 1 x i8> [[TMP10]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP11]], <vscale x 1 x i8> [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP13]], <vscale x 1 x i8> [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP15]], <vscale x 1 x i8> [[TMP16]], 4
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP17]], <vscale x 1 x i8> [[TMP18]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP19]], <vscale x 1 x i8> [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP21]], <vscale x 1 x i8> [[TMP22]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP23]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP23]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP23]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP23]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP23]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP23]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP23]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg8.mask.nxv1i8.i64(<vscale x 1 x i8> [[TMP24]], <vscale x 1 x i8> [[TMP25]], <vscale x 1 x i8> [[TMP26]], <vscale x 1 x i8> [[TMP27]], <vscale x 1 x i8> [[TMP28]], <vscale x 1 x i8> [[TMP29]], <vscale x 1 x i8> [[TMP30]], <vscale x 1 x i8> [[TMP31]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] undef, <vscale x 1 x i8> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP34]], <vscale x 1 x i8> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP36]], <vscale x 1 x i8> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP38]], <vscale x 1 x i8> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP40]], <vscale x 1 x i8> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP42]], <vscale x 1 x i8> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP44]], <vscale x 1 x i8> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT8MF8X8_T]] [[TMP46]], <vscale x 1 x i8> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF8X8_T]] [[TMP48]]
+//
+vint8mf8x8_t test_vlseg8e8_v_i8mf8x8_m (vbool64_t mask, vint8mf8x8_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg8e8_v_i8mf8x8_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_i8mf4x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X2_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X2_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X2_T]] undef, <vscale x 2 x i8> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X2_T]] [[TMP3]], <vscale x 2 x i8> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg2.mask.nxv2i8.i32(<vscale x 2 x i8> [[TMP6]], <vscale x 2 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X2_T]] undef, <vscale x 2 x i8> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X2_T]] [[TMP10]], <vscale x 2 x i8> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF4X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_i8mf4x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X2_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X2_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X2_T]] undef, <vscale x 2 x i8> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X2_T]] [[TMP3]], <vscale x 2 x i8> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg2.mask.nxv2i8.i64(<vscale x 2 x i8> [[TMP6]], <vscale x 2 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X2_T]] undef, <vscale x 2 x i8> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X2_T]] [[TMP10]], <vscale x 2 x i8> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF4X2_T]] [[TMP12]]
+//
+vint8mf4x2_t test_vlseg2e8_v_i8mf4x2_m (vbool32_t mask, vint8mf4x2_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg2e8_v_i8mf4x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e8_v_i8mf4x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T]] undef, <vscale x 2 x i8> [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP4]], <vscale x 2 x i8> [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP6]], <vscale x 2 x i8> [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg3.mask.nxv2i8.i32(<vscale x 2 x i8> [[TMP9]], <vscale x 2 x i8> [[TMP10]], <vscale x 2 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T]] undef, <vscale x 2 x i8> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP14]], <vscale x 2 x i8> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP16]], <vscale x 2 x i8> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF4X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e8_v_i8mf4x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T]] undef, <vscale x 2 x i8> [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP4]], <vscale x 2 x i8> [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP6]], <vscale x 2 x i8> [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg3.mask.nxv2i8.i64(<vscale x 2 x i8> [[TMP9]], <vscale x 2 x i8> [[TMP10]], <vscale x 2 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T]] undef, <vscale x 2 x i8> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP14]], <vscale x 2 x i8> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X3_T]] [[TMP16]], <vscale x 2 x i8> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF4X3_T]] [[TMP18]]
+//
+vint8mf4x3_t test_vlseg3e8_v_i8mf4x3_m (vbool32_t mask, vint8mf4x3_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg3e8_v_i8mf4x3_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e8_v_i8mf4x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] undef, <vscale x 2 x i8> [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP5]], <vscale x 2 x i8> [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP7]], <vscale x 2 x i8> [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP9]], <vscale x 2 x i8> [[TMP10]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP11]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP11]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg4.mask.nxv2i8.i32(<vscale x 2 x i8> [[TMP12]], <vscale x 2 x i8> [[TMP13]], <vscale x 2 x i8> [[TMP14]], <vscale x 2 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] undef, <vscale x 2 x i8> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP18]], <vscale x 2 x i8> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP20]], <vscale x 2 x i8> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP22]], <vscale x 2 x i8> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF4X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e8_v_i8mf4x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] undef, <vscale x 2 x i8> [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP5]], <vscale x 2 x i8> [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP7]], <vscale x 2 x i8> [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP9]], <vscale x 2 x i8> [[TMP10]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP11]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP11]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg4.mask.nxv2i8.i64(<vscale x 2 x i8> [[TMP12]], <vscale x 2 x i8> [[TMP13]], <vscale x 2 x i8> [[TMP14]], <vscale x 2 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] undef, <vscale x 2 x i8> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP18]], <vscale x 2 x i8> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP20]], <vscale x 2 x i8> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X4_T]] [[TMP22]], <vscale x 2 x i8> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF4X4_T]] [[TMP24]]
+//
+vint8mf4x4_t test_vlseg4e8_v_i8mf4x4_m (vbool32_t mask, vint8mf4x4_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg4e8_v_i8mf4x4_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e8_v_i8mf4x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP3]], <vscale x 2 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] undef, <vscale x 2 x i8> [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP6]], <vscale x 2 x i8> [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP8]], <vscale x 2 x i8> [[TMP9]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP10]], <vscale x 2 x i8> [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP12]], <vscale x 2 x i8> [[TMP13]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP14]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP14]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP14]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg5.mask.nxv2i8.i32(<vscale x 2 x i8> [[TMP15]], <vscale x 2 x i8> [[TMP16]], <vscale x 2 x i8> [[TMP17]], <vscale x 2 x i8> [[TMP18]], <vscale x 2 x i8> [[TMP19]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] undef, <vscale x 2 x i8> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP22]], <vscale x 2 x i8> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP24]], <vscale x 2 x i8> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP26]], <vscale x 2 x i8> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP28]], <vscale x 2 x i8> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF4X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e8_v_i8mf4x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP3]], <vscale x 2 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] undef, <vscale x 2 x i8> [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP6]], <vscale x 2 x i8> [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP8]], <vscale x 2 x i8> [[TMP9]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP10]], <vscale x 2 x i8> [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP12]], <vscale x 2 x i8> [[TMP13]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP14]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP14]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP14]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg5.mask.nxv2i8.i64(<vscale x 2 x i8> [[TMP15]], <vscale x 2 x i8> [[TMP16]], <vscale x 2 x i8> [[TMP17]], <vscale x 2 x i8> [[TMP18]], <vscale x 2 x i8> [[TMP19]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] undef, <vscale x 2 x i8> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP22]], <vscale x 2 x i8> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP24]], <vscale x 2 x i8> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP26]], <vscale x 2 x i8> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X5_T]] [[TMP28]], <vscale x 2 x i8> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF4X5_T]] [[TMP30]]
+//
+vint8mf4x5_t test_vlseg5e8_v_i8mf4x5_m (vbool32_t mask, vint8mf4x5_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg5e8_v_i8mf4x5_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e8_v_i8mf4x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP3]], <vscale x 2 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP4]], <vscale x 2 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] undef, <vscale x 2 x i8> [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP7]], <vscale x 2 x i8> [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP9]], <vscale x 2 x i8> [[TMP10]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP11]], <vscale x 2 x i8> [[TMP12]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP13]], <vscale x 2 x i8> [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP15]], <vscale x 2 x i8> [[TMP16]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP17]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP17]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP17]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP17]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg6.mask.nxv2i8.i32(<vscale x 2 x i8> [[TMP18]], <vscale x 2 x i8> [[TMP19]], <vscale x 2 x i8> [[TMP20]], <vscale x 2 x i8> [[TMP21]], <vscale x 2 x i8> [[TMP22]], <vscale x 2 x i8> [[TMP23]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] undef, <vscale x 2 x i8> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP26]], <vscale x 2 x i8> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP28]], <vscale x 2 x i8> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP30]], <vscale x 2 x i8> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP32]], <vscale x 2 x i8> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP34]], <vscale x 2 x i8> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF4X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e8_v_i8mf4x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP3]], <vscale x 2 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP4]], <vscale x 2 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] undef, <vscale x 2 x i8> [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP7]], <vscale x 2 x i8> [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP9]], <vscale x 2 x i8> [[TMP10]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP11]], <vscale x 2 x i8> [[TMP12]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP13]], <vscale x 2 x i8> [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP15]], <vscale x 2 x i8> [[TMP16]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP17]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP17]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP17]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP17]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg6.mask.nxv2i8.i64(<vscale x 2 x i8> [[TMP18]], <vscale x 2 x i8> [[TMP19]], <vscale x 2 x i8> [[TMP20]], <vscale x 2 x i8> [[TMP21]], <vscale x 2 x i8> [[TMP22]], <vscale x 2 x i8> [[TMP23]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] undef, <vscale x 2 x i8> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP26]], <vscale x 2 x i8> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP28]], <vscale x 2 x i8> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP30]], <vscale x 2 x i8> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP32]], <vscale x 2 x i8> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X6_T]] [[TMP34]], <vscale x 2 x i8> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF4X6_T]] [[TMP36]]
+//
+vint8mf4x6_t test_vlseg6e8_v_i8mf4x6_m (vbool32_t mask, vint8mf4x6_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg6e8_v_i8mf4x6_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e8_v_i8mf4x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP3]], <vscale x 2 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP4]], <vscale x 2 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP5]], <vscale x 2 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] undef, <vscale x 2 x i8> [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP8]], <vscale x 2 x i8> [[TMP9]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP10]], <vscale x 2 x i8> [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP12]], <vscale x 2 x i8> [[TMP13]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP14]], <vscale x 2 x i8> [[TMP15]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP16]], <vscale x 2 x i8> [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP18]], <vscale x 2 x i8> [[TMP19]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP20]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg7.mask.nxv2i8.i32(<vscale x 2 x i8> [[TMP21]], <vscale x 2 x i8> [[TMP22]], <vscale x 2 x i8> [[TMP23]], <vscale x 2 x i8> [[TMP24]], <vscale x 2 x i8> [[TMP25]], <vscale x 2 x i8> [[TMP26]], <vscale x 2 x i8> [[TMP27]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] undef, <vscale x 2 x i8> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP30]], <vscale x 2 x i8> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP32]], <vscale x 2 x i8> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP34]], <vscale x 2 x i8> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP36]], <vscale x 2 x i8> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP38]], <vscale x 2 x i8> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP40]], <vscale x 2 x i8> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF4X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e8_v_i8mf4x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP3]], <vscale x 2 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP4]], <vscale x 2 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP5]], <vscale x 2 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] undef, <vscale x 2 x i8> [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP8]], <vscale x 2 x i8> [[TMP9]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP10]], <vscale x 2 x i8> [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP12]], <vscale x 2 x i8> [[TMP13]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP14]], <vscale x 2 x i8> [[TMP15]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP16]], <vscale x 2 x i8> [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP18]], <vscale x 2 x i8> [[TMP19]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP20]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg7.mask.nxv2i8.i64(<vscale x 2 x i8> [[TMP21]], <vscale x 2 x i8> [[TMP22]], <vscale x 2 x i8> [[TMP23]], <vscale x 2 x i8> [[TMP24]], <vscale x 2 x i8> [[TMP25]], <vscale x 2 x i8> [[TMP26]], <vscale x 2 x i8> [[TMP27]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] undef, <vscale x 2 x i8> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP30]], <vscale x 2 x i8> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP32]], <vscale x 2 x i8> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP34]], <vscale x 2 x i8> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP36]], <vscale x 2 x i8> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP38]], <vscale x 2 x i8> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X7_T]] [[TMP40]], <vscale x 2 x i8> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF4X7_T]] [[TMP42]]
+//
+vint8mf4x7_t test_vlseg7e8_v_i8mf4x7_m (vbool32_t mask, vint8mf4x7_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg7e8_v_i8mf4x7_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e8_v_i8mf4x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP3]], <vscale x 2 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP4]], <vscale x 2 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP5]], <vscale x 2 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP6]], <vscale x 2 x i8> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] undef, <vscale x 2 x i8> [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP9]], <vscale x 2 x i8> [[TMP10]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP11]], <vscale x 2 x i8> [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP13]], <vscale x 2 x i8> [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP15]], <vscale x 2 x i8> [[TMP16]], 4
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP17]], <vscale x 2 x i8> [[TMP18]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP19]], <vscale x 2 x i8> [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP21]], <vscale x 2 x i8> [[TMP22]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP23]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP23]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP23]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP23]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP23]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP23]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP23]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg8.mask.nxv2i8.i32(<vscale x 2 x i8> [[TMP24]], <vscale x 2 x i8> [[TMP25]], <vscale x 2 x i8> [[TMP26]], <vscale x 2 x i8> [[TMP27]], <vscale x 2 x i8> [[TMP28]], <vscale x 2 x i8> [[TMP29]], <vscale x 2 x i8> [[TMP30]], <vscale x 2 x i8> [[TMP31]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] undef, <vscale x 2 x i8> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP34]], <vscale x 2 x i8> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP36]], <vscale x 2 x i8> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP38]], <vscale x 2 x i8> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP40]], <vscale x 2 x i8> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP42]], <vscale x 2 x i8> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP44]], <vscale x 2 x i8> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP46]], <vscale x 2 x i8> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF4X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e8_v_i8mf4x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP3]], <vscale x 2 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP4]], <vscale x 2 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP5]], <vscale x 2 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP6]], <vscale x 2 x i8> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] undef, <vscale x 2 x i8> [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP9]], <vscale x 2 x i8> [[TMP10]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP11]], <vscale x 2 x i8> [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP13]], <vscale x 2 x i8> [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP15]], <vscale x 2 x i8> [[TMP16]], 4
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP17]], <vscale x 2 x i8> [[TMP18]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP19]], <vscale x 2 x i8> [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP21]], <vscale x 2 x i8> [[TMP22]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP23]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP23]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP23]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP23]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP23]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP23]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP23]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg8.mask.nxv2i8.i64(<vscale x 2 x i8> [[TMP24]], <vscale x 2 x i8> [[TMP25]], <vscale x 2 x i8> [[TMP26]], <vscale x 2 x i8> [[TMP27]], <vscale x 2 x i8> [[TMP28]], <vscale x 2 x i8> [[TMP29]], <vscale x 2 x i8> [[TMP30]], <vscale x 2 x i8> [[TMP31]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] undef, <vscale x 2 x i8> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP34]], <vscale x 2 x i8> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP36]], <vscale x 2 x i8> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP38]], <vscale x 2 x i8> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP40]], <vscale x 2 x i8> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP42]], <vscale x 2 x i8> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP44]], <vscale x 2 x i8> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT8MF4X8_T]] [[TMP46]], <vscale x 2 x i8> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF4X8_T]] [[TMP48]]
+//
+vint8mf4x8_t test_vlseg8e8_v_i8mf4x8_m (vbool32_t mask, vint8mf4x8_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg8e8_v_i8mf4x8_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_i8mf2x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X2_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X2_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X2_T]] undef, <vscale x 4 x i8> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X2_T]] [[TMP3]], <vscale x 4 x i8> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg2.mask.nxv4i8.i32(<vscale x 4 x i8> [[TMP6]], <vscale x 4 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X2_T]] undef, <vscale x 4 x i8> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X2_T]] [[TMP10]], <vscale x 4 x i8> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF2X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_i8mf2x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X2_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X2_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X2_T]] undef, <vscale x 4 x i8> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X2_T]] [[TMP3]], <vscale x 4 x i8> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg2.mask.nxv4i8.i64(<vscale x 4 x i8> [[TMP6]], <vscale x 4 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X2_T]] undef, <vscale x 4 x i8> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X2_T]] [[TMP10]], <vscale x 4 x i8> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF2X2_T]] [[TMP12]]
+//
+vint8mf2x2_t test_vlseg2e8_v_i8mf2x2_m (vbool16_t mask, vint8mf2x2_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg2e8_v_i8mf2x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e8_v_i8mf2x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T]] undef, <vscale x 4 x i8> [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP4]], <vscale x 4 x i8> [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP6]], <vscale x 4 x i8> [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg3.mask.nxv4i8.i32(<vscale x 4 x i8> [[TMP9]], <vscale x 4 x i8> [[TMP10]], <vscale x 4 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T]] undef, <vscale x 4 x i8> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP14]], <vscale x 4 x i8> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP16]], <vscale x 4 x i8> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF2X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e8_v_i8mf2x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T]] undef, <vscale x 4 x i8> [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP4]], <vscale x 4 x i8> [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP6]], <vscale x 4 x i8> [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg3.mask.nxv4i8.i64(<vscale x 4 x i8> [[TMP9]], <vscale x 4 x i8> [[TMP10]], <vscale x 4 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T]] undef, <vscale x 4 x i8> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP14]], <vscale x 4 x i8> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X3_T]] [[TMP16]], <vscale x 4 x i8> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF2X3_T]] [[TMP18]]
+//
+vint8mf2x3_t test_vlseg3e8_v_i8mf2x3_m (vbool16_t mask, vint8mf2x3_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg3e8_v_i8mf2x3_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e8_v_i8mf2x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] undef, <vscale x 4 x i8> [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP5]], <vscale x 4 x i8> [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP7]], <vscale x 4 x i8> [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP9]], <vscale x 4 x i8> [[TMP10]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP11]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP11]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg4.mask.nxv4i8.i32(<vscale x 4 x i8> [[TMP12]], <vscale x 4 x i8> [[TMP13]], <vscale x 4 x i8> [[TMP14]], <vscale x 4 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] undef, <vscale x 4 x i8> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP18]], <vscale x 4 x i8> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP20]], <vscale x 4 x i8> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP22]], <vscale x 4 x i8> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF2X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e8_v_i8mf2x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] undef, <vscale x 4 x i8> [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP5]], <vscale x 4 x i8> [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP7]], <vscale x 4 x i8> [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP9]], <vscale x 4 x i8> [[TMP10]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP11]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP11]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg4.mask.nxv4i8.i64(<vscale x 4 x i8> [[TMP12]], <vscale x 4 x i8> [[TMP13]], <vscale x 4 x i8> [[TMP14]], <vscale x 4 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] undef, <vscale x 4 x i8> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP18]], <vscale x 4 x i8> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP20]], <vscale x 4 x i8> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X4_T]] [[TMP22]], <vscale x 4 x i8> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF2X4_T]] [[TMP24]]
+//
+vint8mf2x4_t test_vlseg4e8_v_i8mf2x4_m (vbool16_t mask, vint8mf2x4_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg4e8_v_i8mf2x4_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e8_v_i8mf2x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP3]], <vscale x 4 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] undef, <vscale x 4 x i8> [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP6]], <vscale x 4 x i8> [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP8]], <vscale x 4 x i8> [[TMP9]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP10]], <vscale x 4 x i8> [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP12]], <vscale x 4 x i8> [[TMP13]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP14]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP14]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP14]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg5.mask.nxv4i8.i32(<vscale x 4 x i8> [[TMP15]], <vscale x 4 x i8> [[TMP16]], <vscale x 4 x i8> [[TMP17]], <vscale x 4 x i8> [[TMP18]], <vscale x 4 x i8> [[TMP19]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] undef, <vscale x 4 x i8> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP22]], <vscale x 4 x i8> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP24]], <vscale x 4 x i8> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP26]], <vscale x 4 x i8> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP28]], <vscale x 4 x i8> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF2X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e8_v_i8mf2x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP3]], <vscale x 4 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] undef, <vscale x 4 x i8> [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP6]], <vscale x 4 x i8> [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP8]], <vscale x 4 x i8> [[TMP9]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP10]], <vscale x 4 x i8> [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP12]], <vscale x 4 x i8> [[TMP13]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP14]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP14]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP14]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg5.mask.nxv4i8.i64(<vscale x 4 x i8> [[TMP15]], <vscale x 4 x i8> [[TMP16]], <vscale x 4 x i8> [[TMP17]], <vscale x 4 x i8> [[TMP18]], <vscale x 4 x i8> [[TMP19]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] undef, <vscale x 4 x i8> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP22]], <vscale x 4 x i8> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP24]], <vscale x 4 x i8> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP26]], <vscale x 4 x i8> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X5_T]] [[TMP28]], <vscale x 4 x i8> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF2X5_T]] [[TMP30]]
+//
+vint8mf2x5_t test_vlseg5e8_v_i8mf2x5_m (vbool16_t mask, vint8mf2x5_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg5e8_v_i8mf2x5_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e8_v_i8mf2x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP3]], <vscale x 4 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP4]], <vscale x 4 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] undef, <vscale x 4 x i8> [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP7]], <vscale x 4 x i8> [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP9]], <vscale x 4 x i8> [[TMP10]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP11]], <vscale x 4 x i8> [[TMP12]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP13]], <vscale x 4 x i8> [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP15]], <vscale x 4 x i8> [[TMP16]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP17]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP17]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP17]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP17]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg6.mask.nxv4i8.i32(<vscale x 4 x i8> [[TMP18]], <vscale x 4 x i8> [[TMP19]], <vscale x 4 x i8> [[TMP20]], <vscale x 4 x i8> [[TMP21]], <vscale x 4 x i8> [[TMP22]], <vscale x 4 x i8> [[TMP23]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] undef, <vscale x 4 x i8> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP26]], <vscale x 4 x i8> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP28]], <vscale x 4 x i8> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP30]], <vscale x 4 x i8> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP32]], <vscale x 4 x i8> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP34]], <vscale x 4 x i8> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF2X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e8_v_i8mf2x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP3]], <vscale x 4 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP4]], <vscale x 4 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] undef, <vscale x 4 x i8> [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP7]], <vscale x 4 x i8> [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP9]], <vscale x 4 x i8> [[TMP10]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP11]], <vscale x 4 x i8> [[TMP12]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP13]], <vscale x 4 x i8> [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP15]], <vscale x 4 x i8> [[TMP16]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP17]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP17]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP17]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP17]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg6.mask.nxv4i8.i64(<vscale x 4 x i8> [[TMP18]], <vscale x 4 x i8> [[TMP19]], <vscale x 4 x i8> [[TMP20]], <vscale x 4 x i8> [[TMP21]], <vscale x 4 x i8> [[TMP22]], <vscale x 4 x i8> [[TMP23]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] undef, <vscale x 4 x i8> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP26]], <vscale x 4 x i8> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP28]], <vscale x 4 x i8> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP30]], <vscale x 4 x i8> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP32]], <vscale x 4 x i8> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X6_T]] [[TMP34]], <vscale x 4 x i8> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF2X6_T]] [[TMP36]]
+//
+vint8mf2x6_t test_vlseg6e8_v_i8mf2x6_m (vbool16_t mask, vint8mf2x6_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg6e8_v_i8mf2x6_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e8_v_i8mf2x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP3]], <vscale x 4 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP4]], <vscale x 4 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP5]], <vscale x 4 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] undef, <vscale x 4 x i8> [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP8]], <vscale x 4 x i8> [[TMP9]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP10]], <vscale x 4 x i8> [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP12]], <vscale x 4 x i8> [[TMP13]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP14]], <vscale x 4 x i8> [[TMP15]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP16]], <vscale x 4 x i8> [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP18]], <vscale x 4 x i8> [[TMP19]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP20]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg7.mask.nxv4i8.i32(<vscale x 4 x i8> [[TMP21]], <vscale x 4 x i8> [[TMP22]], <vscale x 4 x i8> [[TMP23]], <vscale x 4 x i8> [[TMP24]], <vscale x 4 x i8> [[TMP25]], <vscale x 4 x i8> [[TMP26]], <vscale x 4 x i8> [[TMP27]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] undef, <vscale x 4 x i8> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP30]], <vscale x 4 x i8> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP32]], <vscale x 4 x i8> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP34]], <vscale x 4 x i8> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP36]], <vscale x 4 x i8> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP38]], <vscale x 4 x i8> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP40]], <vscale x 4 x i8> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF2X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e8_v_i8mf2x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP3]], <vscale x 4 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP4]], <vscale x 4 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP5]], <vscale x 4 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] undef, <vscale x 4 x i8> [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP8]], <vscale x 4 x i8> [[TMP9]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP10]], <vscale x 4 x i8> [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP12]], <vscale x 4 x i8> [[TMP13]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP14]], <vscale x 4 x i8> [[TMP15]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP16]], <vscale x 4 x i8> [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP18]], <vscale x 4 x i8> [[TMP19]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP20]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg7.mask.nxv4i8.i64(<vscale x 4 x i8> [[TMP21]], <vscale x 4 x i8> [[TMP22]], <vscale x 4 x i8> [[TMP23]], <vscale x 4 x i8> [[TMP24]], <vscale x 4 x i8> [[TMP25]], <vscale x 4 x i8> [[TMP26]], <vscale x 4 x i8> [[TMP27]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] undef, <vscale x 4 x i8> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP30]], <vscale x 4 x i8> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP32]], <vscale x 4 x i8> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP34]], <vscale x 4 x i8> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP36]], <vscale x 4 x i8> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP38]], <vscale x 4 x i8> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X7_T]] [[TMP40]], <vscale x 4 x i8> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF2X7_T]] [[TMP42]]
+//
+vint8mf2x7_t test_vlseg7e8_v_i8mf2x7_m (vbool16_t mask, vint8mf2x7_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg7e8_v_i8mf2x7_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e8_v_i8mf2x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP3]], <vscale x 4 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP4]], <vscale x 4 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP5]], <vscale x 4 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP6]], <vscale x 4 x i8> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] undef, <vscale x 4 x i8> [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP9]], <vscale x 4 x i8> [[TMP10]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP11]], <vscale x 4 x i8> [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP13]], <vscale x 4 x i8> [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP15]], <vscale x 4 x i8> [[TMP16]], 4
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP17]], <vscale x 4 x i8> [[TMP18]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP19]], <vscale x 4 x i8> [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP21]], <vscale x 4 x i8> [[TMP22]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP23]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP23]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP23]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP23]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP23]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP23]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP23]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg8.mask.nxv4i8.i32(<vscale x 4 x i8> [[TMP24]], <vscale x 4 x i8> [[TMP25]], <vscale x 4 x i8> [[TMP26]], <vscale x 4 x i8> [[TMP27]], <vscale x 4 x i8> [[TMP28]], <vscale x 4 x i8> [[TMP29]], <vscale x 4 x i8> [[TMP30]], <vscale x 4 x i8> [[TMP31]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] undef, <vscale x 4 x i8> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP34]], <vscale x 4 x i8> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP36]], <vscale x 4 x i8> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP38]], <vscale x 4 x i8> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP40]], <vscale x 4 x i8> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP42]], <vscale x 4 x i8> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP44]], <vscale x 4 x i8> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP46]], <vscale x 4 x i8> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8MF2X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e8_v_i8mf2x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP3]], <vscale x 4 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP4]], <vscale x 4 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP5]], <vscale x 4 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP6]], <vscale x 4 x i8> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] undef, <vscale x 4 x i8> [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP9]], <vscale x 4 x i8> [[TMP10]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP11]], <vscale x 4 x i8> [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP13]], <vscale x 4 x i8> [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP15]], <vscale x 4 x i8> [[TMP16]], 4
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP17]], <vscale x 4 x i8> [[TMP18]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP19]], <vscale x 4 x i8> [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP21]], <vscale x 4 x i8> [[TMP22]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP23]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP23]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP23]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP23]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP23]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP23]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP23]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg8.mask.nxv4i8.i64(<vscale x 4 x i8> [[TMP24]], <vscale x 4 x i8> [[TMP25]], <vscale x 4 x i8> [[TMP26]], <vscale x 4 x i8> [[TMP27]], <vscale x 4 x i8> [[TMP28]], <vscale x 4 x i8> [[TMP29]], <vscale x 4 x i8> [[TMP30]], <vscale x 4 x i8> [[TMP31]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] undef, <vscale x 4 x i8> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP34]], <vscale x 4 x i8> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP36]], <vscale x 4 x i8> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP38]], <vscale x 4 x i8> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP40]], <vscale x 4 x i8> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP42]], <vscale x 4 x i8> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP44]], <vscale x 4 x i8> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT8MF2X8_T]] [[TMP46]], <vscale x 4 x i8> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8MF2X8_T]] [[TMP48]]
+//
+vint8mf2x8_t test_vlseg8e8_v_i8mf2x8_m (vbool16_t mask, vint8mf2x8_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg8e8_v_i8mf2x8_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_i8m1x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X2_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X2_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X2_T]] undef, <vscale x 8 x i8> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X2_T]] [[TMP3]], <vscale x 8 x i8> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg2.mask.nxv8i8.i32(<vscale x 8 x i8> [[TMP6]], <vscale x 8 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X2_T]] undef, <vscale x 8 x i8> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X2_T]] [[TMP10]], <vscale x 8 x i8> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8M1X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_i8m1x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X2_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X2_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X2_T]] undef, <vscale x 8 x i8> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X2_T]] [[TMP3]], <vscale x 8 x i8> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg2.mask.nxv8i8.i64(<vscale x 8 x i8> [[TMP6]], <vscale x 8 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X2_T]] undef, <vscale x 8 x i8> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X2_T]] [[TMP10]], <vscale x 8 x i8> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8M1X2_T]] [[TMP12]]
+//
+vint8m1x2_t test_vlseg2e8_v_i8m1x2_m (vbool8_t mask, vint8m1x2_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg2e8_v_i8m1x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e8_v_i8m1x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T]] undef, <vscale x 8 x i8> [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP4]], <vscale x 8 x i8> [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP6]], <vscale x 8 x i8> [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg3.mask.nxv8i8.i32(<vscale x 8 x i8> [[TMP9]], <vscale x 8 x i8> [[TMP10]], <vscale x 8 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T]] undef, <vscale x 8 x i8> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP14]], <vscale x 8 x i8> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP16]], <vscale x 8 x i8> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8M1X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e8_v_i8m1x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T]] undef, <vscale x 8 x i8> [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP4]], <vscale x 8 x i8> [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP6]], <vscale x 8 x i8> [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg3.mask.nxv8i8.i64(<vscale x 8 x i8> [[TMP9]], <vscale x 8 x i8> [[TMP10]], <vscale x 8 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T]] undef, <vscale x 8 x i8> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP14]], <vscale x 8 x i8> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X3_T]] [[TMP16]], <vscale x 8 x i8> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8M1X3_T]] [[TMP18]]
+//
+vint8m1x3_t test_vlseg3e8_v_i8m1x3_m (vbool8_t mask, vint8m1x3_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg3e8_v_i8m1x3_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e8_v_i8m1x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] undef, <vscale x 8 x i8> [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP5]], <vscale x 8 x i8> [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP7]], <vscale x 8 x i8> [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP9]], <vscale x 8 x i8> [[TMP10]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP11]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP11]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg4.mask.nxv8i8.i32(<vscale x 8 x i8> [[TMP12]], <vscale x 8 x i8> [[TMP13]], <vscale x 8 x i8> [[TMP14]], <vscale x 8 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] undef, <vscale x 8 x i8> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP18]], <vscale x 8 x i8> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP20]], <vscale x 8 x i8> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP22]], <vscale x 8 x i8> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8M1X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e8_v_i8m1x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] undef, <vscale x 8 x i8> [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP5]], <vscale x 8 x i8> [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP7]], <vscale x 8 x i8> [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP9]], <vscale x 8 x i8> [[TMP10]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP11]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP11]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg4.mask.nxv8i8.i64(<vscale x 8 x i8> [[TMP12]], <vscale x 8 x i8> [[TMP13]], <vscale x 8 x i8> [[TMP14]], <vscale x 8 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] undef, <vscale x 8 x i8> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP18]], <vscale x 8 x i8> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP20]], <vscale x 8 x i8> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X4_T]] [[TMP22]], <vscale x 8 x i8> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8M1X4_T]] [[TMP24]]
+//
+vint8m1x4_t test_vlseg4e8_v_i8m1x4_m (vbool8_t mask, vint8m1x4_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg4e8_v_i8m1x4_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e8_v_i8m1x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP3]], <vscale x 8 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] undef, <vscale x 8 x i8> [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP6]], <vscale x 8 x i8> [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP8]], <vscale x 8 x i8> [[TMP9]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP10]], <vscale x 8 x i8> [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP12]], <vscale x 8 x i8> [[TMP13]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP14]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP14]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP14]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg5.mask.nxv8i8.i32(<vscale x 8 x i8> [[TMP15]], <vscale x 8 x i8> [[TMP16]], <vscale x 8 x i8> [[TMP17]], <vscale x 8 x i8> [[TMP18]], <vscale x 8 x i8> [[TMP19]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] undef, <vscale x 8 x i8> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP22]], <vscale x 8 x i8> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP24]], <vscale x 8 x i8> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP26]], <vscale x 8 x i8> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP28]], <vscale x 8 x i8> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8M1X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e8_v_i8m1x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP3]], <vscale x 8 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] undef, <vscale x 8 x i8> [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP6]], <vscale x 8 x i8> [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP8]], <vscale x 8 x i8> [[TMP9]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP10]], <vscale x 8 x i8> [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP12]], <vscale x 8 x i8> [[TMP13]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP14]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP14]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP14]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg5.mask.nxv8i8.i64(<vscale x 8 x i8> [[TMP15]], <vscale x 8 x i8> [[TMP16]], <vscale x 8 x i8> [[TMP17]], <vscale x 8 x i8> [[TMP18]], <vscale x 8 x i8> [[TMP19]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] undef, <vscale x 8 x i8> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP22]], <vscale x 8 x i8> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP24]], <vscale x 8 x i8> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP26]], <vscale x 8 x i8> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X5_T]] [[TMP28]], <vscale x 8 x i8> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8M1X5_T]] [[TMP30]]
+//
+vint8m1x5_t test_vlseg5e8_v_i8m1x5_m (vbool8_t mask, vint8m1x5_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg5e8_v_i8m1x5_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e8_v_i8m1x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP3]], <vscale x 8 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP4]], <vscale x 8 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] undef, <vscale x 8 x i8> [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP7]], <vscale x 8 x i8> [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP9]], <vscale x 8 x i8> [[TMP10]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP11]], <vscale x 8 x i8> [[TMP12]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP13]], <vscale x 8 x i8> [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP15]], <vscale x 8 x i8> [[TMP16]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP17]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP17]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP17]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP17]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg6.mask.nxv8i8.i32(<vscale x 8 x i8> [[TMP18]], <vscale x 8 x i8> [[TMP19]], <vscale x 8 x i8> [[TMP20]], <vscale x 8 x i8> [[TMP21]], <vscale x 8 x i8> [[TMP22]], <vscale x 8 x i8> [[TMP23]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] undef, <vscale x 8 x i8> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP26]], <vscale x 8 x i8> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP28]], <vscale x 8 x i8> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP30]], <vscale x 8 x i8> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP32]], <vscale x 8 x i8> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP34]], <vscale x 8 x i8> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8M1X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e8_v_i8m1x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP3]], <vscale x 8 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP4]], <vscale x 8 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] undef, <vscale x 8 x i8> [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP7]], <vscale x 8 x i8> [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP9]], <vscale x 8 x i8> [[TMP10]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP11]], <vscale x 8 x i8> [[TMP12]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP13]], <vscale x 8 x i8> [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP15]], <vscale x 8 x i8> [[TMP16]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP17]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP17]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP17]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP17]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg6.mask.nxv8i8.i64(<vscale x 8 x i8> [[TMP18]], <vscale x 8 x i8> [[TMP19]], <vscale x 8 x i8> [[TMP20]], <vscale x 8 x i8> [[TMP21]], <vscale x 8 x i8> [[TMP22]], <vscale x 8 x i8> [[TMP23]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] undef, <vscale x 8 x i8> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP26]], <vscale x 8 x i8> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP28]], <vscale x 8 x i8> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP30]], <vscale x 8 x i8> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP32]], <vscale x 8 x i8> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X6_T]] [[TMP34]], <vscale x 8 x i8> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8M1X6_T]] [[TMP36]]
+//
+vint8m1x6_t test_vlseg6e8_v_i8m1x6_m (vbool8_t mask, vint8m1x6_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg6e8_v_i8m1x6_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e8_v_i8m1x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP3]], <vscale x 8 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP4]], <vscale x 8 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP5]], <vscale x 8 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] undef, <vscale x 8 x i8> [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP8]], <vscale x 8 x i8> [[TMP9]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP10]], <vscale x 8 x i8> [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP12]], <vscale x 8 x i8> [[TMP13]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP14]], <vscale x 8 x i8> [[TMP15]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP16]], <vscale x 8 x i8> [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP18]], <vscale x 8 x i8> [[TMP19]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP20]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg7.mask.nxv8i8.i32(<vscale x 8 x i8> [[TMP21]], <vscale x 8 x i8> [[TMP22]], <vscale x 8 x i8> [[TMP23]], <vscale x 8 x i8> [[TMP24]], <vscale x 8 x i8> [[TMP25]], <vscale x 8 x i8> [[TMP26]], <vscale x 8 x i8> [[TMP27]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] undef, <vscale x 8 x i8> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP30]], <vscale x 8 x i8> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP32]], <vscale x 8 x i8> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP34]], <vscale x 8 x i8> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP36]], <vscale x 8 x i8> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP38]], <vscale x 8 x i8> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP40]], <vscale x 8 x i8> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8M1X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e8_v_i8m1x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP3]], <vscale x 8 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP4]], <vscale x 8 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP5]], <vscale x 8 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] undef, <vscale x 8 x i8> [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP8]], <vscale x 8 x i8> [[TMP9]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP10]], <vscale x 8 x i8> [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP12]], <vscale x 8 x i8> [[TMP13]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP14]], <vscale x 8 x i8> [[TMP15]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP16]], <vscale x 8 x i8> [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP18]], <vscale x 8 x i8> [[TMP19]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP20]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg7.mask.nxv8i8.i64(<vscale x 8 x i8> [[TMP21]], <vscale x 8 x i8> [[TMP22]], <vscale x 8 x i8> [[TMP23]], <vscale x 8 x i8> [[TMP24]], <vscale x 8 x i8> [[TMP25]], <vscale x 8 x i8> [[TMP26]], <vscale x 8 x i8> [[TMP27]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] undef, <vscale x 8 x i8> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP30]], <vscale x 8 x i8> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP32]], <vscale x 8 x i8> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP34]], <vscale x 8 x i8> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP36]], <vscale x 8 x i8> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP38]], <vscale x 8 x i8> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X7_T]] [[TMP40]], <vscale x 8 x i8> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8M1X7_T]] [[TMP42]]
+//
+vint8m1x7_t test_vlseg7e8_v_i8m1x7_m (vbool8_t mask, vint8m1x7_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg7e8_v_i8m1x7_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e8_v_i8m1x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP3]], <vscale x 8 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP4]], <vscale x 8 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP5]], <vscale x 8 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP6]], <vscale x 8 x i8> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] undef, <vscale x 8 x i8> [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP9]], <vscale x 8 x i8> [[TMP10]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP11]], <vscale x 8 x i8> [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP13]], <vscale x 8 x i8> [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP15]], <vscale x 8 x i8> [[TMP16]], 4
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP17]], <vscale x 8 x i8> [[TMP18]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP19]], <vscale x 8 x i8> [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP21]], <vscale x 8 x i8> [[TMP22]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP23]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP23]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP23]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP23]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP23]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP23]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP23]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg8.mask.nxv8i8.i32(<vscale x 8 x i8> [[TMP24]], <vscale x 8 x i8> [[TMP25]], <vscale x 8 x i8> [[TMP26]], <vscale x 8 x i8> [[TMP27]], <vscale x 8 x i8> [[TMP28]], <vscale x 8 x i8> [[TMP29]], <vscale x 8 x i8> [[TMP30]], <vscale x 8 x i8> [[TMP31]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] undef, <vscale x 8 x i8> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP34]], <vscale x 8 x i8> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP36]], <vscale x 8 x i8> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP38]], <vscale x 8 x i8> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP40]], <vscale x 8 x i8> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP42]], <vscale x 8 x i8> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP44]], <vscale x 8 x i8> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP46]], <vscale x 8 x i8> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8M1X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e8_v_i8m1x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP3]], <vscale x 8 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP4]], <vscale x 8 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP5]], <vscale x 8 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP6]], <vscale x 8 x i8> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] undef, <vscale x 8 x i8> [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP9]], <vscale x 8 x i8> [[TMP10]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP11]], <vscale x 8 x i8> [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP13]], <vscale x 8 x i8> [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP15]], <vscale x 8 x i8> [[TMP16]], 4
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP17]], <vscale x 8 x i8> [[TMP18]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP19]], <vscale x 8 x i8> [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP21]], <vscale x 8 x i8> [[TMP22]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP23]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP23]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP23]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP23]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP23]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP23]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP23]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg8.mask.nxv8i8.i64(<vscale x 8 x i8> [[TMP24]], <vscale x 8 x i8> [[TMP25]], <vscale x 8 x i8> [[TMP26]], <vscale x 8 x i8> [[TMP27]], <vscale x 8 x i8> [[TMP28]], <vscale x 8 x i8> [[TMP29]], <vscale x 8 x i8> [[TMP30]], <vscale x 8 x i8> [[TMP31]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] undef, <vscale x 8 x i8> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP34]], <vscale x 8 x i8> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP36]], <vscale x 8 x i8> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP38]], <vscale x 8 x i8> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP40]], <vscale x 8 x i8> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP42]], <vscale x 8 x i8> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP44]], <vscale x 8 x i8> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT8M1X8_T]] [[TMP46]], <vscale x 8 x i8> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8M1X8_T]] [[TMP48]]
+//
+vint8m1x8_t test_vlseg8e8_v_i8m1x8_m (vbool8_t mask, vint8m1x8_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg8e8_v_i8m1x8_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_i8m2x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X2_T:%.*]] undef, <vscale x 16 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X2_T]] [[TMP0]], <vscale x 16 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X2_T]] undef, <vscale x 16 x i8> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X2_T]] [[TMP3]], <vscale x 16 x i8> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg2.mask.nxv16i8.i32(<vscale x 16 x i8> [[TMP6]], <vscale x 16 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X2_T]] undef, <vscale x 16 x i8> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X2_T]] [[TMP10]], <vscale x 16 x i8> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8M2X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_i8m2x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X2_T:%.*]] undef, <vscale x 16 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X2_T]] [[TMP0]], <vscale x 16 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X2_T]] undef, <vscale x 16 x i8> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X2_T]] [[TMP3]], <vscale x 16 x i8> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg2.mask.nxv16i8.i64(<vscale x 16 x i8> [[TMP6]], <vscale x 16 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X2_T]] undef, <vscale x 16 x i8> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X2_T]] [[TMP10]], <vscale x 16 x i8> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8M2X2_T]] [[TMP12]]
+//
+vint8m2x2_t test_vlseg2e8_v_i8m2x2_m (vbool4_t mask, vint8m2x2_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg2e8_v_i8m2x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e8_v_i8m2x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T:%.*]] undef, <vscale x 16 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP0]], <vscale x 16 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP1]], <vscale x 16 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T]] undef, <vscale x 16 x i8> [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP4]], <vscale x 16 x i8> [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP6]], <vscale x 16 x i8> [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg3.mask.nxv16i8.i32(<vscale x 16 x i8> [[TMP9]], <vscale x 16 x i8> [[TMP10]], <vscale x 16 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T]] undef, <vscale x 16 x i8> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP14]], <vscale x 16 x i8> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP16]], <vscale x 16 x i8> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8M2X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e8_v_i8m2x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T:%.*]] undef, <vscale x 16 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP0]], <vscale x 16 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP1]], <vscale x 16 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T]] undef, <vscale x 16 x i8> [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP4]], <vscale x 16 x i8> [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP6]], <vscale x 16 x i8> [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg3.mask.nxv16i8.i64(<vscale x 16 x i8> [[TMP9]], <vscale x 16 x i8> [[TMP10]], <vscale x 16 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T]] undef, <vscale x 16 x i8> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP14]], <vscale x 16 x i8> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X3_T]] [[TMP16]], <vscale x 16 x i8> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8M2X3_T]] [[TMP18]]
+//
+vint8m2x3_t test_vlseg3e8_v_i8m2x3_m (vbool4_t mask, vint8m2x3_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg3e8_v_i8m2x3_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e8_v_i8m2x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T:%.*]] undef, <vscale x 16 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP0]], <vscale x 16 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP1]], <vscale x 16 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP2]], <vscale x 16 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] undef, <vscale x 16 x i8> [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP5]], <vscale x 16 x i8> [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP7]], <vscale x 16 x i8> [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP9]], <vscale x 16 x i8> [[TMP10]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP11]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP11]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg4.mask.nxv16i8.i32(<vscale x 16 x i8> [[TMP12]], <vscale x 16 x i8> [[TMP13]], <vscale x 16 x i8> [[TMP14]], <vscale x 16 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] undef, <vscale x 16 x i8> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP18]], <vscale x 16 x i8> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP20]], <vscale x 16 x i8> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP22]], <vscale x 16 x i8> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8M2X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e8_v_i8m2x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T:%.*]] undef, <vscale x 16 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP0]], <vscale x 16 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP1]], <vscale x 16 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP2]], <vscale x 16 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] undef, <vscale x 16 x i8> [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP5]], <vscale x 16 x i8> [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP7]], <vscale x 16 x i8> [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP9]], <vscale x 16 x i8> [[TMP10]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP11]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP11]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg4.mask.nxv16i8.i64(<vscale x 16 x i8> [[TMP12]], <vscale x 16 x i8> [[TMP13]], <vscale x 16 x i8> [[TMP14]], <vscale x 16 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] undef, <vscale x 16 x i8> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP18]], <vscale x 16 x i8> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP20]], <vscale x 16 x i8> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT8M2X4_T]] [[TMP22]], <vscale x 16 x i8> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8M2X4_T]] [[TMP24]]
+//
+vint8m2x4_t test_vlseg4e8_v_i8m2x4_m (vbool4_t mask, vint8m2x4_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg4e8_v_i8m2x4_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_i8m4x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M4X2_T:%.*]] undef, <vscale x 32 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M4X2_T]] [[TMP0]], <vscale x 32 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT8M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8M4X2_T]] undef, <vscale x 32 x i8> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8M4X2_T]] [[TMP3]], <vscale x 32 x i8> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8M4X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8M4X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 32 x i8>, <vscale x 32 x i8> } @llvm.riscv.vlseg2.mask.nxv32i8.i32(<vscale x 32 x i8> [[TMP6]], <vscale x 32 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8M4X2_T]] undef, <vscale x 32 x i8> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8M4X2_T]] [[TMP10]], <vscale x 32 x i8> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT8M4X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_i8m4x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT8M4X2_T:%.*]] undef, <vscale x 32 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT8M4X2_T]] [[TMP0]], <vscale x 32 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT8M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT8M4X2_T]] undef, <vscale x 32 x i8> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT8M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT8M4X2_T]] [[TMP3]], <vscale x 32 x i8> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT8M4X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT8M4X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 32 x i8>, <vscale x 32 x i8> } @llvm.riscv.vlseg2.mask.nxv32i8.i64(<vscale x 32 x i8> [[TMP6]], <vscale x 32 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT8M4X2_T]] undef, <vscale x 32 x i8> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT8M4X2_T]] [[TMP10]], <vscale x 32 x i8> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT8M4X2_T]] [[TMP12]]
+//
+vint8m4x2_t test_vlseg2e8_v_i8m4x2_m (vbool2_t mask, vint8m4x2_t maskedoff, const int8_t *base, size_t vl) {
+  return vlseg2e8_v_i8m4x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e16_v_i16mf4x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X2_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X2_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X2_T]] undef, <vscale x 1 x i16> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X2_T]] [[TMP3]], <vscale x 1 x i16> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg2.mask.nxv1i16.i32(<vscale x 1 x i16> [[TMP6]], <vscale x 1 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X2_T]] undef, <vscale x 1 x i16> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X2_T]] [[TMP10]], <vscale x 1 x i16> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF4X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e16_v_i16mf4x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X2_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X2_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X2_T]] undef, <vscale x 1 x i16> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X2_T]] [[TMP3]], <vscale x 1 x i16> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg2.mask.nxv1i16.i64(<vscale x 1 x i16> [[TMP6]], <vscale x 1 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X2_T]] undef, <vscale x 1 x i16> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X2_T]] [[TMP10]], <vscale x 1 x i16> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF4X2_T]] [[TMP12]]
+//
+vint16mf4x2_t test_vlseg2e16_v_i16mf4x2_m (vbool64_t mask, vint16mf4x2_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg2e16_v_i16mf4x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e16_v_i16mf4x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T]] undef, <vscale x 1 x i16> [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP4]], <vscale x 1 x i16> [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP6]], <vscale x 1 x i16> [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg3.mask.nxv1i16.i32(<vscale x 1 x i16> [[TMP9]], <vscale x 1 x i16> [[TMP10]], <vscale x 1 x i16> [[TMP11]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T]] undef, <vscale x 1 x i16> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP14]], <vscale x 1 x i16> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP16]], <vscale x 1 x i16> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF4X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e16_v_i16mf4x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T]] undef, <vscale x 1 x i16> [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP4]], <vscale x 1 x i16> [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP6]], <vscale x 1 x i16> [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg3.mask.nxv1i16.i64(<vscale x 1 x i16> [[TMP9]], <vscale x 1 x i16> [[TMP10]], <vscale x 1 x i16> [[TMP11]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T]] undef, <vscale x 1 x i16> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP14]], <vscale x 1 x i16> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X3_T]] [[TMP16]], <vscale x 1 x i16> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF4X3_T]] [[TMP18]]
+//
+vint16mf4x3_t test_vlseg3e16_v_i16mf4x3_m (vbool64_t mask, vint16mf4x3_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg3e16_v_i16mf4x3_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e16_v_i16mf4x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] undef, <vscale x 1 x i16> [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP5]], <vscale x 1 x i16> [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP7]], <vscale x 1 x i16> [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP9]], <vscale x 1 x i16> [[TMP10]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP11]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP11]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg4.mask.nxv1i16.i32(<vscale x 1 x i16> [[TMP12]], <vscale x 1 x i16> [[TMP13]], <vscale x 1 x i16> [[TMP14]], <vscale x 1 x i16> [[TMP15]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] undef, <vscale x 1 x i16> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP18]], <vscale x 1 x i16> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP20]], <vscale x 1 x i16> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP22]], <vscale x 1 x i16> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF4X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e16_v_i16mf4x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] undef, <vscale x 1 x i16> [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP5]], <vscale x 1 x i16> [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP7]], <vscale x 1 x i16> [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP9]], <vscale x 1 x i16> [[TMP10]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP11]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP11]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg4.mask.nxv1i16.i64(<vscale x 1 x i16> [[TMP12]], <vscale x 1 x i16> [[TMP13]], <vscale x 1 x i16> [[TMP14]], <vscale x 1 x i16> [[TMP15]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] undef, <vscale x 1 x i16> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP18]], <vscale x 1 x i16> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP20]], <vscale x 1 x i16> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X4_T]] [[TMP22]], <vscale x 1 x i16> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF4X4_T]] [[TMP24]]
+//
+vint16mf4x4_t test_vlseg4e16_v_i16mf4x4_m (vbool64_t mask, vint16mf4x4_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg4e16_v_i16mf4x4_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e16_v_i16mf4x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP3]], <vscale x 1 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] undef, <vscale x 1 x i16> [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP6]], <vscale x 1 x i16> [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP8]], <vscale x 1 x i16> [[TMP9]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP10]], <vscale x 1 x i16> [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP12]], <vscale x 1 x i16> [[TMP13]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP14]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP14]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP14]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg5.mask.nxv1i16.i32(<vscale x 1 x i16> [[TMP15]], <vscale x 1 x i16> [[TMP16]], <vscale x 1 x i16> [[TMP17]], <vscale x 1 x i16> [[TMP18]], <vscale x 1 x i16> [[TMP19]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] undef, <vscale x 1 x i16> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP22]], <vscale x 1 x i16> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP24]], <vscale x 1 x i16> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP26]], <vscale x 1 x i16> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP28]], <vscale x 1 x i16> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF4X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e16_v_i16mf4x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP3]], <vscale x 1 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] undef, <vscale x 1 x i16> [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP6]], <vscale x 1 x i16> [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP8]], <vscale x 1 x i16> [[TMP9]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP10]], <vscale x 1 x i16> [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP12]], <vscale x 1 x i16> [[TMP13]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP14]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP14]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP14]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg5.mask.nxv1i16.i64(<vscale x 1 x i16> [[TMP15]], <vscale x 1 x i16> [[TMP16]], <vscale x 1 x i16> [[TMP17]], <vscale x 1 x i16> [[TMP18]], <vscale x 1 x i16> [[TMP19]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] undef, <vscale x 1 x i16> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP22]], <vscale x 1 x i16> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP24]], <vscale x 1 x i16> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP26]], <vscale x 1 x i16> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X5_T]] [[TMP28]], <vscale x 1 x i16> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF4X5_T]] [[TMP30]]
+//
+vint16mf4x5_t test_vlseg5e16_v_i16mf4x5_m (vbool64_t mask, vint16mf4x5_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg5e16_v_i16mf4x5_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e16_v_i16mf4x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP3]], <vscale x 1 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP4]], <vscale x 1 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] undef, <vscale x 1 x i16> [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP7]], <vscale x 1 x i16> [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP9]], <vscale x 1 x i16> [[TMP10]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP11]], <vscale x 1 x i16> [[TMP12]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP13]], <vscale x 1 x i16> [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP15]], <vscale x 1 x i16> [[TMP16]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP17]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP17]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP17]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP17]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg6.mask.nxv1i16.i32(<vscale x 1 x i16> [[TMP18]], <vscale x 1 x i16> [[TMP19]], <vscale x 1 x i16> [[TMP20]], <vscale x 1 x i16> [[TMP21]], <vscale x 1 x i16> [[TMP22]], <vscale x 1 x i16> [[TMP23]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] undef, <vscale x 1 x i16> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP26]], <vscale x 1 x i16> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP28]], <vscale x 1 x i16> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP30]], <vscale x 1 x i16> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP32]], <vscale x 1 x i16> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP34]], <vscale x 1 x i16> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF4X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e16_v_i16mf4x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP3]], <vscale x 1 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP4]], <vscale x 1 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] undef, <vscale x 1 x i16> [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP7]], <vscale x 1 x i16> [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP9]], <vscale x 1 x i16> [[TMP10]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP11]], <vscale x 1 x i16> [[TMP12]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP13]], <vscale x 1 x i16> [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP15]], <vscale x 1 x i16> [[TMP16]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP17]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP17]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP17]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP17]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg6.mask.nxv1i16.i64(<vscale x 1 x i16> [[TMP18]], <vscale x 1 x i16> [[TMP19]], <vscale x 1 x i16> [[TMP20]], <vscale x 1 x i16> [[TMP21]], <vscale x 1 x i16> [[TMP22]], <vscale x 1 x i16> [[TMP23]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] undef, <vscale x 1 x i16> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP26]], <vscale x 1 x i16> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP28]], <vscale x 1 x i16> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP30]], <vscale x 1 x i16> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP32]], <vscale x 1 x i16> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X6_T]] [[TMP34]], <vscale x 1 x i16> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF4X6_T]] [[TMP36]]
+//
+vint16mf4x6_t test_vlseg6e16_v_i16mf4x6_m (vbool64_t mask, vint16mf4x6_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg6e16_v_i16mf4x6_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e16_v_i16mf4x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP3]], <vscale x 1 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP4]], <vscale x 1 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP5]], <vscale x 1 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] undef, <vscale x 1 x i16> [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP8]], <vscale x 1 x i16> [[TMP9]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP10]], <vscale x 1 x i16> [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP12]], <vscale x 1 x i16> [[TMP13]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP14]], <vscale x 1 x i16> [[TMP15]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP16]], <vscale x 1 x i16> [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP18]], <vscale x 1 x i16> [[TMP19]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP20]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg7.mask.nxv1i16.i32(<vscale x 1 x i16> [[TMP21]], <vscale x 1 x i16> [[TMP22]], <vscale x 1 x i16> [[TMP23]], <vscale x 1 x i16> [[TMP24]], <vscale x 1 x i16> [[TMP25]], <vscale x 1 x i16> [[TMP26]], <vscale x 1 x i16> [[TMP27]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] undef, <vscale x 1 x i16> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP30]], <vscale x 1 x i16> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP32]], <vscale x 1 x i16> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP34]], <vscale x 1 x i16> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP36]], <vscale x 1 x i16> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP38]], <vscale x 1 x i16> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP40]], <vscale x 1 x i16> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF4X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e16_v_i16mf4x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP3]], <vscale x 1 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP4]], <vscale x 1 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP5]], <vscale x 1 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] undef, <vscale x 1 x i16> [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP8]], <vscale x 1 x i16> [[TMP9]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP10]], <vscale x 1 x i16> [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP12]], <vscale x 1 x i16> [[TMP13]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP14]], <vscale x 1 x i16> [[TMP15]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP16]], <vscale x 1 x i16> [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP18]], <vscale x 1 x i16> [[TMP19]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP20]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg7.mask.nxv1i16.i64(<vscale x 1 x i16> [[TMP21]], <vscale x 1 x i16> [[TMP22]], <vscale x 1 x i16> [[TMP23]], <vscale x 1 x i16> [[TMP24]], <vscale x 1 x i16> [[TMP25]], <vscale x 1 x i16> [[TMP26]], <vscale x 1 x i16> [[TMP27]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] undef, <vscale x 1 x i16> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP30]], <vscale x 1 x i16> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP32]], <vscale x 1 x i16> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP34]], <vscale x 1 x i16> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP36]], <vscale x 1 x i16> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP38]], <vscale x 1 x i16> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X7_T]] [[TMP40]], <vscale x 1 x i16> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF4X7_T]] [[TMP42]]
+//
+vint16mf4x7_t test_vlseg7e16_v_i16mf4x7_m (vbool64_t mask, vint16mf4x7_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg7e16_v_i16mf4x7_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e16_v_i16mf4x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP3]], <vscale x 1 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP4]], <vscale x 1 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP5]], <vscale x 1 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP6]], <vscale x 1 x i16> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] undef, <vscale x 1 x i16> [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP9]], <vscale x 1 x i16> [[TMP10]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP11]], <vscale x 1 x i16> [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP13]], <vscale x 1 x i16> [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP15]], <vscale x 1 x i16> [[TMP16]], 4
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP17]], <vscale x 1 x i16> [[TMP18]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP19]], <vscale x 1 x i16> [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP21]], <vscale x 1 x i16> [[TMP22]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP23]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP23]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP23]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP23]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP23]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP23]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP23]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg8.mask.nxv1i16.i32(<vscale x 1 x i16> [[TMP24]], <vscale x 1 x i16> [[TMP25]], <vscale x 1 x i16> [[TMP26]], <vscale x 1 x i16> [[TMP27]], <vscale x 1 x i16> [[TMP28]], <vscale x 1 x i16> [[TMP29]], <vscale x 1 x i16> [[TMP30]], <vscale x 1 x i16> [[TMP31]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] undef, <vscale x 1 x i16> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP34]], <vscale x 1 x i16> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP36]], <vscale x 1 x i16> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP38]], <vscale x 1 x i16> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP40]], <vscale x 1 x i16> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP42]], <vscale x 1 x i16> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP44]], <vscale x 1 x i16> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP46]], <vscale x 1 x i16> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF4X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e16_v_i16mf4x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP3]], <vscale x 1 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP4]], <vscale x 1 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP5]], <vscale x 1 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP6]], <vscale x 1 x i16> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] undef, <vscale x 1 x i16> [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP9]], <vscale x 1 x i16> [[TMP10]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP11]], <vscale x 1 x i16> [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP13]], <vscale x 1 x i16> [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP15]], <vscale x 1 x i16> [[TMP16]], 4
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP17]], <vscale x 1 x i16> [[TMP18]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP19]], <vscale x 1 x i16> [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP21]], <vscale x 1 x i16> [[TMP22]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP23]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP23]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP23]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP23]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP23]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP23]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP23]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg8.mask.nxv1i16.i64(<vscale x 1 x i16> [[TMP24]], <vscale x 1 x i16> [[TMP25]], <vscale x 1 x i16> [[TMP26]], <vscale x 1 x i16> [[TMP27]], <vscale x 1 x i16> [[TMP28]], <vscale x 1 x i16> [[TMP29]], <vscale x 1 x i16> [[TMP30]], <vscale x 1 x i16> [[TMP31]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] undef, <vscale x 1 x i16> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP34]], <vscale x 1 x i16> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP36]], <vscale x 1 x i16> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP38]], <vscale x 1 x i16> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP40]], <vscale x 1 x i16> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP42]], <vscale x 1 x i16> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP44]], <vscale x 1 x i16> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT16MF4X8_T]] [[TMP46]], <vscale x 1 x i16> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF4X8_T]] [[TMP48]]
+//
+vint16mf4x8_t test_vlseg8e16_v_i16mf4x8_m (vbool64_t mask, vint16mf4x8_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg8e16_v_i16mf4x8_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e16_v_i16mf2x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X2_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X2_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X2_T]] undef, <vscale x 2 x i16> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X2_T]] [[TMP3]], <vscale x 2 x i16> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg2.mask.nxv2i16.i32(<vscale x 2 x i16> [[TMP6]], <vscale x 2 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X2_T]] undef, <vscale x 2 x i16> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X2_T]] [[TMP10]], <vscale x 2 x i16> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF2X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e16_v_i16mf2x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X2_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X2_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X2_T]] undef, <vscale x 2 x i16> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X2_T]] [[TMP3]], <vscale x 2 x i16> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg2.mask.nxv2i16.i64(<vscale x 2 x i16> [[TMP6]], <vscale x 2 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X2_T]] undef, <vscale x 2 x i16> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X2_T]] [[TMP10]], <vscale x 2 x i16> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF2X2_T]] [[TMP12]]
+//
+vint16mf2x2_t test_vlseg2e16_v_i16mf2x2_m (vbool32_t mask, vint16mf2x2_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg2e16_v_i16mf2x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e16_v_i16mf2x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T]] undef, <vscale x 2 x i16> [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP4]], <vscale x 2 x i16> [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP6]], <vscale x 2 x i16> [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg3.mask.nxv2i16.i32(<vscale x 2 x i16> [[TMP9]], <vscale x 2 x i16> [[TMP10]], <vscale x 2 x i16> [[TMP11]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T]] undef, <vscale x 2 x i16> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP14]], <vscale x 2 x i16> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP16]], <vscale x 2 x i16> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF2X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e16_v_i16mf2x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T]] undef, <vscale x 2 x i16> [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP4]], <vscale x 2 x i16> [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP6]], <vscale x 2 x i16> [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg3.mask.nxv2i16.i64(<vscale x 2 x i16> [[TMP9]], <vscale x 2 x i16> [[TMP10]], <vscale x 2 x i16> [[TMP11]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T]] undef, <vscale x 2 x i16> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP14]], <vscale x 2 x i16> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X3_T]] [[TMP16]], <vscale x 2 x i16> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF2X3_T]] [[TMP18]]
+//
+vint16mf2x3_t test_vlseg3e16_v_i16mf2x3_m (vbool32_t mask, vint16mf2x3_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg3e16_v_i16mf2x3_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e16_v_i16mf2x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] undef, <vscale x 2 x i16> [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP5]], <vscale x 2 x i16> [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP7]], <vscale x 2 x i16> [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP9]], <vscale x 2 x i16> [[TMP10]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP11]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP11]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg4.mask.nxv2i16.i32(<vscale x 2 x i16> [[TMP12]], <vscale x 2 x i16> [[TMP13]], <vscale x 2 x i16> [[TMP14]], <vscale x 2 x i16> [[TMP15]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] undef, <vscale x 2 x i16> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP18]], <vscale x 2 x i16> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP20]], <vscale x 2 x i16> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP22]], <vscale x 2 x i16> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF2X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e16_v_i16mf2x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] undef, <vscale x 2 x i16> [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP5]], <vscale x 2 x i16> [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP7]], <vscale x 2 x i16> [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP9]], <vscale x 2 x i16> [[TMP10]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP11]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP11]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg4.mask.nxv2i16.i64(<vscale x 2 x i16> [[TMP12]], <vscale x 2 x i16> [[TMP13]], <vscale x 2 x i16> [[TMP14]], <vscale x 2 x i16> [[TMP15]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] undef, <vscale x 2 x i16> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP18]], <vscale x 2 x i16> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP20]], <vscale x 2 x i16> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X4_T]] [[TMP22]], <vscale x 2 x i16> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF2X4_T]] [[TMP24]]
+//
+vint16mf2x4_t test_vlseg4e16_v_i16mf2x4_m (vbool32_t mask, vint16mf2x4_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg4e16_v_i16mf2x4_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e16_v_i16mf2x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP3]], <vscale x 2 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] undef, <vscale x 2 x i16> [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP6]], <vscale x 2 x i16> [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP8]], <vscale x 2 x i16> [[TMP9]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP10]], <vscale x 2 x i16> [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP12]], <vscale x 2 x i16> [[TMP13]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP14]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP14]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP14]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg5.mask.nxv2i16.i32(<vscale x 2 x i16> [[TMP15]], <vscale x 2 x i16> [[TMP16]], <vscale x 2 x i16> [[TMP17]], <vscale x 2 x i16> [[TMP18]], <vscale x 2 x i16> [[TMP19]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] undef, <vscale x 2 x i16> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP22]], <vscale x 2 x i16> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP24]], <vscale x 2 x i16> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP26]], <vscale x 2 x i16> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP28]], <vscale x 2 x i16> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF2X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e16_v_i16mf2x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP3]], <vscale x 2 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] undef, <vscale x 2 x i16> [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP6]], <vscale x 2 x i16> [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP8]], <vscale x 2 x i16> [[TMP9]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP10]], <vscale x 2 x i16> [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP12]], <vscale x 2 x i16> [[TMP13]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP14]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP14]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP14]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg5.mask.nxv2i16.i64(<vscale x 2 x i16> [[TMP15]], <vscale x 2 x i16> [[TMP16]], <vscale x 2 x i16> [[TMP17]], <vscale x 2 x i16> [[TMP18]], <vscale x 2 x i16> [[TMP19]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] undef, <vscale x 2 x i16> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP22]], <vscale x 2 x i16> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP24]], <vscale x 2 x i16> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP26]], <vscale x 2 x i16> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X5_T]] [[TMP28]], <vscale x 2 x i16> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF2X5_T]] [[TMP30]]
+//
+vint16mf2x5_t test_vlseg5e16_v_i16mf2x5_m (vbool32_t mask, vint16mf2x5_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg5e16_v_i16mf2x5_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e16_v_i16mf2x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP3]], <vscale x 2 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP4]], <vscale x 2 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] undef, <vscale x 2 x i16> [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP7]], <vscale x 2 x i16> [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP9]], <vscale x 2 x i16> [[TMP10]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP11]], <vscale x 2 x i16> [[TMP12]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP13]], <vscale x 2 x i16> [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP15]], <vscale x 2 x i16> [[TMP16]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP17]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP17]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP17]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP17]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg6.mask.nxv2i16.i32(<vscale x 2 x i16> [[TMP18]], <vscale x 2 x i16> [[TMP19]], <vscale x 2 x i16> [[TMP20]], <vscale x 2 x i16> [[TMP21]], <vscale x 2 x i16> [[TMP22]], <vscale x 2 x i16> [[TMP23]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] undef, <vscale x 2 x i16> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP26]], <vscale x 2 x i16> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP28]], <vscale x 2 x i16> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP30]], <vscale x 2 x i16> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP32]], <vscale x 2 x i16> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP34]], <vscale x 2 x i16> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF2X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e16_v_i16mf2x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP3]], <vscale x 2 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP4]], <vscale x 2 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] undef, <vscale x 2 x i16> [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP7]], <vscale x 2 x i16> [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP9]], <vscale x 2 x i16> [[TMP10]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP11]], <vscale x 2 x i16> [[TMP12]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP13]], <vscale x 2 x i16> [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP15]], <vscale x 2 x i16> [[TMP16]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP17]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP17]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP17]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP17]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg6.mask.nxv2i16.i64(<vscale x 2 x i16> [[TMP18]], <vscale x 2 x i16> [[TMP19]], <vscale x 2 x i16> [[TMP20]], <vscale x 2 x i16> [[TMP21]], <vscale x 2 x i16> [[TMP22]], <vscale x 2 x i16> [[TMP23]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] undef, <vscale x 2 x i16> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP26]], <vscale x 2 x i16> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP28]], <vscale x 2 x i16> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP30]], <vscale x 2 x i16> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP32]], <vscale x 2 x i16> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X6_T]] [[TMP34]], <vscale x 2 x i16> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF2X6_T]] [[TMP36]]
+//
+vint16mf2x6_t test_vlseg6e16_v_i16mf2x6_m (vbool32_t mask, vint16mf2x6_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg6e16_v_i16mf2x6_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e16_v_i16mf2x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP3]], <vscale x 2 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP4]], <vscale x 2 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP5]], <vscale x 2 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] undef, <vscale x 2 x i16> [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP8]], <vscale x 2 x i16> [[TMP9]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP10]], <vscale x 2 x i16> [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP12]], <vscale x 2 x i16> [[TMP13]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP14]], <vscale x 2 x i16> [[TMP15]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP16]], <vscale x 2 x i16> [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP18]], <vscale x 2 x i16> [[TMP19]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP20]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg7.mask.nxv2i16.i32(<vscale x 2 x i16> [[TMP21]], <vscale x 2 x i16> [[TMP22]], <vscale x 2 x i16> [[TMP23]], <vscale x 2 x i16> [[TMP24]], <vscale x 2 x i16> [[TMP25]], <vscale x 2 x i16> [[TMP26]], <vscale x 2 x i16> [[TMP27]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] undef, <vscale x 2 x i16> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP30]], <vscale x 2 x i16> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP32]], <vscale x 2 x i16> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP34]], <vscale x 2 x i16> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP36]], <vscale x 2 x i16> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP38]], <vscale x 2 x i16> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP40]], <vscale x 2 x i16> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF2X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e16_v_i16mf2x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP3]], <vscale x 2 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP4]], <vscale x 2 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP5]], <vscale x 2 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] undef, <vscale x 2 x i16> [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP8]], <vscale x 2 x i16> [[TMP9]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP10]], <vscale x 2 x i16> [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP12]], <vscale x 2 x i16> [[TMP13]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP14]], <vscale x 2 x i16> [[TMP15]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP16]], <vscale x 2 x i16> [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP18]], <vscale x 2 x i16> [[TMP19]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP20]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg7.mask.nxv2i16.i64(<vscale x 2 x i16> [[TMP21]], <vscale x 2 x i16> [[TMP22]], <vscale x 2 x i16> [[TMP23]], <vscale x 2 x i16> [[TMP24]], <vscale x 2 x i16> [[TMP25]], <vscale x 2 x i16> [[TMP26]], <vscale x 2 x i16> [[TMP27]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] undef, <vscale x 2 x i16> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP30]], <vscale x 2 x i16> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP32]], <vscale x 2 x i16> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP34]], <vscale x 2 x i16> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP36]], <vscale x 2 x i16> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP38]], <vscale x 2 x i16> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X7_T]] [[TMP40]], <vscale x 2 x i16> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF2X7_T]] [[TMP42]]
+//
+vint16mf2x7_t test_vlseg7e16_v_i16mf2x7_m (vbool32_t mask, vint16mf2x7_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg7e16_v_i16mf2x7_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e16_v_i16mf2x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP3]], <vscale x 2 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP4]], <vscale x 2 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP5]], <vscale x 2 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP6]], <vscale x 2 x i16> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] undef, <vscale x 2 x i16> [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP9]], <vscale x 2 x i16> [[TMP10]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP11]], <vscale x 2 x i16> [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP13]], <vscale x 2 x i16> [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP15]], <vscale x 2 x i16> [[TMP16]], 4
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP17]], <vscale x 2 x i16> [[TMP18]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP19]], <vscale x 2 x i16> [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP21]], <vscale x 2 x i16> [[TMP22]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP23]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP23]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP23]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP23]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP23]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP23]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP23]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg8.mask.nxv2i16.i32(<vscale x 2 x i16> [[TMP24]], <vscale x 2 x i16> [[TMP25]], <vscale x 2 x i16> [[TMP26]], <vscale x 2 x i16> [[TMP27]], <vscale x 2 x i16> [[TMP28]], <vscale x 2 x i16> [[TMP29]], <vscale x 2 x i16> [[TMP30]], <vscale x 2 x i16> [[TMP31]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] undef, <vscale x 2 x i16> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP34]], <vscale x 2 x i16> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP36]], <vscale x 2 x i16> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP38]], <vscale x 2 x i16> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP40]], <vscale x 2 x i16> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP42]], <vscale x 2 x i16> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP44]], <vscale x 2 x i16> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP46]], <vscale x 2 x i16> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16MF2X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e16_v_i16mf2x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP3]], <vscale x 2 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP4]], <vscale x 2 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP5]], <vscale x 2 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP6]], <vscale x 2 x i16> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] undef, <vscale x 2 x i16> [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP9]], <vscale x 2 x i16> [[TMP10]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP11]], <vscale x 2 x i16> [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP13]], <vscale x 2 x i16> [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP15]], <vscale x 2 x i16> [[TMP16]], 4
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP17]], <vscale x 2 x i16> [[TMP18]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP19]], <vscale x 2 x i16> [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP21]], <vscale x 2 x i16> [[TMP22]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP23]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP23]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP23]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP23]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP23]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP23]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP23]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg8.mask.nxv2i16.i64(<vscale x 2 x i16> [[TMP24]], <vscale x 2 x i16> [[TMP25]], <vscale x 2 x i16> [[TMP26]], <vscale x 2 x i16> [[TMP27]], <vscale x 2 x i16> [[TMP28]], <vscale x 2 x i16> [[TMP29]], <vscale x 2 x i16> [[TMP30]], <vscale x 2 x i16> [[TMP31]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] undef, <vscale x 2 x i16> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP34]], <vscale x 2 x i16> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP36]], <vscale x 2 x i16> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP38]], <vscale x 2 x i16> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP40]], <vscale x 2 x i16> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP42]], <vscale x 2 x i16> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP44]], <vscale x 2 x i16> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT16MF2X8_T]] [[TMP46]], <vscale x 2 x i16> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16MF2X8_T]] [[TMP48]]
+//
+vint16mf2x8_t test_vlseg8e16_v_i16mf2x8_m (vbool32_t mask, vint16mf2x8_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg8e16_v_i16mf2x8_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e16_v_i16m1x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X2_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X2_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X2_T]] undef, <vscale x 4 x i16> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X2_T]] [[TMP3]], <vscale x 4 x i16> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg2.mask.nxv4i16.i32(<vscale x 4 x i16> [[TMP6]], <vscale x 4 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X2_T]] undef, <vscale x 4 x i16> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X2_T]] [[TMP10]], <vscale x 4 x i16> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16M1X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e16_v_i16m1x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X2_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X2_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X2_T]] undef, <vscale x 4 x i16> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X2_T]] [[TMP3]], <vscale x 4 x i16> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg2.mask.nxv4i16.i64(<vscale x 4 x i16> [[TMP6]], <vscale x 4 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X2_T]] undef, <vscale x 4 x i16> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X2_T]] [[TMP10]], <vscale x 4 x i16> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16M1X2_T]] [[TMP12]]
+//
+vint16m1x2_t test_vlseg2e16_v_i16m1x2_m (vbool16_t mask, vint16m1x2_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg2e16_v_i16m1x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e16_v_i16m1x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T]] undef, <vscale x 4 x i16> [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP4]], <vscale x 4 x i16> [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP6]], <vscale x 4 x i16> [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg3.mask.nxv4i16.i32(<vscale x 4 x i16> [[TMP9]], <vscale x 4 x i16> [[TMP10]], <vscale x 4 x i16> [[TMP11]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T]] undef, <vscale x 4 x i16> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP14]], <vscale x 4 x i16> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP16]], <vscale x 4 x i16> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16M1X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e16_v_i16m1x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T]] undef, <vscale x 4 x i16> [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP4]], <vscale x 4 x i16> [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP6]], <vscale x 4 x i16> [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg3.mask.nxv4i16.i64(<vscale x 4 x i16> [[TMP9]], <vscale x 4 x i16> [[TMP10]], <vscale x 4 x i16> [[TMP11]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T]] undef, <vscale x 4 x i16> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP14]], <vscale x 4 x i16> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X3_T]] [[TMP16]], <vscale x 4 x i16> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16M1X3_T]] [[TMP18]]
+//
+vint16m1x3_t test_vlseg3e16_v_i16m1x3_m (vbool16_t mask, vint16m1x3_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg3e16_v_i16m1x3_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e16_v_i16m1x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] undef, <vscale x 4 x i16> [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP5]], <vscale x 4 x i16> [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP7]], <vscale x 4 x i16> [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP9]], <vscale x 4 x i16> [[TMP10]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP11]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP11]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg4.mask.nxv4i16.i32(<vscale x 4 x i16> [[TMP12]], <vscale x 4 x i16> [[TMP13]], <vscale x 4 x i16> [[TMP14]], <vscale x 4 x i16> [[TMP15]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] undef, <vscale x 4 x i16> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP18]], <vscale x 4 x i16> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP20]], <vscale x 4 x i16> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP22]], <vscale x 4 x i16> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16M1X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e16_v_i16m1x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] undef, <vscale x 4 x i16> [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP5]], <vscale x 4 x i16> [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP7]], <vscale x 4 x i16> [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP9]], <vscale x 4 x i16> [[TMP10]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP11]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP11]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg4.mask.nxv4i16.i64(<vscale x 4 x i16> [[TMP12]], <vscale x 4 x i16> [[TMP13]], <vscale x 4 x i16> [[TMP14]], <vscale x 4 x i16> [[TMP15]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] undef, <vscale x 4 x i16> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP18]], <vscale x 4 x i16> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP20]], <vscale x 4 x i16> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X4_T]] [[TMP22]], <vscale x 4 x i16> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16M1X4_T]] [[TMP24]]
+//
+vint16m1x4_t test_vlseg4e16_v_i16m1x4_m (vbool16_t mask, vint16m1x4_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg4e16_v_i16m1x4_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e16_v_i16m1x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP3]], <vscale x 4 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] undef, <vscale x 4 x i16> [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP6]], <vscale x 4 x i16> [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP8]], <vscale x 4 x i16> [[TMP9]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP10]], <vscale x 4 x i16> [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP12]], <vscale x 4 x i16> [[TMP13]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP14]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP14]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP14]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg5.mask.nxv4i16.i32(<vscale x 4 x i16> [[TMP15]], <vscale x 4 x i16> [[TMP16]], <vscale x 4 x i16> [[TMP17]], <vscale x 4 x i16> [[TMP18]], <vscale x 4 x i16> [[TMP19]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] undef, <vscale x 4 x i16> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP22]], <vscale x 4 x i16> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP24]], <vscale x 4 x i16> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP26]], <vscale x 4 x i16> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP28]], <vscale x 4 x i16> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16M1X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e16_v_i16m1x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP3]], <vscale x 4 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] undef, <vscale x 4 x i16> [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP6]], <vscale x 4 x i16> [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP8]], <vscale x 4 x i16> [[TMP9]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP10]], <vscale x 4 x i16> [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP12]], <vscale x 4 x i16> [[TMP13]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP14]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP14]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP14]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg5.mask.nxv4i16.i64(<vscale x 4 x i16> [[TMP15]], <vscale x 4 x i16> [[TMP16]], <vscale x 4 x i16> [[TMP17]], <vscale x 4 x i16> [[TMP18]], <vscale x 4 x i16> [[TMP19]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] undef, <vscale x 4 x i16> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP22]], <vscale x 4 x i16> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP24]], <vscale x 4 x i16> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP26]], <vscale x 4 x i16> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X5_T]] [[TMP28]], <vscale x 4 x i16> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16M1X5_T]] [[TMP30]]
+//
+vint16m1x5_t test_vlseg5e16_v_i16m1x5_m (vbool16_t mask, vint16m1x5_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg5e16_v_i16m1x5_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e16_v_i16m1x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP3]], <vscale x 4 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP4]], <vscale x 4 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] undef, <vscale x 4 x i16> [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP7]], <vscale x 4 x i16> [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP9]], <vscale x 4 x i16> [[TMP10]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP11]], <vscale x 4 x i16> [[TMP12]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP13]], <vscale x 4 x i16> [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP15]], <vscale x 4 x i16> [[TMP16]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP17]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP17]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP17]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP17]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg6.mask.nxv4i16.i32(<vscale x 4 x i16> [[TMP18]], <vscale x 4 x i16> [[TMP19]], <vscale x 4 x i16> [[TMP20]], <vscale x 4 x i16> [[TMP21]], <vscale x 4 x i16> [[TMP22]], <vscale x 4 x i16> [[TMP23]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] undef, <vscale x 4 x i16> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP26]], <vscale x 4 x i16> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP28]], <vscale x 4 x i16> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP30]], <vscale x 4 x i16> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP32]], <vscale x 4 x i16> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP34]], <vscale x 4 x i16> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16M1X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e16_v_i16m1x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP3]], <vscale x 4 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP4]], <vscale x 4 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] undef, <vscale x 4 x i16> [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP7]], <vscale x 4 x i16> [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP9]], <vscale x 4 x i16> [[TMP10]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP11]], <vscale x 4 x i16> [[TMP12]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP13]], <vscale x 4 x i16> [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP15]], <vscale x 4 x i16> [[TMP16]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP17]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP17]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP17]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP17]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg6.mask.nxv4i16.i64(<vscale x 4 x i16> [[TMP18]], <vscale x 4 x i16> [[TMP19]], <vscale x 4 x i16> [[TMP20]], <vscale x 4 x i16> [[TMP21]], <vscale x 4 x i16> [[TMP22]], <vscale x 4 x i16> [[TMP23]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] undef, <vscale x 4 x i16> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP26]], <vscale x 4 x i16> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP28]], <vscale x 4 x i16> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP30]], <vscale x 4 x i16> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP32]], <vscale x 4 x i16> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X6_T]] [[TMP34]], <vscale x 4 x i16> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16M1X6_T]] [[TMP36]]
+//
+vint16m1x6_t test_vlseg6e16_v_i16m1x6_m (vbool16_t mask, vint16m1x6_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg6e16_v_i16m1x6_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e16_v_i16m1x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP3]], <vscale x 4 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP4]], <vscale x 4 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP5]], <vscale x 4 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] undef, <vscale x 4 x i16> [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP8]], <vscale x 4 x i16> [[TMP9]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP10]], <vscale x 4 x i16> [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP12]], <vscale x 4 x i16> [[TMP13]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP14]], <vscale x 4 x i16> [[TMP15]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP16]], <vscale x 4 x i16> [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP18]], <vscale x 4 x i16> [[TMP19]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP20]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg7.mask.nxv4i16.i32(<vscale x 4 x i16> [[TMP21]], <vscale x 4 x i16> [[TMP22]], <vscale x 4 x i16> [[TMP23]], <vscale x 4 x i16> [[TMP24]], <vscale x 4 x i16> [[TMP25]], <vscale x 4 x i16> [[TMP26]], <vscale x 4 x i16> [[TMP27]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] undef, <vscale x 4 x i16> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP30]], <vscale x 4 x i16> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP32]], <vscale x 4 x i16> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP34]], <vscale x 4 x i16> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP36]], <vscale x 4 x i16> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP38]], <vscale x 4 x i16> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP40]], <vscale x 4 x i16> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16M1X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e16_v_i16m1x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP3]], <vscale x 4 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP4]], <vscale x 4 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP5]], <vscale x 4 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] undef, <vscale x 4 x i16> [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP8]], <vscale x 4 x i16> [[TMP9]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP10]], <vscale x 4 x i16> [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP12]], <vscale x 4 x i16> [[TMP13]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP14]], <vscale x 4 x i16> [[TMP15]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP16]], <vscale x 4 x i16> [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP18]], <vscale x 4 x i16> [[TMP19]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP20]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg7.mask.nxv4i16.i64(<vscale x 4 x i16> [[TMP21]], <vscale x 4 x i16> [[TMP22]], <vscale x 4 x i16> [[TMP23]], <vscale x 4 x i16> [[TMP24]], <vscale x 4 x i16> [[TMP25]], <vscale x 4 x i16> [[TMP26]], <vscale x 4 x i16> [[TMP27]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] undef, <vscale x 4 x i16> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP30]], <vscale x 4 x i16> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP32]], <vscale x 4 x i16> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP34]], <vscale x 4 x i16> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP36]], <vscale x 4 x i16> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP38]], <vscale x 4 x i16> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X7_T]] [[TMP40]], <vscale x 4 x i16> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16M1X7_T]] [[TMP42]]
+//
+vint16m1x7_t test_vlseg7e16_v_i16m1x7_m (vbool16_t mask, vint16m1x7_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg7e16_v_i16m1x7_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e16_v_i16m1x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP3]], <vscale x 4 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP4]], <vscale x 4 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP5]], <vscale x 4 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP6]], <vscale x 4 x i16> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] undef, <vscale x 4 x i16> [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP9]], <vscale x 4 x i16> [[TMP10]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP11]], <vscale x 4 x i16> [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP13]], <vscale x 4 x i16> [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP15]], <vscale x 4 x i16> [[TMP16]], 4
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP17]], <vscale x 4 x i16> [[TMP18]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP19]], <vscale x 4 x i16> [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP21]], <vscale x 4 x i16> [[TMP22]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP23]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP23]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP23]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP23]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP23]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP23]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP23]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg8.mask.nxv4i16.i32(<vscale x 4 x i16> [[TMP24]], <vscale x 4 x i16> [[TMP25]], <vscale x 4 x i16> [[TMP26]], <vscale x 4 x i16> [[TMP27]], <vscale x 4 x i16> [[TMP28]], <vscale x 4 x i16> [[TMP29]], <vscale x 4 x i16> [[TMP30]], <vscale x 4 x i16> [[TMP31]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] undef, <vscale x 4 x i16> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP34]], <vscale x 4 x i16> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP36]], <vscale x 4 x i16> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP38]], <vscale x 4 x i16> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP40]], <vscale x 4 x i16> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP42]], <vscale x 4 x i16> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP44]], <vscale x 4 x i16> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP46]], <vscale x 4 x i16> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16M1X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e16_v_i16m1x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP3]], <vscale x 4 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP4]], <vscale x 4 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP5]], <vscale x 4 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP6]], <vscale x 4 x i16> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] undef, <vscale x 4 x i16> [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP9]], <vscale x 4 x i16> [[TMP10]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP11]], <vscale x 4 x i16> [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP13]], <vscale x 4 x i16> [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP15]], <vscale x 4 x i16> [[TMP16]], 4
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP17]], <vscale x 4 x i16> [[TMP18]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP19]], <vscale x 4 x i16> [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP21]], <vscale x 4 x i16> [[TMP22]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP23]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP23]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP23]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP23]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP23]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP23]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP23]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg8.mask.nxv4i16.i64(<vscale x 4 x i16> [[TMP24]], <vscale x 4 x i16> [[TMP25]], <vscale x 4 x i16> [[TMP26]], <vscale x 4 x i16> [[TMP27]], <vscale x 4 x i16> [[TMP28]], <vscale x 4 x i16> [[TMP29]], <vscale x 4 x i16> [[TMP30]], <vscale x 4 x i16> [[TMP31]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] undef, <vscale x 4 x i16> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP34]], <vscale x 4 x i16> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP36]], <vscale x 4 x i16> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP38]], <vscale x 4 x i16> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP40]], <vscale x 4 x i16> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP42]], <vscale x 4 x i16> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP44]], <vscale x 4 x i16> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT16M1X8_T]] [[TMP46]], <vscale x 4 x i16> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16M1X8_T]] [[TMP48]]
+//
+vint16m1x8_t test_vlseg8e16_v_i16m1x8_m (vbool16_t mask, vint16m1x8_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg8e16_v_i16m1x8_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e16_v_i16m2x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X2_T:%.*]] undef, <vscale x 8 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X2_T]] [[TMP0]], <vscale x 8 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X2_T]] undef, <vscale x 8 x i16> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X2_T]] [[TMP3]], <vscale x 8 x i16> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg2.mask.nxv8i16.i32(<vscale x 8 x i16> [[TMP6]], <vscale x 8 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X2_T]] undef, <vscale x 8 x i16> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X2_T]] [[TMP10]], <vscale x 8 x i16> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16M2X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e16_v_i16m2x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X2_T:%.*]] undef, <vscale x 8 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X2_T]] [[TMP0]], <vscale x 8 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X2_T]] undef, <vscale x 8 x i16> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X2_T]] [[TMP3]], <vscale x 8 x i16> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg2.mask.nxv8i16.i64(<vscale x 8 x i16> [[TMP6]], <vscale x 8 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X2_T]] undef, <vscale x 8 x i16> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X2_T]] [[TMP10]], <vscale x 8 x i16> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16M2X2_T]] [[TMP12]]
+//
+vint16m2x2_t test_vlseg2e16_v_i16m2x2_m (vbool8_t mask, vint16m2x2_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg2e16_v_i16m2x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e16_v_i16m2x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T:%.*]] undef, <vscale x 8 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP0]], <vscale x 8 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP1]], <vscale x 8 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T]] undef, <vscale x 8 x i16> [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP4]], <vscale x 8 x i16> [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP6]], <vscale x 8 x i16> [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg3.mask.nxv8i16.i32(<vscale x 8 x i16> [[TMP9]], <vscale x 8 x i16> [[TMP10]], <vscale x 8 x i16> [[TMP11]], i16* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T]] undef, <vscale x 8 x i16> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP14]], <vscale x 8 x i16> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP16]], <vscale x 8 x i16> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16M2X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e16_v_i16m2x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T:%.*]] undef, <vscale x 8 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP0]], <vscale x 8 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP1]], <vscale x 8 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T]] undef, <vscale x 8 x i16> [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP4]], <vscale x 8 x i16> [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP6]], <vscale x 8 x i16> [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg3.mask.nxv8i16.i64(<vscale x 8 x i16> [[TMP9]], <vscale x 8 x i16> [[TMP10]], <vscale x 8 x i16> [[TMP11]], i16* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T]] undef, <vscale x 8 x i16> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP14]], <vscale x 8 x i16> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X3_T]] [[TMP16]], <vscale x 8 x i16> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16M2X3_T]] [[TMP18]]
+//
+vint16m2x3_t test_vlseg3e16_v_i16m2x3_m (vbool8_t mask, vint16m2x3_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg3e16_v_i16m2x3_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e16_v_i16m2x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T:%.*]] undef, <vscale x 8 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP0]], <vscale x 8 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP1]], <vscale x 8 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP2]], <vscale x 8 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] undef, <vscale x 8 x i16> [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP5]], <vscale x 8 x i16> [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP7]], <vscale x 8 x i16> [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP9]], <vscale x 8 x i16> [[TMP10]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP11]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP11]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg4.mask.nxv8i16.i32(<vscale x 8 x i16> [[TMP12]], <vscale x 8 x i16> [[TMP13]], <vscale x 8 x i16> [[TMP14]], <vscale x 8 x i16> [[TMP15]], i16* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] undef, <vscale x 8 x i16> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP18]], <vscale x 8 x i16> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP20]], <vscale x 8 x i16> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP22]], <vscale x 8 x i16> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16M2X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e16_v_i16m2x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T:%.*]] undef, <vscale x 8 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP0]], <vscale x 8 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP1]], <vscale x 8 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP2]], <vscale x 8 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] undef, <vscale x 8 x i16> [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP5]], <vscale x 8 x i16> [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP7]], <vscale x 8 x i16> [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP9]], <vscale x 8 x i16> [[TMP10]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP11]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP11]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg4.mask.nxv8i16.i64(<vscale x 8 x i16> [[TMP12]], <vscale x 8 x i16> [[TMP13]], <vscale x 8 x i16> [[TMP14]], <vscale x 8 x i16> [[TMP15]], i16* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] undef, <vscale x 8 x i16> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP18]], <vscale x 8 x i16> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP20]], <vscale x 8 x i16> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT16M2X4_T]] [[TMP22]], <vscale x 8 x i16> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16M2X4_T]] [[TMP24]]
+//
+vint16m2x4_t test_vlseg4e16_v_i16m2x4_m (vbool8_t mask, vint16m2x4_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg4e16_v_i16m2x4_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e16_v_i16m4x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M4X2_T:%.*]] undef, <vscale x 16 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M4X2_T]] [[TMP0]], <vscale x 16 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT16M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16M4X2_T]] undef, <vscale x 16 x i16> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16M4X2_T]] [[TMP3]], <vscale x 16 x i16> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16M4X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16M4X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 16 x i16>, <vscale x 16 x i16> } @llvm.riscv.vlseg2.mask.nxv16i16.i32(<vscale x 16 x i16> [[TMP6]], <vscale x 16 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i16> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16M4X2_T]] undef, <vscale x 16 x i16> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i16> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16M4X2_T]] [[TMP10]], <vscale x 16 x i16> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT16M4X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e16_v_i16m4x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT16M4X2_T:%.*]] undef, <vscale x 16 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT16M4X2_T]] [[TMP0]], <vscale x 16 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT16M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT16M4X2_T]] undef, <vscale x 16 x i16> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT16M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT16M4X2_T]] [[TMP3]], <vscale x 16 x i16> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT16M4X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT16M4X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 16 x i16>, <vscale x 16 x i16> } @llvm.riscv.vlseg2.mask.nxv16i16.i64(<vscale x 16 x i16> [[TMP6]], <vscale x 16 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i16> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT16M4X2_T]] undef, <vscale x 16 x i16> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i16> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT16M4X2_T]] [[TMP10]], <vscale x 16 x i16> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT16M4X2_T]] [[TMP12]]
+//
+vint16m4x2_t test_vlseg2e16_v_i16m4x2_m (vbool4_t mask, vint16m4x2_t maskedoff, const int16_t *base, size_t vl) {
+  return vlseg2e16_v_i16m4x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_i32mf2x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X2_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X2_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X2_T]] undef, <vscale x 1 x i32> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X2_T]] [[TMP3]], <vscale x 1 x i32> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg2.mask.nxv1i32.i32(<vscale x 1 x i32> [[TMP6]], <vscale x 1 x i32> [[TMP7]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X2_T]] undef, <vscale x 1 x i32> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X2_T]] [[TMP10]], <vscale x 1 x i32> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32MF2X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_i32mf2x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X2_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X2_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X2_T]] undef, <vscale x 1 x i32> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X2_T]] [[TMP3]], <vscale x 1 x i32> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg2.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP6]], <vscale x 1 x i32> [[TMP7]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X2_T]] undef, <vscale x 1 x i32> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X2_T]] [[TMP10]], <vscale x 1 x i32> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32MF2X2_T]] [[TMP12]]
+//
+vint32mf2x2_t test_vlseg2e32_v_i32mf2x2_m (vbool64_t mask, vint32mf2x2_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg2e32_v_i32mf2x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e32_v_i32mf2x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T]] undef, <vscale x 1 x i32> [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP4]], <vscale x 1 x i32> [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP6]], <vscale x 1 x i32> [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg3.mask.nxv1i32.i32(<vscale x 1 x i32> [[TMP9]], <vscale x 1 x i32> [[TMP10]], <vscale x 1 x i32> [[TMP11]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T]] undef, <vscale x 1 x i32> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP14]], <vscale x 1 x i32> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP16]], <vscale x 1 x i32> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32MF2X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e32_v_i32mf2x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T]] undef, <vscale x 1 x i32> [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP4]], <vscale x 1 x i32> [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP6]], <vscale x 1 x i32> [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg3.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP9]], <vscale x 1 x i32> [[TMP10]], <vscale x 1 x i32> [[TMP11]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T]] undef, <vscale x 1 x i32> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP14]], <vscale x 1 x i32> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X3_T]] [[TMP16]], <vscale x 1 x i32> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32MF2X3_T]] [[TMP18]]
+//
+vint32mf2x3_t test_vlseg3e32_v_i32mf2x3_m (vbool64_t mask, vint32mf2x3_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg3e32_v_i32mf2x3_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e32_v_i32mf2x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] undef, <vscale x 1 x i32> [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP5]], <vscale x 1 x i32> [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP7]], <vscale x 1 x i32> [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP9]], <vscale x 1 x i32> [[TMP10]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP11]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP11]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg4.mask.nxv1i32.i32(<vscale x 1 x i32> [[TMP12]], <vscale x 1 x i32> [[TMP13]], <vscale x 1 x i32> [[TMP14]], <vscale x 1 x i32> [[TMP15]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] undef, <vscale x 1 x i32> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP18]], <vscale x 1 x i32> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP20]], <vscale x 1 x i32> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP22]], <vscale x 1 x i32> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32MF2X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e32_v_i32mf2x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] undef, <vscale x 1 x i32> [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP5]], <vscale x 1 x i32> [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP7]], <vscale x 1 x i32> [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP9]], <vscale x 1 x i32> [[TMP10]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP11]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP11]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg4.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP12]], <vscale x 1 x i32> [[TMP13]], <vscale x 1 x i32> [[TMP14]], <vscale x 1 x i32> [[TMP15]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] undef, <vscale x 1 x i32> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP18]], <vscale x 1 x i32> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP20]], <vscale x 1 x i32> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X4_T]] [[TMP22]], <vscale x 1 x i32> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32MF2X4_T]] [[TMP24]]
+//
+vint32mf2x4_t test_vlseg4e32_v_i32mf2x4_m (vbool64_t mask, vint32mf2x4_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg4e32_v_i32mf2x4_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e32_v_i32mf2x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP3]], <vscale x 1 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] undef, <vscale x 1 x i32> [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP6]], <vscale x 1 x i32> [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP8]], <vscale x 1 x i32> [[TMP9]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP10]], <vscale x 1 x i32> [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP12]], <vscale x 1 x i32> [[TMP13]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP14]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP14]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP14]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg5.mask.nxv1i32.i32(<vscale x 1 x i32> [[TMP15]], <vscale x 1 x i32> [[TMP16]], <vscale x 1 x i32> [[TMP17]], <vscale x 1 x i32> [[TMP18]], <vscale x 1 x i32> [[TMP19]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] undef, <vscale x 1 x i32> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP22]], <vscale x 1 x i32> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP24]], <vscale x 1 x i32> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP26]], <vscale x 1 x i32> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP28]], <vscale x 1 x i32> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32MF2X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e32_v_i32mf2x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP3]], <vscale x 1 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] undef, <vscale x 1 x i32> [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP6]], <vscale x 1 x i32> [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP8]], <vscale x 1 x i32> [[TMP9]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP10]], <vscale x 1 x i32> [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP12]], <vscale x 1 x i32> [[TMP13]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP14]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP14]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP14]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg5.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP15]], <vscale x 1 x i32> [[TMP16]], <vscale x 1 x i32> [[TMP17]], <vscale x 1 x i32> [[TMP18]], <vscale x 1 x i32> [[TMP19]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] undef, <vscale x 1 x i32> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP22]], <vscale x 1 x i32> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP24]], <vscale x 1 x i32> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP26]], <vscale x 1 x i32> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X5_T]] [[TMP28]], <vscale x 1 x i32> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32MF2X5_T]] [[TMP30]]
+//
+vint32mf2x5_t test_vlseg5e32_v_i32mf2x5_m (vbool64_t mask, vint32mf2x5_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg5e32_v_i32mf2x5_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e32_v_i32mf2x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP3]], <vscale x 1 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP4]], <vscale x 1 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] undef, <vscale x 1 x i32> [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP7]], <vscale x 1 x i32> [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP9]], <vscale x 1 x i32> [[TMP10]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP11]], <vscale x 1 x i32> [[TMP12]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP13]], <vscale x 1 x i32> [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP15]], <vscale x 1 x i32> [[TMP16]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP17]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP17]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP17]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP17]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg6.mask.nxv1i32.i32(<vscale x 1 x i32> [[TMP18]], <vscale x 1 x i32> [[TMP19]], <vscale x 1 x i32> [[TMP20]], <vscale x 1 x i32> [[TMP21]], <vscale x 1 x i32> [[TMP22]], <vscale x 1 x i32> [[TMP23]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] undef, <vscale x 1 x i32> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP26]], <vscale x 1 x i32> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP28]], <vscale x 1 x i32> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP30]], <vscale x 1 x i32> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP32]], <vscale x 1 x i32> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP34]], <vscale x 1 x i32> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32MF2X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e32_v_i32mf2x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP3]], <vscale x 1 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP4]], <vscale x 1 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] undef, <vscale x 1 x i32> [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP7]], <vscale x 1 x i32> [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP9]], <vscale x 1 x i32> [[TMP10]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP11]], <vscale x 1 x i32> [[TMP12]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP13]], <vscale x 1 x i32> [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP15]], <vscale x 1 x i32> [[TMP16]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP17]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP17]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP17]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP17]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg6.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP18]], <vscale x 1 x i32> [[TMP19]], <vscale x 1 x i32> [[TMP20]], <vscale x 1 x i32> [[TMP21]], <vscale x 1 x i32> [[TMP22]], <vscale x 1 x i32> [[TMP23]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] undef, <vscale x 1 x i32> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP26]], <vscale x 1 x i32> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP28]], <vscale x 1 x i32> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP30]], <vscale x 1 x i32> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP32]], <vscale x 1 x i32> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X6_T]] [[TMP34]], <vscale x 1 x i32> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32MF2X6_T]] [[TMP36]]
+//
+vint32mf2x6_t test_vlseg6e32_v_i32mf2x6_m (vbool64_t mask, vint32mf2x6_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg6e32_v_i32mf2x6_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e32_v_i32mf2x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP3]], <vscale x 1 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP4]], <vscale x 1 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP5]], <vscale x 1 x i32> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] undef, <vscale x 1 x i32> [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP8]], <vscale x 1 x i32> [[TMP9]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP10]], <vscale x 1 x i32> [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP12]], <vscale x 1 x i32> [[TMP13]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP14]], <vscale x 1 x i32> [[TMP15]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP16]], <vscale x 1 x i32> [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP18]], <vscale x 1 x i32> [[TMP19]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP20]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg7.mask.nxv1i32.i32(<vscale x 1 x i32> [[TMP21]], <vscale x 1 x i32> [[TMP22]], <vscale x 1 x i32> [[TMP23]], <vscale x 1 x i32> [[TMP24]], <vscale x 1 x i32> [[TMP25]], <vscale x 1 x i32> [[TMP26]], <vscale x 1 x i32> [[TMP27]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] undef, <vscale x 1 x i32> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP30]], <vscale x 1 x i32> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP32]], <vscale x 1 x i32> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP34]], <vscale x 1 x i32> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP36]], <vscale x 1 x i32> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP38]], <vscale x 1 x i32> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP40]], <vscale x 1 x i32> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32MF2X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e32_v_i32mf2x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP3]], <vscale x 1 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP4]], <vscale x 1 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP5]], <vscale x 1 x i32> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] undef, <vscale x 1 x i32> [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP8]], <vscale x 1 x i32> [[TMP9]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP10]], <vscale x 1 x i32> [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP12]], <vscale x 1 x i32> [[TMP13]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP14]], <vscale x 1 x i32> [[TMP15]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP16]], <vscale x 1 x i32> [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP18]], <vscale x 1 x i32> [[TMP19]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP20]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg7.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP21]], <vscale x 1 x i32> [[TMP22]], <vscale x 1 x i32> [[TMP23]], <vscale x 1 x i32> [[TMP24]], <vscale x 1 x i32> [[TMP25]], <vscale x 1 x i32> [[TMP26]], <vscale x 1 x i32> [[TMP27]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] undef, <vscale x 1 x i32> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP30]], <vscale x 1 x i32> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP32]], <vscale x 1 x i32> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP34]], <vscale x 1 x i32> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP36]], <vscale x 1 x i32> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP38]], <vscale x 1 x i32> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X7_T]] [[TMP40]], <vscale x 1 x i32> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32MF2X7_T]] [[TMP42]]
+//
+vint32mf2x7_t test_vlseg7e32_v_i32mf2x7_m (vbool64_t mask, vint32mf2x7_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg7e32_v_i32mf2x7_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e32_v_i32mf2x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP3]], <vscale x 1 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP4]], <vscale x 1 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP5]], <vscale x 1 x i32> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP6]], <vscale x 1 x i32> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] undef, <vscale x 1 x i32> [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP9]], <vscale x 1 x i32> [[TMP10]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP11]], <vscale x 1 x i32> [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP13]], <vscale x 1 x i32> [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP15]], <vscale x 1 x i32> [[TMP16]], 4
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP17]], <vscale x 1 x i32> [[TMP18]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP19]], <vscale x 1 x i32> [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP21]], <vscale x 1 x i32> [[TMP22]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP23]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP23]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP23]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP23]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP23]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP23]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP23]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg8.mask.nxv1i32.i32(<vscale x 1 x i32> [[TMP24]], <vscale x 1 x i32> [[TMP25]], <vscale x 1 x i32> [[TMP26]], <vscale x 1 x i32> [[TMP27]], <vscale x 1 x i32> [[TMP28]], <vscale x 1 x i32> [[TMP29]], <vscale x 1 x i32> [[TMP30]], <vscale x 1 x i32> [[TMP31]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] undef, <vscale x 1 x i32> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP34]], <vscale x 1 x i32> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP36]], <vscale x 1 x i32> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP38]], <vscale x 1 x i32> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP40]], <vscale x 1 x i32> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP42]], <vscale x 1 x i32> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP44]], <vscale x 1 x i32> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP46]], <vscale x 1 x i32> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32MF2X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e32_v_i32mf2x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP3]], <vscale x 1 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP4]], <vscale x 1 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP5]], <vscale x 1 x i32> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP6]], <vscale x 1 x i32> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] undef, <vscale x 1 x i32> [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP9]], <vscale x 1 x i32> [[TMP10]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP11]], <vscale x 1 x i32> [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP13]], <vscale x 1 x i32> [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP15]], <vscale x 1 x i32> [[TMP16]], 4
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP17]], <vscale x 1 x i32> [[TMP18]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP19]], <vscale x 1 x i32> [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP21]], <vscale x 1 x i32> [[TMP22]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP23]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP23]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP23]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP23]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP23]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP23]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP23]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg8.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP24]], <vscale x 1 x i32> [[TMP25]], <vscale x 1 x i32> [[TMP26]], <vscale x 1 x i32> [[TMP27]], <vscale x 1 x i32> [[TMP28]], <vscale x 1 x i32> [[TMP29]], <vscale x 1 x i32> [[TMP30]], <vscale x 1 x i32> [[TMP31]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] undef, <vscale x 1 x i32> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP34]], <vscale x 1 x i32> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP36]], <vscale x 1 x i32> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP38]], <vscale x 1 x i32> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP40]], <vscale x 1 x i32> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP42]], <vscale x 1 x i32> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP44]], <vscale x 1 x i32> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT32MF2X8_T]] [[TMP46]], <vscale x 1 x i32> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32MF2X8_T]] [[TMP48]]
+//
+vint32mf2x8_t test_vlseg8e32_v_i32mf2x8_m (vbool64_t mask, vint32mf2x8_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg8e32_v_i32mf2x8_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_i32m1x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X2_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X2_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X2_T]] undef, <vscale x 2 x i32> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X2_T]] [[TMP3]], <vscale x 2 x i32> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg2.mask.nxv2i32.i32(<vscale x 2 x i32> [[TMP6]], <vscale x 2 x i32> [[TMP7]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X2_T]] undef, <vscale x 2 x i32> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X2_T]] [[TMP10]], <vscale x 2 x i32> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32M1X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_i32m1x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X2_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X2_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X2_T]] undef, <vscale x 2 x i32> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X2_T]] [[TMP3]], <vscale x 2 x i32> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg2.mask.nxv2i32.i64(<vscale x 2 x i32> [[TMP6]], <vscale x 2 x i32> [[TMP7]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X2_T]] undef, <vscale x 2 x i32> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X2_T]] [[TMP10]], <vscale x 2 x i32> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32M1X2_T]] [[TMP12]]
+//
+vint32m1x2_t test_vlseg2e32_v_i32m1x2_m (vbool32_t mask, vint32m1x2_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg2e32_v_i32m1x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e32_v_i32m1x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T]] undef, <vscale x 2 x i32> [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP4]], <vscale x 2 x i32> [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP6]], <vscale x 2 x i32> [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg3.mask.nxv2i32.i32(<vscale x 2 x i32> [[TMP9]], <vscale x 2 x i32> [[TMP10]], <vscale x 2 x i32> [[TMP11]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T]] undef, <vscale x 2 x i32> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP14]], <vscale x 2 x i32> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP16]], <vscale x 2 x i32> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32M1X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e32_v_i32m1x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T]] undef, <vscale x 2 x i32> [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP4]], <vscale x 2 x i32> [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP6]], <vscale x 2 x i32> [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg3.mask.nxv2i32.i64(<vscale x 2 x i32> [[TMP9]], <vscale x 2 x i32> [[TMP10]], <vscale x 2 x i32> [[TMP11]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T]] undef, <vscale x 2 x i32> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP14]], <vscale x 2 x i32> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X3_T]] [[TMP16]], <vscale x 2 x i32> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32M1X3_T]] [[TMP18]]
+//
+vint32m1x3_t test_vlseg3e32_v_i32m1x3_m (vbool32_t mask, vint32m1x3_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg3e32_v_i32m1x3_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e32_v_i32m1x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] undef, <vscale x 2 x i32> [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP5]], <vscale x 2 x i32> [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP7]], <vscale x 2 x i32> [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP9]], <vscale x 2 x i32> [[TMP10]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP11]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP11]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg4.mask.nxv2i32.i32(<vscale x 2 x i32> [[TMP12]], <vscale x 2 x i32> [[TMP13]], <vscale x 2 x i32> [[TMP14]], <vscale x 2 x i32> [[TMP15]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] undef, <vscale x 2 x i32> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP18]], <vscale x 2 x i32> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP20]], <vscale x 2 x i32> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP22]], <vscale x 2 x i32> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32M1X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e32_v_i32m1x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] undef, <vscale x 2 x i32> [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP5]], <vscale x 2 x i32> [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP7]], <vscale x 2 x i32> [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP9]], <vscale x 2 x i32> [[TMP10]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP11]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP11]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg4.mask.nxv2i32.i64(<vscale x 2 x i32> [[TMP12]], <vscale x 2 x i32> [[TMP13]], <vscale x 2 x i32> [[TMP14]], <vscale x 2 x i32> [[TMP15]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] undef, <vscale x 2 x i32> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP18]], <vscale x 2 x i32> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP20]], <vscale x 2 x i32> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X4_T]] [[TMP22]], <vscale x 2 x i32> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32M1X4_T]] [[TMP24]]
+//
+vint32m1x4_t test_vlseg4e32_v_i32m1x4_m (vbool32_t mask, vint32m1x4_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg4e32_v_i32m1x4_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e32_v_i32m1x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP3]], <vscale x 2 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] undef, <vscale x 2 x i32> [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP6]], <vscale x 2 x i32> [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP8]], <vscale x 2 x i32> [[TMP9]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP10]], <vscale x 2 x i32> [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP12]], <vscale x 2 x i32> [[TMP13]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP14]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP14]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP14]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg5.mask.nxv2i32.i32(<vscale x 2 x i32> [[TMP15]], <vscale x 2 x i32> [[TMP16]], <vscale x 2 x i32> [[TMP17]], <vscale x 2 x i32> [[TMP18]], <vscale x 2 x i32> [[TMP19]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] undef, <vscale x 2 x i32> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP22]], <vscale x 2 x i32> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP24]], <vscale x 2 x i32> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP26]], <vscale x 2 x i32> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP28]], <vscale x 2 x i32> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32M1X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e32_v_i32m1x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP3]], <vscale x 2 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] undef, <vscale x 2 x i32> [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP6]], <vscale x 2 x i32> [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP8]], <vscale x 2 x i32> [[TMP9]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP10]], <vscale x 2 x i32> [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP12]], <vscale x 2 x i32> [[TMP13]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP14]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP14]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP14]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg5.mask.nxv2i32.i64(<vscale x 2 x i32> [[TMP15]], <vscale x 2 x i32> [[TMP16]], <vscale x 2 x i32> [[TMP17]], <vscale x 2 x i32> [[TMP18]], <vscale x 2 x i32> [[TMP19]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] undef, <vscale x 2 x i32> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP22]], <vscale x 2 x i32> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP24]], <vscale x 2 x i32> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP26]], <vscale x 2 x i32> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X5_T]] [[TMP28]], <vscale x 2 x i32> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32M1X5_T]] [[TMP30]]
+//
+vint32m1x5_t test_vlseg5e32_v_i32m1x5_m (vbool32_t mask, vint32m1x5_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg5e32_v_i32m1x5_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e32_v_i32m1x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP3]], <vscale x 2 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP4]], <vscale x 2 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] undef, <vscale x 2 x i32> [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP7]], <vscale x 2 x i32> [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP9]], <vscale x 2 x i32> [[TMP10]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP11]], <vscale x 2 x i32> [[TMP12]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP13]], <vscale x 2 x i32> [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP15]], <vscale x 2 x i32> [[TMP16]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP17]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP17]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP17]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP17]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg6.mask.nxv2i32.i32(<vscale x 2 x i32> [[TMP18]], <vscale x 2 x i32> [[TMP19]], <vscale x 2 x i32> [[TMP20]], <vscale x 2 x i32> [[TMP21]], <vscale x 2 x i32> [[TMP22]], <vscale x 2 x i32> [[TMP23]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] undef, <vscale x 2 x i32> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP26]], <vscale x 2 x i32> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP28]], <vscale x 2 x i32> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP30]], <vscale x 2 x i32> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP32]], <vscale x 2 x i32> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP34]], <vscale x 2 x i32> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32M1X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e32_v_i32m1x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP3]], <vscale x 2 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP4]], <vscale x 2 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] undef, <vscale x 2 x i32> [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP7]], <vscale x 2 x i32> [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP9]], <vscale x 2 x i32> [[TMP10]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP11]], <vscale x 2 x i32> [[TMP12]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP13]], <vscale x 2 x i32> [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP15]], <vscale x 2 x i32> [[TMP16]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP17]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP17]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP17]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP17]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg6.mask.nxv2i32.i64(<vscale x 2 x i32> [[TMP18]], <vscale x 2 x i32> [[TMP19]], <vscale x 2 x i32> [[TMP20]], <vscale x 2 x i32> [[TMP21]], <vscale x 2 x i32> [[TMP22]], <vscale x 2 x i32> [[TMP23]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] undef, <vscale x 2 x i32> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP26]], <vscale x 2 x i32> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP28]], <vscale x 2 x i32> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP30]], <vscale x 2 x i32> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP32]], <vscale x 2 x i32> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X6_T]] [[TMP34]], <vscale x 2 x i32> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32M1X6_T]] [[TMP36]]
+//
+vint32m1x6_t test_vlseg6e32_v_i32m1x6_m (vbool32_t mask, vint32m1x6_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg6e32_v_i32m1x6_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e32_v_i32m1x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP3]], <vscale x 2 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP4]], <vscale x 2 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP5]], <vscale x 2 x i32> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] undef, <vscale x 2 x i32> [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP8]], <vscale x 2 x i32> [[TMP9]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP10]], <vscale x 2 x i32> [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP12]], <vscale x 2 x i32> [[TMP13]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP14]], <vscale x 2 x i32> [[TMP15]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP16]], <vscale x 2 x i32> [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP18]], <vscale x 2 x i32> [[TMP19]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP20]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg7.mask.nxv2i32.i32(<vscale x 2 x i32> [[TMP21]], <vscale x 2 x i32> [[TMP22]], <vscale x 2 x i32> [[TMP23]], <vscale x 2 x i32> [[TMP24]], <vscale x 2 x i32> [[TMP25]], <vscale x 2 x i32> [[TMP26]], <vscale x 2 x i32> [[TMP27]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] undef, <vscale x 2 x i32> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP30]], <vscale x 2 x i32> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP32]], <vscale x 2 x i32> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP34]], <vscale x 2 x i32> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP36]], <vscale x 2 x i32> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP38]], <vscale x 2 x i32> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP40]], <vscale x 2 x i32> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32M1X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e32_v_i32m1x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP3]], <vscale x 2 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP4]], <vscale x 2 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP5]], <vscale x 2 x i32> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] undef, <vscale x 2 x i32> [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP8]], <vscale x 2 x i32> [[TMP9]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP10]], <vscale x 2 x i32> [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP12]], <vscale x 2 x i32> [[TMP13]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP14]], <vscale x 2 x i32> [[TMP15]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP16]], <vscale x 2 x i32> [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP18]], <vscale x 2 x i32> [[TMP19]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP20]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg7.mask.nxv2i32.i64(<vscale x 2 x i32> [[TMP21]], <vscale x 2 x i32> [[TMP22]], <vscale x 2 x i32> [[TMP23]], <vscale x 2 x i32> [[TMP24]], <vscale x 2 x i32> [[TMP25]], <vscale x 2 x i32> [[TMP26]], <vscale x 2 x i32> [[TMP27]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] undef, <vscale x 2 x i32> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP30]], <vscale x 2 x i32> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP32]], <vscale x 2 x i32> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP34]], <vscale x 2 x i32> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP36]], <vscale x 2 x i32> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP38]], <vscale x 2 x i32> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X7_T]] [[TMP40]], <vscale x 2 x i32> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32M1X7_T]] [[TMP42]]
+//
+vint32m1x7_t test_vlseg7e32_v_i32m1x7_m (vbool32_t mask, vint32m1x7_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg7e32_v_i32m1x7_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e32_v_i32m1x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP3]], <vscale x 2 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP4]], <vscale x 2 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP5]], <vscale x 2 x i32> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP6]], <vscale x 2 x i32> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] undef, <vscale x 2 x i32> [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP9]], <vscale x 2 x i32> [[TMP10]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP11]], <vscale x 2 x i32> [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP13]], <vscale x 2 x i32> [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP15]], <vscale x 2 x i32> [[TMP16]], 4
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP17]], <vscale x 2 x i32> [[TMP18]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP19]], <vscale x 2 x i32> [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP21]], <vscale x 2 x i32> [[TMP22]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP23]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP23]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP23]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP23]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP23]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP23]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP23]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg8.mask.nxv2i32.i32(<vscale x 2 x i32> [[TMP24]], <vscale x 2 x i32> [[TMP25]], <vscale x 2 x i32> [[TMP26]], <vscale x 2 x i32> [[TMP27]], <vscale x 2 x i32> [[TMP28]], <vscale x 2 x i32> [[TMP29]], <vscale x 2 x i32> [[TMP30]], <vscale x 2 x i32> [[TMP31]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] undef, <vscale x 2 x i32> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP34]], <vscale x 2 x i32> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP36]], <vscale x 2 x i32> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP38]], <vscale x 2 x i32> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP40]], <vscale x 2 x i32> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP42]], <vscale x 2 x i32> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP44]], <vscale x 2 x i32> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP46]], <vscale x 2 x i32> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32M1X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e32_v_i32m1x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP3]], <vscale x 2 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP4]], <vscale x 2 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP5]], <vscale x 2 x i32> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP6]], <vscale x 2 x i32> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] undef, <vscale x 2 x i32> [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP9]], <vscale x 2 x i32> [[TMP10]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP11]], <vscale x 2 x i32> [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP13]], <vscale x 2 x i32> [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP15]], <vscale x 2 x i32> [[TMP16]], 4
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP17]], <vscale x 2 x i32> [[TMP18]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP19]], <vscale x 2 x i32> [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP21]], <vscale x 2 x i32> [[TMP22]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP23]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP23]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP23]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP23]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP23]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP23]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP23]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg8.mask.nxv2i32.i64(<vscale x 2 x i32> [[TMP24]], <vscale x 2 x i32> [[TMP25]], <vscale x 2 x i32> [[TMP26]], <vscale x 2 x i32> [[TMP27]], <vscale x 2 x i32> [[TMP28]], <vscale x 2 x i32> [[TMP29]], <vscale x 2 x i32> [[TMP30]], <vscale x 2 x i32> [[TMP31]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] undef, <vscale x 2 x i32> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP34]], <vscale x 2 x i32> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP36]], <vscale x 2 x i32> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP38]], <vscale x 2 x i32> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP40]], <vscale x 2 x i32> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP42]], <vscale x 2 x i32> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP44]], <vscale x 2 x i32> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT32M1X8_T]] [[TMP46]], <vscale x 2 x i32> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32M1X8_T]] [[TMP48]]
+//
+vint32m1x8_t test_vlseg8e32_v_i32m1x8_m (vbool32_t mask, vint32m1x8_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg8e32_v_i32m1x8_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_i32m2x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X2_T:%.*]] undef, <vscale x 4 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X2_T]] [[TMP0]], <vscale x 4 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X2_T]] undef, <vscale x 4 x i32> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X2_T]] [[TMP3]], <vscale x 4 x i32> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg2.mask.nxv4i32.i32(<vscale x 4 x i32> [[TMP6]], <vscale x 4 x i32> [[TMP7]], i32* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X2_T]] undef, <vscale x 4 x i32> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X2_T]] [[TMP10]], <vscale x 4 x i32> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32M2X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_i32m2x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X2_T:%.*]] undef, <vscale x 4 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X2_T]] [[TMP0]], <vscale x 4 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X2_T]] undef, <vscale x 4 x i32> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X2_T]] [[TMP3]], <vscale x 4 x i32> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg2.mask.nxv4i32.i64(<vscale x 4 x i32> [[TMP6]], <vscale x 4 x i32> [[TMP7]], i32* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X2_T]] undef, <vscale x 4 x i32> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X2_T]] [[TMP10]], <vscale x 4 x i32> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32M2X2_T]] [[TMP12]]
+//
+vint32m2x2_t test_vlseg2e32_v_i32m2x2_m (vbool16_t mask, vint32m2x2_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg2e32_v_i32m2x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e32_v_i32m2x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T:%.*]] undef, <vscale x 4 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP0]], <vscale x 4 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP1]], <vscale x 4 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T]] undef, <vscale x 4 x i32> [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP4]], <vscale x 4 x i32> [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP6]], <vscale x 4 x i32> [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg3.mask.nxv4i32.i32(<vscale x 4 x i32> [[TMP9]], <vscale x 4 x i32> [[TMP10]], <vscale x 4 x i32> [[TMP11]], i32* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T]] undef, <vscale x 4 x i32> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP14]], <vscale x 4 x i32> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP16]], <vscale x 4 x i32> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32M2X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e32_v_i32m2x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T:%.*]] undef, <vscale x 4 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP0]], <vscale x 4 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP1]], <vscale x 4 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T]] undef, <vscale x 4 x i32> [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP4]], <vscale x 4 x i32> [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP6]], <vscale x 4 x i32> [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg3.mask.nxv4i32.i64(<vscale x 4 x i32> [[TMP9]], <vscale x 4 x i32> [[TMP10]], <vscale x 4 x i32> [[TMP11]], i32* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T]] undef, <vscale x 4 x i32> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP14]], <vscale x 4 x i32> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X3_T]] [[TMP16]], <vscale x 4 x i32> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32M2X3_T]] [[TMP18]]
+//
+vint32m2x3_t test_vlseg3e32_v_i32m2x3_m (vbool16_t mask, vint32m2x3_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg3e32_v_i32m2x3_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e32_v_i32m2x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T:%.*]] undef, <vscale x 4 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP0]], <vscale x 4 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP1]], <vscale x 4 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP2]], <vscale x 4 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] undef, <vscale x 4 x i32> [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP5]], <vscale x 4 x i32> [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP7]], <vscale x 4 x i32> [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP9]], <vscale x 4 x i32> [[TMP10]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP11]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP11]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg4.mask.nxv4i32.i32(<vscale x 4 x i32> [[TMP12]], <vscale x 4 x i32> [[TMP13]], <vscale x 4 x i32> [[TMP14]], <vscale x 4 x i32> [[TMP15]], i32* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] undef, <vscale x 4 x i32> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP18]], <vscale x 4 x i32> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP20]], <vscale x 4 x i32> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP22]], <vscale x 4 x i32> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32M2X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e32_v_i32m2x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T:%.*]] undef, <vscale x 4 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP0]], <vscale x 4 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP1]], <vscale x 4 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP2]], <vscale x 4 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] undef, <vscale x 4 x i32> [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP5]], <vscale x 4 x i32> [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP7]], <vscale x 4 x i32> [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP9]], <vscale x 4 x i32> [[TMP10]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP11]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP11]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg4.mask.nxv4i32.i64(<vscale x 4 x i32> [[TMP12]], <vscale x 4 x i32> [[TMP13]], <vscale x 4 x i32> [[TMP14]], <vscale x 4 x i32> [[TMP15]], i32* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] undef, <vscale x 4 x i32> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP18]], <vscale x 4 x i32> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP20]], <vscale x 4 x i32> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT32M2X4_T]] [[TMP22]], <vscale x 4 x i32> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32M2X4_T]] [[TMP24]]
+//
+vint32m2x4_t test_vlseg4e32_v_i32m2x4_m (vbool16_t mask, vint32m2x4_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg4e32_v_i32m2x4_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_i32m4x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M4X2_T:%.*]] undef, <vscale x 8 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M4X2_T]] [[TMP0]], <vscale x 8 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT32M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32M4X2_T]] undef, <vscale x 8 x i32> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT32M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32M4X2_T]] [[TMP3]], <vscale x 8 x i32> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32M4X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32M4X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 8 x i32>, <vscale x 8 x i32> } @llvm.riscv.vlseg2.mask.nxv8i32.i32(<vscale x 8 x i32> [[TMP6]], <vscale x 8 x i32> [[TMP7]], i32* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32M4X2_T]] undef, <vscale x 8 x i32> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32M4X2_T]] [[TMP10]], <vscale x 8 x i32> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT32M4X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_i32m4x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT32M4X2_T:%.*]] undef, <vscale x 8 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT32M4X2_T]] [[TMP0]], <vscale x 8 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT32M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT32M4X2_T]] undef, <vscale x 8 x i32> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT32M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT32M4X2_T]] [[TMP3]], <vscale x 8 x i32> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT32M4X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT32M4X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 8 x i32>, <vscale x 8 x i32> } @llvm.riscv.vlseg2.mask.nxv8i32.i64(<vscale x 8 x i32> [[TMP6]], <vscale x 8 x i32> [[TMP7]], i32* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT32M4X2_T]] undef, <vscale x 8 x i32> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT32M4X2_T]] [[TMP10]], <vscale x 8 x i32> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT32M4X2_T]] [[TMP12]]
+//
+vint32m4x2_t test_vlseg2e32_v_i32m4x2_m (vbool8_t mask, vint32m4x2_t maskedoff, const int32_t *base, size_t vl) {
+  return vlseg2e32_v_i32m4x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e64_v_i64m1x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X2_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X2_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X2_T]] undef, <vscale x 1 x i64> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X2_T]] [[TMP3]], <vscale x 1 x i64> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg2.mask.nxv1i64.i32(<vscale x 1 x i64> [[TMP6]], <vscale x 1 x i64> [[TMP7]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X2_T]] undef, <vscale x 1 x i64> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X2_T]] [[TMP10]], <vscale x 1 x i64> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT64M1X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e64_v_i64m1x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X2_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X2_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X2_T]] undef, <vscale x 1 x i64> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X2_T]] [[TMP3]], <vscale x 1 x i64> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg2.mask.nxv1i64.i64(<vscale x 1 x i64> [[TMP6]], <vscale x 1 x i64> [[TMP7]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X2_T]] undef, <vscale x 1 x i64> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X2_T]] [[TMP10]], <vscale x 1 x i64> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT64M1X2_T]] [[TMP12]]
+//
+vint64m1x2_t test_vlseg2e64_v_i64m1x2_m (vbool64_t mask, vint64m1x2_t maskedoff, const int64_t *base, size_t vl) {
+  return vlseg2e64_v_i64m1x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e64_v_i64m1x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T]] undef, <vscale x 1 x i64> [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP4]], <vscale x 1 x i64> [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP6]], <vscale x 1 x i64> [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg3.mask.nxv1i64.i32(<vscale x 1 x i64> [[TMP9]], <vscale x 1 x i64> [[TMP10]], <vscale x 1 x i64> [[TMP11]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T]] undef, <vscale x 1 x i64> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP14]], <vscale x 1 x i64> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP16]], <vscale x 1 x i64> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT64M1X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e64_v_i64m1x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T]] undef, <vscale x 1 x i64> [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP4]], <vscale x 1 x i64> [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP6]], <vscale x 1 x i64> [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg3.mask.nxv1i64.i64(<vscale x 1 x i64> [[TMP9]], <vscale x 1 x i64> [[TMP10]], <vscale x 1 x i64> [[TMP11]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T]] undef, <vscale x 1 x i64> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP14]], <vscale x 1 x i64> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X3_T]] [[TMP16]], <vscale x 1 x i64> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT64M1X3_T]] [[TMP18]]
+//
+vint64m1x3_t test_vlseg3e64_v_i64m1x3_m (vbool64_t mask, vint64m1x3_t maskedoff, const int64_t *base, size_t vl) {
+  return vlseg3e64_v_i64m1x3_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e64_v_i64m1x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] undef, <vscale x 1 x i64> [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP5]], <vscale x 1 x i64> [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP7]], <vscale x 1 x i64> [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP9]], <vscale x 1 x i64> [[TMP10]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP11]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP11]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg4.mask.nxv1i64.i32(<vscale x 1 x i64> [[TMP12]], <vscale x 1 x i64> [[TMP13]], <vscale x 1 x i64> [[TMP14]], <vscale x 1 x i64> [[TMP15]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] undef, <vscale x 1 x i64> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP18]], <vscale x 1 x i64> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP20]], <vscale x 1 x i64> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP22]], <vscale x 1 x i64> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT64M1X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e64_v_i64m1x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] undef, <vscale x 1 x i64> [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP5]], <vscale x 1 x i64> [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP7]], <vscale x 1 x i64> [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP9]], <vscale x 1 x i64> [[TMP10]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP11]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP11]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg4.mask.nxv1i64.i64(<vscale x 1 x i64> [[TMP12]], <vscale x 1 x i64> [[TMP13]], <vscale x 1 x i64> [[TMP14]], <vscale x 1 x i64> [[TMP15]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] undef, <vscale x 1 x i64> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP18]], <vscale x 1 x i64> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP20]], <vscale x 1 x i64> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X4_T]] [[TMP22]], <vscale x 1 x i64> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT64M1X4_T]] [[TMP24]]
+//
+vint64m1x4_t test_vlseg4e64_v_i64m1x4_m (vbool64_t mask, vint64m1x4_t maskedoff, const int64_t *base, size_t vl) {
+  return vlseg4e64_v_i64m1x4_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e64_v_i64m1x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP3]], <vscale x 1 x i64> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] undef, <vscale x 1 x i64> [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP6]], <vscale x 1 x i64> [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP8]], <vscale x 1 x i64> [[TMP9]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP10]], <vscale x 1 x i64> [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP12]], <vscale x 1 x i64> [[TMP13]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP14]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP14]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP14]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg5.mask.nxv1i64.i32(<vscale x 1 x i64> [[TMP15]], <vscale x 1 x i64> [[TMP16]], <vscale x 1 x i64> [[TMP17]], <vscale x 1 x i64> [[TMP18]], <vscale x 1 x i64> [[TMP19]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] undef, <vscale x 1 x i64> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP22]], <vscale x 1 x i64> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP24]], <vscale x 1 x i64> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP26]], <vscale x 1 x i64> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP28]], <vscale x 1 x i64> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT64M1X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e64_v_i64m1x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP3]], <vscale x 1 x i64> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] undef, <vscale x 1 x i64> [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP6]], <vscale x 1 x i64> [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP8]], <vscale x 1 x i64> [[TMP9]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP10]], <vscale x 1 x i64> [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP12]], <vscale x 1 x i64> [[TMP13]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP14]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP14]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP14]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg5.mask.nxv1i64.i64(<vscale x 1 x i64> [[TMP15]], <vscale x 1 x i64> [[TMP16]], <vscale x 1 x i64> [[TMP17]], <vscale x 1 x i64> [[TMP18]], <vscale x 1 x i64> [[TMP19]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] undef, <vscale x 1 x i64> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP22]], <vscale x 1 x i64> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP24]], <vscale x 1 x i64> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP26]], <vscale x 1 x i64> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X5_T]] [[TMP28]], <vscale x 1 x i64> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT64M1X5_T]] [[TMP30]]
+//
+vint64m1x5_t test_vlseg5e64_v_i64m1x5_m (vbool64_t mask, vint64m1x5_t maskedoff, const int64_t *base, size_t vl) {
+  return vlseg5e64_v_i64m1x5_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e64_v_i64m1x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP3]], <vscale x 1 x i64> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP4]], <vscale x 1 x i64> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] undef, <vscale x 1 x i64> [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP7]], <vscale x 1 x i64> [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP9]], <vscale x 1 x i64> [[TMP10]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP11]], <vscale x 1 x i64> [[TMP12]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP13]], <vscale x 1 x i64> [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP15]], <vscale x 1 x i64> [[TMP16]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP17]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP17]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP17]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP17]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg6.mask.nxv1i64.i32(<vscale x 1 x i64> [[TMP18]], <vscale x 1 x i64> [[TMP19]], <vscale x 1 x i64> [[TMP20]], <vscale x 1 x i64> [[TMP21]], <vscale x 1 x i64> [[TMP22]], <vscale x 1 x i64> [[TMP23]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] undef, <vscale x 1 x i64> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP26]], <vscale x 1 x i64> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP28]], <vscale x 1 x i64> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP30]], <vscale x 1 x i64> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP32]], <vscale x 1 x i64> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP34]], <vscale x 1 x i64> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT64M1X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e64_v_i64m1x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP3]], <vscale x 1 x i64> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP4]], <vscale x 1 x i64> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] undef, <vscale x 1 x i64> [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP7]], <vscale x 1 x i64> [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP9]], <vscale x 1 x i64> [[TMP10]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP11]], <vscale x 1 x i64> [[TMP12]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP13]], <vscale x 1 x i64> [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP15]], <vscale x 1 x i64> [[TMP16]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP17]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP17]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP17]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP17]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg6.mask.nxv1i64.i64(<vscale x 1 x i64> [[TMP18]], <vscale x 1 x i64> [[TMP19]], <vscale x 1 x i64> [[TMP20]], <vscale x 1 x i64> [[TMP21]], <vscale x 1 x i64> [[TMP22]], <vscale x 1 x i64> [[TMP23]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] undef, <vscale x 1 x i64> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP26]], <vscale x 1 x i64> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP28]], <vscale x 1 x i64> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP30]], <vscale x 1 x i64> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP32]], <vscale x 1 x i64> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X6_T]] [[TMP34]], <vscale x 1 x i64> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT64M1X6_T]] [[TMP36]]
+//
+vint64m1x6_t test_vlseg6e64_v_i64m1x6_m (vbool64_t mask, vint64m1x6_t maskedoff, const int64_t *base, size_t vl) {
+  return vlseg6e64_v_i64m1x6_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e64_v_i64m1x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP3]], <vscale x 1 x i64> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP4]], <vscale x 1 x i64> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP5]], <vscale x 1 x i64> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] undef, <vscale x 1 x i64> [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP8]], <vscale x 1 x i64> [[TMP9]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP10]], <vscale x 1 x i64> [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP12]], <vscale x 1 x i64> [[TMP13]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP14]], <vscale x 1 x i64> [[TMP15]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP16]], <vscale x 1 x i64> [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP18]], <vscale x 1 x i64> [[TMP19]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP20]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg7.mask.nxv1i64.i32(<vscale x 1 x i64> [[TMP21]], <vscale x 1 x i64> [[TMP22]], <vscale x 1 x i64> [[TMP23]], <vscale x 1 x i64> [[TMP24]], <vscale x 1 x i64> [[TMP25]], <vscale x 1 x i64> [[TMP26]], <vscale x 1 x i64> [[TMP27]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] undef, <vscale x 1 x i64> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP30]], <vscale x 1 x i64> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP32]], <vscale x 1 x i64> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP34]], <vscale x 1 x i64> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP36]], <vscale x 1 x i64> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP38]], <vscale x 1 x i64> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP40]], <vscale x 1 x i64> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT64M1X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e64_v_i64m1x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP3]], <vscale x 1 x i64> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP4]], <vscale x 1 x i64> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP5]], <vscale x 1 x i64> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] undef, <vscale x 1 x i64> [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP8]], <vscale x 1 x i64> [[TMP9]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP10]], <vscale x 1 x i64> [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP12]], <vscale x 1 x i64> [[TMP13]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP14]], <vscale x 1 x i64> [[TMP15]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP16]], <vscale x 1 x i64> [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP18]], <vscale x 1 x i64> [[TMP19]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP20]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg7.mask.nxv1i64.i64(<vscale x 1 x i64> [[TMP21]], <vscale x 1 x i64> [[TMP22]], <vscale x 1 x i64> [[TMP23]], <vscale x 1 x i64> [[TMP24]], <vscale x 1 x i64> [[TMP25]], <vscale x 1 x i64> [[TMP26]], <vscale x 1 x i64> [[TMP27]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] undef, <vscale x 1 x i64> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP30]], <vscale x 1 x i64> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP32]], <vscale x 1 x i64> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP34]], <vscale x 1 x i64> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP36]], <vscale x 1 x i64> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP38]], <vscale x 1 x i64> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X7_T]] [[TMP40]], <vscale x 1 x i64> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT64M1X7_T]] [[TMP42]]
+//
+vint64m1x7_t test_vlseg7e64_v_i64m1x7_m (vbool64_t mask, vint64m1x7_t maskedoff, const int64_t *base, size_t vl) {
+  return vlseg7e64_v_i64m1x7_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e64_v_i64m1x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP3]], <vscale x 1 x i64> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP4]], <vscale x 1 x i64> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP5]], <vscale x 1 x i64> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP6]], <vscale x 1 x i64> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] undef, <vscale x 1 x i64> [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP9]], <vscale x 1 x i64> [[TMP10]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP11]], <vscale x 1 x i64> [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP13]], <vscale x 1 x i64> [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP15]], <vscale x 1 x i64> [[TMP16]], 4
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP17]], <vscale x 1 x i64> [[TMP18]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP19]], <vscale x 1 x i64> [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP21]], <vscale x 1 x i64> [[TMP22]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP23]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP23]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP23]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP23]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP23]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP23]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP23]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg8.mask.nxv1i64.i32(<vscale x 1 x i64> [[TMP24]], <vscale x 1 x i64> [[TMP25]], <vscale x 1 x i64> [[TMP26]], <vscale x 1 x i64> [[TMP27]], <vscale x 1 x i64> [[TMP28]], <vscale x 1 x i64> [[TMP29]], <vscale x 1 x i64> [[TMP30]], <vscale x 1 x i64> [[TMP31]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] undef, <vscale x 1 x i64> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP34]], <vscale x 1 x i64> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP36]], <vscale x 1 x i64> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP38]], <vscale x 1 x i64> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP40]], <vscale x 1 x i64> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP42]], <vscale x 1 x i64> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP44]], <vscale x 1 x i64> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP46]], <vscale x 1 x i64> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT64M1X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e64_v_i64m1x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP3]], <vscale x 1 x i64> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP4]], <vscale x 1 x i64> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP5]], <vscale x 1 x i64> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP6]], <vscale x 1 x i64> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] undef, <vscale x 1 x i64> [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP9]], <vscale x 1 x i64> [[TMP10]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP11]], <vscale x 1 x i64> [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP13]], <vscale x 1 x i64> [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP15]], <vscale x 1 x i64> [[TMP16]], 4
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP17]], <vscale x 1 x i64> [[TMP18]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP19]], <vscale x 1 x i64> [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP21]], <vscale x 1 x i64> [[TMP22]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP23]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP23]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP23]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP23]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP23]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP23]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP23]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg8.mask.nxv1i64.i64(<vscale x 1 x i64> [[TMP24]], <vscale x 1 x i64> [[TMP25]], <vscale x 1 x i64> [[TMP26]], <vscale x 1 x i64> [[TMP27]], <vscale x 1 x i64> [[TMP28]], <vscale x 1 x i64> [[TMP29]], <vscale x 1 x i64> [[TMP30]], <vscale x 1 x i64> [[TMP31]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] undef, <vscale x 1 x i64> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP34]], <vscale x 1 x i64> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP36]], <vscale x 1 x i64> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP38]], <vscale x 1 x i64> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP40]], <vscale x 1 x i64> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP42]], <vscale x 1 x i64> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP44]], <vscale x 1 x i64> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_INT64M1X8_T]] [[TMP46]], <vscale x 1 x i64> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT64M1X8_T]] [[TMP48]]
+//
+vint64m1x8_t test_vlseg8e64_v_i64m1x8_m (vbool64_t mask, vint64m1x8_t maskedoff, const int64_t *base, size_t vl) {
+  return vlseg8e64_v_i64m1x8_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e64_v_i64m2x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X2_T:%.*]] undef, <vscale x 2 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X2_T]] [[TMP0]], <vscale x 2 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X2_T]] undef, <vscale x 2 x i64> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X2_T]] [[TMP3]], <vscale x 2 x i64> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg2.mask.nxv2i64.i32(<vscale x 2 x i64> [[TMP6]], <vscale x 2 x i64> [[TMP7]], i64* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X2_T]] undef, <vscale x 2 x i64> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X2_T]] [[TMP10]], <vscale x 2 x i64> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT64M2X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e64_v_i64m2x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X2_T:%.*]] undef, <vscale x 2 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X2_T]] [[TMP0]], <vscale x 2 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X2_T]] undef, <vscale x 2 x i64> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X2_T]] [[TMP3]], <vscale x 2 x i64> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg2.mask.nxv2i64.i64(<vscale x 2 x i64> [[TMP6]], <vscale x 2 x i64> [[TMP7]], i64* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X2_T]] undef, <vscale x 2 x i64> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X2_T]] [[TMP10]], <vscale x 2 x i64> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT64M2X2_T]] [[TMP12]]
+//
+vint64m2x2_t test_vlseg2e64_v_i64m2x2_m (vbool32_t mask, vint64m2x2_t maskedoff, const int64_t *base, size_t vl) {
+  return vlseg2e64_v_i64m2x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e64_v_i64m2x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T:%.*]] undef, <vscale x 2 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP0]], <vscale x 2 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP1]], <vscale x 2 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T]] undef, <vscale x 2 x i64> [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP4]], <vscale x 2 x i64> [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP6]], <vscale x 2 x i64> [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg3.mask.nxv2i64.i32(<vscale x 2 x i64> [[TMP9]], <vscale x 2 x i64> [[TMP10]], <vscale x 2 x i64> [[TMP11]], i64* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T]] undef, <vscale x 2 x i64> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP14]], <vscale x 2 x i64> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP16]], <vscale x 2 x i64> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT64M2X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e64_v_i64m2x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T:%.*]] undef, <vscale x 2 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP0]], <vscale x 2 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP1]], <vscale x 2 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T]] undef, <vscale x 2 x i64> [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP4]], <vscale x 2 x i64> [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP6]], <vscale x 2 x i64> [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg3.mask.nxv2i64.i64(<vscale x 2 x i64> [[TMP9]], <vscale x 2 x i64> [[TMP10]], <vscale x 2 x i64> [[TMP11]], i64* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T]] undef, <vscale x 2 x i64> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP14]], <vscale x 2 x i64> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X3_T]] [[TMP16]], <vscale x 2 x i64> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT64M2X3_T]] [[TMP18]]
+//
+vint64m2x3_t test_vlseg3e64_v_i64m2x3_m (vbool32_t mask, vint64m2x3_t maskedoff, const int64_t *base, size_t vl) {
+  return vlseg3e64_v_i64m2x3_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e64_v_i64m2x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T:%.*]] undef, <vscale x 2 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP0]], <vscale x 2 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP1]], <vscale x 2 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP2]], <vscale x 2 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] undef, <vscale x 2 x i64> [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP5]], <vscale x 2 x i64> [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP7]], <vscale x 2 x i64> [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP9]], <vscale x 2 x i64> [[TMP10]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP11]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP11]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg4.mask.nxv2i64.i32(<vscale x 2 x i64> [[TMP12]], <vscale x 2 x i64> [[TMP13]], <vscale x 2 x i64> [[TMP14]], <vscale x 2 x i64> [[TMP15]], i64* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] undef, <vscale x 2 x i64> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP18]], <vscale x 2 x i64> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP20]], <vscale x 2 x i64> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP22]], <vscale x 2 x i64> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT64M2X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e64_v_i64m2x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T:%.*]] undef, <vscale x 2 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP0]], <vscale x 2 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP1]], <vscale x 2 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP2]], <vscale x 2 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] undef, <vscale x 2 x i64> [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP5]], <vscale x 2 x i64> [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP7]], <vscale x 2 x i64> [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP9]], <vscale x 2 x i64> [[TMP10]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP11]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP11]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg4.mask.nxv2i64.i64(<vscale x 2 x i64> [[TMP12]], <vscale x 2 x i64> [[TMP13]], <vscale x 2 x i64> [[TMP14]], <vscale x 2 x i64> [[TMP15]], i64* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] undef, <vscale x 2 x i64> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP18]], <vscale x 2 x i64> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP20]], <vscale x 2 x i64> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_INT64M2X4_T]] [[TMP22]], <vscale x 2 x i64> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT64M2X4_T]] [[TMP24]]
+//
+vint64m2x4_t test_vlseg4e64_v_i64m2x4_m (vbool32_t mask, vint64m2x4_t maskedoff, const int64_t *base, size_t vl) {
+  return vlseg4e64_v_i64m2x4_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e64_v_i64m4x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M4X2_T:%.*]] undef, <vscale x 4 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M4X2_T]] [[TMP0]], <vscale x 4 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT64M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT64M4X2_T]] undef, <vscale x 4 x i64> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT64M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT64M4X2_T]] [[TMP3]], <vscale x 4 x i64> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT64M4X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT64M4X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x i64>, <vscale x 4 x i64> } @llvm.riscv.vlseg2.mask.nxv4i64.i32(<vscale x 4 x i64> [[TMP6]], <vscale x 4 x i64> [[TMP7]], i64* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT64M4X2_T]] undef, <vscale x 4 x i64> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT64M4X2_T]] [[TMP10]], <vscale x 4 x i64> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_INT64M4X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e64_v_i64m4x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_INT64M4X2_T:%.*]] undef, <vscale x 4 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_INT64M4X2_T]] [[TMP0]], <vscale x 4 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_INT64M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_INT64M4X2_T]] undef, <vscale x 4 x i64> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_INT64M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_INT64M4X2_T]] [[TMP3]], <vscale x 4 x i64> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_INT64M4X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_INT64M4X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x i64>, <vscale x 4 x i64> } @llvm.riscv.vlseg2.mask.nxv4i64.i64(<vscale x 4 x i64> [[TMP6]], <vscale x 4 x i64> [[TMP7]], i64* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_INT64M4X2_T]] undef, <vscale x 4 x i64> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_INT64M4X2_T]] [[TMP10]], <vscale x 4 x i64> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_INT64M4X2_T]] [[TMP12]]
+//
+vint64m4x2_t test_vlseg2e64_v_i64m4x2_m (vbool16_t mask, vint64m4x2_t maskedoff, const int64_t *base, size_t vl) {
+  return vlseg2e64_v_i64m4x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_u8mf8x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X2_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X2_T]] undef, <vscale x 1 x i8> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP3]], <vscale x 1 x i8> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg2.mask.nxv1i8.i32(<vscale x 1 x i8> [[TMP6]], <vscale x 1 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X2_T]] undef, <vscale x 1 x i8> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP10]], <vscale x 1 x i8> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_u8mf8x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X2_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X2_T]] undef, <vscale x 1 x i8> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP3]], <vscale x 1 x i8> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg2.mask.nxv1i8.i64(<vscale x 1 x i8> [[TMP6]], <vscale x 1 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X2_T]] undef, <vscale x 1 x i8> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP10]], <vscale x 1 x i8> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF8X2_T]] [[TMP12]]
+//
+vuint8mf8x2_t test_vlseg2e8_v_u8mf8x2_m (vbool64_t mask, vuint8mf8x2_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg2e8_v_u8mf8x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e8_v_u8mf8x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T]] undef, <vscale x 1 x i8> [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP4]], <vscale x 1 x i8> [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP6]], <vscale x 1 x i8> [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg3.mask.nxv1i8.i32(<vscale x 1 x i8> [[TMP9]], <vscale x 1 x i8> [[TMP10]], <vscale x 1 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T]] undef, <vscale x 1 x i8> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP14]], <vscale x 1 x i8> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP16]], <vscale x 1 x i8> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e8_v_u8mf8x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T]] undef, <vscale x 1 x i8> [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP4]], <vscale x 1 x i8> [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP6]], <vscale x 1 x i8> [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg3.mask.nxv1i8.i64(<vscale x 1 x i8> [[TMP9]], <vscale x 1 x i8> [[TMP10]], <vscale x 1 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T]] undef, <vscale x 1 x i8> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP14]], <vscale x 1 x i8> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP16]], <vscale x 1 x i8> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF8X3_T]] [[TMP18]]
+//
+vuint8mf8x3_t test_vlseg3e8_v_u8mf8x3_m (vbool64_t mask, vuint8mf8x3_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg3e8_v_u8mf8x3_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e8_v_u8mf8x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] undef, <vscale x 1 x i8> [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP5]], <vscale x 1 x i8> [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP7]], <vscale x 1 x i8> [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP9]], <vscale x 1 x i8> [[TMP10]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP11]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP11]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg4.mask.nxv1i8.i32(<vscale x 1 x i8> [[TMP12]], <vscale x 1 x i8> [[TMP13]], <vscale x 1 x i8> [[TMP14]], <vscale x 1 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] undef, <vscale x 1 x i8> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP18]], <vscale x 1 x i8> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP20]], <vscale x 1 x i8> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP22]], <vscale x 1 x i8> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e8_v_u8mf8x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] undef, <vscale x 1 x i8> [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP5]], <vscale x 1 x i8> [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP7]], <vscale x 1 x i8> [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP9]], <vscale x 1 x i8> [[TMP10]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP11]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP11]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg4.mask.nxv1i8.i64(<vscale x 1 x i8> [[TMP12]], <vscale x 1 x i8> [[TMP13]], <vscale x 1 x i8> [[TMP14]], <vscale x 1 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] undef, <vscale x 1 x i8> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP18]], <vscale x 1 x i8> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP20]], <vscale x 1 x i8> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP22]], <vscale x 1 x i8> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF8X4_T]] [[TMP24]]
+//
+vuint8mf8x4_t test_vlseg4e8_v_u8mf8x4_m (vbool64_t mask, vuint8mf8x4_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg4e8_v_u8mf8x4_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e8_v_u8mf8x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP3]], <vscale x 1 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] undef, <vscale x 1 x i8> [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP6]], <vscale x 1 x i8> [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP8]], <vscale x 1 x i8> [[TMP9]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP10]], <vscale x 1 x i8> [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP12]], <vscale x 1 x i8> [[TMP13]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP14]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP14]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP14]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg5.mask.nxv1i8.i32(<vscale x 1 x i8> [[TMP15]], <vscale x 1 x i8> [[TMP16]], <vscale x 1 x i8> [[TMP17]], <vscale x 1 x i8> [[TMP18]], <vscale x 1 x i8> [[TMP19]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] undef, <vscale x 1 x i8> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP22]], <vscale x 1 x i8> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP24]], <vscale x 1 x i8> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP26]], <vscale x 1 x i8> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP28]], <vscale x 1 x i8> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e8_v_u8mf8x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP3]], <vscale x 1 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] undef, <vscale x 1 x i8> [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP6]], <vscale x 1 x i8> [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP8]], <vscale x 1 x i8> [[TMP9]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP10]], <vscale x 1 x i8> [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP12]], <vscale x 1 x i8> [[TMP13]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP14]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP14]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP14]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg5.mask.nxv1i8.i64(<vscale x 1 x i8> [[TMP15]], <vscale x 1 x i8> [[TMP16]], <vscale x 1 x i8> [[TMP17]], <vscale x 1 x i8> [[TMP18]], <vscale x 1 x i8> [[TMP19]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] undef, <vscale x 1 x i8> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP22]], <vscale x 1 x i8> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP24]], <vscale x 1 x i8> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP26]], <vscale x 1 x i8> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP28]], <vscale x 1 x i8> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF8X5_T]] [[TMP30]]
+//
+vuint8mf8x5_t test_vlseg5e8_v_u8mf8x5_m (vbool64_t mask, vuint8mf8x5_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg5e8_v_u8mf8x5_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e8_v_u8mf8x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP3]], <vscale x 1 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP4]], <vscale x 1 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] undef, <vscale x 1 x i8> [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP7]], <vscale x 1 x i8> [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP9]], <vscale x 1 x i8> [[TMP10]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP11]], <vscale x 1 x i8> [[TMP12]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP13]], <vscale x 1 x i8> [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP15]], <vscale x 1 x i8> [[TMP16]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP17]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP17]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP17]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP17]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg6.mask.nxv1i8.i32(<vscale x 1 x i8> [[TMP18]], <vscale x 1 x i8> [[TMP19]], <vscale x 1 x i8> [[TMP20]], <vscale x 1 x i8> [[TMP21]], <vscale x 1 x i8> [[TMP22]], <vscale x 1 x i8> [[TMP23]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] undef, <vscale x 1 x i8> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP26]], <vscale x 1 x i8> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP28]], <vscale x 1 x i8> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP30]], <vscale x 1 x i8> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP32]], <vscale x 1 x i8> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP34]], <vscale x 1 x i8> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e8_v_u8mf8x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP3]], <vscale x 1 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP4]], <vscale x 1 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] undef, <vscale x 1 x i8> [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP7]], <vscale x 1 x i8> [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP9]], <vscale x 1 x i8> [[TMP10]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP11]], <vscale x 1 x i8> [[TMP12]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP13]], <vscale x 1 x i8> [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP15]], <vscale x 1 x i8> [[TMP16]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP17]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP17]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP17]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP17]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg6.mask.nxv1i8.i64(<vscale x 1 x i8> [[TMP18]], <vscale x 1 x i8> [[TMP19]], <vscale x 1 x i8> [[TMP20]], <vscale x 1 x i8> [[TMP21]], <vscale x 1 x i8> [[TMP22]], <vscale x 1 x i8> [[TMP23]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] undef, <vscale x 1 x i8> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP26]], <vscale x 1 x i8> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP28]], <vscale x 1 x i8> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP30]], <vscale x 1 x i8> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP32]], <vscale x 1 x i8> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP34]], <vscale x 1 x i8> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF8X6_T]] [[TMP36]]
+//
+vuint8mf8x6_t test_vlseg6e8_v_u8mf8x6_m (vbool64_t mask, vuint8mf8x6_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg6e8_v_u8mf8x6_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e8_v_u8mf8x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP3]], <vscale x 1 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP4]], <vscale x 1 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP5]], <vscale x 1 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] undef, <vscale x 1 x i8> [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP8]], <vscale x 1 x i8> [[TMP9]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP10]], <vscale x 1 x i8> [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP12]], <vscale x 1 x i8> [[TMP13]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP14]], <vscale x 1 x i8> [[TMP15]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP16]], <vscale x 1 x i8> [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP18]], <vscale x 1 x i8> [[TMP19]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP20]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg7.mask.nxv1i8.i32(<vscale x 1 x i8> [[TMP21]], <vscale x 1 x i8> [[TMP22]], <vscale x 1 x i8> [[TMP23]], <vscale x 1 x i8> [[TMP24]], <vscale x 1 x i8> [[TMP25]], <vscale x 1 x i8> [[TMP26]], <vscale x 1 x i8> [[TMP27]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] undef, <vscale x 1 x i8> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP30]], <vscale x 1 x i8> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP32]], <vscale x 1 x i8> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP34]], <vscale x 1 x i8> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP36]], <vscale x 1 x i8> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP38]], <vscale x 1 x i8> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP40]], <vscale x 1 x i8> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e8_v_u8mf8x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP3]], <vscale x 1 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP4]], <vscale x 1 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP5]], <vscale x 1 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] undef, <vscale x 1 x i8> [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP8]], <vscale x 1 x i8> [[TMP9]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP10]], <vscale x 1 x i8> [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP12]], <vscale x 1 x i8> [[TMP13]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP14]], <vscale x 1 x i8> [[TMP15]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP16]], <vscale x 1 x i8> [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP18]], <vscale x 1 x i8> [[TMP19]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP20]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg7.mask.nxv1i8.i64(<vscale x 1 x i8> [[TMP21]], <vscale x 1 x i8> [[TMP22]], <vscale x 1 x i8> [[TMP23]], <vscale x 1 x i8> [[TMP24]], <vscale x 1 x i8> [[TMP25]], <vscale x 1 x i8> [[TMP26]], <vscale x 1 x i8> [[TMP27]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] undef, <vscale x 1 x i8> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP30]], <vscale x 1 x i8> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP32]], <vscale x 1 x i8> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP34]], <vscale x 1 x i8> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP36]], <vscale x 1 x i8> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP38]], <vscale x 1 x i8> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP40]], <vscale x 1 x i8> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF8X7_T]] [[TMP42]]
+//
+vuint8mf8x7_t test_vlseg7e8_v_u8mf8x7_m (vbool64_t mask, vuint8mf8x7_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg7e8_v_u8mf8x7_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e8_v_u8mf8x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP3]], <vscale x 1 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP4]], <vscale x 1 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP5]], <vscale x 1 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP6]], <vscale x 1 x i8> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] undef, <vscale x 1 x i8> [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP9]], <vscale x 1 x i8> [[TMP10]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP11]], <vscale x 1 x i8> [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP13]], <vscale x 1 x i8> [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP15]], <vscale x 1 x i8> [[TMP16]], 4
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP17]], <vscale x 1 x i8> [[TMP18]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP19]], <vscale x 1 x i8> [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP21]], <vscale x 1 x i8> [[TMP22]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP23]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP23]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP23]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP23]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP23]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP23]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP23]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg8.mask.nxv1i8.i32(<vscale x 1 x i8> [[TMP24]], <vscale x 1 x i8> [[TMP25]], <vscale x 1 x i8> [[TMP26]], <vscale x 1 x i8> [[TMP27]], <vscale x 1 x i8> [[TMP28]], <vscale x 1 x i8> [[TMP29]], <vscale x 1 x i8> [[TMP30]], <vscale x 1 x i8> [[TMP31]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] undef, <vscale x 1 x i8> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP34]], <vscale x 1 x i8> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP36]], <vscale x 1 x i8> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP38]], <vscale x 1 x i8> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP40]], <vscale x 1 x i8> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP42]], <vscale x 1 x i8> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP44]], <vscale x 1 x i8> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP46]], <vscale x 1 x i8> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e8_v_u8mf8x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T:%.*]] undef, <vscale x 1 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP0]], <vscale x 1 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP1]], <vscale x 1 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP2]], <vscale x 1 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP3]], <vscale x 1 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP4]], <vscale x 1 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP5]], <vscale x 1 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP6]], <vscale x 1 x i8> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] undef, <vscale x 1 x i8> [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP9]], <vscale x 1 x i8> [[TMP10]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP11]], <vscale x 1 x i8> [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP13]], <vscale x 1 x i8> [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP15]], <vscale x 1 x i8> [[TMP16]], 4
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP17]], <vscale x 1 x i8> [[TMP18]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP19]], <vscale x 1 x i8> [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP21]], <vscale x 1 x i8> [[TMP22]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP23]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP23]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP23]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP23]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP23]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP23]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP23]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } @llvm.riscv.vlseg8.mask.nxv1i8.i64(<vscale x 1 x i8> [[TMP24]], <vscale x 1 x i8> [[TMP25]], <vscale x 1 x i8> [[TMP26]], <vscale x 1 x i8> [[TMP27]], <vscale x 1 x i8> [[TMP28]], <vscale x 1 x i8> [[TMP29]], <vscale x 1 x i8> [[TMP30]], <vscale x 1 x i8> [[TMP31]], i8* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] undef, <vscale x 1 x i8> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP34]], <vscale x 1 x i8> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP36]], <vscale x 1 x i8> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP38]], <vscale x 1 x i8> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP40]], <vscale x 1 x i8> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP42]], <vscale x 1 x i8> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP44]], <vscale x 1 x i8> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP46]], <vscale x 1 x i8> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF8X8_T]] [[TMP48]]
+//
+vuint8mf8x8_t test_vlseg8e8_v_u8mf8x8_m (vbool64_t mask, vuint8mf8x8_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg8e8_v_u8mf8x8_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_u8mf4x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X2_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X2_T]] undef, <vscale x 2 x i8> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP3]], <vscale x 2 x i8> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg2.mask.nxv2i8.i32(<vscale x 2 x i8> [[TMP6]], <vscale x 2 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X2_T]] undef, <vscale x 2 x i8> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP10]], <vscale x 2 x i8> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_u8mf4x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X2_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X2_T]] undef, <vscale x 2 x i8> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP3]], <vscale x 2 x i8> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg2.mask.nxv2i8.i64(<vscale x 2 x i8> [[TMP6]], <vscale x 2 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X2_T]] undef, <vscale x 2 x i8> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP10]], <vscale x 2 x i8> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF4X2_T]] [[TMP12]]
+//
+vuint8mf4x2_t test_vlseg2e8_v_u8mf4x2_m (vbool32_t mask, vuint8mf4x2_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg2e8_v_u8mf4x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e8_v_u8mf4x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T]] undef, <vscale x 2 x i8> [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP4]], <vscale x 2 x i8> [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP6]], <vscale x 2 x i8> [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg3.mask.nxv2i8.i32(<vscale x 2 x i8> [[TMP9]], <vscale x 2 x i8> [[TMP10]], <vscale x 2 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T]] undef, <vscale x 2 x i8> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP14]], <vscale x 2 x i8> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP16]], <vscale x 2 x i8> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e8_v_u8mf4x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T]] undef, <vscale x 2 x i8> [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP4]], <vscale x 2 x i8> [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP6]], <vscale x 2 x i8> [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg3.mask.nxv2i8.i64(<vscale x 2 x i8> [[TMP9]], <vscale x 2 x i8> [[TMP10]], <vscale x 2 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T]] undef, <vscale x 2 x i8> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP14]], <vscale x 2 x i8> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP16]], <vscale x 2 x i8> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF4X3_T]] [[TMP18]]
+//
+vuint8mf4x3_t test_vlseg3e8_v_u8mf4x3_m (vbool32_t mask, vuint8mf4x3_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg3e8_v_u8mf4x3_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e8_v_u8mf4x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] undef, <vscale x 2 x i8> [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP5]], <vscale x 2 x i8> [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP7]], <vscale x 2 x i8> [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP9]], <vscale x 2 x i8> [[TMP10]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP11]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP11]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg4.mask.nxv2i8.i32(<vscale x 2 x i8> [[TMP12]], <vscale x 2 x i8> [[TMP13]], <vscale x 2 x i8> [[TMP14]], <vscale x 2 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] undef, <vscale x 2 x i8> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP18]], <vscale x 2 x i8> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP20]], <vscale x 2 x i8> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP22]], <vscale x 2 x i8> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e8_v_u8mf4x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] undef, <vscale x 2 x i8> [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP5]], <vscale x 2 x i8> [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP7]], <vscale x 2 x i8> [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP9]], <vscale x 2 x i8> [[TMP10]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP11]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP11]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg4.mask.nxv2i8.i64(<vscale x 2 x i8> [[TMP12]], <vscale x 2 x i8> [[TMP13]], <vscale x 2 x i8> [[TMP14]], <vscale x 2 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] undef, <vscale x 2 x i8> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP18]], <vscale x 2 x i8> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP20]], <vscale x 2 x i8> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP22]], <vscale x 2 x i8> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF4X4_T]] [[TMP24]]
+//
+vuint8mf4x4_t test_vlseg4e8_v_u8mf4x4_m (vbool32_t mask, vuint8mf4x4_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg4e8_v_u8mf4x4_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e8_v_u8mf4x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP3]], <vscale x 2 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] undef, <vscale x 2 x i8> [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP6]], <vscale x 2 x i8> [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP8]], <vscale x 2 x i8> [[TMP9]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP10]], <vscale x 2 x i8> [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP12]], <vscale x 2 x i8> [[TMP13]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP14]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP14]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP14]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg5.mask.nxv2i8.i32(<vscale x 2 x i8> [[TMP15]], <vscale x 2 x i8> [[TMP16]], <vscale x 2 x i8> [[TMP17]], <vscale x 2 x i8> [[TMP18]], <vscale x 2 x i8> [[TMP19]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] undef, <vscale x 2 x i8> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP22]], <vscale x 2 x i8> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP24]], <vscale x 2 x i8> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP26]], <vscale x 2 x i8> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP28]], <vscale x 2 x i8> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e8_v_u8mf4x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP3]], <vscale x 2 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] undef, <vscale x 2 x i8> [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP6]], <vscale x 2 x i8> [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP8]], <vscale x 2 x i8> [[TMP9]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP10]], <vscale x 2 x i8> [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP12]], <vscale x 2 x i8> [[TMP13]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP14]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP14]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP14]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg5.mask.nxv2i8.i64(<vscale x 2 x i8> [[TMP15]], <vscale x 2 x i8> [[TMP16]], <vscale x 2 x i8> [[TMP17]], <vscale x 2 x i8> [[TMP18]], <vscale x 2 x i8> [[TMP19]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] undef, <vscale x 2 x i8> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP22]], <vscale x 2 x i8> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP24]], <vscale x 2 x i8> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP26]], <vscale x 2 x i8> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP28]], <vscale x 2 x i8> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF4X5_T]] [[TMP30]]
+//
+vuint8mf4x5_t test_vlseg5e8_v_u8mf4x5_m (vbool32_t mask, vuint8mf4x5_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg5e8_v_u8mf4x5_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e8_v_u8mf4x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP3]], <vscale x 2 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP4]], <vscale x 2 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] undef, <vscale x 2 x i8> [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP7]], <vscale x 2 x i8> [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP9]], <vscale x 2 x i8> [[TMP10]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP11]], <vscale x 2 x i8> [[TMP12]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP13]], <vscale x 2 x i8> [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP15]], <vscale x 2 x i8> [[TMP16]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP17]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP17]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP17]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP17]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg6.mask.nxv2i8.i32(<vscale x 2 x i8> [[TMP18]], <vscale x 2 x i8> [[TMP19]], <vscale x 2 x i8> [[TMP20]], <vscale x 2 x i8> [[TMP21]], <vscale x 2 x i8> [[TMP22]], <vscale x 2 x i8> [[TMP23]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] undef, <vscale x 2 x i8> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP26]], <vscale x 2 x i8> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP28]], <vscale x 2 x i8> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP30]], <vscale x 2 x i8> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP32]], <vscale x 2 x i8> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP34]], <vscale x 2 x i8> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e8_v_u8mf4x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP3]], <vscale x 2 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP4]], <vscale x 2 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] undef, <vscale x 2 x i8> [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP7]], <vscale x 2 x i8> [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP9]], <vscale x 2 x i8> [[TMP10]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP11]], <vscale x 2 x i8> [[TMP12]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP13]], <vscale x 2 x i8> [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP15]], <vscale x 2 x i8> [[TMP16]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP17]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP17]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP17]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP17]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg6.mask.nxv2i8.i64(<vscale x 2 x i8> [[TMP18]], <vscale x 2 x i8> [[TMP19]], <vscale x 2 x i8> [[TMP20]], <vscale x 2 x i8> [[TMP21]], <vscale x 2 x i8> [[TMP22]], <vscale x 2 x i8> [[TMP23]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] undef, <vscale x 2 x i8> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP26]], <vscale x 2 x i8> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP28]], <vscale x 2 x i8> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP30]], <vscale x 2 x i8> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP32]], <vscale x 2 x i8> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP34]], <vscale x 2 x i8> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF4X6_T]] [[TMP36]]
+//
+vuint8mf4x6_t test_vlseg6e8_v_u8mf4x6_m (vbool32_t mask, vuint8mf4x6_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg6e8_v_u8mf4x6_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e8_v_u8mf4x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP3]], <vscale x 2 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP4]], <vscale x 2 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP5]], <vscale x 2 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] undef, <vscale x 2 x i8> [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP8]], <vscale x 2 x i8> [[TMP9]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP10]], <vscale x 2 x i8> [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP12]], <vscale x 2 x i8> [[TMP13]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP14]], <vscale x 2 x i8> [[TMP15]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP16]], <vscale x 2 x i8> [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP18]], <vscale x 2 x i8> [[TMP19]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP20]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg7.mask.nxv2i8.i32(<vscale x 2 x i8> [[TMP21]], <vscale x 2 x i8> [[TMP22]], <vscale x 2 x i8> [[TMP23]], <vscale x 2 x i8> [[TMP24]], <vscale x 2 x i8> [[TMP25]], <vscale x 2 x i8> [[TMP26]], <vscale x 2 x i8> [[TMP27]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] undef, <vscale x 2 x i8> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP30]], <vscale x 2 x i8> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP32]], <vscale x 2 x i8> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP34]], <vscale x 2 x i8> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP36]], <vscale x 2 x i8> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP38]], <vscale x 2 x i8> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP40]], <vscale x 2 x i8> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e8_v_u8mf4x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP3]], <vscale x 2 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP4]], <vscale x 2 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP5]], <vscale x 2 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] undef, <vscale x 2 x i8> [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP8]], <vscale x 2 x i8> [[TMP9]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP10]], <vscale x 2 x i8> [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP12]], <vscale x 2 x i8> [[TMP13]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP14]], <vscale x 2 x i8> [[TMP15]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP16]], <vscale x 2 x i8> [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP18]], <vscale x 2 x i8> [[TMP19]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP20]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg7.mask.nxv2i8.i64(<vscale x 2 x i8> [[TMP21]], <vscale x 2 x i8> [[TMP22]], <vscale x 2 x i8> [[TMP23]], <vscale x 2 x i8> [[TMP24]], <vscale x 2 x i8> [[TMP25]], <vscale x 2 x i8> [[TMP26]], <vscale x 2 x i8> [[TMP27]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] undef, <vscale x 2 x i8> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP30]], <vscale x 2 x i8> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP32]], <vscale x 2 x i8> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP34]], <vscale x 2 x i8> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP36]], <vscale x 2 x i8> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP38]], <vscale x 2 x i8> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP40]], <vscale x 2 x i8> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF4X7_T]] [[TMP42]]
+//
+vuint8mf4x7_t test_vlseg7e8_v_u8mf4x7_m (vbool32_t mask, vuint8mf4x7_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg7e8_v_u8mf4x7_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e8_v_u8mf4x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP3]], <vscale x 2 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP4]], <vscale x 2 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP5]], <vscale x 2 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP6]], <vscale x 2 x i8> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] undef, <vscale x 2 x i8> [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP9]], <vscale x 2 x i8> [[TMP10]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP11]], <vscale x 2 x i8> [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP13]], <vscale x 2 x i8> [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP15]], <vscale x 2 x i8> [[TMP16]], 4
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP17]], <vscale x 2 x i8> [[TMP18]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP19]], <vscale x 2 x i8> [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP21]], <vscale x 2 x i8> [[TMP22]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP23]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP23]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP23]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP23]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP23]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP23]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP23]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg8.mask.nxv2i8.i32(<vscale x 2 x i8> [[TMP24]], <vscale x 2 x i8> [[TMP25]], <vscale x 2 x i8> [[TMP26]], <vscale x 2 x i8> [[TMP27]], <vscale x 2 x i8> [[TMP28]], <vscale x 2 x i8> [[TMP29]], <vscale x 2 x i8> [[TMP30]], <vscale x 2 x i8> [[TMP31]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] undef, <vscale x 2 x i8> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP34]], <vscale x 2 x i8> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP36]], <vscale x 2 x i8> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP38]], <vscale x 2 x i8> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP40]], <vscale x 2 x i8> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP42]], <vscale x 2 x i8> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP44]], <vscale x 2 x i8> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP46]], <vscale x 2 x i8> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e8_v_u8mf4x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T:%.*]] undef, <vscale x 2 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP0]], <vscale x 2 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP1]], <vscale x 2 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP2]], <vscale x 2 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP3]], <vscale x 2 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP4]], <vscale x 2 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP5]], <vscale x 2 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP6]], <vscale x 2 x i8> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] undef, <vscale x 2 x i8> [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP9]], <vscale x 2 x i8> [[TMP10]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP11]], <vscale x 2 x i8> [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP13]], <vscale x 2 x i8> [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP15]], <vscale x 2 x i8> [[TMP16]], 4
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP17]], <vscale x 2 x i8> [[TMP18]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP19]], <vscale x 2 x i8> [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP21]], <vscale x 2 x i8> [[TMP22]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP23]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP23]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP23]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP23]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP23]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP23]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP23]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } @llvm.riscv.vlseg8.mask.nxv2i8.i64(<vscale x 2 x i8> [[TMP24]], <vscale x 2 x i8> [[TMP25]], <vscale x 2 x i8> [[TMP26]], <vscale x 2 x i8> [[TMP27]], <vscale x 2 x i8> [[TMP28]], <vscale x 2 x i8> [[TMP29]], <vscale x 2 x i8> [[TMP30]], <vscale x 2 x i8> [[TMP31]], i8* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] undef, <vscale x 2 x i8> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP34]], <vscale x 2 x i8> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP36]], <vscale x 2 x i8> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP38]], <vscale x 2 x i8> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP40]], <vscale x 2 x i8> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP42]], <vscale x 2 x i8> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP44]], <vscale x 2 x i8> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP46]], <vscale x 2 x i8> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF4X8_T]] [[TMP48]]
+//
+vuint8mf4x8_t test_vlseg8e8_v_u8mf4x8_m (vbool32_t mask, vuint8mf4x8_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg8e8_v_u8mf4x8_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_u8mf2x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X2_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X2_T]] undef, <vscale x 4 x i8> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP3]], <vscale x 4 x i8> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg2.mask.nxv4i8.i32(<vscale x 4 x i8> [[TMP6]], <vscale x 4 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X2_T]] undef, <vscale x 4 x i8> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP10]], <vscale x 4 x i8> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_u8mf2x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X2_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X2_T]] undef, <vscale x 4 x i8> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP3]], <vscale x 4 x i8> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg2.mask.nxv4i8.i64(<vscale x 4 x i8> [[TMP6]], <vscale x 4 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X2_T]] undef, <vscale x 4 x i8> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP10]], <vscale x 4 x i8> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF2X2_T]] [[TMP12]]
+//
+vuint8mf2x2_t test_vlseg2e8_v_u8mf2x2_m (vbool16_t mask, vuint8mf2x2_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg2e8_v_u8mf2x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e8_v_u8mf2x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T]] undef, <vscale x 4 x i8> [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP4]], <vscale x 4 x i8> [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP6]], <vscale x 4 x i8> [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg3.mask.nxv4i8.i32(<vscale x 4 x i8> [[TMP9]], <vscale x 4 x i8> [[TMP10]], <vscale x 4 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T]] undef, <vscale x 4 x i8> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP14]], <vscale x 4 x i8> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP16]], <vscale x 4 x i8> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e8_v_u8mf2x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T]] undef, <vscale x 4 x i8> [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP4]], <vscale x 4 x i8> [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP6]], <vscale x 4 x i8> [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg3.mask.nxv4i8.i64(<vscale x 4 x i8> [[TMP9]], <vscale x 4 x i8> [[TMP10]], <vscale x 4 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T]] undef, <vscale x 4 x i8> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP14]], <vscale x 4 x i8> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP16]], <vscale x 4 x i8> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF2X3_T]] [[TMP18]]
+//
+vuint8mf2x3_t test_vlseg3e8_v_u8mf2x3_m (vbool16_t mask, vuint8mf2x3_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg3e8_v_u8mf2x3_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e8_v_u8mf2x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] undef, <vscale x 4 x i8> [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP5]], <vscale x 4 x i8> [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP7]], <vscale x 4 x i8> [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP9]], <vscale x 4 x i8> [[TMP10]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP11]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP11]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg4.mask.nxv4i8.i32(<vscale x 4 x i8> [[TMP12]], <vscale x 4 x i8> [[TMP13]], <vscale x 4 x i8> [[TMP14]], <vscale x 4 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] undef, <vscale x 4 x i8> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP18]], <vscale x 4 x i8> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP20]], <vscale x 4 x i8> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP22]], <vscale x 4 x i8> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e8_v_u8mf2x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] undef, <vscale x 4 x i8> [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP5]], <vscale x 4 x i8> [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP7]], <vscale x 4 x i8> [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP9]], <vscale x 4 x i8> [[TMP10]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP11]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP11]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg4.mask.nxv4i8.i64(<vscale x 4 x i8> [[TMP12]], <vscale x 4 x i8> [[TMP13]], <vscale x 4 x i8> [[TMP14]], <vscale x 4 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] undef, <vscale x 4 x i8> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP18]], <vscale x 4 x i8> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP20]], <vscale x 4 x i8> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP22]], <vscale x 4 x i8> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF2X4_T]] [[TMP24]]
+//
+vuint8mf2x4_t test_vlseg4e8_v_u8mf2x4_m (vbool16_t mask, vuint8mf2x4_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg4e8_v_u8mf2x4_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e8_v_u8mf2x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP3]], <vscale x 4 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] undef, <vscale x 4 x i8> [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP6]], <vscale x 4 x i8> [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP8]], <vscale x 4 x i8> [[TMP9]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP10]], <vscale x 4 x i8> [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP12]], <vscale x 4 x i8> [[TMP13]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP14]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP14]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP14]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg5.mask.nxv4i8.i32(<vscale x 4 x i8> [[TMP15]], <vscale x 4 x i8> [[TMP16]], <vscale x 4 x i8> [[TMP17]], <vscale x 4 x i8> [[TMP18]], <vscale x 4 x i8> [[TMP19]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] undef, <vscale x 4 x i8> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP22]], <vscale x 4 x i8> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP24]], <vscale x 4 x i8> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP26]], <vscale x 4 x i8> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP28]], <vscale x 4 x i8> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e8_v_u8mf2x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP3]], <vscale x 4 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] undef, <vscale x 4 x i8> [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP6]], <vscale x 4 x i8> [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP8]], <vscale x 4 x i8> [[TMP9]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP10]], <vscale x 4 x i8> [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP12]], <vscale x 4 x i8> [[TMP13]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP14]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP14]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP14]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg5.mask.nxv4i8.i64(<vscale x 4 x i8> [[TMP15]], <vscale x 4 x i8> [[TMP16]], <vscale x 4 x i8> [[TMP17]], <vscale x 4 x i8> [[TMP18]], <vscale x 4 x i8> [[TMP19]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] undef, <vscale x 4 x i8> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP22]], <vscale x 4 x i8> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP24]], <vscale x 4 x i8> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP26]], <vscale x 4 x i8> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP28]], <vscale x 4 x i8> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF2X5_T]] [[TMP30]]
+//
+vuint8mf2x5_t test_vlseg5e8_v_u8mf2x5_m (vbool16_t mask, vuint8mf2x5_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg5e8_v_u8mf2x5_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e8_v_u8mf2x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP3]], <vscale x 4 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP4]], <vscale x 4 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] undef, <vscale x 4 x i8> [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP7]], <vscale x 4 x i8> [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP9]], <vscale x 4 x i8> [[TMP10]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP11]], <vscale x 4 x i8> [[TMP12]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP13]], <vscale x 4 x i8> [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP15]], <vscale x 4 x i8> [[TMP16]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP17]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP17]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP17]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP17]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg6.mask.nxv4i8.i32(<vscale x 4 x i8> [[TMP18]], <vscale x 4 x i8> [[TMP19]], <vscale x 4 x i8> [[TMP20]], <vscale x 4 x i8> [[TMP21]], <vscale x 4 x i8> [[TMP22]], <vscale x 4 x i8> [[TMP23]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] undef, <vscale x 4 x i8> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP26]], <vscale x 4 x i8> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP28]], <vscale x 4 x i8> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP30]], <vscale x 4 x i8> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP32]], <vscale x 4 x i8> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP34]], <vscale x 4 x i8> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e8_v_u8mf2x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP3]], <vscale x 4 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP4]], <vscale x 4 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] undef, <vscale x 4 x i8> [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP7]], <vscale x 4 x i8> [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP9]], <vscale x 4 x i8> [[TMP10]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP11]], <vscale x 4 x i8> [[TMP12]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP13]], <vscale x 4 x i8> [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP15]], <vscale x 4 x i8> [[TMP16]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP17]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP17]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP17]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP17]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg6.mask.nxv4i8.i64(<vscale x 4 x i8> [[TMP18]], <vscale x 4 x i8> [[TMP19]], <vscale x 4 x i8> [[TMP20]], <vscale x 4 x i8> [[TMP21]], <vscale x 4 x i8> [[TMP22]], <vscale x 4 x i8> [[TMP23]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] undef, <vscale x 4 x i8> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP26]], <vscale x 4 x i8> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP28]], <vscale x 4 x i8> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP30]], <vscale x 4 x i8> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP32]], <vscale x 4 x i8> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP34]], <vscale x 4 x i8> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF2X6_T]] [[TMP36]]
+//
+vuint8mf2x6_t test_vlseg6e8_v_u8mf2x6_m (vbool16_t mask, vuint8mf2x6_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg6e8_v_u8mf2x6_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e8_v_u8mf2x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP3]], <vscale x 4 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP4]], <vscale x 4 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP5]], <vscale x 4 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] undef, <vscale x 4 x i8> [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP8]], <vscale x 4 x i8> [[TMP9]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP10]], <vscale x 4 x i8> [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP12]], <vscale x 4 x i8> [[TMP13]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP14]], <vscale x 4 x i8> [[TMP15]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP16]], <vscale x 4 x i8> [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP18]], <vscale x 4 x i8> [[TMP19]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP20]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg7.mask.nxv4i8.i32(<vscale x 4 x i8> [[TMP21]], <vscale x 4 x i8> [[TMP22]], <vscale x 4 x i8> [[TMP23]], <vscale x 4 x i8> [[TMP24]], <vscale x 4 x i8> [[TMP25]], <vscale x 4 x i8> [[TMP26]], <vscale x 4 x i8> [[TMP27]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] undef, <vscale x 4 x i8> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP30]], <vscale x 4 x i8> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP32]], <vscale x 4 x i8> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP34]], <vscale x 4 x i8> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP36]], <vscale x 4 x i8> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP38]], <vscale x 4 x i8> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP40]], <vscale x 4 x i8> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e8_v_u8mf2x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP3]], <vscale x 4 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP4]], <vscale x 4 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP5]], <vscale x 4 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] undef, <vscale x 4 x i8> [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP8]], <vscale x 4 x i8> [[TMP9]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP10]], <vscale x 4 x i8> [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP12]], <vscale x 4 x i8> [[TMP13]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP14]], <vscale x 4 x i8> [[TMP15]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP16]], <vscale x 4 x i8> [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP18]], <vscale x 4 x i8> [[TMP19]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP20]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg7.mask.nxv4i8.i64(<vscale x 4 x i8> [[TMP21]], <vscale x 4 x i8> [[TMP22]], <vscale x 4 x i8> [[TMP23]], <vscale x 4 x i8> [[TMP24]], <vscale x 4 x i8> [[TMP25]], <vscale x 4 x i8> [[TMP26]], <vscale x 4 x i8> [[TMP27]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] undef, <vscale x 4 x i8> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP30]], <vscale x 4 x i8> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP32]], <vscale x 4 x i8> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP34]], <vscale x 4 x i8> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP36]], <vscale x 4 x i8> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP38]], <vscale x 4 x i8> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP40]], <vscale x 4 x i8> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF2X7_T]] [[TMP42]]
+//
+vuint8mf2x7_t test_vlseg7e8_v_u8mf2x7_m (vbool16_t mask, vuint8mf2x7_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg7e8_v_u8mf2x7_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e8_v_u8mf2x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP3]], <vscale x 4 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP4]], <vscale x 4 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP5]], <vscale x 4 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP6]], <vscale x 4 x i8> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] undef, <vscale x 4 x i8> [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP9]], <vscale x 4 x i8> [[TMP10]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP11]], <vscale x 4 x i8> [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP13]], <vscale x 4 x i8> [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP15]], <vscale x 4 x i8> [[TMP16]], 4
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP17]], <vscale x 4 x i8> [[TMP18]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP19]], <vscale x 4 x i8> [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP21]], <vscale x 4 x i8> [[TMP22]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP23]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP23]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP23]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP23]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP23]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP23]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP23]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg8.mask.nxv4i8.i32(<vscale x 4 x i8> [[TMP24]], <vscale x 4 x i8> [[TMP25]], <vscale x 4 x i8> [[TMP26]], <vscale x 4 x i8> [[TMP27]], <vscale x 4 x i8> [[TMP28]], <vscale x 4 x i8> [[TMP29]], <vscale x 4 x i8> [[TMP30]], <vscale x 4 x i8> [[TMP31]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] undef, <vscale x 4 x i8> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP34]], <vscale x 4 x i8> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP36]], <vscale x 4 x i8> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP38]], <vscale x 4 x i8> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP40]], <vscale x 4 x i8> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP42]], <vscale x 4 x i8> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP44]], <vscale x 4 x i8> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP46]], <vscale x 4 x i8> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e8_v_u8mf2x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T:%.*]] undef, <vscale x 4 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP0]], <vscale x 4 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP1]], <vscale x 4 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP2]], <vscale x 4 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP3]], <vscale x 4 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP4]], <vscale x 4 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP5]], <vscale x 4 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP6]], <vscale x 4 x i8> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] undef, <vscale x 4 x i8> [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP9]], <vscale x 4 x i8> [[TMP10]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP11]], <vscale x 4 x i8> [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP13]], <vscale x 4 x i8> [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP15]], <vscale x 4 x i8> [[TMP16]], 4
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP17]], <vscale x 4 x i8> [[TMP18]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP19]], <vscale x 4 x i8> [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP21]], <vscale x 4 x i8> [[TMP22]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP23]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP23]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP23]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP23]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP23]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP23]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP23]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.riscv.vlseg8.mask.nxv4i8.i64(<vscale x 4 x i8> [[TMP24]], <vscale x 4 x i8> [[TMP25]], <vscale x 4 x i8> [[TMP26]], <vscale x 4 x i8> [[TMP27]], <vscale x 4 x i8> [[TMP28]], <vscale x 4 x i8> [[TMP29]], <vscale x 4 x i8> [[TMP30]], <vscale x 4 x i8> [[TMP31]], i8* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] undef, <vscale x 4 x i8> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP34]], <vscale x 4 x i8> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP36]], <vscale x 4 x i8> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP38]], <vscale x 4 x i8> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP40]], <vscale x 4 x i8> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP42]], <vscale x 4 x i8> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP44]], <vscale x 4 x i8> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP46]], <vscale x 4 x i8> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8MF2X8_T]] [[TMP48]]
+//
+vuint8mf2x8_t test_vlseg8e8_v_u8mf2x8_m (vbool16_t mask, vuint8mf2x8_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg8e8_v_u8mf2x8_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_u8m1x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X2_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X2_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X2_T]] undef, <vscale x 8 x i8> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X2_T]] [[TMP3]], <vscale x 8 x i8> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg2.mask.nxv8i8.i32(<vscale x 8 x i8> [[TMP6]], <vscale x 8 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X2_T]] undef, <vscale x 8 x i8> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X2_T]] [[TMP10]], <vscale x 8 x i8> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8M1X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_u8m1x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X2_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X2_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X2_T]] undef, <vscale x 8 x i8> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X2_T]] [[TMP3]], <vscale x 8 x i8> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg2.mask.nxv8i8.i64(<vscale x 8 x i8> [[TMP6]], <vscale x 8 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X2_T]] undef, <vscale x 8 x i8> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X2_T]] [[TMP10]], <vscale x 8 x i8> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8M1X2_T]] [[TMP12]]
+//
+vuint8m1x2_t test_vlseg2e8_v_u8m1x2_m (vbool8_t mask, vuint8m1x2_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg2e8_v_u8m1x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e8_v_u8m1x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T]] undef, <vscale x 8 x i8> [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP4]], <vscale x 8 x i8> [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP6]], <vscale x 8 x i8> [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg3.mask.nxv8i8.i32(<vscale x 8 x i8> [[TMP9]], <vscale x 8 x i8> [[TMP10]], <vscale x 8 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T]] undef, <vscale x 8 x i8> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP14]], <vscale x 8 x i8> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP16]], <vscale x 8 x i8> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8M1X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e8_v_u8m1x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T]] undef, <vscale x 8 x i8> [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP4]], <vscale x 8 x i8> [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP6]], <vscale x 8 x i8> [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg3.mask.nxv8i8.i64(<vscale x 8 x i8> [[TMP9]], <vscale x 8 x i8> [[TMP10]], <vscale x 8 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T]] undef, <vscale x 8 x i8> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP14]], <vscale x 8 x i8> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X3_T]] [[TMP16]], <vscale x 8 x i8> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8M1X3_T]] [[TMP18]]
+//
+vuint8m1x3_t test_vlseg3e8_v_u8m1x3_m (vbool8_t mask, vuint8m1x3_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg3e8_v_u8m1x3_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e8_v_u8m1x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] undef, <vscale x 8 x i8> [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP5]], <vscale x 8 x i8> [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP7]], <vscale x 8 x i8> [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP9]], <vscale x 8 x i8> [[TMP10]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP11]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP11]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg4.mask.nxv8i8.i32(<vscale x 8 x i8> [[TMP12]], <vscale x 8 x i8> [[TMP13]], <vscale x 8 x i8> [[TMP14]], <vscale x 8 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] undef, <vscale x 8 x i8> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP18]], <vscale x 8 x i8> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP20]], <vscale x 8 x i8> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP22]], <vscale x 8 x i8> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8M1X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e8_v_u8m1x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] undef, <vscale x 8 x i8> [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP5]], <vscale x 8 x i8> [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP7]], <vscale x 8 x i8> [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP9]], <vscale x 8 x i8> [[TMP10]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP11]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP11]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg4.mask.nxv8i8.i64(<vscale x 8 x i8> [[TMP12]], <vscale x 8 x i8> [[TMP13]], <vscale x 8 x i8> [[TMP14]], <vscale x 8 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] undef, <vscale x 8 x i8> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP18]], <vscale x 8 x i8> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP20]], <vscale x 8 x i8> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X4_T]] [[TMP22]], <vscale x 8 x i8> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8M1X4_T]] [[TMP24]]
+//
+vuint8m1x4_t test_vlseg4e8_v_u8m1x4_m (vbool8_t mask, vuint8m1x4_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg4e8_v_u8m1x4_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e8_v_u8m1x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP3]], <vscale x 8 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] undef, <vscale x 8 x i8> [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP6]], <vscale x 8 x i8> [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP8]], <vscale x 8 x i8> [[TMP9]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP10]], <vscale x 8 x i8> [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP12]], <vscale x 8 x i8> [[TMP13]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP14]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP14]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP14]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg5.mask.nxv8i8.i32(<vscale x 8 x i8> [[TMP15]], <vscale x 8 x i8> [[TMP16]], <vscale x 8 x i8> [[TMP17]], <vscale x 8 x i8> [[TMP18]], <vscale x 8 x i8> [[TMP19]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] undef, <vscale x 8 x i8> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP22]], <vscale x 8 x i8> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP24]], <vscale x 8 x i8> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP26]], <vscale x 8 x i8> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP28]], <vscale x 8 x i8> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8M1X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e8_v_u8m1x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP3]], <vscale x 8 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] undef, <vscale x 8 x i8> [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP6]], <vscale x 8 x i8> [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP8]], <vscale x 8 x i8> [[TMP9]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP10]], <vscale x 8 x i8> [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP12]], <vscale x 8 x i8> [[TMP13]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP14]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP14]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP14]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg5.mask.nxv8i8.i64(<vscale x 8 x i8> [[TMP15]], <vscale x 8 x i8> [[TMP16]], <vscale x 8 x i8> [[TMP17]], <vscale x 8 x i8> [[TMP18]], <vscale x 8 x i8> [[TMP19]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] undef, <vscale x 8 x i8> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP22]], <vscale x 8 x i8> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP24]], <vscale x 8 x i8> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP26]], <vscale x 8 x i8> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X5_T]] [[TMP28]], <vscale x 8 x i8> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8M1X5_T]] [[TMP30]]
+//
+vuint8m1x5_t test_vlseg5e8_v_u8m1x5_m (vbool8_t mask, vuint8m1x5_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg5e8_v_u8m1x5_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e8_v_u8m1x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP3]], <vscale x 8 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP4]], <vscale x 8 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] undef, <vscale x 8 x i8> [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP7]], <vscale x 8 x i8> [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP9]], <vscale x 8 x i8> [[TMP10]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP11]], <vscale x 8 x i8> [[TMP12]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP13]], <vscale x 8 x i8> [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP15]], <vscale x 8 x i8> [[TMP16]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP17]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP17]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP17]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP17]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg6.mask.nxv8i8.i32(<vscale x 8 x i8> [[TMP18]], <vscale x 8 x i8> [[TMP19]], <vscale x 8 x i8> [[TMP20]], <vscale x 8 x i8> [[TMP21]], <vscale x 8 x i8> [[TMP22]], <vscale x 8 x i8> [[TMP23]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] undef, <vscale x 8 x i8> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP26]], <vscale x 8 x i8> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP28]], <vscale x 8 x i8> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP30]], <vscale x 8 x i8> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP32]], <vscale x 8 x i8> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP34]], <vscale x 8 x i8> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8M1X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e8_v_u8m1x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP3]], <vscale x 8 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP4]], <vscale x 8 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] undef, <vscale x 8 x i8> [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP7]], <vscale x 8 x i8> [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP9]], <vscale x 8 x i8> [[TMP10]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP11]], <vscale x 8 x i8> [[TMP12]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP13]], <vscale x 8 x i8> [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP15]], <vscale x 8 x i8> [[TMP16]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP17]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP17]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP17]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP17]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg6.mask.nxv8i8.i64(<vscale x 8 x i8> [[TMP18]], <vscale x 8 x i8> [[TMP19]], <vscale x 8 x i8> [[TMP20]], <vscale x 8 x i8> [[TMP21]], <vscale x 8 x i8> [[TMP22]], <vscale x 8 x i8> [[TMP23]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] undef, <vscale x 8 x i8> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP26]], <vscale x 8 x i8> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP28]], <vscale x 8 x i8> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP30]], <vscale x 8 x i8> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP32]], <vscale x 8 x i8> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X6_T]] [[TMP34]], <vscale x 8 x i8> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8M1X6_T]] [[TMP36]]
+//
+vuint8m1x6_t test_vlseg6e8_v_u8m1x6_m (vbool8_t mask, vuint8m1x6_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg6e8_v_u8m1x6_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e8_v_u8m1x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP3]], <vscale x 8 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP4]], <vscale x 8 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP5]], <vscale x 8 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] undef, <vscale x 8 x i8> [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP8]], <vscale x 8 x i8> [[TMP9]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP10]], <vscale x 8 x i8> [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP12]], <vscale x 8 x i8> [[TMP13]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP14]], <vscale x 8 x i8> [[TMP15]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP16]], <vscale x 8 x i8> [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP18]], <vscale x 8 x i8> [[TMP19]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP20]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg7.mask.nxv8i8.i32(<vscale x 8 x i8> [[TMP21]], <vscale x 8 x i8> [[TMP22]], <vscale x 8 x i8> [[TMP23]], <vscale x 8 x i8> [[TMP24]], <vscale x 8 x i8> [[TMP25]], <vscale x 8 x i8> [[TMP26]], <vscale x 8 x i8> [[TMP27]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] undef, <vscale x 8 x i8> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP30]], <vscale x 8 x i8> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP32]], <vscale x 8 x i8> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP34]], <vscale x 8 x i8> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP36]], <vscale x 8 x i8> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP38]], <vscale x 8 x i8> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP40]], <vscale x 8 x i8> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8M1X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e8_v_u8m1x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP3]], <vscale x 8 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP4]], <vscale x 8 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP5]], <vscale x 8 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] undef, <vscale x 8 x i8> [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP8]], <vscale x 8 x i8> [[TMP9]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP10]], <vscale x 8 x i8> [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP12]], <vscale x 8 x i8> [[TMP13]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP14]], <vscale x 8 x i8> [[TMP15]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP16]], <vscale x 8 x i8> [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP18]], <vscale x 8 x i8> [[TMP19]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP20]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg7.mask.nxv8i8.i64(<vscale x 8 x i8> [[TMP21]], <vscale x 8 x i8> [[TMP22]], <vscale x 8 x i8> [[TMP23]], <vscale x 8 x i8> [[TMP24]], <vscale x 8 x i8> [[TMP25]], <vscale x 8 x i8> [[TMP26]], <vscale x 8 x i8> [[TMP27]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] undef, <vscale x 8 x i8> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP30]], <vscale x 8 x i8> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP32]], <vscale x 8 x i8> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP34]], <vscale x 8 x i8> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP36]], <vscale x 8 x i8> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP38]], <vscale x 8 x i8> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X7_T]] [[TMP40]], <vscale x 8 x i8> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8M1X7_T]] [[TMP42]]
+//
+vuint8m1x7_t test_vlseg7e8_v_u8m1x7_m (vbool8_t mask, vuint8m1x7_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg7e8_v_u8m1x7_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e8_v_u8m1x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP3]], <vscale x 8 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP4]], <vscale x 8 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP5]], <vscale x 8 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP6]], <vscale x 8 x i8> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] undef, <vscale x 8 x i8> [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP9]], <vscale x 8 x i8> [[TMP10]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP11]], <vscale x 8 x i8> [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP13]], <vscale x 8 x i8> [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP15]], <vscale x 8 x i8> [[TMP16]], 4
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP17]], <vscale x 8 x i8> [[TMP18]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP19]], <vscale x 8 x i8> [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP21]], <vscale x 8 x i8> [[TMP22]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP23]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP23]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP23]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP23]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP23]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP23]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP23]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg8.mask.nxv8i8.i32(<vscale x 8 x i8> [[TMP24]], <vscale x 8 x i8> [[TMP25]], <vscale x 8 x i8> [[TMP26]], <vscale x 8 x i8> [[TMP27]], <vscale x 8 x i8> [[TMP28]], <vscale x 8 x i8> [[TMP29]], <vscale x 8 x i8> [[TMP30]], <vscale x 8 x i8> [[TMP31]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] undef, <vscale x 8 x i8> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP34]], <vscale x 8 x i8> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP36]], <vscale x 8 x i8> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP38]], <vscale x 8 x i8> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP40]], <vscale x 8 x i8> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP42]], <vscale x 8 x i8> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP44]], <vscale x 8 x i8> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP46]], <vscale x 8 x i8> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8M1X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e8_v_u8m1x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T:%.*]] undef, <vscale x 8 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP0]], <vscale x 8 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP1]], <vscale x 8 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP2]], <vscale x 8 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP3]], <vscale x 8 x i8> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP4]], <vscale x 8 x i8> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP5]], <vscale x 8 x i8> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP6]], <vscale x 8 x i8> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] undef, <vscale x 8 x i8> [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP9]], <vscale x 8 x i8> [[TMP10]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP11]], <vscale x 8 x i8> [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP13]], <vscale x 8 x i8> [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP15]], <vscale x 8 x i8> [[TMP16]], 4
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP17]], <vscale x 8 x i8> [[TMP18]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP19]], <vscale x 8 x i8> [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP21]], <vscale x 8 x i8> [[TMP22]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP23]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP23]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP23]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP23]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP23]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP23]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP23]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.riscv.vlseg8.mask.nxv8i8.i64(<vscale x 8 x i8> [[TMP24]], <vscale x 8 x i8> [[TMP25]], <vscale x 8 x i8> [[TMP26]], <vscale x 8 x i8> [[TMP27]], <vscale x 8 x i8> [[TMP28]], <vscale x 8 x i8> [[TMP29]], <vscale x 8 x i8> [[TMP30]], <vscale x 8 x i8> [[TMP31]], i8* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] undef, <vscale x 8 x i8> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP34]], <vscale x 8 x i8> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP36]], <vscale x 8 x i8> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP38]], <vscale x 8 x i8> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP40]], <vscale x 8 x i8> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP42]], <vscale x 8 x i8> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP44]], <vscale x 8 x i8> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT8M1X8_T]] [[TMP46]], <vscale x 8 x i8> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8M1X8_T]] [[TMP48]]
+//
+vuint8m1x8_t test_vlseg8e8_v_u8m1x8_m (vbool8_t mask, vuint8m1x8_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg8e8_v_u8m1x8_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_u8m2x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X2_T:%.*]] undef, <vscale x 16 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X2_T]] [[TMP0]], <vscale x 16 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X2_T]] undef, <vscale x 16 x i8> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X2_T]] [[TMP3]], <vscale x 16 x i8> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg2.mask.nxv16i8.i32(<vscale x 16 x i8> [[TMP6]], <vscale x 16 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X2_T]] undef, <vscale x 16 x i8> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X2_T]] [[TMP10]], <vscale x 16 x i8> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8M2X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_u8m2x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X2_T:%.*]] undef, <vscale x 16 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X2_T]] [[TMP0]], <vscale x 16 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X2_T]] undef, <vscale x 16 x i8> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X2_T]] [[TMP3]], <vscale x 16 x i8> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg2.mask.nxv16i8.i64(<vscale x 16 x i8> [[TMP6]], <vscale x 16 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X2_T]] undef, <vscale x 16 x i8> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X2_T]] [[TMP10]], <vscale x 16 x i8> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8M2X2_T]] [[TMP12]]
+//
+vuint8m2x2_t test_vlseg2e8_v_u8m2x2_m (vbool4_t mask, vuint8m2x2_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg2e8_v_u8m2x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e8_v_u8m2x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T:%.*]] undef, <vscale x 16 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP0]], <vscale x 16 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP1]], <vscale x 16 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T]] undef, <vscale x 16 x i8> [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP4]], <vscale x 16 x i8> [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP6]], <vscale x 16 x i8> [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg3.mask.nxv16i8.i32(<vscale x 16 x i8> [[TMP9]], <vscale x 16 x i8> [[TMP10]], <vscale x 16 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T]] undef, <vscale x 16 x i8> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP14]], <vscale x 16 x i8> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP16]], <vscale x 16 x i8> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8M2X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e8_v_u8m2x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T:%.*]] undef, <vscale x 16 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP0]], <vscale x 16 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP1]], <vscale x 16 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T]] undef, <vscale x 16 x i8> [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP4]], <vscale x 16 x i8> [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP6]], <vscale x 16 x i8> [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg3.mask.nxv16i8.i64(<vscale x 16 x i8> [[TMP9]], <vscale x 16 x i8> [[TMP10]], <vscale x 16 x i8> [[TMP11]], i8* [[BASE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T]] undef, <vscale x 16 x i8> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP14]], <vscale x 16 x i8> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X3_T]] [[TMP16]], <vscale x 16 x i8> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8M2X3_T]] [[TMP18]]
+//
+vuint8m2x3_t test_vlseg3e8_v_u8m2x3_m (vbool4_t mask, vuint8m2x3_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg3e8_v_u8m2x3_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e8_v_u8m2x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T:%.*]] undef, <vscale x 16 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP0]], <vscale x 16 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP1]], <vscale x 16 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP2]], <vscale x 16 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] undef, <vscale x 16 x i8> [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP5]], <vscale x 16 x i8> [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP7]], <vscale x 16 x i8> [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP9]], <vscale x 16 x i8> [[TMP10]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP11]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP11]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg4.mask.nxv16i8.i32(<vscale x 16 x i8> [[TMP12]], <vscale x 16 x i8> [[TMP13]], <vscale x 16 x i8> [[TMP14]], <vscale x 16 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] undef, <vscale x 16 x i8> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP18]], <vscale x 16 x i8> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP20]], <vscale x 16 x i8> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP22]], <vscale x 16 x i8> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8M2X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e8_v_u8m2x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T:%.*]] undef, <vscale x 16 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP0]], <vscale x 16 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP1]], <vscale x 16 x i8> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP2]], <vscale x 16 x i8> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] undef, <vscale x 16 x i8> [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP5]], <vscale x 16 x i8> [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP7]], <vscale x 16 x i8> [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP9]], <vscale x 16 x i8> [[TMP10]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP11]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP11]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.riscv.vlseg4.mask.nxv16i8.i64(<vscale x 16 x i8> [[TMP12]], <vscale x 16 x i8> [[TMP13]], <vscale x 16 x i8> [[TMP14]], <vscale x 16 x i8> [[TMP15]], i8* [[BASE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] undef, <vscale x 16 x i8> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP18]], <vscale x 16 x i8> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP20]], <vscale x 16 x i8> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT8M2X4_T]] [[TMP22]], <vscale x 16 x i8> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8M2X4_T]] [[TMP24]]
+//
+vuint8m2x4_t test_vlseg4e8_v_u8m2x4_m (vbool4_t mask, vuint8m2x4_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg4e8_v_u8m2x4_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e8_v_u8m4x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M4X2_T:%.*]] undef, <vscale x 32 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M4X2_T]] [[TMP0]], <vscale x 32 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT8M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8M4X2_T]] undef, <vscale x 32 x i8> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8M4X2_T]] [[TMP3]], <vscale x 32 x i8> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8M4X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8M4X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 32 x i8>, <vscale x 32 x i8> } @llvm.riscv.vlseg2.mask.nxv32i8.i32(<vscale x 32 x i8> [[TMP6]], <vscale x 32 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8M4X2_T]] undef, <vscale x 32 x i8> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8M4X2_T]] [[TMP10]], <vscale x 32 x i8> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT8M4X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e8_v_u8m4x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT8M4X2_T:%.*]] undef, <vscale x 32 x i8> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT8M4X2_T]] [[TMP0]], <vscale x 32 x i8> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT8M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT8M4X2_T]] undef, <vscale x 32 x i8> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT8M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT8M4X2_T]] [[TMP3]], <vscale x 32 x i8> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT8M4X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT8M4X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 32 x i8>, <vscale x 32 x i8> } @llvm.riscv.vlseg2.mask.nxv32i8.i64(<vscale x 32 x i8> [[TMP6]], <vscale x 32 x i8> [[TMP7]], i8* [[BASE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT8M4X2_T]] undef, <vscale x 32 x i8> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i8> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT8M4X2_T]] [[TMP10]], <vscale x 32 x i8> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT8M4X2_T]] [[TMP12]]
+//
+vuint8m4x2_t test_vlseg2e8_v_u8m4x2_m (vbool2_t mask, vuint8m4x2_t maskedoff, const uint8_t *base, size_t vl) {
+  return vlseg2e8_v_u8m4x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e16_v_u16mf4x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X2_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X2_T]] undef, <vscale x 1 x i16> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP3]], <vscale x 1 x i16> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg2.mask.nxv1i16.i32(<vscale x 1 x i16> [[TMP6]], <vscale x 1 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X2_T]] undef, <vscale x 1 x i16> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP10]], <vscale x 1 x i16> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e16_v_u16mf4x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X2_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X2_T]] undef, <vscale x 1 x i16> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP3]], <vscale x 1 x i16> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg2.mask.nxv1i16.i64(<vscale x 1 x i16> [[TMP6]], <vscale x 1 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X2_T]] undef, <vscale x 1 x i16> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP10]], <vscale x 1 x i16> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF4X2_T]] [[TMP12]]
+//
+vuint16mf4x2_t test_vlseg2e16_v_u16mf4x2_m (vbool64_t mask, vuint16mf4x2_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg2e16_v_u16mf4x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e16_v_u16mf4x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T]] undef, <vscale x 1 x i16> [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP4]], <vscale x 1 x i16> [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP6]], <vscale x 1 x i16> [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg3.mask.nxv1i16.i32(<vscale x 1 x i16> [[TMP9]], <vscale x 1 x i16> [[TMP10]], <vscale x 1 x i16> [[TMP11]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T]] undef, <vscale x 1 x i16> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP14]], <vscale x 1 x i16> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP16]], <vscale x 1 x i16> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e16_v_u16mf4x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T]] undef, <vscale x 1 x i16> [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP4]], <vscale x 1 x i16> [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP6]], <vscale x 1 x i16> [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg3.mask.nxv1i16.i64(<vscale x 1 x i16> [[TMP9]], <vscale x 1 x i16> [[TMP10]], <vscale x 1 x i16> [[TMP11]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T]] undef, <vscale x 1 x i16> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP14]], <vscale x 1 x i16> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP16]], <vscale x 1 x i16> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF4X3_T]] [[TMP18]]
+//
+vuint16mf4x3_t test_vlseg3e16_v_u16mf4x3_m (vbool64_t mask, vuint16mf4x3_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg3e16_v_u16mf4x3_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e16_v_u16mf4x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] undef, <vscale x 1 x i16> [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP5]], <vscale x 1 x i16> [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP7]], <vscale x 1 x i16> [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP9]], <vscale x 1 x i16> [[TMP10]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP11]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP11]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg4.mask.nxv1i16.i32(<vscale x 1 x i16> [[TMP12]], <vscale x 1 x i16> [[TMP13]], <vscale x 1 x i16> [[TMP14]], <vscale x 1 x i16> [[TMP15]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] undef, <vscale x 1 x i16> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP18]], <vscale x 1 x i16> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP20]], <vscale x 1 x i16> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP22]], <vscale x 1 x i16> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e16_v_u16mf4x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] undef, <vscale x 1 x i16> [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP5]], <vscale x 1 x i16> [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP7]], <vscale x 1 x i16> [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP9]], <vscale x 1 x i16> [[TMP10]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP11]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP11]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg4.mask.nxv1i16.i64(<vscale x 1 x i16> [[TMP12]], <vscale x 1 x i16> [[TMP13]], <vscale x 1 x i16> [[TMP14]], <vscale x 1 x i16> [[TMP15]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] undef, <vscale x 1 x i16> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP18]], <vscale x 1 x i16> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP20]], <vscale x 1 x i16> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP22]], <vscale x 1 x i16> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF4X4_T]] [[TMP24]]
+//
+vuint16mf4x4_t test_vlseg4e16_v_u16mf4x4_m (vbool64_t mask, vuint16mf4x4_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg4e16_v_u16mf4x4_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e16_v_u16mf4x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP3]], <vscale x 1 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] undef, <vscale x 1 x i16> [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP6]], <vscale x 1 x i16> [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP8]], <vscale x 1 x i16> [[TMP9]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP10]], <vscale x 1 x i16> [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP12]], <vscale x 1 x i16> [[TMP13]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP14]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP14]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP14]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg5.mask.nxv1i16.i32(<vscale x 1 x i16> [[TMP15]], <vscale x 1 x i16> [[TMP16]], <vscale x 1 x i16> [[TMP17]], <vscale x 1 x i16> [[TMP18]], <vscale x 1 x i16> [[TMP19]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] undef, <vscale x 1 x i16> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP22]], <vscale x 1 x i16> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP24]], <vscale x 1 x i16> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP26]], <vscale x 1 x i16> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP28]], <vscale x 1 x i16> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e16_v_u16mf4x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP3]], <vscale x 1 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] undef, <vscale x 1 x i16> [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP6]], <vscale x 1 x i16> [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP8]], <vscale x 1 x i16> [[TMP9]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP10]], <vscale x 1 x i16> [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP12]], <vscale x 1 x i16> [[TMP13]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP14]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP14]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP14]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg5.mask.nxv1i16.i64(<vscale x 1 x i16> [[TMP15]], <vscale x 1 x i16> [[TMP16]], <vscale x 1 x i16> [[TMP17]], <vscale x 1 x i16> [[TMP18]], <vscale x 1 x i16> [[TMP19]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] undef, <vscale x 1 x i16> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP22]], <vscale x 1 x i16> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP24]], <vscale x 1 x i16> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP26]], <vscale x 1 x i16> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP28]], <vscale x 1 x i16> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF4X5_T]] [[TMP30]]
+//
+vuint16mf4x5_t test_vlseg5e16_v_u16mf4x5_m (vbool64_t mask, vuint16mf4x5_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg5e16_v_u16mf4x5_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e16_v_u16mf4x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP3]], <vscale x 1 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP4]], <vscale x 1 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] undef, <vscale x 1 x i16> [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP7]], <vscale x 1 x i16> [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP9]], <vscale x 1 x i16> [[TMP10]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP11]], <vscale x 1 x i16> [[TMP12]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP13]], <vscale x 1 x i16> [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP15]], <vscale x 1 x i16> [[TMP16]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP17]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP17]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP17]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP17]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg6.mask.nxv1i16.i32(<vscale x 1 x i16> [[TMP18]], <vscale x 1 x i16> [[TMP19]], <vscale x 1 x i16> [[TMP20]], <vscale x 1 x i16> [[TMP21]], <vscale x 1 x i16> [[TMP22]], <vscale x 1 x i16> [[TMP23]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] undef, <vscale x 1 x i16> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP26]], <vscale x 1 x i16> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP28]], <vscale x 1 x i16> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP30]], <vscale x 1 x i16> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP32]], <vscale x 1 x i16> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP34]], <vscale x 1 x i16> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e16_v_u16mf4x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP3]], <vscale x 1 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP4]], <vscale x 1 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] undef, <vscale x 1 x i16> [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP7]], <vscale x 1 x i16> [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP9]], <vscale x 1 x i16> [[TMP10]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP11]], <vscale x 1 x i16> [[TMP12]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP13]], <vscale x 1 x i16> [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP15]], <vscale x 1 x i16> [[TMP16]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP17]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP17]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP17]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP17]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg6.mask.nxv1i16.i64(<vscale x 1 x i16> [[TMP18]], <vscale x 1 x i16> [[TMP19]], <vscale x 1 x i16> [[TMP20]], <vscale x 1 x i16> [[TMP21]], <vscale x 1 x i16> [[TMP22]], <vscale x 1 x i16> [[TMP23]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] undef, <vscale x 1 x i16> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP26]], <vscale x 1 x i16> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP28]], <vscale x 1 x i16> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP30]], <vscale x 1 x i16> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP32]], <vscale x 1 x i16> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP34]], <vscale x 1 x i16> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF4X6_T]] [[TMP36]]
+//
+vuint16mf4x6_t test_vlseg6e16_v_u16mf4x6_m (vbool64_t mask, vuint16mf4x6_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg6e16_v_u16mf4x6_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e16_v_u16mf4x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP3]], <vscale x 1 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP4]], <vscale x 1 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP5]], <vscale x 1 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] undef, <vscale x 1 x i16> [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP8]], <vscale x 1 x i16> [[TMP9]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP10]], <vscale x 1 x i16> [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP12]], <vscale x 1 x i16> [[TMP13]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP14]], <vscale x 1 x i16> [[TMP15]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP16]], <vscale x 1 x i16> [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP18]], <vscale x 1 x i16> [[TMP19]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP20]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg7.mask.nxv1i16.i32(<vscale x 1 x i16> [[TMP21]], <vscale x 1 x i16> [[TMP22]], <vscale x 1 x i16> [[TMP23]], <vscale x 1 x i16> [[TMP24]], <vscale x 1 x i16> [[TMP25]], <vscale x 1 x i16> [[TMP26]], <vscale x 1 x i16> [[TMP27]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] undef, <vscale x 1 x i16> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP30]], <vscale x 1 x i16> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP32]], <vscale x 1 x i16> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP34]], <vscale x 1 x i16> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP36]], <vscale x 1 x i16> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP38]], <vscale x 1 x i16> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP40]], <vscale x 1 x i16> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e16_v_u16mf4x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP3]], <vscale x 1 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP4]], <vscale x 1 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP5]], <vscale x 1 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] undef, <vscale x 1 x i16> [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP8]], <vscale x 1 x i16> [[TMP9]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP10]], <vscale x 1 x i16> [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP12]], <vscale x 1 x i16> [[TMP13]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP14]], <vscale x 1 x i16> [[TMP15]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP16]], <vscale x 1 x i16> [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP18]], <vscale x 1 x i16> [[TMP19]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP20]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg7.mask.nxv1i16.i64(<vscale x 1 x i16> [[TMP21]], <vscale x 1 x i16> [[TMP22]], <vscale x 1 x i16> [[TMP23]], <vscale x 1 x i16> [[TMP24]], <vscale x 1 x i16> [[TMP25]], <vscale x 1 x i16> [[TMP26]], <vscale x 1 x i16> [[TMP27]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] undef, <vscale x 1 x i16> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP30]], <vscale x 1 x i16> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP32]], <vscale x 1 x i16> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP34]], <vscale x 1 x i16> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP36]], <vscale x 1 x i16> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP38]], <vscale x 1 x i16> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP40]], <vscale x 1 x i16> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF4X7_T]] [[TMP42]]
+//
+vuint16mf4x7_t test_vlseg7e16_v_u16mf4x7_m (vbool64_t mask, vuint16mf4x7_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg7e16_v_u16mf4x7_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e16_v_u16mf4x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP3]], <vscale x 1 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP4]], <vscale x 1 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP5]], <vscale x 1 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP6]], <vscale x 1 x i16> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] undef, <vscale x 1 x i16> [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP9]], <vscale x 1 x i16> [[TMP10]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP11]], <vscale x 1 x i16> [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP13]], <vscale x 1 x i16> [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP15]], <vscale x 1 x i16> [[TMP16]], 4
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP17]], <vscale x 1 x i16> [[TMP18]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP19]], <vscale x 1 x i16> [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP21]], <vscale x 1 x i16> [[TMP22]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP23]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP23]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP23]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP23]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP23]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP23]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP23]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg8.mask.nxv1i16.i32(<vscale x 1 x i16> [[TMP24]], <vscale x 1 x i16> [[TMP25]], <vscale x 1 x i16> [[TMP26]], <vscale x 1 x i16> [[TMP27]], <vscale x 1 x i16> [[TMP28]], <vscale x 1 x i16> [[TMP29]], <vscale x 1 x i16> [[TMP30]], <vscale x 1 x i16> [[TMP31]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] undef, <vscale x 1 x i16> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP34]], <vscale x 1 x i16> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP36]], <vscale x 1 x i16> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP38]], <vscale x 1 x i16> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP40]], <vscale x 1 x i16> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP42]], <vscale x 1 x i16> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP44]], <vscale x 1 x i16> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP46]], <vscale x 1 x i16> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e16_v_u16mf4x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T:%.*]] undef, <vscale x 1 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP0]], <vscale x 1 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP1]], <vscale x 1 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP2]], <vscale x 1 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP3]], <vscale x 1 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP4]], <vscale x 1 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP5]], <vscale x 1 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP6]], <vscale x 1 x i16> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] undef, <vscale x 1 x i16> [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP9]], <vscale x 1 x i16> [[TMP10]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP11]], <vscale x 1 x i16> [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP13]], <vscale x 1 x i16> [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP15]], <vscale x 1 x i16> [[TMP16]], 4
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP17]], <vscale x 1 x i16> [[TMP18]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP19]], <vscale x 1 x i16> [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP21]], <vscale x 1 x i16> [[TMP22]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP23]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP23]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP23]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP23]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP23]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP23]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP23]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } @llvm.riscv.vlseg8.mask.nxv1i16.i64(<vscale x 1 x i16> [[TMP24]], <vscale x 1 x i16> [[TMP25]], <vscale x 1 x i16> [[TMP26]], <vscale x 1 x i16> [[TMP27]], <vscale x 1 x i16> [[TMP28]], <vscale x 1 x i16> [[TMP29]], <vscale x 1 x i16> [[TMP30]], <vscale x 1 x i16> [[TMP31]], i16* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] undef, <vscale x 1 x i16> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP34]], <vscale x 1 x i16> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP36]], <vscale x 1 x i16> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP38]], <vscale x 1 x i16> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP40]], <vscale x 1 x i16> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP42]], <vscale x 1 x i16> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP44]], <vscale x 1 x i16> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP46]], <vscale x 1 x i16> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF4X8_T]] [[TMP48]]
+//
+vuint16mf4x8_t test_vlseg8e16_v_u16mf4x8_m (vbool64_t mask, vuint16mf4x8_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg8e16_v_u16mf4x8_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e16_v_u16mf2x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X2_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X2_T]] undef, <vscale x 2 x i16> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP3]], <vscale x 2 x i16> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg2.mask.nxv2i16.i32(<vscale x 2 x i16> [[TMP6]], <vscale x 2 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X2_T]] undef, <vscale x 2 x i16> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP10]], <vscale x 2 x i16> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e16_v_u16mf2x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X2_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X2_T]] undef, <vscale x 2 x i16> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP3]], <vscale x 2 x i16> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg2.mask.nxv2i16.i64(<vscale x 2 x i16> [[TMP6]], <vscale x 2 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X2_T]] undef, <vscale x 2 x i16> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP10]], <vscale x 2 x i16> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF2X2_T]] [[TMP12]]
+//
+vuint16mf2x2_t test_vlseg2e16_v_u16mf2x2_m (vbool32_t mask, vuint16mf2x2_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg2e16_v_u16mf2x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e16_v_u16mf2x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T]] undef, <vscale x 2 x i16> [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP4]], <vscale x 2 x i16> [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP6]], <vscale x 2 x i16> [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg3.mask.nxv2i16.i32(<vscale x 2 x i16> [[TMP9]], <vscale x 2 x i16> [[TMP10]], <vscale x 2 x i16> [[TMP11]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T]] undef, <vscale x 2 x i16> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP14]], <vscale x 2 x i16> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP16]], <vscale x 2 x i16> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e16_v_u16mf2x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T]] undef, <vscale x 2 x i16> [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP4]], <vscale x 2 x i16> [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP6]], <vscale x 2 x i16> [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg3.mask.nxv2i16.i64(<vscale x 2 x i16> [[TMP9]], <vscale x 2 x i16> [[TMP10]], <vscale x 2 x i16> [[TMP11]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T]] undef, <vscale x 2 x i16> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP14]], <vscale x 2 x i16> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP16]], <vscale x 2 x i16> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF2X3_T]] [[TMP18]]
+//
+vuint16mf2x3_t test_vlseg3e16_v_u16mf2x3_m (vbool32_t mask, vuint16mf2x3_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg3e16_v_u16mf2x3_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e16_v_u16mf2x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] undef, <vscale x 2 x i16> [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP5]], <vscale x 2 x i16> [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP7]], <vscale x 2 x i16> [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP9]], <vscale x 2 x i16> [[TMP10]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP11]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP11]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg4.mask.nxv2i16.i32(<vscale x 2 x i16> [[TMP12]], <vscale x 2 x i16> [[TMP13]], <vscale x 2 x i16> [[TMP14]], <vscale x 2 x i16> [[TMP15]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] undef, <vscale x 2 x i16> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP18]], <vscale x 2 x i16> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP20]], <vscale x 2 x i16> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP22]], <vscale x 2 x i16> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e16_v_u16mf2x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] undef, <vscale x 2 x i16> [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP5]], <vscale x 2 x i16> [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP7]], <vscale x 2 x i16> [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP9]], <vscale x 2 x i16> [[TMP10]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP11]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP11]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg4.mask.nxv2i16.i64(<vscale x 2 x i16> [[TMP12]], <vscale x 2 x i16> [[TMP13]], <vscale x 2 x i16> [[TMP14]], <vscale x 2 x i16> [[TMP15]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] undef, <vscale x 2 x i16> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP18]], <vscale x 2 x i16> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP20]], <vscale x 2 x i16> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP22]], <vscale x 2 x i16> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF2X4_T]] [[TMP24]]
+//
+vuint16mf2x4_t test_vlseg4e16_v_u16mf2x4_m (vbool32_t mask, vuint16mf2x4_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg4e16_v_u16mf2x4_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e16_v_u16mf2x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP3]], <vscale x 2 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] undef, <vscale x 2 x i16> [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP6]], <vscale x 2 x i16> [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP8]], <vscale x 2 x i16> [[TMP9]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP10]], <vscale x 2 x i16> [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP12]], <vscale x 2 x i16> [[TMP13]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP14]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP14]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP14]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg5.mask.nxv2i16.i32(<vscale x 2 x i16> [[TMP15]], <vscale x 2 x i16> [[TMP16]], <vscale x 2 x i16> [[TMP17]], <vscale x 2 x i16> [[TMP18]], <vscale x 2 x i16> [[TMP19]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] undef, <vscale x 2 x i16> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP22]], <vscale x 2 x i16> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP24]], <vscale x 2 x i16> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP26]], <vscale x 2 x i16> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP28]], <vscale x 2 x i16> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e16_v_u16mf2x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP3]], <vscale x 2 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] undef, <vscale x 2 x i16> [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP6]], <vscale x 2 x i16> [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP8]], <vscale x 2 x i16> [[TMP9]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP10]], <vscale x 2 x i16> [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP12]], <vscale x 2 x i16> [[TMP13]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP14]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP14]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP14]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg5.mask.nxv2i16.i64(<vscale x 2 x i16> [[TMP15]], <vscale x 2 x i16> [[TMP16]], <vscale x 2 x i16> [[TMP17]], <vscale x 2 x i16> [[TMP18]], <vscale x 2 x i16> [[TMP19]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] undef, <vscale x 2 x i16> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP22]], <vscale x 2 x i16> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP24]], <vscale x 2 x i16> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP26]], <vscale x 2 x i16> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP28]], <vscale x 2 x i16> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF2X5_T]] [[TMP30]]
+//
+vuint16mf2x5_t test_vlseg5e16_v_u16mf2x5_m (vbool32_t mask, vuint16mf2x5_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg5e16_v_u16mf2x5_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e16_v_u16mf2x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP3]], <vscale x 2 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP4]], <vscale x 2 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] undef, <vscale x 2 x i16> [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP7]], <vscale x 2 x i16> [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP9]], <vscale x 2 x i16> [[TMP10]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP11]], <vscale x 2 x i16> [[TMP12]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP13]], <vscale x 2 x i16> [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP15]], <vscale x 2 x i16> [[TMP16]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP17]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP17]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP17]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP17]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg6.mask.nxv2i16.i32(<vscale x 2 x i16> [[TMP18]], <vscale x 2 x i16> [[TMP19]], <vscale x 2 x i16> [[TMP20]], <vscale x 2 x i16> [[TMP21]], <vscale x 2 x i16> [[TMP22]], <vscale x 2 x i16> [[TMP23]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] undef, <vscale x 2 x i16> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP26]], <vscale x 2 x i16> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP28]], <vscale x 2 x i16> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP30]], <vscale x 2 x i16> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP32]], <vscale x 2 x i16> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP34]], <vscale x 2 x i16> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e16_v_u16mf2x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP3]], <vscale x 2 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP4]], <vscale x 2 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] undef, <vscale x 2 x i16> [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP7]], <vscale x 2 x i16> [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP9]], <vscale x 2 x i16> [[TMP10]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP11]], <vscale x 2 x i16> [[TMP12]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP13]], <vscale x 2 x i16> [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP15]], <vscale x 2 x i16> [[TMP16]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP17]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP17]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP17]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP17]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg6.mask.nxv2i16.i64(<vscale x 2 x i16> [[TMP18]], <vscale x 2 x i16> [[TMP19]], <vscale x 2 x i16> [[TMP20]], <vscale x 2 x i16> [[TMP21]], <vscale x 2 x i16> [[TMP22]], <vscale x 2 x i16> [[TMP23]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] undef, <vscale x 2 x i16> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP26]], <vscale x 2 x i16> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP28]], <vscale x 2 x i16> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP30]], <vscale x 2 x i16> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP32]], <vscale x 2 x i16> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP34]], <vscale x 2 x i16> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF2X6_T]] [[TMP36]]
+//
+vuint16mf2x6_t test_vlseg6e16_v_u16mf2x6_m (vbool32_t mask, vuint16mf2x6_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg6e16_v_u16mf2x6_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e16_v_u16mf2x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP3]], <vscale x 2 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP4]], <vscale x 2 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP5]], <vscale x 2 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] undef, <vscale x 2 x i16> [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP8]], <vscale x 2 x i16> [[TMP9]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP10]], <vscale x 2 x i16> [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP12]], <vscale x 2 x i16> [[TMP13]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP14]], <vscale x 2 x i16> [[TMP15]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP16]], <vscale x 2 x i16> [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP18]], <vscale x 2 x i16> [[TMP19]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP20]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg7.mask.nxv2i16.i32(<vscale x 2 x i16> [[TMP21]], <vscale x 2 x i16> [[TMP22]], <vscale x 2 x i16> [[TMP23]], <vscale x 2 x i16> [[TMP24]], <vscale x 2 x i16> [[TMP25]], <vscale x 2 x i16> [[TMP26]], <vscale x 2 x i16> [[TMP27]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] undef, <vscale x 2 x i16> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP30]], <vscale x 2 x i16> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP32]], <vscale x 2 x i16> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP34]], <vscale x 2 x i16> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP36]], <vscale x 2 x i16> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP38]], <vscale x 2 x i16> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP40]], <vscale x 2 x i16> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e16_v_u16mf2x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP3]], <vscale x 2 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP4]], <vscale x 2 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP5]], <vscale x 2 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] undef, <vscale x 2 x i16> [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP8]], <vscale x 2 x i16> [[TMP9]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP10]], <vscale x 2 x i16> [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP12]], <vscale x 2 x i16> [[TMP13]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP14]], <vscale x 2 x i16> [[TMP15]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP16]], <vscale x 2 x i16> [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP18]], <vscale x 2 x i16> [[TMP19]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP20]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg7.mask.nxv2i16.i64(<vscale x 2 x i16> [[TMP21]], <vscale x 2 x i16> [[TMP22]], <vscale x 2 x i16> [[TMP23]], <vscale x 2 x i16> [[TMP24]], <vscale x 2 x i16> [[TMP25]], <vscale x 2 x i16> [[TMP26]], <vscale x 2 x i16> [[TMP27]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] undef, <vscale x 2 x i16> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP30]], <vscale x 2 x i16> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP32]], <vscale x 2 x i16> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP34]], <vscale x 2 x i16> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP36]], <vscale x 2 x i16> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP38]], <vscale x 2 x i16> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP40]], <vscale x 2 x i16> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF2X7_T]] [[TMP42]]
+//
+vuint16mf2x7_t test_vlseg7e16_v_u16mf2x7_m (vbool32_t mask, vuint16mf2x7_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg7e16_v_u16mf2x7_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e16_v_u16mf2x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP3]], <vscale x 2 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP4]], <vscale x 2 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP5]], <vscale x 2 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP6]], <vscale x 2 x i16> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] undef, <vscale x 2 x i16> [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP9]], <vscale x 2 x i16> [[TMP10]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP11]], <vscale x 2 x i16> [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP13]], <vscale x 2 x i16> [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP15]], <vscale x 2 x i16> [[TMP16]], 4
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP17]], <vscale x 2 x i16> [[TMP18]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP19]], <vscale x 2 x i16> [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP21]], <vscale x 2 x i16> [[TMP22]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP23]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP23]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP23]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP23]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP23]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP23]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP23]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg8.mask.nxv2i16.i32(<vscale x 2 x i16> [[TMP24]], <vscale x 2 x i16> [[TMP25]], <vscale x 2 x i16> [[TMP26]], <vscale x 2 x i16> [[TMP27]], <vscale x 2 x i16> [[TMP28]], <vscale x 2 x i16> [[TMP29]], <vscale x 2 x i16> [[TMP30]], <vscale x 2 x i16> [[TMP31]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] undef, <vscale x 2 x i16> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP34]], <vscale x 2 x i16> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP36]], <vscale x 2 x i16> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP38]], <vscale x 2 x i16> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP40]], <vscale x 2 x i16> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP42]], <vscale x 2 x i16> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP44]], <vscale x 2 x i16> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP46]], <vscale x 2 x i16> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e16_v_u16mf2x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T:%.*]] undef, <vscale x 2 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP0]], <vscale x 2 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP1]], <vscale x 2 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP2]], <vscale x 2 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP3]], <vscale x 2 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP4]], <vscale x 2 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP5]], <vscale x 2 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP6]], <vscale x 2 x i16> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] undef, <vscale x 2 x i16> [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP9]], <vscale x 2 x i16> [[TMP10]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP11]], <vscale x 2 x i16> [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP13]], <vscale x 2 x i16> [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP15]], <vscale x 2 x i16> [[TMP16]], 4
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP17]], <vscale x 2 x i16> [[TMP18]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP19]], <vscale x 2 x i16> [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP21]], <vscale x 2 x i16> [[TMP22]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP23]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP23]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP23]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP23]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP23]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP23]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP23]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.riscv.vlseg8.mask.nxv2i16.i64(<vscale x 2 x i16> [[TMP24]], <vscale x 2 x i16> [[TMP25]], <vscale x 2 x i16> [[TMP26]], <vscale x 2 x i16> [[TMP27]], <vscale x 2 x i16> [[TMP28]], <vscale x 2 x i16> [[TMP29]], <vscale x 2 x i16> [[TMP30]], <vscale x 2 x i16> [[TMP31]], i16* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] undef, <vscale x 2 x i16> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP34]], <vscale x 2 x i16> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP36]], <vscale x 2 x i16> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP38]], <vscale x 2 x i16> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP40]], <vscale x 2 x i16> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP42]], <vscale x 2 x i16> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP44]], <vscale x 2 x i16> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP46]], <vscale x 2 x i16> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16MF2X8_T]] [[TMP48]]
+//
+vuint16mf2x8_t test_vlseg8e16_v_u16mf2x8_m (vbool32_t mask, vuint16mf2x8_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg8e16_v_u16mf2x8_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e16_v_u16m1x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X2_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X2_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X2_T]] undef, <vscale x 4 x i16> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X2_T]] [[TMP3]], <vscale x 4 x i16> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg2.mask.nxv4i16.i32(<vscale x 4 x i16> [[TMP6]], <vscale x 4 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X2_T]] undef, <vscale x 4 x i16> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X2_T]] [[TMP10]], <vscale x 4 x i16> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16M1X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e16_v_u16m1x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X2_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X2_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X2_T]] undef, <vscale x 4 x i16> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X2_T]] [[TMP3]], <vscale x 4 x i16> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg2.mask.nxv4i16.i64(<vscale x 4 x i16> [[TMP6]], <vscale x 4 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X2_T]] undef, <vscale x 4 x i16> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X2_T]] [[TMP10]], <vscale x 4 x i16> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16M1X2_T]] [[TMP12]]
+//
+vuint16m1x2_t test_vlseg2e16_v_u16m1x2_m (vbool16_t mask, vuint16m1x2_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg2e16_v_u16m1x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e16_v_u16m1x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T]] undef, <vscale x 4 x i16> [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP4]], <vscale x 4 x i16> [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP6]], <vscale x 4 x i16> [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg3.mask.nxv4i16.i32(<vscale x 4 x i16> [[TMP9]], <vscale x 4 x i16> [[TMP10]], <vscale x 4 x i16> [[TMP11]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T]] undef, <vscale x 4 x i16> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP14]], <vscale x 4 x i16> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP16]], <vscale x 4 x i16> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16M1X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e16_v_u16m1x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T]] undef, <vscale x 4 x i16> [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP4]], <vscale x 4 x i16> [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP6]], <vscale x 4 x i16> [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg3.mask.nxv4i16.i64(<vscale x 4 x i16> [[TMP9]], <vscale x 4 x i16> [[TMP10]], <vscale x 4 x i16> [[TMP11]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T]] undef, <vscale x 4 x i16> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP14]], <vscale x 4 x i16> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X3_T]] [[TMP16]], <vscale x 4 x i16> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16M1X3_T]] [[TMP18]]
+//
+vuint16m1x3_t test_vlseg3e16_v_u16m1x3_m (vbool16_t mask, vuint16m1x3_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg3e16_v_u16m1x3_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e16_v_u16m1x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] undef, <vscale x 4 x i16> [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP5]], <vscale x 4 x i16> [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP7]], <vscale x 4 x i16> [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP9]], <vscale x 4 x i16> [[TMP10]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP11]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP11]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg4.mask.nxv4i16.i32(<vscale x 4 x i16> [[TMP12]], <vscale x 4 x i16> [[TMP13]], <vscale x 4 x i16> [[TMP14]], <vscale x 4 x i16> [[TMP15]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] undef, <vscale x 4 x i16> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP18]], <vscale x 4 x i16> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP20]], <vscale x 4 x i16> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP22]], <vscale x 4 x i16> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16M1X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e16_v_u16m1x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] undef, <vscale x 4 x i16> [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP5]], <vscale x 4 x i16> [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP7]], <vscale x 4 x i16> [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP9]], <vscale x 4 x i16> [[TMP10]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP11]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP11]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg4.mask.nxv4i16.i64(<vscale x 4 x i16> [[TMP12]], <vscale x 4 x i16> [[TMP13]], <vscale x 4 x i16> [[TMP14]], <vscale x 4 x i16> [[TMP15]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] undef, <vscale x 4 x i16> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP18]], <vscale x 4 x i16> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP20]], <vscale x 4 x i16> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X4_T]] [[TMP22]], <vscale x 4 x i16> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16M1X4_T]] [[TMP24]]
+//
+vuint16m1x4_t test_vlseg4e16_v_u16m1x4_m (vbool16_t mask, vuint16m1x4_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg4e16_v_u16m1x4_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e16_v_u16m1x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP3]], <vscale x 4 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] undef, <vscale x 4 x i16> [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP6]], <vscale x 4 x i16> [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP8]], <vscale x 4 x i16> [[TMP9]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP10]], <vscale x 4 x i16> [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP12]], <vscale x 4 x i16> [[TMP13]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP14]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP14]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP14]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg5.mask.nxv4i16.i32(<vscale x 4 x i16> [[TMP15]], <vscale x 4 x i16> [[TMP16]], <vscale x 4 x i16> [[TMP17]], <vscale x 4 x i16> [[TMP18]], <vscale x 4 x i16> [[TMP19]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] undef, <vscale x 4 x i16> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP22]], <vscale x 4 x i16> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP24]], <vscale x 4 x i16> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP26]], <vscale x 4 x i16> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP28]], <vscale x 4 x i16> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16M1X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e16_v_u16m1x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP3]], <vscale x 4 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] undef, <vscale x 4 x i16> [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP6]], <vscale x 4 x i16> [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP8]], <vscale x 4 x i16> [[TMP9]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP10]], <vscale x 4 x i16> [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP12]], <vscale x 4 x i16> [[TMP13]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP14]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP14]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP14]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg5.mask.nxv4i16.i64(<vscale x 4 x i16> [[TMP15]], <vscale x 4 x i16> [[TMP16]], <vscale x 4 x i16> [[TMP17]], <vscale x 4 x i16> [[TMP18]], <vscale x 4 x i16> [[TMP19]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] undef, <vscale x 4 x i16> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP22]], <vscale x 4 x i16> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP24]], <vscale x 4 x i16> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP26]], <vscale x 4 x i16> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X5_T]] [[TMP28]], <vscale x 4 x i16> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16M1X5_T]] [[TMP30]]
+//
+vuint16m1x5_t test_vlseg5e16_v_u16m1x5_m (vbool16_t mask, vuint16m1x5_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg5e16_v_u16m1x5_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e16_v_u16m1x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP3]], <vscale x 4 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP4]], <vscale x 4 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] undef, <vscale x 4 x i16> [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP7]], <vscale x 4 x i16> [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP9]], <vscale x 4 x i16> [[TMP10]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP11]], <vscale x 4 x i16> [[TMP12]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP13]], <vscale x 4 x i16> [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP15]], <vscale x 4 x i16> [[TMP16]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP17]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP17]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP17]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP17]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg6.mask.nxv4i16.i32(<vscale x 4 x i16> [[TMP18]], <vscale x 4 x i16> [[TMP19]], <vscale x 4 x i16> [[TMP20]], <vscale x 4 x i16> [[TMP21]], <vscale x 4 x i16> [[TMP22]], <vscale x 4 x i16> [[TMP23]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] undef, <vscale x 4 x i16> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP26]], <vscale x 4 x i16> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP28]], <vscale x 4 x i16> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP30]], <vscale x 4 x i16> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP32]], <vscale x 4 x i16> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP34]], <vscale x 4 x i16> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16M1X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e16_v_u16m1x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP3]], <vscale x 4 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP4]], <vscale x 4 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] undef, <vscale x 4 x i16> [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP7]], <vscale x 4 x i16> [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP9]], <vscale x 4 x i16> [[TMP10]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP11]], <vscale x 4 x i16> [[TMP12]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP13]], <vscale x 4 x i16> [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP15]], <vscale x 4 x i16> [[TMP16]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP17]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP17]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP17]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP17]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg6.mask.nxv4i16.i64(<vscale x 4 x i16> [[TMP18]], <vscale x 4 x i16> [[TMP19]], <vscale x 4 x i16> [[TMP20]], <vscale x 4 x i16> [[TMP21]], <vscale x 4 x i16> [[TMP22]], <vscale x 4 x i16> [[TMP23]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] undef, <vscale x 4 x i16> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP26]], <vscale x 4 x i16> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP28]], <vscale x 4 x i16> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP30]], <vscale x 4 x i16> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP32]], <vscale x 4 x i16> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X6_T]] [[TMP34]], <vscale x 4 x i16> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16M1X6_T]] [[TMP36]]
+//
+vuint16m1x6_t test_vlseg6e16_v_u16m1x6_m (vbool16_t mask, vuint16m1x6_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg6e16_v_u16m1x6_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e16_v_u16m1x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP3]], <vscale x 4 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP4]], <vscale x 4 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP5]], <vscale x 4 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] undef, <vscale x 4 x i16> [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP8]], <vscale x 4 x i16> [[TMP9]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP10]], <vscale x 4 x i16> [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP12]], <vscale x 4 x i16> [[TMP13]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP14]], <vscale x 4 x i16> [[TMP15]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP16]], <vscale x 4 x i16> [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP18]], <vscale x 4 x i16> [[TMP19]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP20]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg7.mask.nxv4i16.i32(<vscale x 4 x i16> [[TMP21]], <vscale x 4 x i16> [[TMP22]], <vscale x 4 x i16> [[TMP23]], <vscale x 4 x i16> [[TMP24]], <vscale x 4 x i16> [[TMP25]], <vscale x 4 x i16> [[TMP26]], <vscale x 4 x i16> [[TMP27]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] undef, <vscale x 4 x i16> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP30]], <vscale x 4 x i16> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP32]], <vscale x 4 x i16> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP34]], <vscale x 4 x i16> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP36]], <vscale x 4 x i16> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP38]], <vscale x 4 x i16> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP40]], <vscale x 4 x i16> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16M1X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e16_v_u16m1x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP3]], <vscale x 4 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP4]], <vscale x 4 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP5]], <vscale x 4 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] undef, <vscale x 4 x i16> [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP8]], <vscale x 4 x i16> [[TMP9]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP10]], <vscale x 4 x i16> [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP12]], <vscale x 4 x i16> [[TMP13]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP14]], <vscale x 4 x i16> [[TMP15]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP16]], <vscale x 4 x i16> [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP18]], <vscale x 4 x i16> [[TMP19]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP20]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg7.mask.nxv4i16.i64(<vscale x 4 x i16> [[TMP21]], <vscale x 4 x i16> [[TMP22]], <vscale x 4 x i16> [[TMP23]], <vscale x 4 x i16> [[TMP24]], <vscale x 4 x i16> [[TMP25]], <vscale x 4 x i16> [[TMP26]], <vscale x 4 x i16> [[TMP27]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] undef, <vscale x 4 x i16> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP30]], <vscale x 4 x i16> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP32]], <vscale x 4 x i16> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP34]], <vscale x 4 x i16> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP36]], <vscale x 4 x i16> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP38]], <vscale x 4 x i16> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X7_T]] [[TMP40]], <vscale x 4 x i16> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16M1X7_T]] [[TMP42]]
+//
+vuint16m1x7_t test_vlseg7e16_v_u16m1x7_m (vbool16_t mask, vuint16m1x7_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg7e16_v_u16m1x7_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e16_v_u16m1x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP3]], <vscale x 4 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP4]], <vscale x 4 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP5]], <vscale x 4 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP6]], <vscale x 4 x i16> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] undef, <vscale x 4 x i16> [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP9]], <vscale x 4 x i16> [[TMP10]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP11]], <vscale x 4 x i16> [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP13]], <vscale x 4 x i16> [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP15]], <vscale x 4 x i16> [[TMP16]], 4
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP17]], <vscale x 4 x i16> [[TMP18]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP19]], <vscale x 4 x i16> [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP21]], <vscale x 4 x i16> [[TMP22]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP23]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP23]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP23]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP23]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP23]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP23]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP23]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg8.mask.nxv4i16.i32(<vscale x 4 x i16> [[TMP24]], <vscale x 4 x i16> [[TMP25]], <vscale x 4 x i16> [[TMP26]], <vscale x 4 x i16> [[TMP27]], <vscale x 4 x i16> [[TMP28]], <vscale x 4 x i16> [[TMP29]], <vscale x 4 x i16> [[TMP30]], <vscale x 4 x i16> [[TMP31]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] undef, <vscale x 4 x i16> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP34]], <vscale x 4 x i16> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP36]], <vscale x 4 x i16> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP38]], <vscale x 4 x i16> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP40]], <vscale x 4 x i16> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP42]], <vscale x 4 x i16> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP44]], <vscale x 4 x i16> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP46]], <vscale x 4 x i16> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16M1X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e16_v_u16m1x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T:%.*]] undef, <vscale x 4 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP0]], <vscale x 4 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP1]], <vscale x 4 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP2]], <vscale x 4 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP3]], <vscale x 4 x i16> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP4]], <vscale x 4 x i16> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP5]], <vscale x 4 x i16> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP6]], <vscale x 4 x i16> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] undef, <vscale x 4 x i16> [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP9]], <vscale x 4 x i16> [[TMP10]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP11]], <vscale x 4 x i16> [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP13]], <vscale x 4 x i16> [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP15]], <vscale x 4 x i16> [[TMP16]], 4
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP17]], <vscale x 4 x i16> [[TMP18]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP19]], <vscale x 4 x i16> [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP21]], <vscale x 4 x i16> [[TMP22]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP23]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP23]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP23]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP23]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP23]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP23]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP23]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.riscv.vlseg8.mask.nxv4i16.i64(<vscale x 4 x i16> [[TMP24]], <vscale x 4 x i16> [[TMP25]], <vscale x 4 x i16> [[TMP26]], <vscale x 4 x i16> [[TMP27]], <vscale x 4 x i16> [[TMP28]], <vscale x 4 x i16> [[TMP29]], <vscale x 4 x i16> [[TMP30]], <vscale x 4 x i16> [[TMP31]], i16* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] undef, <vscale x 4 x i16> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP34]], <vscale x 4 x i16> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP36]], <vscale x 4 x i16> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP38]], <vscale x 4 x i16> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP40]], <vscale x 4 x i16> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP42]], <vscale x 4 x i16> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP44]], <vscale x 4 x i16> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT16M1X8_T]] [[TMP46]], <vscale x 4 x i16> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16M1X8_T]] [[TMP48]]
+//
+vuint16m1x8_t test_vlseg8e16_v_u16m1x8_m (vbool16_t mask, vuint16m1x8_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg8e16_v_u16m1x8_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e16_v_u16m2x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X2_T:%.*]] undef, <vscale x 8 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X2_T]] [[TMP0]], <vscale x 8 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X2_T]] undef, <vscale x 8 x i16> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X2_T]] [[TMP3]], <vscale x 8 x i16> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg2.mask.nxv8i16.i32(<vscale x 8 x i16> [[TMP6]], <vscale x 8 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X2_T]] undef, <vscale x 8 x i16> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X2_T]] [[TMP10]], <vscale x 8 x i16> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16M2X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e16_v_u16m2x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X2_T:%.*]] undef, <vscale x 8 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X2_T]] [[TMP0]], <vscale x 8 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X2_T]] undef, <vscale x 8 x i16> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X2_T]] [[TMP3]], <vscale x 8 x i16> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg2.mask.nxv8i16.i64(<vscale x 8 x i16> [[TMP6]], <vscale x 8 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X2_T]] undef, <vscale x 8 x i16> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X2_T]] [[TMP10]], <vscale x 8 x i16> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16M2X2_T]] [[TMP12]]
+//
+vuint16m2x2_t test_vlseg2e16_v_u16m2x2_m (vbool8_t mask, vuint16m2x2_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg2e16_v_u16m2x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e16_v_u16m2x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T:%.*]] undef, <vscale x 8 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP0]], <vscale x 8 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP1]], <vscale x 8 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T]] undef, <vscale x 8 x i16> [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP4]], <vscale x 8 x i16> [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP6]], <vscale x 8 x i16> [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg3.mask.nxv8i16.i32(<vscale x 8 x i16> [[TMP9]], <vscale x 8 x i16> [[TMP10]], <vscale x 8 x i16> [[TMP11]], i16* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T]] undef, <vscale x 8 x i16> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP14]], <vscale x 8 x i16> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP16]], <vscale x 8 x i16> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16M2X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e16_v_u16m2x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T:%.*]] undef, <vscale x 8 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP0]], <vscale x 8 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP1]], <vscale x 8 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T]] undef, <vscale x 8 x i16> [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP4]], <vscale x 8 x i16> [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP6]], <vscale x 8 x i16> [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg3.mask.nxv8i16.i64(<vscale x 8 x i16> [[TMP9]], <vscale x 8 x i16> [[TMP10]], <vscale x 8 x i16> [[TMP11]], i16* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T]] undef, <vscale x 8 x i16> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP14]], <vscale x 8 x i16> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X3_T]] [[TMP16]], <vscale x 8 x i16> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16M2X3_T]] [[TMP18]]
+//
+vuint16m2x3_t test_vlseg3e16_v_u16m2x3_m (vbool8_t mask, vuint16m2x3_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg3e16_v_u16m2x3_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e16_v_u16m2x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T:%.*]] undef, <vscale x 8 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP0]], <vscale x 8 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP1]], <vscale x 8 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP2]], <vscale x 8 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] undef, <vscale x 8 x i16> [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP5]], <vscale x 8 x i16> [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP7]], <vscale x 8 x i16> [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP9]], <vscale x 8 x i16> [[TMP10]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP11]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP11]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg4.mask.nxv8i16.i32(<vscale x 8 x i16> [[TMP12]], <vscale x 8 x i16> [[TMP13]], <vscale x 8 x i16> [[TMP14]], <vscale x 8 x i16> [[TMP15]], i16* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] undef, <vscale x 8 x i16> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP18]], <vscale x 8 x i16> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP20]], <vscale x 8 x i16> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP22]], <vscale x 8 x i16> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16M2X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e16_v_u16m2x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T:%.*]] undef, <vscale x 8 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP0]], <vscale x 8 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP1]], <vscale x 8 x i16> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP2]], <vscale x 8 x i16> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] undef, <vscale x 8 x i16> [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP5]], <vscale x 8 x i16> [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP7]], <vscale x 8 x i16> [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP9]], <vscale x 8 x i16> [[TMP10]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP11]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP11]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.riscv.vlseg4.mask.nxv8i16.i64(<vscale x 8 x i16> [[TMP12]], <vscale x 8 x i16> [[TMP13]], <vscale x 8 x i16> [[TMP14]], <vscale x 8 x i16> [[TMP15]], i16* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] undef, <vscale x 8 x i16> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP18]], <vscale x 8 x i16> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP20]], <vscale x 8 x i16> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT16M2X4_T]] [[TMP22]], <vscale x 8 x i16> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16M2X4_T]] [[TMP24]]
+//
+vuint16m2x4_t test_vlseg4e16_v_u16m2x4_m (vbool8_t mask, vuint16m2x4_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg4e16_v_u16m2x4_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e16_v_u16m4x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M4X2_T:%.*]] undef, <vscale x 16 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M4X2_T]] [[TMP0]], <vscale x 16 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT16M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16M4X2_T]] undef, <vscale x 16 x i16> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16M4X2_T]] [[TMP3]], <vscale x 16 x i16> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16M4X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16M4X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 16 x i16>, <vscale x 16 x i16> } @llvm.riscv.vlseg2.mask.nxv16i16.i32(<vscale x 16 x i16> [[TMP6]], <vscale x 16 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i16> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16M4X2_T]] undef, <vscale x 16 x i16> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i16> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16M4X2_T]] [[TMP10]], <vscale x 16 x i16> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT16M4X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e16_v_u16m4x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT16M4X2_T:%.*]] undef, <vscale x 16 x i16> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT16M4X2_T]] [[TMP0]], <vscale x 16 x i16> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT16M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT16M4X2_T]] undef, <vscale x 16 x i16> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT16M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT16M4X2_T]] [[TMP3]], <vscale x 16 x i16> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT16M4X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT16M4X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 16 x i16>, <vscale x 16 x i16> } @llvm.riscv.vlseg2.mask.nxv16i16.i64(<vscale x 16 x i16> [[TMP6]], <vscale x 16 x i16> [[TMP7]], i16* [[BASE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i16> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT16M4X2_T]] undef, <vscale x 16 x i16> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i16> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT16M4X2_T]] [[TMP10]], <vscale x 16 x i16> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT16M4X2_T]] [[TMP12]]
+//
+vuint16m4x2_t test_vlseg2e16_v_u16m4x2_m (vbool4_t mask, vuint16m4x2_t maskedoff, const uint16_t *base, size_t vl) {
+  return vlseg2e16_v_u16m4x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_u32mf2x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X2_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X2_T]] undef, <vscale x 1 x i32> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP3]], <vscale x 1 x i32> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg2.mask.nxv1i32.i32(<vscale x 1 x i32> [[TMP6]], <vscale x 1 x i32> [[TMP7]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X2_T]] undef, <vscale x 1 x i32> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP10]], <vscale x 1 x i32> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_u32mf2x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X2_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X2_T]] undef, <vscale x 1 x i32> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP3]], <vscale x 1 x i32> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg2.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP6]], <vscale x 1 x i32> [[TMP7]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X2_T]] undef, <vscale x 1 x i32> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP10]], <vscale x 1 x i32> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32MF2X2_T]] [[TMP12]]
+//
+vuint32mf2x2_t test_vlseg2e32_v_u32mf2x2_m (vbool64_t mask, vuint32mf2x2_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg2e32_v_u32mf2x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e32_v_u32mf2x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T]] undef, <vscale x 1 x i32> [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP4]], <vscale x 1 x i32> [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP6]], <vscale x 1 x i32> [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg3.mask.nxv1i32.i32(<vscale x 1 x i32> [[TMP9]], <vscale x 1 x i32> [[TMP10]], <vscale x 1 x i32> [[TMP11]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T]] undef, <vscale x 1 x i32> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP14]], <vscale x 1 x i32> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP16]], <vscale x 1 x i32> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e32_v_u32mf2x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T]] undef, <vscale x 1 x i32> [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP4]], <vscale x 1 x i32> [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP6]], <vscale x 1 x i32> [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg3.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP9]], <vscale x 1 x i32> [[TMP10]], <vscale x 1 x i32> [[TMP11]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T]] undef, <vscale x 1 x i32> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP14]], <vscale x 1 x i32> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP16]], <vscale x 1 x i32> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32MF2X3_T]] [[TMP18]]
+//
+vuint32mf2x3_t test_vlseg3e32_v_u32mf2x3_m (vbool64_t mask, vuint32mf2x3_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg3e32_v_u32mf2x3_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e32_v_u32mf2x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] undef, <vscale x 1 x i32> [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP5]], <vscale x 1 x i32> [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP7]], <vscale x 1 x i32> [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP9]], <vscale x 1 x i32> [[TMP10]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP11]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP11]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg4.mask.nxv1i32.i32(<vscale x 1 x i32> [[TMP12]], <vscale x 1 x i32> [[TMP13]], <vscale x 1 x i32> [[TMP14]], <vscale x 1 x i32> [[TMP15]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] undef, <vscale x 1 x i32> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP18]], <vscale x 1 x i32> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP20]], <vscale x 1 x i32> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP22]], <vscale x 1 x i32> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e32_v_u32mf2x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] undef, <vscale x 1 x i32> [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP5]], <vscale x 1 x i32> [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP7]], <vscale x 1 x i32> [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP9]], <vscale x 1 x i32> [[TMP10]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP11]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP11]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg4.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP12]], <vscale x 1 x i32> [[TMP13]], <vscale x 1 x i32> [[TMP14]], <vscale x 1 x i32> [[TMP15]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] undef, <vscale x 1 x i32> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP18]], <vscale x 1 x i32> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP20]], <vscale x 1 x i32> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP22]], <vscale x 1 x i32> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32MF2X4_T]] [[TMP24]]
+//
+vuint32mf2x4_t test_vlseg4e32_v_u32mf2x4_m (vbool64_t mask, vuint32mf2x4_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg4e32_v_u32mf2x4_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e32_v_u32mf2x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP3]], <vscale x 1 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] undef, <vscale x 1 x i32> [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP6]], <vscale x 1 x i32> [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP8]], <vscale x 1 x i32> [[TMP9]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP10]], <vscale x 1 x i32> [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP12]], <vscale x 1 x i32> [[TMP13]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP14]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP14]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP14]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg5.mask.nxv1i32.i32(<vscale x 1 x i32> [[TMP15]], <vscale x 1 x i32> [[TMP16]], <vscale x 1 x i32> [[TMP17]], <vscale x 1 x i32> [[TMP18]], <vscale x 1 x i32> [[TMP19]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] undef, <vscale x 1 x i32> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP22]], <vscale x 1 x i32> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP24]], <vscale x 1 x i32> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP26]], <vscale x 1 x i32> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP28]], <vscale x 1 x i32> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e32_v_u32mf2x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP3]], <vscale x 1 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] undef, <vscale x 1 x i32> [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP6]], <vscale x 1 x i32> [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP8]], <vscale x 1 x i32> [[TMP9]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP10]], <vscale x 1 x i32> [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP12]], <vscale x 1 x i32> [[TMP13]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP14]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP14]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP14]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg5.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP15]], <vscale x 1 x i32> [[TMP16]], <vscale x 1 x i32> [[TMP17]], <vscale x 1 x i32> [[TMP18]], <vscale x 1 x i32> [[TMP19]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] undef, <vscale x 1 x i32> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP22]], <vscale x 1 x i32> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP24]], <vscale x 1 x i32> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP26]], <vscale x 1 x i32> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP28]], <vscale x 1 x i32> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32MF2X5_T]] [[TMP30]]
+//
+vuint32mf2x5_t test_vlseg5e32_v_u32mf2x5_m (vbool64_t mask, vuint32mf2x5_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg5e32_v_u32mf2x5_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e32_v_u32mf2x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP3]], <vscale x 1 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP4]], <vscale x 1 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] undef, <vscale x 1 x i32> [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP7]], <vscale x 1 x i32> [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP9]], <vscale x 1 x i32> [[TMP10]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP11]], <vscale x 1 x i32> [[TMP12]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP13]], <vscale x 1 x i32> [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP15]], <vscale x 1 x i32> [[TMP16]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP17]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP17]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP17]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP17]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg6.mask.nxv1i32.i32(<vscale x 1 x i32> [[TMP18]], <vscale x 1 x i32> [[TMP19]], <vscale x 1 x i32> [[TMP20]], <vscale x 1 x i32> [[TMP21]], <vscale x 1 x i32> [[TMP22]], <vscale x 1 x i32> [[TMP23]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] undef, <vscale x 1 x i32> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP26]], <vscale x 1 x i32> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP28]], <vscale x 1 x i32> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP30]], <vscale x 1 x i32> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP32]], <vscale x 1 x i32> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP34]], <vscale x 1 x i32> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e32_v_u32mf2x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP3]], <vscale x 1 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP4]], <vscale x 1 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] undef, <vscale x 1 x i32> [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP7]], <vscale x 1 x i32> [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP9]], <vscale x 1 x i32> [[TMP10]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP11]], <vscale x 1 x i32> [[TMP12]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP13]], <vscale x 1 x i32> [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP15]], <vscale x 1 x i32> [[TMP16]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP17]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP17]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP17]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP17]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg6.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP18]], <vscale x 1 x i32> [[TMP19]], <vscale x 1 x i32> [[TMP20]], <vscale x 1 x i32> [[TMP21]], <vscale x 1 x i32> [[TMP22]], <vscale x 1 x i32> [[TMP23]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] undef, <vscale x 1 x i32> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP26]], <vscale x 1 x i32> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP28]], <vscale x 1 x i32> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP30]], <vscale x 1 x i32> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP32]], <vscale x 1 x i32> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP34]], <vscale x 1 x i32> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32MF2X6_T]] [[TMP36]]
+//
+vuint32mf2x6_t test_vlseg6e32_v_u32mf2x6_m (vbool64_t mask, vuint32mf2x6_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg6e32_v_u32mf2x6_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e32_v_u32mf2x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP3]], <vscale x 1 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP4]], <vscale x 1 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP5]], <vscale x 1 x i32> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] undef, <vscale x 1 x i32> [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP8]], <vscale x 1 x i32> [[TMP9]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP10]], <vscale x 1 x i32> [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP12]], <vscale x 1 x i32> [[TMP13]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP14]], <vscale x 1 x i32> [[TMP15]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP16]], <vscale x 1 x i32> [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP18]], <vscale x 1 x i32> [[TMP19]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP20]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg7.mask.nxv1i32.i32(<vscale x 1 x i32> [[TMP21]], <vscale x 1 x i32> [[TMP22]], <vscale x 1 x i32> [[TMP23]], <vscale x 1 x i32> [[TMP24]], <vscale x 1 x i32> [[TMP25]], <vscale x 1 x i32> [[TMP26]], <vscale x 1 x i32> [[TMP27]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] undef, <vscale x 1 x i32> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP30]], <vscale x 1 x i32> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP32]], <vscale x 1 x i32> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP34]], <vscale x 1 x i32> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP36]], <vscale x 1 x i32> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP38]], <vscale x 1 x i32> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP40]], <vscale x 1 x i32> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e32_v_u32mf2x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP3]], <vscale x 1 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP4]], <vscale x 1 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP5]], <vscale x 1 x i32> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] undef, <vscale x 1 x i32> [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP8]], <vscale x 1 x i32> [[TMP9]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP10]], <vscale x 1 x i32> [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP12]], <vscale x 1 x i32> [[TMP13]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP14]], <vscale x 1 x i32> [[TMP15]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP16]], <vscale x 1 x i32> [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP18]], <vscale x 1 x i32> [[TMP19]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP20]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg7.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP21]], <vscale x 1 x i32> [[TMP22]], <vscale x 1 x i32> [[TMP23]], <vscale x 1 x i32> [[TMP24]], <vscale x 1 x i32> [[TMP25]], <vscale x 1 x i32> [[TMP26]], <vscale x 1 x i32> [[TMP27]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] undef, <vscale x 1 x i32> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP30]], <vscale x 1 x i32> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP32]], <vscale x 1 x i32> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP34]], <vscale x 1 x i32> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP36]], <vscale x 1 x i32> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP38]], <vscale x 1 x i32> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP40]], <vscale x 1 x i32> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32MF2X7_T]] [[TMP42]]
+//
+vuint32mf2x7_t test_vlseg7e32_v_u32mf2x7_m (vbool64_t mask, vuint32mf2x7_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg7e32_v_u32mf2x7_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e32_v_u32mf2x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP3]], <vscale x 1 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP4]], <vscale x 1 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP5]], <vscale x 1 x i32> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP6]], <vscale x 1 x i32> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] undef, <vscale x 1 x i32> [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP9]], <vscale x 1 x i32> [[TMP10]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP11]], <vscale x 1 x i32> [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP13]], <vscale x 1 x i32> [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP15]], <vscale x 1 x i32> [[TMP16]], 4
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP17]], <vscale x 1 x i32> [[TMP18]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP19]], <vscale x 1 x i32> [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP21]], <vscale x 1 x i32> [[TMP22]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP23]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP23]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP23]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP23]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP23]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP23]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP23]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg8.mask.nxv1i32.i32(<vscale x 1 x i32> [[TMP24]], <vscale x 1 x i32> [[TMP25]], <vscale x 1 x i32> [[TMP26]], <vscale x 1 x i32> [[TMP27]], <vscale x 1 x i32> [[TMP28]], <vscale x 1 x i32> [[TMP29]], <vscale x 1 x i32> [[TMP30]], <vscale x 1 x i32> [[TMP31]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] undef, <vscale x 1 x i32> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP34]], <vscale x 1 x i32> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP36]], <vscale x 1 x i32> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP38]], <vscale x 1 x i32> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP40]], <vscale x 1 x i32> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP42]], <vscale x 1 x i32> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP44]], <vscale x 1 x i32> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP46]], <vscale x 1 x i32> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e32_v_u32mf2x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T:%.*]] undef, <vscale x 1 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP0]], <vscale x 1 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP1]], <vscale x 1 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP2]], <vscale x 1 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP3]], <vscale x 1 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP4]], <vscale x 1 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP5]], <vscale x 1 x i32> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP6]], <vscale x 1 x i32> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] undef, <vscale x 1 x i32> [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP9]], <vscale x 1 x i32> [[TMP10]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP11]], <vscale x 1 x i32> [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP13]], <vscale x 1 x i32> [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP15]], <vscale x 1 x i32> [[TMP16]], 4
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP17]], <vscale x 1 x i32> [[TMP18]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP19]], <vscale x 1 x i32> [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP21]], <vscale x 1 x i32> [[TMP22]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP23]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP23]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP23]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP23]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP23]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP23]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP23]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } @llvm.riscv.vlseg8.mask.nxv1i32.i64(<vscale x 1 x i32> [[TMP24]], <vscale x 1 x i32> [[TMP25]], <vscale x 1 x i32> [[TMP26]], <vscale x 1 x i32> [[TMP27]], <vscale x 1 x i32> [[TMP28]], <vscale x 1 x i32> [[TMP29]], <vscale x 1 x i32> [[TMP30]], <vscale x 1 x i32> [[TMP31]], i32* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] undef, <vscale x 1 x i32> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP34]], <vscale x 1 x i32> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP36]], <vscale x 1 x i32> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP38]], <vscale x 1 x i32> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP40]], <vscale x 1 x i32> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP42]], <vscale x 1 x i32> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP44]], <vscale x 1 x i32> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP46]], <vscale x 1 x i32> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32MF2X8_T]] [[TMP48]]
+//
+vuint32mf2x8_t test_vlseg8e32_v_u32mf2x8_m (vbool64_t mask, vuint32mf2x8_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg8e32_v_u32mf2x8_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_u32m1x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X2_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X2_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X2_T]] undef, <vscale x 2 x i32> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X2_T]] [[TMP3]], <vscale x 2 x i32> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg2.mask.nxv2i32.i32(<vscale x 2 x i32> [[TMP6]], <vscale x 2 x i32> [[TMP7]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X2_T]] undef, <vscale x 2 x i32> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X2_T]] [[TMP10]], <vscale x 2 x i32> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32M1X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_u32m1x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X2_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X2_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X2_T]] undef, <vscale x 2 x i32> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X2_T]] [[TMP3]], <vscale x 2 x i32> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg2.mask.nxv2i32.i64(<vscale x 2 x i32> [[TMP6]], <vscale x 2 x i32> [[TMP7]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X2_T]] undef, <vscale x 2 x i32> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X2_T]] [[TMP10]], <vscale x 2 x i32> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32M1X2_T]] [[TMP12]]
+//
+vuint32m1x2_t test_vlseg2e32_v_u32m1x2_m (vbool32_t mask, vuint32m1x2_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg2e32_v_u32m1x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e32_v_u32m1x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T]] undef, <vscale x 2 x i32> [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP4]], <vscale x 2 x i32> [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP6]], <vscale x 2 x i32> [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg3.mask.nxv2i32.i32(<vscale x 2 x i32> [[TMP9]], <vscale x 2 x i32> [[TMP10]], <vscale x 2 x i32> [[TMP11]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T]] undef, <vscale x 2 x i32> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP14]], <vscale x 2 x i32> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP16]], <vscale x 2 x i32> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32M1X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e32_v_u32m1x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T]] undef, <vscale x 2 x i32> [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP4]], <vscale x 2 x i32> [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP6]], <vscale x 2 x i32> [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg3.mask.nxv2i32.i64(<vscale x 2 x i32> [[TMP9]], <vscale x 2 x i32> [[TMP10]], <vscale x 2 x i32> [[TMP11]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T]] undef, <vscale x 2 x i32> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP14]], <vscale x 2 x i32> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X3_T]] [[TMP16]], <vscale x 2 x i32> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32M1X3_T]] [[TMP18]]
+//
+vuint32m1x3_t test_vlseg3e32_v_u32m1x3_m (vbool32_t mask, vuint32m1x3_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg3e32_v_u32m1x3_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e32_v_u32m1x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] undef, <vscale x 2 x i32> [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP5]], <vscale x 2 x i32> [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP7]], <vscale x 2 x i32> [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP9]], <vscale x 2 x i32> [[TMP10]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP11]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP11]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg4.mask.nxv2i32.i32(<vscale x 2 x i32> [[TMP12]], <vscale x 2 x i32> [[TMP13]], <vscale x 2 x i32> [[TMP14]], <vscale x 2 x i32> [[TMP15]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] undef, <vscale x 2 x i32> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP18]], <vscale x 2 x i32> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP20]], <vscale x 2 x i32> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP22]], <vscale x 2 x i32> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32M1X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e32_v_u32m1x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] undef, <vscale x 2 x i32> [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP5]], <vscale x 2 x i32> [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP7]], <vscale x 2 x i32> [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP9]], <vscale x 2 x i32> [[TMP10]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP11]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP11]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg4.mask.nxv2i32.i64(<vscale x 2 x i32> [[TMP12]], <vscale x 2 x i32> [[TMP13]], <vscale x 2 x i32> [[TMP14]], <vscale x 2 x i32> [[TMP15]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] undef, <vscale x 2 x i32> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP18]], <vscale x 2 x i32> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP20]], <vscale x 2 x i32> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X4_T]] [[TMP22]], <vscale x 2 x i32> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32M1X4_T]] [[TMP24]]
+//
+vuint32m1x4_t test_vlseg4e32_v_u32m1x4_m (vbool32_t mask, vuint32m1x4_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg4e32_v_u32m1x4_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e32_v_u32m1x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP3]], <vscale x 2 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] undef, <vscale x 2 x i32> [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP6]], <vscale x 2 x i32> [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP8]], <vscale x 2 x i32> [[TMP9]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP10]], <vscale x 2 x i32> [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP12]], <vscale x 2 x i32> [[TMP13]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP14]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP14]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP14]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg5.mask.nxv2i32.i32(<vscale x 2 x i32> [[TMP15]], <vscale x 2 x i32> [[TMP16]], <vscale x 2 x i32> [[TMP17]], <vscale x 2 x i32> [[TMP18]], <vscale x 2 x i32> [[TMP19]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] undef, <vscale x 2 x i32> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP22]], <vscale x 2 x i32> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP24]], <vscale x 2 x i32> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP26]], <vscale x 2 x i32> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP28]], <vscale x 2 x i32> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32M1X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e32_v_u32m1x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP3]], <vscale x 2 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] undef, <vscale x 2 x i32> [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP6]], <vscale x 2 x i32> [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP8]], <vscale x 2 x i32> [[TMP9]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP10]], <vscale x 2 x i32> [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP12]], <vscale x 2 x i32> [[TMP13]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP14]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP14]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP14]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg5.mask.nxv2i32.i64(<vscale x 2 x i32> [[TMP15]], <vscale x 2 x i32> [[TMP16]], <vscale x 2 x i32> [[TMP17]], <vscale x 2 x i32> [[TMP18]], <vscale x 2 x i32> [[TMP19]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] undef, <vscale x 2 x i32> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP22]], <vscale x 2 x i32> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP24]], <vscale x 2 x i32> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP26]], <vscale x 2 x i32> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X5_T]] [[TMP28]], <vscale x 2 x i32> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32M1X5_T]] [[TMP30]]
+//
+vuint32m1x5_t test_vlseg5e32_v_u32m1x5_m (vbool32_t mask, vuint32m1x5_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg5e32_v_u32m1x5_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e32_v_u32m1x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP3]], <vscale x 2 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP4]], <vscale x 2 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] undef, <vscale x 2 x i32> [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP7]], <vscale x 2 x i32> [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP9]], <vscale x 2 x i32> [[TMP10]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP11]], <vscale x 2 x i32> [[TMP12]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP13]], <vscale x 2 x i32> [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP15]], <vscale x 2 x i32> [[TMP16]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP17]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP17]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP17]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP17]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg6.mask.nxv2i32.i32(<vscale x 2 x i32> [[TMP18]], <vscale x 2 x i32> [[TMP19]], <vscale x 2 x i32> [[TMP20]], <vscale x 2 x i32> [[TMP21]], <vscale x 2 x i32> [[TMP22]], <vscale x 2 x i32> [[TMP23]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] undef, <vscale x 2 x i32> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP26]], <vscale x 2 x i32> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP28]], <vscale x 2 x i32> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP30]], <vscale x 2 x i32> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP32]], <vscale x 2 x i32> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP34]], <vscale x 2 x i32> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32M1X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e32_v_u32m1x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP3]], <vscale x 2 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP4]], <vscale x 2 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] undef, <vscale x 2 x i32> [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP7]], <vscale x 2 x i32> [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP9]], <vscale x 2 x i32> [[TMP10]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP11]], <vscale x 2 x i32> [[TMP12]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP13]], <vscale x 2 x i32> [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP15]], <vscale x 2 x i32> [[TMP16]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP17]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP17]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP17]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP17]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg6.mask.nxv2i32.i64(<vscale x 2 x i32> [[TMP18]], <vscale x 2 x i32> [[TMP19]], <vscale x 2 x i32> [[TMP20]], <vscale x 2 x i32> [[TMP21]], <vscale x 2 x i32> [[TMP22]], <vscale x 2 x i32> [[TMP23]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] undef, <vscale x 2 x i32> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP26]], <vscale x 2 x i32> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP28]], <vscale x 2 x i32> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP30]], <vscale x 2 x i32> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP32]], <vscale x 2 x i32> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X6_T]] [[TMP34]], <vscale x 2 x i32> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32M1X6_T]] [[TMP36]]
+//
+vuint32m1x6_t test_vlseg6e32_v_u32m1x6_m (vbool32_t mask, vuint32m1x6_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg6e32_v_u32m1x6_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e32_v_u32m1x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP3]], <vscale x 2 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP4]], <vscale x 2 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP5]], <vscale x 2 x i32> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] undef, <vscale x 2 x i32> [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP8]], <vscale x 2 x i32> [[TMP9]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP10]], <vscale x 2 x i32> [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP12]], <vscale x 2 x i32> [[TMP13]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP14]], <vscale x 2 x i32> [[TMP15]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP16]], <vscale x 2 x i32> [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP18]], <vscale x 2 x i32> [[TMP19]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP20]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg7.mask.nxv2i32.i32(<vscale x 2 x i32> [[TMP21]], <vscale x 2 x i32> [[TMP22]], <vscale x 2 x i32> [[TMP23]], <vscale x 2 x i32> [[TMP24]], <vscale x 2 x i32> [[TMP25]], <vscale x 2 x i32> [[TMP26]], <vscale x 2 x i32> [[TMP27]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] undef, <vscale x 2 x i32> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP30]], <vscale x 2 x i32> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP32]], <vscale x 2 x i32> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP34]], <vscale x 2 x i32> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP36]], <vscale x 2 x i32> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP38]], <vscale x 2 x i32> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP40]], <vscale x 2 x i32> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32M1X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e32_v_u32m1x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP3]], <vscale x 2 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP4]], <vscale x 2 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP5]], <vscale x 2 x i32> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] undef, <vscale x 2 x i32> [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP8]], <vscale x 2 x i32> [[TMP9]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP10]], <vscale x 2 x i32> [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP12]], <vscale x 2 x i32> [[TMP13]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP14]], <vscale x 2 x i32> [[TMP15]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP16]], <vscale x 2 x i32> [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP18]], <vscale x 2 x i32> [[TMP19]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP20]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg7.mask.nxv2i32.i64(<vscale x 2 x i32> [[TMP21]], <vscale x 2 x i32> [[TMP22]], <vscale x 2 x i32> [[TMP23]], <vscale x 2 x i32> [[TMP24]], <vscale x 2 x i32> [[TMP25]], <vscale x 2 x i32> [[TMP26]], <vscale x 2 x i32> [[TMP27]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] undef, <vscale x 2 x i32> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP30]], <vscale x 2 x i32> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP32]], <vscale x 2 x i32> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP34]], <vscale x 2 x i32> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP36]], <vscale x 2 x i32> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP38]], <vscale x 2 x i32> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X7_T]] [[TMP40]], <vscale x 2 x i32> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32M1X7_T]] [[TMP42]]
+//
+vuint32m1x7_t test_vlseg7e32_v_u32m1x7_m (vbool32_t mask, vuint32m1x7_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg7e32_v_u32m1x7_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e32_v_u32m1x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP3]], <vscale x 2 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP4]], <vscale x 2 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP5]], <vscale x 2 x i32> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP6]], <vscale x 2 x i32> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] undef, <vscale x 2 x i32> [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP9]], <vscale x 2 x i32> [[TMP10]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP11]], <vscale x 2 x i32> [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP13]], <vscale x 2 x i32> [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP15]], <vscale x 2 x i32> [[TMP16]], 4
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP17]], <vscale x 2 x i32> [[TMP18]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP19]], <vscale x 2 x i32> [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP21]], <vscale x 2 x i32> [[TMP22]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP23]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP23]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP23]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP23]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP23]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP23]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP23]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg8.mask.nxv2i32.i32(<vscale x 2 x i32> [[TMP24]], <vscale x 2 x i32> [[TMP25]], <vscale x 2 x i32> [[TMP26]], <vscale x 2 x i32> [[TMP27]], <vscale x 2 x i32> [[TMP28]], <vscale x 2 x i32> [[TMP29]], <vscale x 2 x i32> [[TMP30]], <vscale x 2 x i32> [[TMP31]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] undef, <vscale x 2 x i32> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP34]], <vscale x 2 x i32> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP36]], <vscale x 2 x i32> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP38]], <vscale x 2 x i32> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP40]], <vscale x 2 x i32> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP42]], <vscale x 2 x i32> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP44]], <vscale x 2 x i32> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP46]], <vscale x 2 x i32> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32M1X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e32_v_u32m1x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T:%.*]] undef, <vscale x 2 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP0]], <vscale x 2 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP1]], <vscale x 2 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP2]], <vscale x 2 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP3]], <vscale x 2 x i32> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP4]], <vscale x 2 x i32> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP5]], <vscale x 2 x i32> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP6]], <vscale x 2 x i32> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] undef, <vscale x 2 x i32> [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP9]], <vscale x 2 x i32> [[TMP10]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP11]], <vscale x 2 x i32> [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP13]], <vscale x 2 x i32> [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP15]], <vscale x 2 x i32> [[TMP16]], 4
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP17]], <vscale x 2 x i32> [[TMP18]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP19]], <vscale x 2 x i32> [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP21]], <vscale x 2 x i32> [[TMP22]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP23]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP23]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP23]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP23]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP23]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP23]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP23]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.riscv.vlseg8.mask.nxv2i32.i64(<vscale x 2 x i32> [[TMP24]], <vscale x 2 x i32> [[TMP25]], <vscale x 2 x i32> [[TMP26]], <vscale x 2 x i32> [[TMP27]], <vscale x 2 x i32> [[TMP28]], <vscale x 2 x i32> [[TMP29]], <vscale x 2 x i32> [[TMP30]], <vscale x 2 x i32> [[TMP31]], i32* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] undef, <vscale x 2 x i32> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP34]], <vscale x 2 x i32> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP36]], <vscale x 2 x i32> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP38]], <vscale x 2 x i32> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP40]], <vscale x 2 x i32> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP42]], <vscale x 2 x i32> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP44]], <vscale x 2 x i32> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT32M1X8_T]] [[TMP46]], <vscale x 2 x i32> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32M1X8_T]] [[TMP48]]
+//
+vuint32m1x8_t test_vlseg8e32_v_u32m1x8_m (vbool32_t mask, vuint32m1x8_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg8e32_v_u32m1x8_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_u32m2x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X2_T:%.*]] undef, <vscale x 4 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X2_T]] [[TMP0]], <vscale x 4 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X2_T]] undef, <vscale x 4 x i32> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X2_T]] [[TMP3]], <vscale x 4 x i32> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg2.mask.nxv4i32.i32(<vscale x 4 x i32> [[TMP6]], <vscale x 4 x i32> [[TMP7]], i32* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X2_T]] undef, <vscale x 4 x i32> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X2_T]] [[TMP10]], <vscale x 4 x i32> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32M2X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_u32m2x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X2_T:%.*]] undef, <vscale x 4 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X2_T]] [[TMP0]], <vscale x 4 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X2_T]] undef, <vscale x 4 x i32> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X2_T]] [[TMP3]], <vscale x 4 x i32> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg2.mask.nxv4i32.i64(<vscale x 4 x i32> [[TMP6]], <vscale x 4 x i32> [[TMP7]], i32* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X2_T]] undef, <vscale x 4 x i32> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X2_T]] [[TMP10]], <vscale x 4 x i32> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32M2X2_T]] [[TMP12]]
+//
+vuint32m2x2_t test_vlseg2e32_v_u32m2x2_m (vbool16_t mask, vuint32m2x2_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg2e32_v_u32m2x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e32_v_u32m2x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T:%.*]] undef, <vscale x 4 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP0]], <vscale x 4 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP1]], <vscale x 4 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T]] undef, <vscale x 4 x i32> [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP4]], <vscale x 4 x i32> [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP6]], <vscale x 4 x i32> [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg3.mask.nxv4i32.i32(<vscale x 4 x i32> [[TMP9]], <vscale x 4 x i32> [[TMP10]], <vscale x 4 x i32> [[TMP11]], i32* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T]] undef, <vscale x 4 x i32> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP14]], <vscale x 4 x i32> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP16]], <vscale x 4 x i32> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32M2X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e32_v_u32m2x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T:%.*]] undef, <vscale x 4 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP0]], <vscale x 4 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP1]], <vscale x 4 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T]] undef, <vscale x 4 x i32> [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP4]], <vscale x 4 x i32> [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP6]], <vscale x 4 x i32> [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg3.mask.nxv4i32.i64(<vscale x 4 x i32> [[TMP9]], <vscale x 4 x i32> [[TMP10]], <vscale x 4 x i32> [[TMP11]], i32* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T]] undef, <vscale x 4 x i32> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP14]], <vscale x 4 x i32> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X3_T]] [[TMP16]], <vscale x 4 x i32> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32M2X3_T]] [[TMP18]]
+//
+vuint32m2x3_t test_vlseg3e32_v_u32m2x3_m (vbool16_t mask, vuint32m2x3_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg3e32_v_u32m2x3_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e32_v_u32m2x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T:%.*]] undef, <vscale x 4 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP0]], <vscale x 4 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP1]], <vscale x 4 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP2]], <vscale x 4 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] undef, <vscale x 4 x i32> [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP5]], <vscale x 4 x i32> [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP7]], <vscale x 4 x i32> [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP9]], <vscale x 4 x i32> [[TMP10]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP11]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP11]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg4.mask.nxv4i32.i32(<vscale x 4 x i32> [[TMP12]], <vscale x 4 x i32> [[TMP13]], <vscale x 4 x i32> [[TMP14]], <vscale x 4 x i32> [[TMP15]], i32* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] undef, <vscale x 4 x i32> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP18]], <vscale x 4 x i32> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP20]], <vscale x 4 x i32> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP22]], <vscale x 4 x i32> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32M2X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e32_v_u32m2x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T:%.*]] undef, <vscale x 4 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP0]], <vscale x 4 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP1]], <vscale x 4 x i32> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP2]], <vscale x 4 x i32> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] undef, <vscale x 4 x i32> [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP5]], <vscale x 4 x i32> [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP7]], <vscale x 4 x i32> [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP9]], <vscale x 4 x i32> [[TMP10]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP11]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP11]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.riscv.vlseg4.mask.nxv4i32.i64(<vscale x 4 x i32> [[TMP12]], <vscale x 4 x i32> [[TMP13]], <vscale x 4 x i32> [[TMP14]], <vscale x 4 x i32> [[TMP15]], i32* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] undef, <vscale x 4 x i32> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP18]], <vscale x 4 x i32> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP20]], <vscale x 4 x i32> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT32M2X4_T]] [[TMP22]], <vscale x 4 x i32> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32M2X4_T]] [[TMP24]]
+//
+vuint32m2x4_t test_vlseg4e32_v_u32m2x4_m (vbool16_t mask, vuint32m2x4_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg4e32_v_u32m2x4_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_u32m4x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M4X2_T:%.*]] undef, <vscale x 8 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M4X2_T]] [[TMP0]], <vscale x 8 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT32M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32M4X2_T]] undef, <vscale x 8 x i32> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT32M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32M4X2_T]] [[TMP3]], <vscale x 8 x i32> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32M4X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32M4X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 8 x i32>, <vscale x 8 x i32> } @llvm.riscv.vlseg2.mask.nxv8i32.i32(<vscale x 8 x i32> [[TMP6]], <vscale x 8 x i32> [[TMP7]], i32* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32M4X2_T]] undef, <vscale x 8 x i32> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32M4X2_T]] [[TMP10]], <vscale x 8 x i32> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT32M4X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_u32m4x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT32M4X2_T:%.*]] undef, <vscale x 8 x i32> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT32M4X2_T]] [[TMP0]], <vscale x 8 x i32> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT32M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT32M4X2_T]] undef, <vscale x 8 x i32> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT32M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT32M4X2_T]] [[TMP3]], <vscale x 8 x i32> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT32M4X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT32M4X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 8 x i32>, <vscale x 8 x i32> } @llvm.riscv.vlseg2.mask.nxv8i32.i64(<vscale x 8 x i32> [[TMP6]], <vscale x 8 x i32> [[TMP7]], i32* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT32M4X2_T]] undef, <vscale x 8 x i32> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT32M4X2_T]] [[TMP10]], <vscale x 8 x i32> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT32M4X2_T]] [[TMP12]]
+//
+vuint32m4x2_t test_vlseg2e32_v_u32m4x2_m (vbool8_t mask, vuint32m4x2_t maskedoff, const uint32_t *base, size_t vl) {
+  return vlseg2e32_v_u32m4x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e64_v_u64m1x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X2_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X2_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X2_T]] undef, <vscale x 1 x i64> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X2_T]] [[TMP3]], <vscale x 1 x i64> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg2.mask.nxv1i64.i32(<vscale x 1 x i64> [[TMP6]], <vscale x 1 x i64> [[TMP7]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X2_T]] undef, <vscale x 1 x i64> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X2_T]] [[TMP10]], <vscale x 1 x i64> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT64M1X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e64_v_u64m1x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X2_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X2_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X2_T]] undef, <vscale x 1 x i64> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X2_T]] [[TMP3]], <vscale x 1 x i64> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg2.mask.nxv1i64.i64(<vscale x 1 x i64> [[TMP6]], <vscale x 1 x i64> [[TMP7]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X2_T]] undef, <vscale x 1 x i64> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X2_T]] [[TMP10]], <vscale x 1 x i64> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT64M1X2_T]] [[TMP12]]
+//
+vuint64m1x2_t test_vlseg2e64_v_u64m1x2_m (vbool64_t mask, vuint64m1x2_t maskedoff, const uint64_t *base, size_t vl) {
+  return vlseg2e64_v_u64m1x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e64_v_u64m1x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T]] undef, <vscale x 1 x i64> [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP4]], <vscale x 1 x i64> [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP6]], <vscale x 1 x i64> [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg3.mask.nxv1i64.i32(<vscale x 1 x i64> [[TMP9]], <vscale x 1 x i64> [[TMP10]], <vscale x 1 x i64> [[TMP11]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T]] undef, <vscale x 1 x i64> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP14]], <vscale x 1 x i64> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP16]], <vscale x 1 x i64> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT64M1X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e64_v_u64m1x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T]] undef, <vscale x 1 x i64> [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP4]], <vscale x 1 x i64> [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP6]], <vscale x 1 x i64> [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg3.mask.nxv1i64.i64(<vscale x 1 x i64> [[TMP9]], <vscale x 1 x i64> [[TMP10]], <vscale x 1 x i64> [[TMP11]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T]] undef, <vscale x 1 x i64> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP14]], <vscale x 1 x i64> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X3_T]] [[TMP16]], <vscale x 1 x i64> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT64M1X3_T]] [[TMP18]]
+//
+vuint64m1x3_t test_vlseg3e64_v_u64m1x3_m (vbool64_t mask, vuint64m1x3_t maskedoff, const uint64_t *base, size_t vl) {
+  return vlseg3e64_v_u64m1x3_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e64_v_u64m1x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] undef, <vscale x 1 x i64> [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP5]], <vscale x 1 x i64> [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP7]], <vscale x 1 x i64> [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP9]], <vscale x 1 x i64> [[TMP10]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP11]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP11]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg4.mask.nxv1i64.i32(<vscale x 1 x i64> [[TMP12]], <vscale x 1 x i64> [[TMP13]], <vscale x 1 x i64> [[TMP14]], <vscale x 1 x i64> [[TMP15]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] undef, <vscale x 1 x i64> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP18]], <vscale x 1 x i64> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP20]], <vscale x 1 x i64> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP22]], <vscale x 1 x i64> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT64M1X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e64_v_u64m1x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] undef, <vscale x 1 x i64> [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP5]], <vscale x 1 x i64> [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP7]], <vscale x 1 x i64> [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP9]], <vscale x 1 x i64> [[TMP10]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP11]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP11]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg4.mask.nxv1i64.i64(<vscale x 1 x i64> [[TMP12]], <vscale x 1 x i64> [[TMP13]], <vscale x 1 x i64> [[TMP14]], <vscale x 1 x i64> [[TMP15]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] undef, <vscale x 1 x i64> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP18]], <vscale x 1 x i64> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP20]], <vscale x 1 x i64> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X4_T]] [[TMP22]], <vscale x 1 x i64> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT64M1X4_T]] [[TMP24]]
+//
+vuint64m1x4_t test_vlseg4e64_v_u64m1x4_m (vbool64_t mask, vuint64m1x4_t maskedoff, const uint64_t *base, size_t vl) {
+  return vlseg4e64_v_u64m1x4_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e64_v_u64m1x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP3]], <vscale x 1 x i64> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] undef, <vscale x 1 x i64> [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP6]], <vscale x 1 x i64> [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP8]], <vscale x 1 x i64> [[TMP9]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP10]], <vscale x 1 x i64> [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP12]], <vscale x 1 x i64> [[TMP13]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP14]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP14]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP14]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg5.mask.nxv1i64.i32(<vscale x 1 x i64> [[TMP15]], <vscale x 1 x i64> [[TMP16]], <vscale x 1 x i64> [[TMP17]], <vscale x 1 x i64> [[TMP18]], <vscale x 1 x i64> [[TMP19]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] undef, <vscale x 1 x i64> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP22]], <vscale x 1 x i64> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP24]], <vscale x 1 x i64> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP26]], <vscale x 1 x i64> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP28]], <vscale x 1 x i64> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT64M1X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e64_v_u64m1x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP3]], <vscale x 1 x i64> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] undef, <vscale x 1 x i64> [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP6]], <vscale x 1 x i64> [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP8]], <vscale x 1 x i64> [[TMP9]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP10]], <vscale x 1 x i64> [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP12]], <vscale x 1 x i64> [[TMP13]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP14]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP14]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP14]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg5.mask.nxv1i64.i64(<vscale x 1 x i64> [[TMP15]], <vscale x 1 x i64> [[TMP16]], <vscale x 1 x i64> [[TMP17]], <vscale x 1 x i64> [[TMP18]], <vscale x 1 x i64> [[TMP19]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] undef, <vscale x 1 x i64> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP22]], <vscale x 1 x i64> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP24]], <vscale x 1 x i64> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP26]], <vscale x 1 x i64> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X5_T]] [[TMP28]], <vscale x 1 x i64> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT64M1X5_T]] [[TMP30]]
+//
+vuint64m1x5_t test_vlseg5e64_v_u64m1x5_m (vbool64_t mask, vuint64m1x5_t maskedoff, const uint64_t *base, size_t vl) {
+  return vlseg5e64_v_u64m1x5_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e64_v_u64m1x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP3]], <vscale x 1 x i64> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP4]], <vscale x 1 x i64> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] undef, <vscale x 1 x i64> [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP7]], <vscale x 1 x i64> [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP9]], <vscale x 1 x i64> [[TMP10]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP11]], <vscale x 1 x i64> [[TMP12]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP13]], <vscale x 1 x i64> [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP15]], <vscale x 1 x i64> [[TMP16]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP17]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP17]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP17]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP17]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg6.mask.nxv1i64.i32(<vscale x 1 x i64> [[TMP18]], <vscale x 1 x i64> [[TMP19]], <vscale x 1 x i64> [[TMP20]], <vscale x 1 x i64> [[TMP21]], <vscale x 1 x i64> [[TMP22]], <vscale x 1 x i64> [[TMP23]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] undef, <vscale x 1 x i64> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP26]], <vscale x 1 x i64> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP28]], <vscale x 1 x i64> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP30]], <vscale x 1 x i64> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP32]], <vscale x 1 x i64> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP34]], <vscale x 1 x i64> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT64M1X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e64_v_u64m1x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP3]], <vscale x 1 x i64> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP4]], <vscale x 1 x i64> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] undef, <vscale x 1 x i64> [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP7]], <vscale x 1 x i64> [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP9]], <vscale x 1 x i64> [[TMP10]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP11]], <vscale x 1 x i64> [[TMP12]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP13]], <vscale x 1 x i64> [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP15]], <vscale x 1 x i64> [[TMP16]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP17]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP17]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP17]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP17]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg6.mask.nxv1i64.i64(<vscale x 1 x i64> [[TMP18]], <vscale x 1 x i64> [[TMP19]], <vscale x 1 x i64> [[TMP20]], <vscale x 1 x i64> [[TMP21]], <vscale x 1 x i64> [[TMP22]], <vscale x 1 x i64> [[TMP23]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] undef, <vscale x 1 x i64> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP26]], <vscale x 1 x i64> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP28]], <vscale x 1 x i64> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP30]], <vscale x 1 x i64> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP32]], <vscale x 1 x i64> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X6_T]] [[TMP34]], <vscale x 1 x i64> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT64M1X6_T]] [[TMP36]]
+//
+vuint64m1x6_t test_vlseg6e64_v_u64m1x6_m (vbool64_t mask, vuint64m1x6_t maskedoff, const uint64_t *base, size_t vl) {
+  return vlseg6e64_v_u64m1x6_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e64_v_u64m1x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP3]], <vscale x 1 x i64> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP4]], <vscale x 1 x i64> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP5]], <vscale x 1 x i64> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] undef, <vscale x 1 x i64> [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP8]], <vscale x 1 x i64> [[TMP9]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP10]], <vscale x 1 x i64> [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP12]], <vscale x 1 x i64> [[TMP13]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP14]], <vscale x 1 x i64> [[TMP15]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP16]], <vscale x 1 x i64> [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP18]], <vscale x 1 x i64> [[TMP19]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP20]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg7.mask.nxv1i64.i32(<vscale x 1 x i64> [[TMP21]], <vscale x 1 x i64> [[TMP22]], <vscale x 1 x i64> [[TMP23]], <vscale x 1 x i64> [[TMP24]], <vscale x 1 x i64> [[TMP25]], <vscale x 1 x i64> [[TMP26]], <vscale x 1 x i64> [[TMP27]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] undef, <vscale x 1 x i64> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP30]], <vscale x 1 x i64> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP32]], <vscale x 1 x i64> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP34]], <vscale x 1 x i64> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP36]], <vscale x 1 x i64> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP38]], <vscale x 1 x i64> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP40]], <vscale x 1 x i64> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT64M1X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e64_v_u64m1x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP3]], <vscale x 1 x i64> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP4]], <vscale x 1 x i64> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP5]], <vscale x 1 x i64> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] undef, <vscale x 1 x i64> [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP8]], <vscale x 1 x i64> [[TMP9]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP10]], <vscale x 1 x i64> [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP12]], <vscale x 1 x i64> [[TMP13]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP14]], <vscale x 1 x i64> [[TMP15]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP16]], <vscale x 1 x i64> [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP18]], <vscale x 1 x i64> [[TMP19]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP20]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg7.mask.nxv1i64.i64(<vscale x 1 x i64> [[TMP21]], <vscale x 1 x i64> [[TMP22]], <vscale x 1 x i64> [[TMP23]], <vscale x 1 x i64> [[TMP24]], <vscale x 1 x i64> [[TMP25]], <vscale x 1 x i64> [[TMP26]], <vscale x 1 x i64> [[TMP27]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] undef, <vscale x 1 x i64> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP30]], <vscale x 1 x i64> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP32]], <vscale x 1 x i64> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP34]], <vscale x 1 x i64> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP36]], <vscale x 1 x i64> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP38]], <vscale x 1 x i64> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X7_T]] [[TMP40]], <vscale x 1 x i64> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT64M1X7_T]] [[TMP42]]
+//
+vuint64m1x7_t test_vlseg7e64_v_u64m1x7_m (vbool64_t mask, vuint64m1x7_t maskedoff, const uint64_t *base, size_t vl) {
+  return vlseg7e64_v_u64m1x7_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e64_v_u64m1x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP3]], <vscale x 1 x i64> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP4]], <vscale x 1 x i64> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP5]], <vscale x 1 x i64> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP6]], <vscale x 1 x i64> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] undef, <vscale x 1 x i64> [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP9]], <vscale x 1 x i64> [[TMP10]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP11]], <vscale x 1 x i64> [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP13]], <vscale x 1 x i64> [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP15]], <vscale x 1 x i64> [[TMP16]], 4
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP17]], <vscale x 1 x i64> [[TMP18]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP19]], <vscale x 1 x i64> [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP21]], <vscale x 1 x i64> [[TMP22]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP23]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP23]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP23]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP23]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP23]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP23]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP23]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg8.mask.nxv1i64.i32(<vscale x 1 x i64> [[TMP24]], <vscale x 1 x i64> [[TMP25]], <vscale x 1 x i64> [[TMP26]], <vscale x 1 x i64> [[TMP27]], <vscale x 1 x i64> [[TMP28]], <vscale x 1 x i64> [[TMP29]], <vscale x 1 x i64> [[TMP30]], <vscale x 1 x i64> [[TMP31]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] undef, <vscale x 1 x i64> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP34]], <vscale x 1 x i64> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP36]], <vscale x 1 x i64> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP38]], <vscale x 1 x i64> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP40]], <vscale x 1 x i64> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP42]], <vscale x 1 x i64> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP44]], <vscale x 1 x i64> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP46]], <vscale x 1 x i64> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT64M1X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e64_v_u64m1x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T:%.*]] undef, <vscale x 1 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP0]], <vscale x 1 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP1]], <vscale x 1 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP2]], <vscale x 1 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP3]], <vscale x 1 x i64> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP4]], <vscale x 1 x i64> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP5]], <vscale x 1 x i64> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP6]], <vscale x 1 x i64> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] undef, <vscale x 1 x i64> [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP9]], <vscale x 1 x i64> [[TMP10]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP11]], <vscale x 1 x i64> [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP13]], <vscale x 1 x i64> [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP15]], <vscale x 1 x i64> [[TMP16]], 4
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP17]], <vscale x 1 x i64> [[TMP18]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP19]], <vscale x 1 x i64> [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP21]], <vscale x 1 x i64> [[TMP22]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP23]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP23]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP23]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP23]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP23]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP23]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP23]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.riscv.vlseg8.mask.nxv1i64.i64(<vscale x 1 x i64> [[TMP24]], <vscale x 1 x i64> [[TMP25]], <vscale x 1 x i64> [[TMP26]], <vscale x 1 x i64> [[TMP27]], <vscale x 1 x i64> [[TMP28]], <vscale x 1 x i64> [[TMP29]], <vscale x 1 x i64> [[TMP30]], <vscale x 1 x i64> [[TMP31]], i64* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] undef, <vscale x 1 x i64> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP34]], <vscale x 1 x i64> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP36]], <vscale x 1 x i64> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP38]], <vscale x 1 x i64> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP40]], <vscale x 1 x i64> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP42]], <vscale x 1 x i64> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP44]], <vscale x 1 x i64> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_UINT64M1X8_T]] [[TMP46]], <vscale x 1 x i64> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT64M1X8_T]] [[TMP48]]
+//
+vuint64m1x8_t test_vlseg8e64_v_u64m1x8_m (vbool64_t mask, vuint64m1x8_t maskedoff, const uint64_t *base, size_t vl) {
+  return vlseg8e64_v_u64m1x8_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e64_v_u64m2x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X2_T:%.*]] undef, <vscale x 2 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X2_T]] [[TMP0]], <vscale x 2 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X2_T]] undef, <vscale x 2 x i64> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X2_T]] [[TMP3]], <vscale x 2 x i64> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg2.mask.nxv2i64.i32(<vscale x 2 x i64> [[TMP6]], <vscale x 2 x i64> [[TMP7]], i64* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X2_T]] undef, <vscale x 2 x i64> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X2_T]] [[TMP10]], <vscale x 2 x i64> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT64M2X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e64_v_u64m2x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X2_T:%.*]] undef, <vscale x 2 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X2_T]] [[TMP0]], <vscale x 2 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X2_T]] undef, <vscale x 2 x i64> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X2_T]] [[TMP3]], <vscale x 2 x i64> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg2.mask.nxv2i64.i64(<vscale x 2 x i64> [[TMP6]], <vscale x 2 x i64> [[TMP7]], i64* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X2_T]] undef, <vscale x 2 x i64> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X2_T]] [[TMP10]], <vscale x 2 x i64> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT64M2X2_T]] [[TMP12]]
+//
+vuint64m2x2_t test_vlseg2e64_v_u64m2x2_m (vbool32_t mask, vuint64m2x2_t maskedoff, const uint64_t *base, size_t vl) {
+  return vlseg2e64_v_u64m2x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e64_v_u64m2x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T:%.*]] undef, <vscale x 2 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP0]], <vscale x 2 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP1]], <vscale x 2 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T]] undef, <vscale x 2 x i64> [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP4]], <vscale x 2 x i64> [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP6]], <vscale x 2 x i64> [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg3.mask.nxv2i64.i32(<vscale x 2 x i64> [[TMP9]], <vscale x 2 x i64> [[TMP10]], <vscale x 2 x i64> [[TMP11]], i64* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T]] undef, <vscale x 2 x i64> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP14]], <vscale x 2 x i64> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP16]], <vscale x 2 x i64> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT64M2X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e64_v_u64m2x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T:%.*]] undef, <vscale x 2 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP0]], <vscale x 2 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP1]], <vscale x 2 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T]] undef, <vscale x 2 x i64> [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP4]], <vscale x 2 x i64> [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP6]], <vscale x 2 x i64> [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg3.mask.nxv2i64.i64(<vscale x 2 x i64> [[TMP9]], <vscale x 2 x i64> [[TMP10]], <vscale x 2 x i64> [[TMP11]], i64* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T]] undef, <vscale x 2 x i64> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP14]], <vscale x 2 x i64> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X3_T]] [[TMP16]], <vscale x 2 x i64> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT64M2X3_T]] [[TMP18]]
+//
+vuint64m2x3_t test_vlseg3e64_v_u64m2x3_m (vbool32_t mask, vuint64m2x3_t maskedoff, const uint64_t *base, size_t vl) {
+  return vlseg3e64_v_u64m2x3_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e64_v_u64m2x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T:%.*]] undef, <vscale x 2 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP0]], <vscale x 2 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP1]], <vscale x 2 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP2]], <vscale x 2 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] undef, <vscale x 2 x i64> [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP5]], <vscale x 2 x i64> [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP7]], <vscale x 2 x i64> [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP9]], <vscale x 2 x i64> [[TMP10]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP11]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP11]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg4.mask.nxv2i64.i32(<vscale x 2 x i64> [[TMP12]], <vscale x 2 x i64> [[TMP13]], <vscale x 2 x i64> [[TMP14]], <vscale x 2 x i64> [[TMP15]], i64* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] undef, <vscale x 2 x i64> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP18]], <vscale x 2 x i64> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP20]], <vscale x 2 x i64> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP22]], <vscale x 2 x i64> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT64M2X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e64_v_u64m2x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T:%.*]] undef, <vscale x 2 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP0]], <vscale x 2 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP1]], <vscale x 2 x i64> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP2]], <vscale x 2 x i64> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] undef, <vscale x 2 x i64> [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP5]], <vscale x 2 x i64> [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP7]], <vscale x 2 x i64> [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP9]], <vscale x 2 x i64> [[TMP10]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP11]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP11]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.riscv.vlseg4.mask.nxv2i64.i64(<vscale x 2 x i64> [[TMP12]], <vscale x 2 x i64> [[TMP13]], <vscale x 2 x i64> [[TMP14]], <vscale x 2 x i64> [[TMP15]], i64* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] undef, <vscale x 2 x i64> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP18]], <vscale x 2 x i64> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP20]], <vscale x 2 x i64> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_UINT64M2X4_T]] [[TMP22]], <vscale x 2 x i64> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT64M2X4_T]] [[TMP24]]
+//
+vuint64m2x4_t test_vlseg4e64_v_u64m2x4_m (vbool32_t mask, vuint64m2x4_t maskedoff, const uint64_t *base, size_t vl) {
+  return vlseg4e64_v_u64m2x4_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e64_v_u64m4x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M4X2_T:%.*]] undef, <vscale x 4 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M4X2_T]] [[TMP0]], <vscale x 4 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT64M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT64M4X2_T]] undef, <vscale x 4 x i64> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT64M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT64M4X2_T]] [[TMP3]], <vscale x 4 x i64> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT64M4X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT64M4X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x i64>, <vscale x 4 x i64> } @llvm.riscv.vlseg2.mask.nxv4i64.i32(<vscale x 4 x i64> [[TMP6]], <vscale x 4 x i64> [[TMP7]], i64* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT64M4X2_T]] undef, <vscale x 4 x i64> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT64M4X2_T]] [[TMP10]], <vscale x 4 x i64> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_UINT64M4X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e64_v_u64m4x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_UINT64M4X2_T:%.*]] undef, <vscale x 4 x i64> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_UINT64M4X2_T]] [[TMP0]], <vscale x 4 x i64> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_UINT64M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_UINT64M4X2_T]] undef, <vscale x 4 x i64> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_UINT64M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_UINT64M4X2_T]] [[TMP3]], <vscale x 4 x i64> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_UINT64M4X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_UINT64M4X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x i64>, <vscale x 4 x i64> } @llvm.riscv.vlseg2.mask.nxv4i64.i64(<vscale x 4 x i64> [[TMP6]], <vscale x 4 x i64> [[TMP7]], i64* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_UINT64M4X2_T]] undef, <vscale x 4 x i64> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_UINT64M4X2_T]] [[TMP10]], <vscale x 4 x i64> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_UINT64M4X2_T]] [[TMP12]]
+//
+vuint64m4x2_t test_vlseg2e64_v_u64m4x2_m (vbool16_t mask, vuint64m4x2_t maskedoff, const uint64_t *base, size_t vl) {
+  return vlseg2e64_v_u64m4x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_f32mf2x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X2_T:%.*]] undef, <vscale x 1 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP0]], <vscale x 1 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] undef, <vscale x 1 x float> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP3]], <vscale x 1 x float> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg2.mask.nxv1f32.i32(<vscale x 1 x float> [[TMP6]], <vscale x 1 x float> [[TMP7]], float* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] undef, <vscale x 1 x float> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP10]], <vscale x 1 x float> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_f32mf2x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X2_T:%.*]] undef, <vscale x 1 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP0]], <vscale x 1 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] undef, <vscale x 1 x float> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP3]], <vscale x 1 x float> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg2.mask.nxv1f32.i64(<vscale x 1 x float> [[TMP6]], <vscale x 1 x float> [[TMP7]], float* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] undef, <vscale x 1 x float> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP10]], <vscale x 1 x float> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X2_T]] [[TMP12]]
+//
+vfloat32mf2x2_t test_vlseg2e32_v_f32mf2x2_m (vbool64_t mask, vfloat32mf2x2_t maskedoff, const float *base, size_t vl) {
+  return vlseg2e32_v_f32mf2x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e32_v_f32mf2x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T:%.*]] undef, <vscale x 1 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP0]], <vscale x 1 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP1]], <vscale x 1 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] undef, <vscale x 1 x float> [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP4]], <vscale x 1 x float> [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP6]], <vscale x 1 x float> [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg3.mask.nxv1f32.i32(<vscale x 1 x float> [[TMP9]], <vscale x 1 x float> [[TMP10]], <vscale x 1 x float> [[TMP11]], float* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] undef, <vscale x 1 x float> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP14]], <vscale x 1 x float> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP16]], <vscale x 1 x float> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e32_v_f32mf2x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T:%.*]] undef, <vscale x 1 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP0]], <vscale x 1 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP1]], <vscale x 1 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] undef, <vscale x 1 x float> [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP4]], <vscale x 1 x float> [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP6]], <vscale x 1 x float> [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg3.mask.nxv1f32.i64(<vscale x 1 x float> [[TMP9]], <vscale x 1 x float> [[TMP10]], <vscale x 1 x float> [[TMP11]], float* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] undef, <vscale x 1 x float> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP14]], <vscale x 1 x float> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP16]], <vscale x 1 x float> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X3_T]] [[TMP18]]
+//
+vfloat32mf2x3_t test_vlseg3e32_v_f32mf2x3_m (vbool64_t mask, vfloat32mf2x3_t maskedoff, const float *base, size_t vl) {
+  return vlseg3e32_v_f32mf2x3_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e32_v_f32mf2x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T:%.*]] undef, <vscale x 1 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP0]], <vscale x 1 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP1]], <vscale x 1 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP2]], <vscale x 1 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] undef, <vscale x 1 x float> [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP5]], <vscale x 1 x float> [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP7]], <vscale x 1 x float> [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP9]], <vscale x 1 x float> [[TMP10]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP11]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP11]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg4.mask.nxv1f32.i32(<vscale x 1 x float> [[TMP12]], <vscale x 1 x float> [[TMP13]], <vscale x 1 x float> [[TMP14]], <vscale x 1 x float> [[TMP15]], float* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] undef, <vscale x 1 x float> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP18]], <vscale x 1 x float> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP20]], <vscale x 1 x float> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP22]], <vscale x 1 x float> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e32_v_f32mf2x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T:%.*]] undef, <vscale x 1 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP0]], <vscale x 1 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP1]], <vscale x 1 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP2]], <vscale x 1 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] undef, <vscale x 1 x float> [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP5]], <vscale x 1 x float> [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP7]], <vscale x 1 x float> [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP9]], <vscale x 1 x float> [[TMP10]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP11]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP11]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg4.mask.nxv1f32.i64(<vscale x 1 x float> [[TMP12]], <vscale x 1 x float> [[TMP13]], <vscale x 1 x float> [[TMP14]], <vscale x 1 x float> [[TMP15]], float* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] undef, <vscale x 1 x float> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP18]], <vscale x 1 x float> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP20]], <vscale x 1 x float> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP22]], <vscale x 1 x float> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X4_T]] [[TMP24]]
+//
+vfloat32mf2x4_t test_vlseg4e32_v_f32mf2x4_m (vbool64_t mask, vfloat32mf2x4_t maskedoff, const float *base, size_t vl) {
+  return vlseg4e32_v_f32mf2x4_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e32_v_f32mf2x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T:%.*]] undef, <vscale x 1 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP0]], <vscale x 1 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP1]], <vscale x 1 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP2]], <vscale x 1 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP3]], <vscale x 1 x float> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] undef, <vscale x 1 x float> [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP6]], <vscale x 1 x float> [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP8]], <vscale x 1 x float> [[TMP9]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP10]], <vscale x 1 x float> [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP12]], <vscale x 1 x float> [[TMP13]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP14]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP14]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP14]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg5.mask.nxv1f32.i32(<vscale x 1 x float> [[TMP15]], <vscale x 1 x float> [[TMP16]], <vscale x 1 x float> [[TMP17]], <vscale x 1 x float> [[TMP18]], <vscale x 1 x float> [[TMP19]], float* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] undef, <vscale x 1 x float> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP22]], <vscale x 1 x float> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP24]], <vscale x 1 x float> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP26]], <vscale x 1 x float> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP28]], <vscale x 1 x float> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e32_v_f32mf2x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T:%.*]] undef, <vscale x 1 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP0]], <vscale x 1 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP1]], <vscale x 1 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP2]], <vscale x 1 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP3]], <vscale x 1 x float> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] undef, <vscale x 1 x float> [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP6]], <vscale x 1 x float> [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP8]], <vscale x 1 x float> [[TMP9]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP10]], <vscale x 1 x float> [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP12]], <vscale x 1 x float> [[TMP13]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP14]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP14]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP14]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg5.mask.nxv1f32.i64(<vscale x 1 x float> [[TMP15]], <vscale x 1 x float> [[TMP16]], <vscale x 1 x float> [[TMP17]], <vscale x 1 x float> [[TMP18]], <vscale x 1 x float> [[TMP19]], float* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] undef, <vscale x 1 x float> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP22]], <vscale x 1 x float> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP24]], <vscale x 1 x float> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP26]], <vscale x 1 x float> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP28]], <vscale x 1 x float> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X5_T]] [[TMP30]]
+//
+vfloat32mf2x5_t test_vlseg5e32_v_f32mf2x5_m (vbool64_t mask, vfloat32mf2x5_t maskedoff, const float *base, size_t vl) {
+  return vlseg5e32_v_f32mf2x5_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e32_v_f32mf2x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T:%.*]] undef, <vscale x 1 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP0]], <vscale x 1 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP1]], <vscale x 1 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP2]], <vscale x 1 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP3]], <vscale x 1 x float> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP4]], <vscale x 1 x float> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] undef, <vscale x 1 x float> [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP7]], <vscale x 1 x float> [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP9]], <vscale x 1 x float> [[TMP10]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP11]], <vscale x 1 x float> [[TMP12]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP13]], <vscale x 1 x float> [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP15]], <vscale x 1 x float> [[TMP16]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP17]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP17]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP17]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP17]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg6.mask.nxv1f32.i32(<vscale x 1 x float> [[TMP18]], <vscale x 1 x float> [[TMP19]], <vscale x 1 x float> [[TMP20]], <vscale x 1 x float> [[TMP21]], <vscale x 1 x float> [[TMP22]], <vscale x 1 x float> [[TMP23]], float* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] undef, <vscale x 1 x float> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP26]], <vscale x 1 x float> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP28]], <vscale x 1 x float> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP30]], <vscale x 1 x float> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP32]], <vscale x 1 x float> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP34]], <vscale x 1 x float> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e32_v_f32mf2x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T:%.*]] undef, <vscale x 1 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP0]], <vscale x 1 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP1]], <vscale x 1 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP2]], <vscale x 1 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP3]], <vscale x 1 x float> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP4]], <vscale x 1 x float> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] undef, <vscale x 1 x float> [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP7]], <vscale x 1 x float> [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP9]], <vscale x 1 x float> [[TMP10]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP11]], <vscale x 1 x float> [[TMP12]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP13]], <vscale x 1 x float> [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP15]], <vscale x 1 x float> [[TMP16]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP17]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP17]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP17]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP17]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg6.mask.nxv1f32.i64(<vscale x 1 x float> [[TMP18]], <vscale x 1 x float> [[TMP19]], <vscale x 1 x float> [[TMP20]], <vscale x 1 x float> [[TMP21]], <vscale x 1 x float> [[TMP22]], <vscale x 1 x float> [[TMP23]], float* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] undef, <vscale x 1 x float> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP26]], <vscale x 1 x float> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP28]], <vscale x 1 x float> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP30]], <vscale x 1 x float> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP32]], <vscale x 1 x float> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP34]], <vscale x 1 x float> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X6_T]] [[TMP36]]
+//
+vfloat32mf2x6_t test_vlseg6e32_v_f32mf2x6_m (vbool64_t mask, vfloat32mf2x6_t maskedoff, const float *base, size_t vl) {
+  return vlseg6e32_v_f32mf2x6_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e32_v_f32mf2x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T:%.*]] undef, <vscale x 1 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP0]], <vscale x 1 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP1]], <vscale x 1 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP2]], <vscale x 1 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP3]], <vscale x 1 x float> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP4]], <vscale x 1 x float> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP5]], <vscale x 1 x float> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] undef, <vscale x 1 x float> [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP8]], <vscale x 1 x float> [[TMP9]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP10]], <vscale x 1 x float> [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP12]], <vscale x 1 x float> [[TMP13]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP14]], <vscale x 1 x float> [[TMP15]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP16]], <vscale x 1 x float> [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP18]], <vscale x 1 x float> [[TMP19]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP20]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg7.mask.nxv1f32.i32(<vscale x 1 x float> [[TMP21]], <vscale x 1 x float> [[TMP22]], <vscale x 1 x float> [[TMP23]], <vscale x 1 x float> [[TMP24]], <vscale x 1 x float> [[TMP25]], <vscale x 1 x float> [[TMP26]], <vscale x 1 x float> [[TMP27]], float* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] undef, <vscale x 1 x float> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP30]], <vscale x 1 x float> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP32]], <vscale x 1 x float> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP34]], <vscale x 1 x float> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP36]], <vscale x 1 x float> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP38]], <vscale x 1 x float> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP40]], <vscale x 1 x float> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e32_v_f32mf2x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T:%.*]] undef, <vscale x 1 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP0]], <vscale x 1 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP1]], <vscale x 1 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP2]], <vscale x 1 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP3]], <vscale x 1 x float> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP4]], <vscale x 1 x float> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP5]], <vscale x 1 x float> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] undef, <vscale x 1 x float> [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP8]], <vscale x 1 x float> [[TMP9]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP10]], <vscale x 1 x float> [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP12]], <vscale x 1 x float> [[TMP13]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP14]], <vscale x 1 x float> [[TMP15]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP16]], <vscale x 1 x float> [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP18]], <vscale x 1 x float> [[TMP19]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP20]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg7.mask.nxv1f32.i64(<vscale x 1 x float> [[TMP21]], <vscale x 1 x float> [[TMP22]], <vscale x 1 x float> [[TMP23]], <vscale x 1 x float> [[TMP24]], <vscale x 1 x float> [[TMP25]], <vscale x 1 x float> [[TMP26]], <vscale x 1 x float> [[TMP27]], float* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] undef, <vscale x 1 x float> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP30]], <vscale x 1 x float> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP32]], <vscale x 1 x float> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP34]], <vscale x 1 x float> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP36]], <vscale x 1 x float> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP38]], <vscale x 1 x float> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP40]], <vscale x 1 x float> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X7_T]] [[TMP42]]
+//
+vfloat32mf2x7_t test_vlseg7e32_v_f32mf2x7_m (vbool64_t mask, vfloat32mf2x7_t maskedoff, const float *base, size_t vl) {
+  return vlseg7e32_v_f32mf2x7_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e32_v_f32mf2x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T:%.*]] undef, <vscale x 1 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP0]], <vscale x 1 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP1]], <vscale x 1 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP2]], <vscale x 1 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP3]], <vscale x 1 x float> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP4]], <vscale x 1 x float> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP5]], <vscale x 1 x float> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP6]], <vscale x 1 x float> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] undef, <vscale x 1 x float> [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP9]], <vscale x 1 x float> [[TMP10]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP11]], <vscale x 1 x float> [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP13]], <vscale x 1 x float> [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP15]], <vscale x 1 x float> [[TMP16]], 4
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP17]], <vscale x 1 x float> [[TMP18]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP19]], <vscale x 1 x float> [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP21]], <vscale x 1 x float> [[TMP22]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP23]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP23]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP23]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP23]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP23]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP23]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP23]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg8.mask.nxv1f32.i32(<vscale x 1 x float> [[TMP24]], <vscale x 1 x float> [[TMP25]], <vscale x 1 x float> [[TMP26]], <vscale x 1 x float> [[TMP27]], <vscale x 1 x float> [[TMP28]], <vscale x 1 x float> [[TMP29]], <vscale x 1 x float> [[TMP30]], <vscale x 1 x float> [[TMP31]], float* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] undef, <vscale x 1 x float> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP34]], <vscale x 1 x float> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP36]], <vscale x 1 x float> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP38]], <vscale x 1 x float> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP40]], <vscale x 1 x float> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP42]], <vscale x 1 x float> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP44]], <vscale x 1 x float> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP46]], <vscale x 1 x float> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e32_v_f32mf2x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T:%.*]] undef, <vscale x 1 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP0]], <vscale x 1 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP1]], <vscale x 1 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP2]], <vscale x 1 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP3]], <vscale x 1 x float> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP4]], <vscale x 1 x float> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP5]], <vscale x 1 x float> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP6]], <vscale x 1 x float> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] undef, <vscale x 1 x float> [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP9]], <vscale x 1 x float> [[TMP10]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP11]], <vscale x 1 x float> [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP13]], <vscale x 1 x float> [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP15]], <vscale x 1 x float> [[TMP16]], 4
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP17]], <vscale x 1 x float> [[TMP18]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP19]], <vscale x 1 x float> [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP21]], <vscale x 1 x float> [[TMP22]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP23]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP23]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP23]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP23]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP23]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP23]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP23]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } @llvm.riscv.vlseg8.mask.nxv1f32.i64(<vscale x 1 x float> [[TMP24]], <vscale x 1 x float> [[TMP25]], <vscale x 1 x float> [[TMP26]], <vscale x 1 x float> [[TMP27]], <vscale x 1 x float> [[TMP28]], <vscale x 1 x float> [[TMP29]], <vscale x 1 x float> [[TMP30]], <vscale x 1 x float> [[TMP31]], float* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] undef, <vscale x 1 x float> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP34]], <vscale x 1 x float> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP36]], <vscale x 1 x float> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP38]], <vscale x 1 x float> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP40]], <vscale x 1 x float> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP42]], <vscale x 1 x float> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP44]], <vscale x 1 x float> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP46]], <vscale x 1 x float> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32MF2X8_T]] [[TMP48]]
+//
+vfloat32mf2x8_t test_vlseg8e32_v_f32mf2x8_m (vbool64_t mask, vfloat32mf2x8_t maskedoff, const float *base, size_t vl) {
+  return vlseg8e32_v_f32mf2x8_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_f32m1x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X2_T:%.*]] undef, <vscale x 2 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP0]], <vscale x 2 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X2_T]] undef, <vscale x 2 x float> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP3]], <vscale x 2 x float> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg2.mask.nxv2f32.i32(<vscale x 2 x float> [[TMP6]], <vscale x 2 x float> [[TMP7]], float* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X2_T]] undef, <vscale x 2 x float> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP10]], <vscale x 2 x float> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_f32m1x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X2_T:%.*]] undef, <vscale x 2 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP0]], <vscale x 2 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X2_T]] undef, <vscale x 2 x float> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP3]], <vscale x 2 x float> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg2.mask.nxv2f32.i64(<vscale x 2 x float> [[TMP6]], <vscale x 2 x float> [[TMP7]], float* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X2_T]] undef, <vscale x 2 x float> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP10]], <vscale x 2 x float> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X2_T]] [[TMP12]]
+//
+vfloat32m1x2_t test_vlseg2e32_v_f32m1x2_m (vbool32_t mask, vfloat32m1x2_t maskedoff, const float *base, size_t vl) {
+  return vlseg2e32_v_f32m1x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e32_v_f32m1x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T:%.*]] undef, <vscale x 2 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP0]], <vscale x 2 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP1]], <vscale x 2 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T]] undef, <vscale x 2 x float> [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP4]], <vscale x 2 x float> [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP6]], <vscale x 2 x float> [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg3.mask.nxv2f32.i32(<vscale x 2 x float> [[TMP9]], <vscale x 2 x float> [[TMP10]], <vscale x 2 x float> [[TMP11]], float* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T]] undef, <vscale x 2 x float> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP14]], <vscale x 2 x float> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP16]], <vscale x 2 x float> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e32_v_f32m1x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T:%.*]] undef, <vscale x 2 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP0]], <vscale x 2 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP1]], <vscale x 2 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T]] undef, <vscale x 2 x float> [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP4]], <vscale x 2 x float> [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP6]], <vscale x 2 x float> [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg3.mask.nxv2f32.i64(<vscale x 2 x float> [[TMP9]], <vscale x 2 x float> [[TMP10]], <vscale x 2 x float> [[TMP11]], float* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T]] undef, <vscale x 2 x float> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP14]], <vscale x 2 x float> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP16]], <vscale x 2 x float> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X3_T]] [[TMP18]]
+//
+vfloat32m1x3_t test_vlseg3e32_v_f32m1x3_m (vbool32_t mask, vfloat32m1x3_t maskedoff, const float *base, size_t vl) {
+  return vlseg3e32_v_f32m1x3_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e32_v_f32m1x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T:%.*]] undef, <vscale x 2 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP0]], <vscale x 2 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP1]], <vscale x 2 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP2]], <vscale x 2 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] undef, <vscale x 2 x float> [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP5]], <vscale x 2 x float> [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP7]], <vscale x 2 x float> [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP9]], <vscale x 2 x float> [[TMP10]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP11]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP11]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg4.mask.nxv2f32.i32(<vscale x 2 x float> [[TMP12]], <vscale x 2 x float> [[TMP13]], <vscale x 2 x float> [[TMP14]], <vscale x 2 x float> [[TMP15]], float* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] undef, <vscale x 2 x float> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP18]], <vscale x 2 x float> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP20]], <vscale x 2 x float> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP22]], <vscale x 2 x float> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e32_v_f32m1x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T:%.*]] undef, <vscale x 2 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP0]], <vscale x 2 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP1]], <vscale x 2 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP2]], <vscale x 2 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] undef, <vscale x 2 x float> [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP5]], <vscale x 2 x float> [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP7]], <vscale x 2 x float> [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP9]], <vscale x 2 x float> [[TMP10]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP11]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP11]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg4.mask.nxv2f32.i64(<vscale x 2 x float> [[TMP12]], <vscale x 2 x float> [[TMP13]], <vscale x 2 x float> [[TMP14]], <vscale x 2 x float> [[TMP15]], float* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] undef, <vscale x 2 x float> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP18]], <vscale x 2 x float> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP20]], <vscale x 2 x float> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP22]], <vscale x 2 x float> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X4_T]] [[TMP24]]
+//
+vfloat32m1x4_t test_vlseg4e32_v_f32m1x4_m (vbool32_t mask, vfloat32m1x4_t maskedoff, const float *base, size_t vl) {
+  return vlseg4e32_v_f32m1x4_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e32_v_f32m1x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T:%.*]] undef, <vscale x 2 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP0]], <vscale x 2 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP1]], <vscale x 2 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP2]], <vscale x 2 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP3]], <vscale x 2 x float> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] undef, <vscale x 2 x float> [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP6]], <vscale x 2 x float> [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP8]], <vscale x 2 x float> [[TMP9]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP10]], <vscale x 2 x float> [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP12]], <vscale x 2 x float> [[TMP13]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP14]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP14]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP14]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg5.mask.nxv2f32.i32(<vscale x 2 x float> [[TMP15]], <vscale x 2 x float> [[TMP16]], <vscale x 2 x float> [[TMP17]], <vscale x 2 x float> [[TMP18]], <vscale x 2 x float> [[TMP19]], float* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] undef, <vscale x 2 x float> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP22]], <vscale x 2 x float> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP24]], <vscale x 2 x float> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP26]], <vscale x 2 x float> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP28]], <vscale x 2 x float> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e32_v_f32m1x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T:%.*]] undef, <vscale x 2 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP0]], <vscale x 2 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP1]], <vscale x 2 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP2]], <vscale x 2 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP3]], <vscale x 2 x float> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] undef, <vscale x 2 x float> [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP6]], <vscale x 2 x float> [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP8]], <vscale x 2 x float> [[TMP9]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP10]], <vscale x 2 x float> [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP12]], <vscale x 2 x float> [[TMP13]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP14]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP14]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP14]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg5.mask.nxv2f32.i64(<vscale x 2 x float> [[TMP15]], <vscale x 2 x float> [[TMP16]], <vscale x 2 x float> [[TMP17]], <vscale x 2 x float> [[TMP18]], <vscale x 2 x float> [[TMP19]], float* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] undef, <vscale x 2 x float> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP22]], <vscale x 2 x float> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP24]], <vscale x 2 x float> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP26]], <vscale x 2 x float> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP28]], <vscale x 2 x float> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X5_T]] [[TMP30]]
+//
+vfloat32m1x5_t test_vlseg5e32_v_f32m1x5_m (vbool32_t mask, vfloat32m1x5_t maskedoff, const float *base, size_t vl) {
+  return vlseg5e32_v_f32m1x5_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e32_v_f32m1x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T:%.*]] undef, <vscale x 2 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP0]], <vscale x 2 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP1]], <vscale x 2 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP2]], <vscale x 2 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP3]], <vscale x 2 x float> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP4]], <vscale x 2 x float> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] undef, <vscale x 2 x float> [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP7]], <vscale x 2 x float> [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP9]], <vscale x 2 x float> [[TMP10]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP11]], <vscale x 2 x float> [[TMP12]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP13]], <vscale x 2 x float> [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP15]], <vscale x 2 x float> [[TMP16]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP17]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP17]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP17]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP17]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg6.mask.nxv2f32.i32(<vscale x 2 x float> [[TMP18]], <vscale x 2 x float> [[TMP19]], <vscale x 2 x float> [[TMP20]], <vscale x 2 x float> [[TMP21]], <vscale x 2 x float> [[TMP22]], <vscale x 2 x float> [[TMP23]], float* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] undef, <vscale x 2 x float> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP26]], <vscale x 2 x float> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP28]], <vscale x 2 x float> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP30]], <vscale x 2 x float> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP32]], <vscale x 2 x float> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP34]], <vscale x 2 x float> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e32_v_f32m1x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T:%.*]] undef, <vscale x 2 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP0]], <vscale x 2 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP1]], <vscale x 2 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP2]], <vscale x 2 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP3]], <vscale x 2 x float> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP4]], <vscale x 2 x float> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] undef, <vscale x 2 x float> [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP7]], <vscale x 2 x float> [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP9]], <vscale x 2 x float> [[TMP10]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP11]], <vscale x 2 x float> [[TMP12]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP13]], <vscale x 2 x float> [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP15]], <vscale x 2 x float> [[TMP16]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP17]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP17]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP17]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP17]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg6.mask.nxv2f32.i64(<vscale x 2 x float> [[TMP18]], <vscale x 2 x float> [[TMP19]], <vscale x 2 x float> [[TMP20]], <vscale x 2 x float> [[TMP21]], <vscale x 2 x float> [[TMP22]], <vscale x 2 x float> [[TMP23]], float* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] undef, <vscale x 2 x float> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP26]], <vscale x 2 x float> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP28]], <vscale x 2 x float> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP30]], <vscale x 2 x float> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP32]], <vscale x 2 x float> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP34]], <vscale x 2 x float> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X6_T]] [[TMP36]]
+//
+vfloat32m1x6_t test_vlseg6e32_v_f32m1x6_m (vbool32_t mask, vfloat32m1x6_t maskedoff, const float *base, size_t vl) {
+  return vlseg6e32_v_f32m1x6_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e32_v_f32m1x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T:%.*]] undef, <vscale x 2 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP0]], <vscale x 2 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP1]], <vscale x 2 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP2]], <vscale x 2 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP3]], <vscale x 2 x float> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP4]], <vscale x 2 x float> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP5]], <vscale x 2 x float> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] undef, <vscale x 2 x float> [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP8]], <vscale x 2 x float> [[TMP9]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP10]], <vscale x 2 x float> [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP12]], <vscale x 2 x float> [[TMP13]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP14]], <vscale x 2 x float> [[TMP15]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP16]], <vscale x 2 x float> [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP18]], <vscale x 2 x float> [[TMP19]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP20]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg7.mask.nxv2f32.i32(<vscale x 2 x float> [[TMP21]], <vscale x 2 x float> [[TMP22]], <vscale x 2 x float> [[TMP23]], <vscale x 2 x float> [[TMP24]], <vscale x 2 x float> [[TMP25]], <vscale x 2 x float> [[TMP26]], <vscale x 2 x float> [[TMP27]], float* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] undef, <vscale x 2 x float> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP30]], <vscale x 2 x float> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP32]], <vscale x 2 x float> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP34]], <vscale x 2 x float> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP36]], <vscale x 2 x float> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP38]], <vscale x 2 x float> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP40]], <vscale x 2 x float> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e32_v_f32m1x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T:%.*]] undef, <vscale x 2 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP0]], <vscale x 2 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP1]], <vscale x 2 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP2]], <vscale x 2 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP3]], <vscale x 2 x float> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP4]], <vscale x 2 x float> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP5]], <vscale x 2 x float> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] undef, <vscale x 2 x float> [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP8]], <vscale x 2 x float> [[TMP9]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP10]], <vscale x 2 x float> [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP12]], <vscale x 2 x float> [[TMP13]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP14]], <vscale x 2 x float> [[TMP15]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP16]], <vscale x 2 x float> [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP18]], <vscale x 2 x float> [[TMP19]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP20]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg7.mask.nxv2f32.i64(<vscale x 2 x float> [[TMP21]], <vscale x 2 x float> [[TMP22]], <vscale x 2 x float> [[TMP23]], <vscale x 2 x float> [[TMP24]], <vscale x 2 x float> [[TMP25]], <vscale x 2 x float> [[TMP26]], <vscale x 2 x float> [[TMP27]], float* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] undef, <vscale x 2 x float> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP30]], <vscale x 2 x float> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP32]], <vscale x 2 x float> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP34]], <vscale x 2 x float> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP36]], <vscale x 2 x float> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP38]], <vscale x 2 x float> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP40]], <vscale x 2 x float> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X7_T]] [[TMP42]]
+//
+vfloat32m1x7_t test_vlseg7e32_v_f32m1x7_m (vbool32_t mask, vfloat32m1x7_t maskedoff, const float *base, size_t vl) {
+  return vlseg7e32_v_f32m1x7_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e32_v_f32m1x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T:%.*]] undef, <vscale x 2 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP0]], <vscale x 2 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP1]], <vscale x 2 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP2]], <vscale x 2 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP3]], <vscale x 2 x float> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP4]], <vscale x 2 x float> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP5]], <vscale x 2 x float> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP6]], <vscale x 2 x float> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] undef, <vscale x 2 x float> [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP9]], <vscale x 2 x float> [[TMP10]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP11]], <vscale x 2 x float> [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP13]], <vscale x 2 x float> [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP15]], <vscale x 2 x float> [[TMP16]], 4
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP17]], <vscale x 2 x float> [[TMP18]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP19]], <vscale x 2 x float> [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP21]], <vscale x 2 x float> [[TMP22]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP23]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP23]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP23]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP23]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP23]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP23]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP23]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg8.mask.nxv2f32.i32(<vscale x 2 x float> [[TMP24]], <vscale x 2 x float> [[TMP25]], <vscale x 2 x float> [[TMP26]], <vscale x 2 x float> [[TMP27]], <vscale x 2 x float> [[TMP28]], <vscale x 2 x float> [[TMP29]], <vscale x 2 x float> [[TMP30]], <vscale x 2 x float> [[TMP31]], float* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] undef, <vscale x 2 x float> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP34]], <vscale x 2 x float> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP36]], <vscale x 2 x float> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP38]], <vscale x 2 x float> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP40]], <vscale x 2 x float> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP42]], <vscale x 2 x float> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP44]], <vscale x 2 x float> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP46]], <vscale x 2 x float> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e32_v_f32m1x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T:%.*]] undef, <vscale x 2 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP0]], <vscale x 2 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP1]], <vscale x 2 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP2]], <vscale x 2 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP3]], <vscale x 2 x float> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP4]], <vscale x 2 x float> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP5]], <vscale x 2 x float> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP6]], <vscale x 2 x float> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] undef, <vscale x 2 x float> [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP9]], <vscale x 2 x float> [[TMP10]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP11]], <vscale x 2 x float> [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP13]], <vscale x 2 x float> [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP15]], <vscale x 2 x float> [[TMP16]], 4
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP17]], <vscale x 2 x float> [[TMP18]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP19]], <vscale x 2 x float> [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP21]], <vscale x 2 x float> [[TMP22]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP23]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP23]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP23]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP23]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP23]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP23]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP23]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } @llvm.riscv.vlseg8.mask.nxv2f32.i64(<vscale x 2 x float> [[TMP24]], <vscale x 2 x float> [[TMP25]], <vscale x 2 x float> [[TMP26]], <vscale x 2 x float> [[TMP27]], <vscale x 2 x float> [[TMP28]], <vscale x 2 x float> [[TMP29]], <vscale x 2 x float> [[TMP30]], <vscale x 2 x float> [[TMP31]], float* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] undef, <vscale x 2 x float> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP34]], <vscale x 2 x float> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP36]], <vscale x 2 x float> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP38]], <vscale x 2 x float> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP40]], <vscale x 2 x float> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP42]], <vscale x 2 x float> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP44]], <vscale x 2 x float> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP46]], <vscale x 2 x float> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32M1X8_T]] [[TMP48]]
+//
+vfloat32m1x8_t test_vlseg8e32_v_f32m1x8_m (vbool32_t mask, vfloat32m1x8_t maskedoff, const float *base, size_t vl) {
+  return vlseg8e32_v_f32m1x8_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_f32m2x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X2_T:%.*]] undef, <vscale x 4 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP0]], <vscale x 4 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X2_T]] undef, <vscale x 4 x float> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP3]], <vscale x 4 x float> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.riscv.vlseg2.mask.nxv4f32.i32(<vscale x 4 x float> [[TMP6]], <vscale x 4 x float> [[TMP7]], float* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X2_T]] undef, <vscale x 4 x float> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP10]], <vscale x 4 x float> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_f32m2x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X2_T:%.*]] undef, <vscale x 4 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP0]], <vscale x 4 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X2_T]] undef, <vscale x 4 x float> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP3]], <vscale x 4 x float> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.riscv.vlseg2.mask.nxv4f32.i64(<vscale x 4 x float> [[TMP6]], <vscale x 4 x float> [[TMP7]], float* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X2_T]] undef, <vscale x 4 x float> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP10]], <vscale x 4 x float> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32M2X2_T]] [[TMP12]]
+//
+vfloat32m2x2_t test_vlseg2e32_v_f32m2x2_m (vbool16_t mask, vfloat32m2x2_t maskedoff, const float *base, size_t vl) {
+  return vlseg2e32_v_f32m2x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e32_v_f32m2x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T:%.*]] undef, <vscale x 4 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP0]], <vscale x 4 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP1]], <vscale x 4 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T]] undef, <vscale x 4 x float> [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP4]], <vscale x 4 x float> [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP6]], <vscale x 4 x float> [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.riscv.vlseg3.mask.nxv4f32.i32(<vscale x 4 x float> [[TMP9]], <vscale x 4 x float> [[TMP10]], <vscale x 4 x float> [[TMP11]], float* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T]] undef, <vscale x 4 x float> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP14]], <vscale x 4 x float> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP16]], <vscale x 4 x float> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e32_v_f32m2x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T:%.*]] undef, <vscale x 4 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP0]], <vscale x 4 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP1]], <vscale x 4 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T]] undef, <vscale x 4 x float> [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP4]], <vscale x 4 x float> [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP6]], <vscale x 4 x float> [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.riscv.vlseg3.mask.nxv4f32.i64(<vscale x 4 x float> [[TMP9]], <vscale x 4 x float> [[TMP10]], <vscale x 4 x float> [[TMP11]], float* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T]] undef, <vscale x 4 x float> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP14]], <vscale x 4 x float> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP16]], <vscale x 4 x float> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32M2X3_T]] [[TMP18]]
+//
+vfloat32m2x3_t test_vlseg3e32_v_f32m2x3_m (vbool16_t mask, vfloat32m2x3_t maskedoff, const float *base, size_t vl) {
+  return vlseg3e32_v_f32m2x3_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e32_v_f32m2x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T:%.*]] undef, <vscale x 4 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP0]], <vscale x 4 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP1]], <vscale x 4 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP2]], <vscale x 4 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] undef, <vscale x 4 x float> [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP5]], <vscale x 4 x float> [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP7]], <vscale x 4 x float> [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP9]], <vscale x 4 x float> [[TMP10]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP11]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP11]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.riscv.vlseg4.mask.nxv4f32.i32(<vscale x 4 x float> [[TMP12]], <vscale x 4 x float> [[TMP13]], <vscale x 4 x float> [[TMP14]], <vscale x 4 x float> [[TMP15]], float* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] undef, <vscale x 4 x float> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP18]], <vscale x 4 x float> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP20]], <vscale x 4 x float> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP22]], <vscale x 4 x float> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e32_v_f32m2x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T:%.*]] undef, <vscale x 4 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP0]], <vscale x 4 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP1]], <vscale x 4 x float> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP2]], <vscale x 4 x float> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] undef, <vscale x 4 x float> [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP5]], <vscale x 4 x float> [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP7]], <vscale x 4 x float> [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP9]], <vscale x 4 x float> [[TMP10]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP11]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP11]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.riscv.vlseg4.mask.nxv4f32.i64(<vscale x 4 x float> [[TMP12]], <vscale x 4 x float> [[TMP13]], <vscale x 4 x float> [[TMP14]], <vscale x 4 x float> [[TMP15]], float* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] undef, <vscale x 4 x float> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP18]], <vscale x 4 x float> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP20]], <vscale x 4 x float> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP22]], <vscale x 4 x float> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32M2X4_T]] [[TMP24]]
+//
+vfloat32m2x4_t test_vlseg4e32_v_f32m2x4_m (vbool16_t mask, vfloat32m2x4_t maskedoff, const float *base, size_t vl) {
+  return vlseg4e32_v_f32m2x4_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32_v_f32m4x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M4X2_T:%.*]] undef, <vscale x 8 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP0]], <vscale x 8 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M4X2_T]] undef, <vscale x 8 x float> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP3]], <vscale x 8 x float> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 8 x float>, <vscale x 8 x float> } @llvm.riscv.vlseg2.mask.nxv8f32.i32(<vscale x 8 x float> [[TMP6]], <vscale x 8 x float> [[TMP7]], float* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x float>, <vscale x 8 x float> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M4X2_T]] undef, <vscale x 8 x float> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x float>, <vscale x 8 x float> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP10]], <vscale x 8 x float> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32_v_f32m4x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M4X2_T:%.*]] undef, <vscale x 8 x float> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP0]], <vscale x 8 x float> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M4X2_T]] undef, <vscale x 8 x float> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP3]], <vscale x 8 x float> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 8 x float>, <vscale x 8 x float> } @llvm.riscv.vlseg2.mask.nxv8f32.i64(<vscale x 8 x float> [[TMP6]], <vscale x 8 x float> [[TMP7]], float* [[BASE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 8 x float>, <vscale x 8 x float> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M4X2_T]] undef, <vscale x 8 x float> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 8 x float>, <vscale x 8 x float> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP10]], <vscale x 8 x float> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT32M4X2_T]] [[TMP12]]
+//
+vfloat32m4x2_t test_vlseg2e32_v_f32m4x2_m (vbool8_t mask, vfloat32m4x2_t maskedoff, const float *base, size_t vl) {
+  return vlseg2e32_v_f32m4x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e64_v_f64m1x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X2_T:%.*]] undef, <vscale x 1 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP0]], <vscale x 1 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X2_T]] undef, <vscale x 1 x double> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP3]], <vscale x 1 x double> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg2.mask.nxv1f64.i32(<vscale x 1 x double> [[TMP6]], <vscale x 1 x double> [[TMP7]], double* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X2_T]] undef, <vscale x 1 x double> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP10]], <vscale x 1 x double> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e64_v_f64m1x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X2_T:%.*]] undef, <vscale x 1 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP0]], <vscale x 1 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X2_T]] undef, <vscale x 1 x double> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP3]], <vscale x 1 x double> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg2.mask.nxv1f64.i64(<vscale x 1 x double> [[TMP6]], <vscale x 1 x double> [[TMP7]], double* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X2_T]] undef, <vscale x 1 x double> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP10]], <vscale x 1 x double> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X2_T]] [[TMP12]]
+//
+vfloat64m1x2_t test_vlseg2e64_v_f64m1x2_m (vbool64_t mask, vfloat64m1x2_t maskedoff, const double *base, size_t vl) {
+  return vlseg2e64_v_f64m1x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e64_v_f64m1x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T:%.*]] undef, <vscale x 1 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP0]], <vscale x 1 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP1]], <vscale x 1 x double> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T]] undef, <vscale x 1 x double> [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP4]], <vscale x 1 x double> [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP6]], <vscale x 1 x double> [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg3.mask.nxv1f64.i32(<vscale x 1 x double> [[TMP9]], <vscale x 1 x double> [[TMP10]], <vscale x 1 x double> [[TMP11]], double* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T]] undef, <vscale x 1 x double> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP14]], <vscale x 1 x double> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP16]], <vscale x 1 x double> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e64_v_f64m1x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T:%.*]] undef, <vscale x 1 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP0]], <vscale x 1 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP1]], <vscale x 1 x double> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T]] undef, <vscale x 1 x double> [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP4]], <vscale x 1 x double> [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP6]], <vscale x 1 x double> [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg3.mask.nxv1f64.i64(<vscale x 1 x double> [[TMP9]], <vscale x 1 x double> [[TMP10]], <vscale x 1 x double> [[TMP11]], double* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T]] undef, <vscale x 1 x double> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP14]], <vscale x 1 x double> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP16]], <vscale x 1 x double> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X3_T]] [[TMP18]]
+//
+vfloat64m1x3_t test_vlseg3e64_v_f64m1x3_m (vbool64_t mask, vfloat64m1x3_t maskedoff, const double *base, size_t vl) {
+  return vlseg3e64_v_f64m1x3_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e64_v_f64m1x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T:%.*]] undef, <vscale x 1 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP0]], <vscale x 1 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP1]], <vscale x 1 x double> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP2]], <vscale x 1 x double> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] undef, <vscale x 1 x double> [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP5]], <vscale x 1 x double> [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP7]], <vscale x 1 x double> [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP9]], <vscale x 1 x double> [[TMP10]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP11]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP11]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg4.mask.nxv1f64.i32(<vscale x 1 x double> [[TMP12]], <vscale x 1 x double> [[TMP13]], <vscale x 1 x double> [[TMP14]], <vscale x 1 x double> [[TMP15]], double* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] undef, <vscale x 1 x double> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP18]], <vscale x 1 x double> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP20]], <vscale x 1 x double> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP22]], <vscale x 1 x double> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e64_v_f64m1x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T:%.*]] undef, <vscale x 1 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP0]], <vscale x 1 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP1]], <vscale x 1 x double> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP2]], <vscale x 1 x double> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] undef, <vscale x 1 x double> [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP5]], <vscale x 1 x double> [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP7]], <vscale x 1 x double> [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP9]], <vscale x 1 x double> [[TMP10]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP11]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP11]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg4.mask.nxv1f64.i64(<vscale x 1 x double> [[TMP12]], <vscale x 1 x double> [[TMP13]], <vscale x 1 x double> [[TMP14]], <vscale x 1 x double> [[TMP15]], double* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] undef, <vscale x 1 x double> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP18]], <vscale x 1 x double> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP20]], <vscale x 1 x double> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP22]], <vscale x 1 x double> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X4_T]] [[TMP24]]
+//
+vfloat64m1x4_t test_vlseg4e64_v_f64m1x4_m (vbool64_t mask, vfloat64m1x4_t maskedoff, const double *base, size_t vl) {
+  return vlseg4e64_v_f64m1x4_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg5e64_v_f64m1x5_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T:%.*]] undef, <vscale x 1 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP0]], <vscale x 1 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP1]], <vscale x 1 x double> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP2]], <vscale x 1 x double> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP3]], <vscale x 1 x double> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] undef, <vscale x 1 x double> [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP6]], <vscale x 1 x double> [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP8]], <vscale x 1 x double> [[TMP9]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP10]], <vscale x 1 x double> [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 4
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP12]], <vscale x 1 x double> [[TMP13]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP14]], 0
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP14]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP14]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg5.mask.nxv1f64.i32(<vscale x 1 x double> [[TMP15]], <vscale x 1 x double> [[TMP16]], <vscale x 1 x double> [[TMP17]], <vscale x 1 x double> [[TMP18]], <vscale x 1 x double> [[TMP19]], double* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] undef, <vscale x 1 x double> [[TMP21]], 0
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP22]], <vscale x 1 x double> [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP24]], <vscale x 1 x double> [[TMP25]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP26]], <vscale x 1 x double> [[TMP27]], 3
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP28]], <vscale x 1 x double> [[TMP29]], 4
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP30]]
+//
+// CHECK-RV64-LABEL: @test_vlseg5e64_v_f64m1x5_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T:%.*]] undef, <vscale x 1 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP0]], <vscale x 1 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP1]], <vscale x 1 x double> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP2]], <vscale x 1 x double> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP3]], <vscale x 1 x double> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] undef, <vscale x 1 x double> [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP6]], <vscale x 1 x double> [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP8]], <vscale x 1 x double> [[TMP9]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP10]], <vscale x 1 x double> [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP4]], 4
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP12]], <vscale x 1 x double> [[TMP13]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP14]], 0
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP14]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP14]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg5.mask.nxv1f64.i64(<vscale x 1 x double> [[TMP15]], <vscale x 1 x double> [[TMP16]], <vscale x 1 x double> [[TMP17]], <vscale x 1 x double> [[TMP18]], <vscale x 1 x double> [[TMP19]], double* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] undef, <vscale x 1 x double> [[TMP21]], 0
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP22]], <vscale x 1 x double> [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP24]], <vscale x 1 x double> [[TMP25]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP26]], <vscale x 1 x double> [[TMP27]], 3
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP28]], <vscale x 1 x double> [[TMP29]], 4
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X5_T]] [[TMP30]]
+//
+vfloat64m1x5_t test_vlseg5e64_v_f64m1x5_m (vbool64_t mask, vfloat64m1x5_t maskedoff, const double *base, size_t vl) {
+  return vlseg5e64_v_f64m1x5_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg6e64_v_f64m1x6_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T:%.*]] undef, <vscale x 1 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP0]], <vscale x 1 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP1]], <vscale x 1 x double> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP2]], <vscale x 1 x double> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP3]], <vscale x 1 x double> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP4]], <vscale x 1 x double> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] undef, <vscale x 1 x double> [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP7]], <vscale x 1 x double> [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 2
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP9]], <vscale x 1 x double> [[TMP10]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 3
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP11]], <vscale x 1 x double> [[TMP12]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 4
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP13]], <vscale x 1 x double> [[TMP14]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 5
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP15]], <vscale x 1 x double> [[TMP16]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP17]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP17]], 2
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP17]], 3
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP17]], 4
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg6.mask.nxv1f64.i32(<vscale x 1 x double> [[TMP18]], <vscale x 1 x double> [[TMP19]], <vscale x 1 x double> [[TMP20]], <vscale x 1 x double> [[TMP21]], <vscale x 1 x double> [[TMP22]], <vscale x 1 x double> [[TMP23]], double* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP24]], 0
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] undef, <vscale x 1 x double> [[TMP25]], 0
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP24]], 1
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP26]], <vscale x 1 x double> [[TMP27]], 1
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP24]], 2
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP28]], <vscale x 1 x double> [[TMP29]], 2
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP24]], 3
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP30]], <vscale x 1 x double> [[TMP31]], 3
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP24]], 4
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP32]], <vscale x 1 x double> [[TMP33]], 4
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP24]], 5
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP34]], <vscale x 1 x double> [[TMP35]], 5
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP36]]
+//
+// CHECK-RV64-LABEL: @test_vlseg6e64_v_f64m1x6_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T:%.*]] undef, <vscale x 1 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP0]], <vscale x 1 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP1]], <vscale x 1 x double> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP2]], <vscale x 1 x double> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP3]], <vscale x 1 x double> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP4]], <vscale x 1 x double> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] undef, <vscale x 1 x double> [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP7]], <vscale x 1 x double> [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 2
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP9]], <vscale x 1 x double> [[TMP10]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 3
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP11]], <vscale x 1 x double> [[TMP12]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 4
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP13]], <vscale x 1 x double> [[TMP14]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP5]], 5
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP15]], <vscale x 1 x double> [[TMP16]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP17]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP17]], 2
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP17]], 3
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP17]], 4
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg6.mask.nxv1f64.i64(<vscale x 1 x double> [[TMP18]], <vscale x 1 x double> [[TMP19]], <vscale x 1 x double> [[TMP20]], <vscale x 1 x double> [[TMP21]], <vscale x 1 x double> [[TMP22]], <vscale x 1 x double> [[TMP23]], double* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP24]], 0
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] undef, <vscale x 1 x double> [[TMP25]], 0
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP24]], 1
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP26]], <vscale x 1 x double> [[TMP27]], 1
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP24]], 2
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP28]], <vscale x 1 x double> [[TMP29]], 2
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP24]], 3
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP30]], <vscale x 1 x double> [[TMP31]], 3
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP24]], 4
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP32]], <vscale x 1 x double> [[TMP33]], 4
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP24]], 5
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP34]], <vscale x 1 x double> [[TMP35]], 5
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X6_T]] [[TMP36]]
+//
+vfloat64m1x6_t test_vlseg6e64_v_f64m1x6_m (vbool64_t mask, vfloat64m1x6_t maskedoff, const double *base, size_t vl) {
+  return vlseg6e64_v_f64m1x6_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg7e64_v_f64m1x7_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T:%.*]] undef, <vscale x 1 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP0]], <vscale x 1 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP1]], <vscale x 1 x double> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP2]], <vscale x 1 x double> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP3]], <vscale x 1 x double> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP4]], <vscale x 1 x double> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP5]], <vscale x 1 x double> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 0
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] undef, <vscale x 1 x double> [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP8]], <vscale x 1 x double> [[TMP9]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP10]], <vscale x 1 x double> [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 3
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP12]], <vscale x 1 x double> [[TMP13]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 4
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP14]], <vscale x 1 x double> [[TMP15]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 5
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP16]], <vscale x 1 x double> [[TMP17]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 6
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP18]], <vscale x 1 x double> [[TMP19]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP20]], 0
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP20]], 1
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP20]], 2
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP20]], 3
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP20]], 4
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP20]], 5
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg7.mask.nxv1f64.i32(<vscale x 1 x double> [[TMP21]], <vscale x 1 x double> [[TMP22]], <vscale x 1 x double> [[TMP23]], <vscale x 1 x double> [[TMP24]], <vscale x 1 x double> [[TMP25]], <vscale x 1 x double> [[TMP26]], <vscale x 1 x double> [[TMP27]], double* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP28]], 0
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] undef, <vscale x 1 x double> [[TMP29]], 0
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP28]], 1
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP30]], <vscale x 1 x double> [[TMP31]], 1
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP28]], 2
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP32]], <vscale x 1 x double> [[TMP33]], 2
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP28]], 3
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP34]], <vscale x 1 x double> [[TMP35]], 3
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP28]], 4
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP36]], <vscale x 1 x double> [[TMP37]], 4
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP28]], 5
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP38]], <vscale x 1 x double> [[TMP39]], 5
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP28]], 6
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP40]], <vscale x 1 x double> [[TMP41]], 6
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP42]]
+//
+// CHECK-RV64-LABEL: @test_vlseg7e64_v_f64m1x7_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T:%.*]] undef, <vscale x 1 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP0]], <vscale x 1 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP1]], <vscale x 1 x double> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP2]], <vscale x 1 x double> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP3]], <vscale x 1 x double> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP4]], <vscale x 1 x double> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP5]], <vscale x 1 x double> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 0
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] undef, <vscale x 1 x double> [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP8]], <vscale x 1 x double> [[TMP9]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP10]], <vscale x 1 x double> [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 3
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP12]], <vscale x 1 x double> [[TMP13]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 4
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP14]], <vscale x 1 x double> [[TMP15]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 5
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP16]], <vscale x 1 x double> [[TMP17]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP6]], 6
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP18]], <vscale x 1 x double> [[TMP19]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP20]], 0
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP20]], 1
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP20]], 2
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP20]], 3
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP20]], 4
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP20]], 5
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg7.mask.nxv1f64.i64(<vscale x 1 x double> [[TMP21]], <vscale x 1 x double> [[TMP22]], <vscale x 1 x double> [[TMP23]], <vscale x 1 x double> [[TMP24]], <vscale x 1 x double> [[TMP25]], <vscale x 1 x double> [[TMP26]], <vscale x 1 x double> [[TMP27]], double* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP28]], 0
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] undef, <vscale x 1 x double> [[TMP29]], 0
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP28]], 1
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP30]], <vscale x 1 x double> [[TMP31]], 1
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP28]], 2
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP32]], <vscale x 1 x double> [[TMP33]], 2
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP28]], 3
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP34]], <vscale x 1 x double> [[TMP35]], 3
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP28]], 4
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP36]], <vscale x 1 x double> [[TMP37]], 4
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP28]], 5
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP38]], <vscale x 1 x double> [[TMP39]], 5
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP28]], 6
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP40]], <vscale x 1 x double> [[TMP41]], 6
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X7_T]] [[TMP42]]
+//
+vfloat64m1x7_t test_vlseg7e64_v_f64m1x7_m (vbool64_t mask, vfloat64m1x7_t maskedoff, const double *base, size_t vl) {
+  return vlseg7e64_v_f64m1x7_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg8e64_v_f64m1x8_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T:%.*]] undef, <vscale x 1 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP0]], <vscale x 1 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP1]], <vscale x 1 x double> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP2]], <vscale x 1 x double> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP3]], <vscale x 1 x double> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP4]], <vscale x 1 x double> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP5]], <vscale x 1 x double> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP6]], <vscale x 1 x double> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 0
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] undef, <vscale x 1 x double> [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP9]], <vscale x 1 x double> [[TMP10]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP11]], <vscale x 1 x double> [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 3
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP13]], <vscale x 1 x double> [[TMP14]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 4
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP15]], <vscale x 1 x double> [[TMP16]], 4
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 5
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP17]], <vscale x 1 x double> [[TMP18]], 5
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 6
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP19]], <vscale x 1 x double> [[TMP20]], 6
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 7
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP21]], <vscale x 1 x double> [[TMP22]], 7
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP23]], 0
+// CHECK-RV32-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP23]], 1
+// CHECK-RV32-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP23]], 2
+// CHECK-RV32-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP23]], 3
+// CHECK-RV32-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP23]], 4
+// CHECK-RV32-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP23]], 5
+// CHECK-RV32-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP23]], 6
+// CHECK-RV32-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP23]], 7
+// CHECK-RV32-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg8.mask.nxv1f64.i32(<vscale x 1 x double> [[TMP24]], <vscale x 1 x double> [[TMP25]], <vscale x 1 x double> [[TMP26]], <vscale x 1 x double> [[TMP27]], <vscale x 1 x double> [[TMP28]], <vscale x 1 x double> [[TMP29]], <vscale x 1 x double> [[TMP30]], <vscale x 1 x double> [[TMP31]], double* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP32]], 0
+// CHECK-RV32-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] undef, <vscale x 1 x double> [[TMP33]], 0
+// CHECK-RV32-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP32]], 1
+// CHECK-RV32-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP34]], <vscale x 1 x double> [[TMP35]], 1
+// CHECK-RV32-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP32]], 2
+// CHECK-RV32-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP36]], <vscale x 1 x double> [[TMP37]], 2
+// CHECK-RV32-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP32]], 3
+// CHECK-RV32-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP38]], <vscale x 1 x double> [[TMP39]], 3
+// CHECK-RV32-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP32]], 4
+// CHECK-RV32-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP40]], <vscale x 1 x double> [[TMP41]], 4
+// CHECK-RV32-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP32]], 5
+// CHECK-RV32-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP42]], <vscale x 1 x double> [[TMP43]], 5
+// CHECK-RV32-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP32]], 6
+// CHECK-RV32-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP44]], <vscale x 1 x double> [[TMP45]], 6
+// CHECK-RV32-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP32]], 7
+// CHECK-RV32-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP46]], <vscale x 1 x double> [[TMP47]], 7
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP48]]
+//
+// CHECK-RV64-LABEL: @test_vlseg8e64_v_f64m1x8_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T:%.*]] undef, <vscale x 1 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP0]], <vscale x 1 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP1]], <vscale x 1 x double> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP2]], <vscale x 1 x double> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP3]], <vscale x 1 x double> [[MASKEDOFF_COERCE4:%.*]], 4
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP4]], <vscale x 1 x double> [[MASKEDOFF_COERCE5:%.*]], 5
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP5]], <vscale x 1 x double> [[MASKEDOFF_COERCE6:%.*]], 6
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP6]], <vscale x 1 x double> [[MASKEDOFF_COERCE7:%.*]], 7
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 0
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] undef, <vscale x 1 x double> [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP9]], <vscale x 1 x double> [[TMP10]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP11]], <vscale x 1 x double> [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 3
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP13]], <vscale x 1 x double> [[TMP14]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 4
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP15]], <vscale x 1 x double> [[TMP16]], 4
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 5
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP17]], <vscale x 1 x double> [[TMP18]], 5
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 6
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP19]], <vscale x 1 x double> [[TMP20]], 6
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP7]], 7
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP21]], <vscale x 1 x double> [[TMP22]], 7
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP23]], 0
+// CHECK-RV64-NEXT:    [[TMP25:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP23]], 1
+// CHECK-RV64-NEXT:    [[TMP26:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP23]], 2
+// CHECK-RV64-NEXT:    [[TMP27:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP23]], 3
+// CHECK-RV64-NEXT:    [[TMP28:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP23]], 4
+// CHECK-RV64-NEXT:    [[TMP29:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP23]], 5
+// CHECK-RV64-NEXT:    [[TMP30:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP23]], 6
+// CHECK-RV64-NEXT:    [[TMP31:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP23]], 7
+// CHECK-RV64-NEXT:    [[TMP32:%.*]] = call { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } @llvm.riscv.vlseg8.mask.nxv1f64.i64(<vscale x 1 x double> [[TMP24]], <vscale x 1 x double> [[TMP25]], <vscale x 1 x double> [[TMP26]], <vscale x 1 x double> [[TMP27]], <vscale x 1 x double> [[TMP28]], <vscale x 1 x double> [[TMP29]], <vscale x 1 x double> [[TMP30]], <vscale x 1 x double> [[TMP31]], double* [[BASE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP33:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP32]], 0
+// CHECK-RV64-NEXT:    [[TMP34:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] undef, <vscale x 1 x double> [[TMP33]], 0
+// CHECK-RV64-NEXT:    [[TMP35:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP32]], 1
+// CHECK-RV64-NEXT:    [[TMP36:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP34]], <vscale x 1 x double> [[TMP35]], 1
+// CHECK-RV64-NEXT:    [[TMP37:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP32]], 2
+// CHECK-RV64-NEXT:    [[TMP38:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP36]], <vscale x 1 x double> [[TMP37]], 2
+// CHECK-RV64-NEXT:    [[TMP39:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP32]], 3
+// CHECK-RV64-NEXT:    [[TMP40:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP38]], <vscale x 1 x double> [[TMP39]], 3
+// CHECK-RV64-NEXT:    [[TMP41:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP32]], 4
+// CHECK-RV64-NEXT:    [[TMP42:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP40]], <vscale x 1 x double> [[TMP41]], 4
+// CHECK-RV64-NEXT:    [[TMP43:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP32]], 5
+// CHECK-RV64-NEXT:    [[TMP44:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP42]], <vscale x 1 x double> [[TMP43]], 5
+// CHECK-RV64-NEXT:    [[TMP45:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP32]], 6
+// CHECK-RV64-NEXT:    [[TMP46:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP44]], <vscale x 1 x double> [[TMP45]], 6
+// CHECK-RV64-NEXT:    [[TMP47:%.*]] = extractvalue { <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double> } [[TMP32]], 7
+// CHECK-RV64-NEXT:    [[TMP48:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP46]], <vscale x 1 x double> [[TMP47]], 7
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT64M1X8_T]] [[TMP48]]
+//
+vfloat64m1x8_t test_vlseg8e64_v_f64m1x8_m (vbool64_t mask, vfloat64m1x8_t maskedoff, const double *base, size_t vl) {
+  return vlseg8e64_v_f64m1x8_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e64_v_f64m2x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X2_T:%.*]] undef, <vscale x 2 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP0]], <vscale x 2 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X2_T]] undef, <vscale x 2 x double> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP3]], <vscale x 2 x double> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.riscv.vlseg2.mask.nxv2f64.i32(<vscale x 2 x double> [[TMP6]], <vscale x 2 x double> [[TMP7]], double* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X2_T]] undef, <vscale x 2 x double> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP10]], <vscale x 2 x double> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e64_v_f64m2x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X2_T:%.*]] undef, <vscale x 2 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP0]], <vscale x 2 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X2_T]] undef, <vscale x 2 x double> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP3]], <vscale x 2 x double> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.riscv.vlseg2.mask.nxv2f64.i64(<vscale x 2 x double> [[TMP6]], <vscale x 2 x double> [[TMP7]], double* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X2_T]] undef, <vscale x 2 x double> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP10]], <vscale x 2 x double> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT64M2X2_T]] [[TMP12]]
+//
+vfloat64m2x2_t test_vlseg2e64_v_f64m2x2_m (vbool32_t mask, vfloat64m2x2_t maskedoff, const double *base, size_t vl) {
+  return vlseg2e64_v_f64m2x2_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg3e64_v_f64m2x3_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T:%.*]] undef, <vscale x 2 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP0]], <vscale x 2 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP1]], <vscale x 2 x double> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T]] undef, <vscale x 2 x double> [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP2]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP4]], <vscale x 2 x double> [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP2]], 2
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP6]], <vscale x 2 x double> [[TMP7]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @llvm.riscv.vlseg3.mask.nxv2f64.i32(<vscale x 2 x double> [[TMP9]], <vscale x 2 x double> [[TMP10]], <vscale x 2 x double> [[TMP11]], double* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP12]], 0
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T]] undef, <vscale x 2 x double> [[TMP13]], 0
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP12]], 1
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP14]], <vscale x 2 x double> [[TMP15]], 1
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP12]], 2
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP16]], <vscale x 2 x double> [[TMP17]], 2
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP18]]
+//
+// CHECK-RV64-LABEL: @test_vlseg3e64_v_f64m2x3_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T:%.*]] undef, <vscale x 2 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP0]], <vscale x 2 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP1]], <vscale x 2 x double> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T]] undef, <vscale x 2 x double> [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP2]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP4]], <vscale x 2 x double> [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP2]], 2
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP6]], <vscale x 2 x double> [[TMP7]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @llvm.riscv.vlseg3.mask.nxv2f64.i64(<vscale x 2 x double> [[TMP9]], <vscale x 2 x double> [[TMP10]], <vscale x 2 x double> [[TMP11]], double* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP12]], 0
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T]] undef, <vscale x 2 x double> [[TMP13]], 0
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP12]], 1
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP14]], <vscale x 2 x double> [[TMP15]], 1
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP12]], 2
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP16]], <vscale x 2 x double> [[TMP17]], 2
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT64M2X3_T]] [[TMP18]]
+//
+vfloat64m2x3_t test_vlseg3e64_v_f64m2x3_m (vbool32_t mask, vfloat64m2x3_t maskedoff, const double *base, size_t vl) {
+  return vlseg3e64_v_f64m2x3_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg4e64_v_f64m2x4_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T:%.*]] undef, <vscale x 2 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP0]], <vscale x 2 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP1]], <vscale x 2 x double> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP2]], <vscale x 2 x double> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP3]], 0
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] undef, <vscale x 2 x double> [[TMP4]], 0
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP3]], 1
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP5]], <vscale x 2 x double> [[TMP6]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP3]], 2
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP7]], <vscale x 2 x double> [[TMP8]], 2
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP3]], 3
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP9]], <vscale x 2 x double> [[TMP10]], 3
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP11]], 0
+// CHECK-RV32-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP11]], 1
+// CHECK-RV32-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP11]], 2
+// CHECK-RV32-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP11]], 3
+// CHECK-RV32-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @llvm.riscv.vlseg4.mask.nxv2f64.i32(<vscale x 2 x double> [[TMP12]], <vscale x 2 x double> [[TMP13]], <vscale x 2 x double> [[TMP14]], <vscale x 2 x double> [[TMP15]], double* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP16]], 0
+// CHECK-RV32-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] undef, <vscale x 2 x double> [[TMP17]], 0
+// CHECK-RV32-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP16]], 1
+// CHECK-RV32-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP18]], <vscale x 2 x double> [[TMP19]], 1
+// CHECK-RV32-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP16]], 2
+// CHECK-RV32-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP20]], <vscale x 2 x double> [[TMP21]], 2
+// CHECK-RV32-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP16]], 3
+// CHECK-RV32-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP22]], <vscale x 2 x double> [[TMP23]], 3
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP24]]
+//
+// CHECK-RV64-LABEL: @test_vlseg4e64_v_f64m2x4_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T:%.*]] undef, <vscale x 2 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP0]], <vscale x 2 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP1]], <vscale x 2 x double> [[MASKEDOFF_COERCE2:%.*]], 2
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP2]], <vscale x 2 x double> [[MASKEDOFF_COERCE3:%.*]], 3
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP3]], 0
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] undef, <vscale x 2 x double> [[TMP4]], 0
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP3]], 1
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP5]], <vscale x 2 x double> [[TMP6]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP3]], 2
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP7]], <vscale x 2 x double> [[TMP8]], 2
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP3]], 3
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP9]], <vscale x 2 x double> [[TMP10]], 3
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP11]], 0
+// CHECK-RV64-NEXT:    [[TMP13:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP11]], 1
+// CHECK-RV64-NEXT:    [[TMP14:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP11]], 2
+// CHECK-RV64-NEXT:    [[TMP15:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP11]], 3
+// CHECK-RV64-NEXT:    [[TMP16:%.*]] = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @llvm.riscv.vlseg4.mask.nxv2f64.i64(<vscale x 2 x double> [[TMP12]], <vscale x 2 x double> [[TMP13]], <vscale x 2 x double> [[TMP14]], <vscale x 2 x double> [[TMP15]], double* [[BASE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP17:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP16]], 0
+// CHECK-RV64-NEXT:    [[TMP18:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] undef, <vscale x 2 x double> [[TMP17]], 0
+// CHECK-RV64-NEXT:    [[TMP19:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP16]], 1
+// CHECK-RV64-NEXT:    [[TMP20:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP18]], <vscale x 2 x double> [[TMP19]], 1
+// CHECK-RV64-NEXT:    [[TMP21:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP16]], 2
+// CHECK-RV64-NEXT:    [[TMP22:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP20]], <vscale x 2 x double> [[TMP21]], 2
+// CHECK-RV64-NEXT:    [[TMP23:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } [[TMP16]], 3
+// CHECK-RV64-NEXT:    [[TMP24:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP22]], <vscale x 2 x double> [[TMP23]], 3
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT64M2X4_T]] [[TMP24]]
+//
+vfloat64m2x4_t test_vlseg4e64_v_f64m2x4_m (vbool32_t mask, vfloat64m2x4_t maskedoff, const double *base, size_t vl) {
+  return vlseg4e64_v_f64m2x4_m(mask, maskedoff, base, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e64_v_f64m4x2_m(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M4X2_T:%.*]] undef, <vscale x 4 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV32-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP0]], <vscale x 4 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV32-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP1]], 0
+// CHECK-RV32-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M4X2_T]] undef, <vscale x 4 x double> [[TMP2]], 0
+// CHECK-RV32-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP1]], 1
+// CHECK-RV32-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP3]], <vscale x 4 x double> [[TMP4]], 1
+// CHECK-RV32-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP5]], 0
+// CHECK-RV32-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP5]], 1
+// CHECK-RV32-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x double>, <vscale x 4 x double> } @llvm.riscv.vlseg2.mask.nxv4f64.i32(<vscale x 4 x double> [[TMP6]], <vscale x 4 x double> [[TMP7]], double* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]])
+// CHECK-RV32-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x double>, <vscale x 4 x double> } [[TMP8]], 0
+// CHECK-RV32-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M4X2_T]] undef, <vscale x 4 x double> [[TMP9]], 0
+// CHECK-RV32-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x double>, <vscale x 4 x double> } [[TMP8]], 1
+// CHECK-RV32-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP10]], <vscale x 4 x double> [[TMP11]], 1
+// CHECK-RV32-NEXT:    ret [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP12]]
+//
+// CHECK-RV64-LABEL: @test_vlseg2e64_v_f64m4x2_m(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M4X2_T:%.*]] undef, <vscale x 4 x double> [[MASKEDOFF_COERCE0:%.*]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP0]], <vscale x 4 x double> [[MASKEDOFF_COERCE1:%.*]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP1]], 0
+// CHECK-RV64-NEXT:    [[TMP3:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M4X2_T]] undef, <vscale x 4 x double> [[TMP2]], 0
+// CHECK-RV64-NEXT:    [[TMP4:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP1]], 1
+// CHECK-RV64-NEXT:    [[TMP5:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP3]], <vscale x 4 x double> [[TMP4]], 1
+// CHECK-RV64-NEXT:    [[TMP6:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP5]], 0
+// CHECK-RV64-NEXT:    [[TMP7:%.*]] = extractvalue [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP5]], 1
+// CHECK-RV64-NEXT:    [[TMP8:%.*]] = call { <vscale x 4 x double>, <vscale x 4 x double> } @llvm.riscv.vlseg2.mask.nxv4f64.i64(<vscale x 4 x double> [[TMP6]], <vscale x 4 x double> [[TMP7]], double* [[BASE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    [[TMP9:%.*]] = extractvalue { <vscale x 4 x double>, <vscale x 4 x double> } [[TMP8]], 0
+// CHECK-RV64-NEXT:    [[TMP10:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M4X2_T]] undef, <vscale x 4 x double> [[TMP9]], 0
+// CHECK-RV64-NEXT:    [[TMP11:%.*]] = extractvalue { <vscale x 4 x double>, <vscale x 4 x double> } [[TMP8]], 1
+// CHECK-RV64-NEXT:    [[TMP12:%.*]] = insertvalue [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP10]], <vscale x 4 x double> [[TMP11]], 1
+// CHECK-RV64-NEXT:    ret [[STRUCT___RVV_FLOAT64M4X2_T]] [[TMP12]]
+//
+vfloat64m4x2_t test_vlseg2e64_v_f64m4x2_m (vbool16_t mask, vfloat64m4x2_t maskedoff, const double *base, size_t vl) {
+  return vlseg2e64_v_f64m4x2_m(mask, maskedoff, base, vl);
+}

clang/utils/TableGen/RISCVVEmitter.cpp

class RVVType {
   BasicType BT;
   ScalarTypeKind ScalarType = Invalid;
   LMULType LMUL;
   bool IsPointer = false;
   // IsConstant indices are "int", but have the constant expression.
   bool IsImmediate = false;
   // Const qualifier for pointer to const object or object of const type.
   bool IsConstant = false;
+  bool IsTuple = false;
   unsigned ElementBitwidth = 0;
   VScaleVal Scale = 0;
   bool Valid;
+  unsigned NF = 0;
 
   std::string BuiltinStr;
   std::string ClangBuiltinStr;
   std::string Str;
   std::string ShortStr;
 
 public:
   RVVType() : RVVType(BasicType(), 0, StringRef()) {}
bool RVVType::verifyType() const {
   if (ScalarType == Invalid)
     return false;
   if (isScalar())
     return true;
   if (!Scale.hasValue())
     return false;
   if (isFloat() && ElementBitwidth == 8)
     return false;
+  if (IsTuple && (NF == 1 || NF > 8))
+    return false;
   unsigned V = Scale.getValue();
   switch (ElementBitwidth) {
   case 1:
   case 8:
+    if (IsTuple)
+      return (V * NF <= 64);
     // Check Scale is 1,2,4,8,16,32,64
     return (V <= 64 && isPowerOf2_32(V));
   case 16:
+    if (IsTuple)
+      return (V * NF <= 32);
     // Check Scale is 1,2,4,8,16,32
     return (V <= 32 && isPowerOf2_32(V));
   case 32:
+    if (IsTuple)
+      return (V * NF <= 16);
     // Check Scale is 1,2,4,8,16
     return (V <= 16 && isPowerOf2_32(V));
   case 64:
+    if (IsTuple)
+      return (V * NF <= 8);
     // Check Scale is 1,2,4,8
     return (V <= 8 && isPowerOf2_32(V));
   }
   return false;
 }
 
 void RVVType::initBuiltinStr() {
   assert(isValid() && "RVVType is invalid");
void RVVType::initBuiltinStr() {
   if (isScalar()) {
     if (IsConstant)
       BuiltinStr += "C";
     if (IsPointer)
       BuiltinStr += "*";
     return;
   }
   BuiltinStr = "q" + utostr(Scale.getValue()) + BuiltinStr;
+
+  if (IsTuple)
+    BuiltinStr = "T" + utostr(NF) + BuiltinStr;
 }
 
 void RVVType::initClangBuiltinStr() {
   assert(isValid() && "RVVType is invalid");
   assert(isVector() && "Handle Vector type only");
 
   ClangBuiltinStr = "__rvv_";
   switch (ScalarType) {
   case ScalarTypeKind::Boolean:
     ClangBuiltinStr += "bool" + utostr(64 / Scale.getValue()) + "_t";
     return;
   case ScalarTypeKind::Float:
     ClangBuiltinStr += "float";
     break;
   case ScalarTypeKind::SignedInteger:
     ClangBuiltinStr += "int";
     break;
   case ScalarTypeKind::UnsignedInteger:
     ClangBuiltinStr += "uint";
     break;
   default:
     llvm_unreachable("ScalarTypeKind is invalid");
   }
-  ClangBuiltinStr += utostr(ElementBitwidth) + LMUL.str() + "_t";
+  ClangBuiltinStr += utostr(ElementBitwidth) + LMUL.str();
+  if (IsTuple)
+    ClangBuiltinStr += "x" + utostr(NF);
+  ClangBuiltinStr += "_t";
 }
 
 void RVVType::initTypeStr() {
   assert(isValid() && "RVVType is invalid");
 
   if (IsConstant)
     Str += "const ";
 
   auto getTypeString = [&](StringRef TypeStr) {
     if (isScalar())
       return Twine(TypeStr + Twine(ElementBitwidth) + "_t").str();
-    return Twine("v" + TypeStr + Twine(ElementBitwidth) + LMUL.str() + "_t")
+    return Twine("v" + TypeStr + Twine(ElementBitwidth) + LMUL.str() +
+                 (IsTuple ? "x" + utostr(NF) : "") + "_t")
         .str();
   };
 
   switch (ScalarType) {
   case ScalarTypeKind::Void:
     Str = "void";
     return;
   case ScalarTypeKind::Size_t:
case ScalarTypeKind::SignedInteger:
     ShortStr = "i" + utostr(ElementBitwidth) + LMUL.str();
     break;
   case ScalarTypeKind::UnsignedInteger:
     ShortStr = "u" + utostr(ElementBitwidth) + LMUL.str();
     break;
   default:
     llvm_unreachable("Unhandled case!");
   }
+  if (IsTuple)
+    ShortStr += "x" + utostr(NF);
 }
 
 void RVVType::applyBasicType() {
   switch (BT) {
   case 'c':
     ElementBitwidth = 8;
     ScalarType = ScalarTypeKind::SignedInteger;
     break;
void RVVType::applyBasicType() {
   assert(ElementBitwidth != 0 && "Bad element bitwidth!");
 }
 
 void RVVType::applyModifier(StringRef Transformer) {
   if (Transformer.empty())
     return;
   // Handle primitive type transformer
   auto PType = Transformer.back();
+  unsigned NFCount = 0;
   switch (PType) {
   case 'e':
     Scale = 0;
     break;
   case 'v':
     Scale = LMUL.getScale(ElementBitwidth);
     break;
   case 'w':
if (ComplexTT.first == "Log2EEW") {
       uint32_t Log2EEW;
       ComplexTT.second.getAsInteger(10, Log2EEW);
       // update new elmul = (eew/sew) * lmul
       LMUL.MulLog2LMUL(Log2EEW - Log2_32(ElementBitwidth));
       // update new eew
       ElementBitwidth = 1 << Log2EEW;
       ScalarType = ScalarTypeKind::SignedInteger;
       UpdateAndCheckComplexProto();
+    } else if (ComplexTT.first == "Tuple") {
+      ComplexTT.second.getAsInteger(10, NFCount);
+      assert(2 <= NFCount && NFCount <= 8);
     } else {
       PrintFatalError("Illegal complex type transformers!");
     }
   }
 
   // Compute the remain type transformers
   for (char I : Transformer) {
     switch (I) {
case 'S':
       LMUL = LMULType(0);
       // Update ElementBitwidth need to update Scale too.
       Scale = LMUL.getScale(ElementBitwidth);
       break;
     default:
       PrintFatalError("Illegal non-primitive type transformer!");
     }
   }
+
+  if (PType == 'v' && NFCount > 0) {
+    IsTuple = true;
+    NF = NFCount;
+  }
 }
 
 //===----------------------------------------------------------------------===//
 // RVVIntrinsic implementation
 //===----------------------------------------------------------------------===//
 RVVIntrinsic::RVVIntrinsic(StringRef NewName, StringRef Suffix,
                            StringRef NewMangledName, StringRef IRName,
                            bool HasSideEffects, bool IsMask,
void RVVEmitter::createHeader(raw_ostream &OS) {
   }
 
   auto printType = [&](auto T) {
     OS << "typedef " << T->getClangBuiltinStr() << " " << T->getTypeStr()
        << ";\n";
   };
 
   constexpr int Log2LMULs[] = {-3, -2, -1, 0, 1, 2, 3};
+  constexpr int NF[] = {2, 3, 4, 5, 6, 7, 8};
   // Print RVV boolean types.
   for (int Log2LMUL : Log2LMULs) {
     auto T = computeType('c', Log2LMUL, "m");
     if (T.hasValue())
       printType(T.getValue());
   }
   // Print RVV int/float types.
   for (char I : StringRef("csil")) {
     for (int Log2LMUL : Log2LMULs) {
       auto T = computeType(I, Log2LMUL, "v");
       if (T.hasValue()) {
         printType(T.getValue());
         auto UT = computeType(I, Log2LMUL, "Uv");
         printType(UT.getValue());
       }
+      for (int N : NF) {
+        auto T = computeType(I, Log2LMUL, "(Tuple:" + utostr(N) + ")v");
+        if (T.hasValue()) {
+          printType(T.getValue());
+          auto UT = computeType(I, Log2LMUL, "(Tuple:" + utostr(N) + ")Uv");
+          printType(UT.getValue());
+        }
+      }
     }
   }
   OS << "#if defined(__riscv_zfh)\n";
   for (int Log2LMUL : Log2LMULs) {
     auto T = computeType('h', Log2LMUL, "v");
     if (T.hasValue())
       printType(T.getValue());
+    for (int N : NF) {
+      auto T = computeType('h', Log2LMUL, "(Tuple:" + utostr(N) + ")v");
+      if (T.hasValue())
+        printType(T.getValue());
+    }
   }
   OS << "#endif\n";
 
   OS << "#if defined(__riscv_f)\n";
   for (int Log2LMUL : Log2LMULs) {
     auto T = computeType('f', Log2LMUL, "v");
     if (T.hasValue())
       printType(T.getValue());
+    for (int N : NF) {
+      auto T = computeType('f', Log2LMUL, "(Tuple:" + utostr(N) + ")v");
+      if (T.hasValue())
+        printType(T.getValue());
+    }
   }
   OS << "#endif\n";
 
   OS << "#if defined(__riscv_d)\n";
   for (int Log2LMUL : Log2LMULs) {
     auto T = computeType('d', Log2LMUL, "v");
     if (T.hasValue())
       printType(T.getValue());
+    for (int N : NF) {
+      auto T = computeType('d', Log2LMUL, "(Tuple:" + utostr(N) + ")v");
+      if (T.hasValue())
+        printType(T.getValue());
+    }
   }
   OS << "#endif\n\n";
 
   // The same extension include in the same arch guard marco.
   std::stable_sort(Defs.begin(), Defs.end(),
                    [](const std::unique_ptr<RVVIntrinsic> &A,
                       const std::unique_ptr<RVVIntrinsic> &B) {
                      return A->getRISCVExtensions() < B->getRISCVExtensions();