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[RISCV] Support fixed-length vector sign/zero extension
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Authored by frasercrmck on Feb 22 2021, 7:28 AM.

Details

Summary

This patch adds support for the custom lowering sign- and zero-extension
of fixed-length vector types. It does so through custom nodes. Since the
source and destination types are (necessarily) of different sizes, it is
possible that the source type is legal whilst the larger destination
type isn't. In this case the legalization makes heavy use of
EXTRACT_SUBVECTOR.

Diff Detail

Event Timeline

frasercrmck created this revision.Feb 22 2021, 7:28 AM
frasercrmck requested review of this revision.Feb 22 2021, 7:28 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 22 2021, 7:28 AM
craig.topper added inline comments.Feb 22 2021, 12:44 PM
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
15

This is using LMUL 4 for a result that fits in 128 bits. Should we be getting the container from the destination and deriving the source lmul from it instead?

frasercrmck marked an inline comment as done.
  • rebase
  • address review feedback: grab container from extended type
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
15

That was what I tried at first, but I was seeing incorrect codegen when it came to split legalized vectors and subvector extraction. It seems to have resolved itself now though so I was obviously wrong about where the bug was. I've fixed this up now, cheers.

This revision is now accepted and ready to land.Feb 23 2021, 10:11 AM
  • rebase
  • regenerate test cases (vsetivli)