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[RISCV] Unify scalable- and fixed-vector EXTRACT_SUBVECTOR lowering
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Authored by frasercrmck on Mon, Feb 22, 6:59 AM.

Details

Summary

This patch unifies the two disparate paths for lowering
EXTRACT_SUBVECTOR operations under one roof. Consequently, with this
patch it is possible to support any fixed-length subvector extraction,
not just "cast-like" ones.

Diff Detail

Event Timeline

frasercrmck created this revision.Mon, Feb 22, 6:59 AM
frasercrmck requested review of this revision.Mon, Feb 22, 6:59 AM
Herald added a project: Restricted Project. · View Herald TranscriptMon, Feb 22, 6:59 AM
craig.topper added inline comments.Mon, Feb 22, 12:35 PM
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
28

Should we be using a VL of 8 here?

craig.topper added inline comments.Mon, Feb 22, 4:15 PM
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
74

The elements we're looking for aren't guaranteed to be in v27. We only know the minimum width of a register is 128 bits. It might be 256 bits or more. In which case all 8 elements are all in v26. I think we have to always slide down to 0 using the full lmul.

  • rebase
  • fix codegen for fixed-length types
  • add tests for extraction from scalable to fixed-length types
frasercrmck marked 2 inline comments as done.Tue, Feb 23, 2:50 AM
frasercrmck added inline comments.
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
28

Hmm yes we should. Let me find it.

74

Oh snap, you're right. Sliding down the full amount seems like the way to go.

craig.topper added inline comments.Tue, Feb 23, 10:19 AM
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
28

Based on a conversation with Andrew Waterman I had yesterday, the VL for the slidedown should just cover the elements we care about. Especially when the input LMUL > 1 and the output is LMUL <= 1. The smaller VL would allow the computation for the upper registers to be skipped. It still could be beneficial on CPUs with ALUs narrower than the VLEN.

frasercrmck marked 2 inline comments as done.
  • shrink VL for vslidedown as per Craig's feedback
frasercrmck marked an inline comment as done.Wed, Feb 24, 3:44 AM
frasercrmck added inline comments.
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
28

Ah that's interesting, thanks. I've updated the VL for the fixed-length lowering accordingly.

This revision is now accepted and ready to land.Wed, Feb 24, 12:22 PM
frasercrmck marked an inline comment as done.
  • rebase
  • regenerate test cases (vsetivli)