[PowerPC] Implement XL compact math builtins

[lei]

Summary

Implement a subset of builtins required for compatiblilty with AIX XL compiler.

[lei]

update tc to only check for pwr7 and up

[nemanjai]

llvm/lib/Target/PowerPC/PPCInstrInfo.td

3092

I think we should conservatively set RM as an implicit def here. @ZhangKang you modified this code most recently, please provide your opinion here.

[lei]

cleanup tests

[nemanjai]

Please change compact in the title to compat.

clang/include/clang/Basic/BuiltinsPPC.def

78–81

I think at least some of these should be I because the parameter must be foldable to an integer constant expression (see Builtins.def).

llvm/include/llvm/IR/IntrinsicsPowerPC.td

1588

For parameters that need to be immediates, please mark them as such with the respective intrinsic property.

llvm/lib/Target/PowerPC/PPCInstrInfo.td

3655

Please review the order of operands carefully here. I believe the order is wrong either for this one or for the VSX version. Double-check all of the others as well please.

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll

3

Please add -mattr=-vsx to one of the run lines since you have added patterns for non-VSX but do not appear to be testing that code path.

[lei]

Address review comments to add/upate:

• builtin encoding for params that need to be folded into constant expr
• llvm intrinsic property for immediates
• test line for -mattr=-vsx

llvm/lib/Target/PowerPC/PPCInstrInfo.td

3655

I double checked and both seem correct to me.

[lei]

rebase to ToT

[nemanjai]

LGTM other than the comment that wasn't addressed (which I assume will be addressed in a subsequent patch).

llvm/lib/Target/PowerPC/PPCInstrInfo.td

3092

This was not addressed. Will this be added in a follow-up patch?

[lei]

llvm/lib/Target/PowerPC/PPCInstrInfo.td

3092

Yes, sorry I will address this in a subsequent patch since adding RM will cause unrelated LIT failures.

clang/include/clang/Basic/BuiltinsPPC.def

#   define CUSTOM_BUILTIN(ID, INTR, TYPES, ACCUMULATE) \
       BUILTIN(__builtin_##ID, "i.", "t")
 #elif defined(CUSTOM_BUILTIN) && !defined(BUILTIN)
 #   define BUILTIN(ID, TYPES, ATTRS)
 #endif
 
 #define UNALIASED_CUSTOM_BUILTIN(ID, TYPES, ACCUMULATE) \
    CUSTOM_BUILTIN(ID, ID, TYPES, ACCUMULATE)
 
-// builtins for compatibility with the XL compiler
+// XL Compatibility built-ins
 BUILTIN(__builtin_ppc_popcntb, "ULiULi", "")
 BUILTIN(__builtin_ppc_poppar4, "iUi", "")
 BUILTIN(__builtin_ppc_poppar8, "iULLi", "")
 BUILTIN(__builtin_ppc_eieio, "v", "")
 BUILTIN(__builtin_ppc_iospace_eieio, "v", "")
 BUILTIN(__builtin_ppc_isync, "v", "")
 BUILTIN(__builtin_ppc_lwsync, "v", "")
 BUILTIN(__builtin_ppc_iospace_lwsync, "v", "")

 BUILTIN(__builtin_ppc_fctid, "dd", "")
 BUILTIN(__builtin_ppc_fctidz, "dd", "")
 BUILTIN(__builtin_ppc_fctiw, "dd", "")
 BUILTIN(__builtin_ppc_fctiwz, "dd", "")
 BUILTIN(__builtin_ppc_fctudz, "dd", "")
 BUILTIN(__builtin_ppc_fctuwz, "dd", "")
 // Compare
 BUILTIN(__builtin_ppc_cmpeqb, "LLiLLiLLi", "")
 BUILTIN(__builtin_ppc_cmprb, "iCIiii", "")
 BUILTIN(__builtin_ppc_setb, "LLiLLiLLi", "")
 // Multiply
 BUILTIN(__builtin_ppc_mulhd, "LLiLiLi", "")
 BUILTIN(__builtin_ppc_mulhdu, "ULLiULiULi", "")
 BUILTIN(__builtin_ppc_mulhw, "iii", "")
 BUILTIN(__builtin_ppc_mulhwu, "UiUiUi", "")
 BUILTIN(__builtin_ppc_maddhd, "LLiLLiLLiLLi", "")
 BUILTIN(__builtin_ppc_maddhdu, "ULLiULLiULLiULLi", "")
 BUILTIN(__builtin_ppc_maddld, "LLiLLiLLiLLi", "")
 // Rotate
 BUILTIN(__builtin_ppc_rlwnm, "UiUiIUiIUi", "")
 BUILTIN(__builtin_ppc_rlwimi, "UiUiUiIUiIUi", "")
 BUILTIN(__builtin_ppc_rldimi, "ULLiULLiULLiIUiIULLi", "")
 // load
 BUILTIN(__builtin_ppc_load2r, "UiUs*", "")
 BUILTIN(__builtin_ppc_load4r, "UiUi*", "")
 BUILTIN(__builtin_ppc_load8r, "ULLiULLi*", "")
 // store
 BUILTIN(__builtin_ppc_store2r, "vUiUs*", "")
 BUILTIN(__builtin_ppc_store4r, "vUiUi*", "")
 BUILTIN(__builtin_ppc_store8r, "vULLiULLi*", "")
+BUILTIN(__builtin_ppc_extract_exp, "Uid", "")
+BUILTIN(__builtin_ppc_extract_sig, "ULLid", "")
+BUILTIN(__builtin_ppc_mtfsb0, "vUIi", "")
+BUILTIN(__builtin_ppc_mtfsb1, "vUIi", "")
+BUILTIN(__builtin_ppc_mtfsf, "vUIiUi", "")
+BUILTIN(__builtin_ppc_mtfsfi, "vUIiUIi", "")
+BUILTIN(__builtin_ppc_insert_exp, "ddULLi", "")
+BUILTIN(__builtin_ppc_fmsub, "dddd", "")
+BUILTIN(__builtin_ppc_fmsubs, "ffff", "")
+BUILTIN(__builtin_ppc_fnmadd, "dddd", "")
+BUILTIN(__builtin_ppc_fnmadds, "ffff", "")
+BUILTIN(__builtin_ppc_fnmsub, "dddd", "")
+BUILTIN(__builtin_ppc_fnmsubs, "ffff", "")
+BUILTIN(__builtin_ppc_fre, "dd", "")
+BUILTIN(__builtin_ppc_fres, "ff", "")
 
 BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
 
 // This is just a placeholder, the types and attributes are wrong.
 BUILTIN(__builtin_altivec_vaddcuw, "V4UiV4UiV4Ui", "")
 
 BUILTIN(__builtin_altivec_vaddsbs, "V16ScV16ScV16Sc", "")
 BUILTIN(__builtin_altivec_vaddubs, "V16UcV16UcV16Uc", "")

clang/lib/Basic/Targets/PPC.cpp

static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__rlwimi", "__builtin_ppc_rlwimi");
   Builder.defineMacro("__rldimi", "__builtin_ppc_rldimi");
   Builder.defineMacro("__load2r", "__builtin_ppc_load2r");
   Builder.defineMacro("__load4r", "__builtin_ppc_load4r");
   Builder.defineMacro("__load8r", "__builtin_ppc_load8r");
   Builder.defineMacro("__store2r", "__builtin_ppc_store2r");
   Builder.defineMacro("__store4r", "__builtin_ppc_store4r");
   Builder.defineMacro("__store8r", "__builtin_ppc_store8r");
+  Builder.defineMacro("__extract_exp", "__builtin_ppc_extract_exp");
+  Builder.defineMacro("__extract_sig", "__builtin_ppc_extract_sig");
+  Builder.defineMacro("__mtfsb0", "__builtin_ppc_mtfsb0");
+  Builder.defineMacro("__mtfsb1", "__builtin_ppc_mtfsb1");
+  Builder.defineMacro("__mtfsf", "__builtin_ppc_mtfsf");
+  Builder.defineMacro("__mtfsfi", "__builtin_ppc_mtfsfi");
+  Builder.defineMacro("__insert_exp", "__builtin_ppc_insert_exp");
+  Builder.defineMacro("__fmsub", "__builtin_ppc_fmsub");
+  Builder.defineMacro("__fmsubs", "__builtin_ppc_fmsubs");
+  Builder.defineMacro("__fnmadd", "__builtin_ppc_fnmadd");
+  Builder.defineMacro("__fnmadds", "__builtin_ppc_fnmadds");
+  Builder.defineMacro("__fnmsub", "__builtin_ppc_fnmsub");
+  Builder.defineMacro("__fnmsubs", "__builtin_ppc_fnmsubs");
+  Builder.defineMacro("__fre", "__builtin_ppc_fre");
+  Builder.defineMacro("__fres", "__builtin_ppc_fres");
 }
 
 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
 /// #defines that are not tied to a specific subtarget.
 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
                                      MacroBuilder &Builder) const {
 
   defineXLCompatMacros(Builder);

clang/lib/Sema/SemaChecking.cpp

static bool isPPC_64Builtin(unsigned BuiltinID) {
   case PPC::BI__builtin_ppc_setb:
   case PPC::BI__builtin_ppc_mulhd:
   case PPC::BI__builtin_ppc_mulhdu:
   case PPC::BI__builtin_ppc_maddhd:
   case PPC::BI__builtin_ppc_maddhdu:
   case PPC::BI__builtin_ppc_maddld:
   case PPC::BI__builtin_ppc_load8r:
   case PPC::BI__builtin_ppc_store8r:
+  case PPC::BI__builtin_ppc_insert_exp:
+  case PPC::BI__builtin_ppc_extract_sig:
     return true;
   }
   return false;
 }
 
 static bool SemaFeatureCheck(Sema &S, CallExpr *TheCall,
                              StringRef FeatureToCheck, unsigned DiagID,
                              StringRef DiagArg = "") {
bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
   // be a constant that represents a contiguous bit field.
   case PPC::BI__builtin_ppc_rlwnm:
     return SemaBuiltinConstantArg(TheCall, 1, Result) ||
            SemaValueIsRunOfOnes(TheCall, 2);
   case PPC::BI__builtin_ppc_rlwimi:
   case PPC::BI__builtin_ppc_rldimi:
     return SemaBuiltinConstantArg(TheCall, 2, Result) ||
            SemaValueIsRunOfOnes(TheCall, 3);
+  case PPC::BI__builtin_ppc_extract_exp:
+  case PPC::BI__builtin_ppc_extract_sig:
+  case PPC::BI__builtin_ppc_insert_exp:
+    return SemaFeatureCheck(*this, TheCall, "power9-vector",
+                            diag::err_ppc_builtin_only_on_arch, "9");
+  case PPC::BI__builtin_ppc_mtfsb0:
+  case PPC::BI__builtin_ppc_mtfsb1:
+    return SemaBuiltinConstantArgRange(TheCall, 0, 0, 31);
+  case PPC::BI__builtin_ppc_mtfsf:
+    return SemaBuiltinConstantArgRange(TheCall, 0, 0, 255);
+  case PPC::BI__builtin_ppc_mtfsfi:
+    return SemaBuiltinConstantArgRange(TheCall, 0, 0, 7) ||
+           SemaBuiltinConstantArgRange(TheCall, 1, 0, 15);
 #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
   case PPC::BI__builtin_##Name: \
     return SemaBuiltinPPCMMACall(TheCall, Types);
 #include "clang/Basic/BuiltinsPPC.def"
   }
   return SemaBuiltinConstantArgRange(TheCall, i, l, u);
 }
 

clang/test/CodeGen/builtins-ppc-xlcompat-error.c

 
 void test_builtin_ppc_rlwnm() {
   unsigned int shift;
   unsigned int mask;
   unsigned int res = __builtin_ppc_rlwnm(ui, shift, 7); // expected-error {{argument to '__builtin_ppc_rlwnm' must be a constant integer}}
   res = __builtin_ppc_rlwnm(ui, 31, mask);              // expected-error {{argument to '__builtin_ppc_rlwnm' must be a constant integer}}
   res = __builtin_ppc_rlwnm(ui, 31, 0xFF0F0F00);        // expected-error {{argument 2 value should represent a contiguous bit field}}
 }
+
+extern unsigned int usi;
+extern double d;
+extern float f;
+
+void testMathBuiltin(void) {
+  __mtfsb0(usi); //expected-error {{argument to '__builtin_ppc_mtfsb0' must be a constant integer}}
+  __mtfsb0(32); //expected-error {{argument value 32 is outside the valid range [0, 31]}}
+  __mtfsb1(usi); //expected-error {{argument to '__builtin_ppc_mtfsb1' must be a constant integer}}
+  __mtfsb1(45); //expected-error {{argument value 45 is outside the valid range [0, 31]}}
+  __mtfsf(usi, usi); //expected-error {{argument to '__builtin_ppc_mtfsf' must be a constant integer}}
+  __mtfsf(350, usi); //expected-error {{argument value 350 is outside the valid range [0, 255]}}
+  __mtfsfi(usi, 0); //expected-error {{argument to '__builtin_ppc_mtfsfi' must be a constant integer}}
+  __mtfsfi(0, usi); //expected-error {{argument to '__builtin_ppc_mtfsfi' must be a constant integer}}
+  __mtfsfi(8, 0); //expected-error {{argument value 8 is outside the valid range [0, 7]}}
+  __mtfsfi(5, 24); //expected-error {{argument value 24 is outside the valid range [0, 15]}}
+}

clang/test/CodeGen/builtins-ppc-xlcompat-math.c

+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -emit-llvm %s \
+// RUN:   -target-cpu pwr7 -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -emit-llvm %s \
+// RUN:   -target-cpu pwr8 -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -emit-llvm %s \
+// RUN:   -target-cpu pwr7 -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -emit-llvm %s \
+// RUN:   -target-cpu pwr7 -o - | FileCheck %s
+
+// CHECK-LABEL: @mtfsb0(
+// CHECK:         call void @llvm.ppc.mtfsb0(i32 10)
+// CHECK-NEXT:    ret void
+//
+void mtfsb0 () {
+  __mtfsb0 (10);
+}
+
+// CHECK-LABEL: @mtfsb1(
+// CHECK:         call void @llvm.ppc.mtfsb1(i32 0)
+// CHECK-NEXT:    ret void
+//
+void mtfsb1 () {
+  __mtfsb1 (0);
+}
+
+// CHECK-LABEL: @mtfsf(
+// CHECK:         [[UI_ADDR:%.*]] = alloca i32, align 4
+// CHECK-NEXT:    store i32 [[UI:%.*]], i32* [[UI_ADDR]], align 4
+// CHECK-NEXT:    [[TMP0:%.*]] = load i32, i32* [[UI_ADDR]], align 4
+// CHECK-NEXT:    call void @llvm.ppc.mtfsf(i32 8, i32 [[TMP0]])
+// CHECK-NEXT:    ret void
+//
+void mtfsf (unsigned int ui) {
+  __mtfsf (8, ui);
+}
+
+// CHECK-LABEL: @mtfsfi(
+// CHECK:         call void @llvm.ppc.mtfsfi(i32 7, i32 15)
+// CHECK-NEXT:    ret void
+//
+void mtfsfi () {
+  __mtfsfi (7, 15);
+}
+
+// CHECK-LABEL: @fmsub(
+// CHECK:         [[D_ADDR:%.*]] = alloca double, align 8
+// CHECK-NEXT:    store double [[D:%.*]], double* [[D_ADDR]], align 8
+// CHECK-NEXT:    [[TMP0:%.*]] = load double, double* [[D_ADDR]], align 8
+// CHECK-NEXT:    [[TMP1:%.*]] = load double, double* [[D_ADDR]], align 8
+// CHECK-NEXT:    [[TMP2:%.*]] = load double, double* [[D_ADDR]], align 8
+// CHECK-NEXT:    [[TMP3:%.*]] = call double @llvm.ppc.fmsub(double [[TMP0]], double [[TMP1]], double [[TMP2]])
+// CHECK-NEXT:    ret double [[TMP3]]
+//
+double fmsub (double d) {
+  return __fmsub (d, d, d);
+}
+
+// CHECK-LABEL: @fmsubs(
+// CHECK:         [[F_ADDR:%.*]] = alloca float, align 4
+// CHECK-NEXT:    store float [[F:%.*]], float* [[F_ADDR]], align 4
+// CHECK-NEXT:    [[TMP0:%.*]] = load float, float* [[F_ADDR]], align 4
+// CHECK-NEXT:    [[TMP1:%.*]] = load float, float* [[F_ADDR]], align 4
+// CHECK-NEXT:    [[TMP2:%.*]] = load float, float* [[F_ADDR]], align 4
+// CHECK-NEXT:    [[TMP3:%.*]] = call float @llvm.ppc.fmsubs(float [[TMP0]], float [[TMP1]], float [[TMP2]])
+// CHECK-NEXT:    ret float [[TMP3]]
+//
+float fmsubs (float f) {
+  return __fmsubs (f, f, f);
+}
+
+// CHECK-LABEL: @fnmadd(
+// CHECK:         [[D_ADDR:%.*]] = alloca double, align 8
+// CHECK-NEXT:    store double [[D:%.*]], double* [[D_ADDR]], align 8
+// CHECK-NEXT:    [[TMP0:%.*]] = load double, double* [[D_ADDR]], align 8
+// CHECK-NEXT:    [[TMP1:%.*]] = load double, double* [[D_ADDR]], align 8
+// CHECK-NEXT:    [[TMP2:%.*]] = load double, double* [[D_ADDR]], align 8
+// CHECK-NEXT:    [[TMP3:%.*]] = call double @llvm.ppc.fnmadd(double [[TMP0]], double [[TMP1]], double [[TMP2]])
+// CHECK-NEXT:    ret double [[TMP3]]
+//
+double fnmadd (double d) {
+  return __fnmadd (d, d, d);
+}
+
+// CHECK-LABEL: @fnmadds(
+// CHECK:         [[F_ADDR:%.*]] = alloca float, align 4
+// CHECK-NEXT:    store float [[F:%.*]], float* [[F_ADDR]], align 4
+// CHECK-NEXT:    [[TMP0:%.*]] = load float, float* [[F_ADDR]], align 4
+// CHECK-NEXT:    [[TMP1:%.*]] = load float, float* [[F_ADDR]], align 4
+// CHECK-NEXT:    [[TMP2:%.*]] = load float, float* [[F_ADDR]], align 4
+// CHECK-NEXT:    [[TMP3:%.*]] = call float @llvm.ppc.fnmadds(float [[TMP0]], float [[TMP1]], float [[TMP2]])
+// CHECK-NEXT:    ret float [[TMP3]]
+//
+float fnmadds (float f) {
+  return __fnmadds (f, f, f);
+}
+
+// CHECK-LABEL: @fnmsub(
+// CHECK:         [[D_ADDR:%.*]] = alloca double, align 8
+// CHECK-NEXT:    store double [[D:%.*]], double* [[D_ADDR]], align 8
+// CHECK-NEXT:    [[TMP0:%.*]] = load double, double* [[D_ADDR]], align 8
+// CHECK-NEXT:    [[TMP1:%.*]] = load double, double* [[D_ADDR]], align 8
+// CHECK-NEXT:    [[TMP2:%.*]] = load double, double* [[D_ADDR]], align 8
+// CHECK-NEXT:    [[TMP3:%.*]] = call double @llvm.ppc.fnmsub(double [[TMP0]], double [[TMP1]], double [[TMP2]])
+// CHECK-NEXT:    ret double [[TMP3]]
+//
+double fnmsub (double d) {
+  return __fnmsub (d, d, d);
+}
+
+// CHECK-LABEL: @fnmsubs(
+// CHECK:         [[F_ADDR:%.*]] = alloca float, align 4
+// CHECK-NEXT:    store float [[F:%.*]], float* [[F_ADDR]], align 4
+// CHECK-NEXT:    [[TMP0:%.*]] = load float, float* [[F_ADDR]], align 4
+// CHECK-NEXT:    [[TMP1:%.*]] = load float, float* [[F_ADDR]], align 4
+// CHECK-NEXT:    [[TMP2:%.*]] = load float, float* [[F_ADDR]], align 4
+// CHECK-NEXT:    [[TMP3:%.*]] = call float @llvm.ppc.fnmsubs(float [[TMP0]], float [[TMP1]], float [[TMP2]])
+// CHECK-NEXT:    ret float [[TMP3]]
+//
+float fnmsubs (float f) {
+  return __fnmsubs (f, f, f);
+}
+
+// CHECK-LABEL: @fre(
+// CHECK:         [[D_ADDR:%.*]] = alloca double, align 8
+// CHECK-NEXT:    store double [[D:%.*]], double* [[D_ADDR]], align 8
+// CHECK-NEXT:    [[TMP0:%.*]] = load double, double* [[D_ADDR]], align 8
+// CHECK-NEXT:    [[TMP1:%.*]] = call double @llvm.ppc.fre(double [[TMP0]])
+// CHECK-NEXT:    ret double [[TMP1]]
+//
+double fre (double d) {
+  return __fre (d);
+}
+
+// CHECK-LABEL: @fres(
+// CHECK:         [[F_ADDR:%.*]] = alloca float, align 4
+// CHECK-NEXT:    store float [[F:%.*]], float* [[F_ADDR]], align 4
+// CHECK-NEXT:    [[TMP0:%.*]] = load float, float* [[F_ADDR]], align 4
+// CHECK-NEXT:    [[TMP1:%.*]] = call float @llvm.ppc.fres(float [[TMP0]])
+// CHECK-NEXT:    ret float [[TMP1]]
+//
+float fres (float f) {
+  return __fres (f);
+}

clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c

 
 unsigned long long test_builtin_ppc_maddld_unsigned() {
   // CHECK-LABEL:    @test_builtin_ppc_maddld_unsigned(
   // CHECK:          %3 = call i64 @llvm.ppc.maddld(i64 %0, i64 %1, i64 %2)
   // CHECK-32-ERROR: error: this builtin is only available on 64-bit targets
   // CHECK-NONPWR9-ERR:  error: this builtin is only valid on POWER9 or later CPUs
   return __builtin_ppc_maddld(ull, ull, ull);
 }
+
+unsigned long long extract_sig (double d) {
+// CHECK-LABEL: @extract_sig(
+// CHECK:       [[TMP1:%.*]] = call i64 @llvm.ppc.extract.sig(double %0)
+// CHECK-NEXT:  ret i64 [[TMP1]]
+//
+// CHECK-32-ERROR: error: this builtin is only available on 64-bit targets
+// CHECK-NONPWR9-ERR:  error: this builtin is only valid on POWER9 or later CPUs
+  return __extract_sig (d);
+}
+
+double insert_exp (double d, unsigned long long ull) {
+// CHECK-LABEL: @insert_exp(
+// CHECK:       [[TMP2:%.*]] = call double @llvm.ppc.insert.exp(double %0, i64 %1)
+// CHECK-NEXT:    ret double [[TMP2]]
+//
+// CHECK-32-ERROR: error: this builtin is only available on 64-bit targets
+// CHECK-NONPWR9-ERR:  error: this builtin is only valid on POWER9 or later CPUs
+  return __insert_exp (d, ull);
+}

clang/test/CodeGen/builtins-ppc-xlcompat-pwr9.c

 
 int test_builtin_ppc_cmprb() {
   // CHECK-LABEL: @test_builtin_ppc_cmprb(
   // CHECK:       %2 = call i32 @llvm.ppc.cmprb(i32 0, i32 %0, i32 %1)
   // CHECK:       %5 = call i32 @llvm.ppc.cmprb(i32 1, i32 %3, i32 %4)
   // CHECK-NONPWR9-ERR:  error: this builtin is only valid on POWER9 or later CPUs
   return __builtin_ppc_cmprb(0, ui, ui) + __builtin_ppc_cmprb(1, ui, ui);
 }
+
+unsigned int extract_exp (double d) {
+// CHECK-LABEL: @extract_exp
+// CHECK:    [[TMP1:%.*]] = call i32 @llvm.ppc.extract.exp(double %0)
+// CHECK-NEXT:    ret i32 [[TMP1]]
+// CHECK-NONPWR9-ERR:  error: this builtin is only valid on POWER9 or later CPUs
+  return __extract_exp (d);
+}

llvm/include/llvm/IR/IntrinsicsPowerPC.td

// FIXME: __icbt is only valid for pwr8 and up.
   def int_ppc_mulhd
       : GCCBuiltin<"__builtin_ppc_mulhd">,
         Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
   def int_ppc_mulhdu
       : GCCBuiltin<"__builtin_ppc_mulhdu">,
         Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
   def int_ppc_mulhw
       : GCCBuiltin<"__builtin_ppc_mulhw">,
         Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
   def int_ppc_mulhwu
       : GCCBuiltin<"__builtin_ppc_mulhwu">,
         Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
   def int_ppc_maddhd
       : GCCBuiltin<"__builtin_ppc_maddhd">,
         Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
   def int_ppc_maddhdu
       : GCCBuiltin<"__builtin_ppc_maddhdu">,
def int_ppc_store2r
       : GCCBuiltin<"__builtin_ppc_store2r">,
         Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty], [IntrWriteMem]>;
   def int_ppc_store4r
       : GCCBuiltin<"__builtin_ppc_store4r">,
         Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty], [IntrWriteMem]>;
   def int_ppc_store8r
       : GCCBuiltin<"__builtin_ppc_store8r">,
         Intrinsic<[], [llvm_i64_ty, llvm_ptr_ty], [IntrWriteMem]>;
+  def int_ppc_insert_exp
+      : GCCBuiltin<"__builtin_ppc_insert_exp">,
+        Intrinsic <[llvm_double_ty], [llvm_double_ty, llvm_i64_ty],
+                   [IntrNoMem]>;
+  def int_ppc_extract_exp
+      : GCCBuiltin<"__builtin_ppc_extract_exp">,
+        Intrinsic <[llvm_i32_ty], [llvm_double_ty], [IntrNoMem]>;
+  def int_ppc_extract_sig
+      : GCCBuiltin<"__builtin_ppc_extract_sig">,
+        Intrinsic <[llvm_i64_ty], [llvm_double_ty], [IntrNoMem]>;
+  def int_ppc_mtfsb0
+      : GCCBuiltin<"__builtin_ppc_mtfsb0">,
+        Intrinsic <[], [llvm_i32_ty],
+                   [IntrNoMem, IntrHasSideEffects, ImmArg<ArgIndex<0>>]>;
+  def int_ppc_mtfsb1
+      : GCCBuiltin<"__builtin_ppc_mtfsb1">,
+        Intrinsic <[], [llvm_i32_ty],
+                   [IntrNoMem, IntrHasSideEffects, ImmArg<ArgIndex<0>>]>;
+  def int_ppc_mtfsf
+      : GCCBuiltin<"__builtin_ppc_mtfsf">,
+        Intrinsic <[], [llvm_i32_ty, llvm_i32_ty],
+                   [IntrNoMem, IntrHasSideEffects, ImmArg<ArgIndex<0>>]>;
+  def int_ppc_mtfsfi
+      : GCCBuiltin<"__builtin_ppc_mtfsfi">,
+        Intrinsic <[], [llvm_i32_ty, llvm_i32_ty],
+                   [IntrNoMem, IntrHasSideEffects,
+                    ImmArg<ArgIndex<0>>,ImmArg<ArgIndex<1>>]>;
+  def int_ppc_fmsub
+      : GCCBuiltin<"__builtin_ppc_fmsub">,
+        Intrinsic <[llvm_double_ty],
+                   [llvm_double_ty, llvm_double_ty, llvm_double_ty],
+                   [IntrNoMem]>;
+  def int_ppc_fmsubs
+      : GCCBuiltin<"__builtin_ppc_fmsubs">,
+        Intrinsic <[llvm_float_ty],
+                   [llvm_float_ty, llvm_float_ty, llvm_float_ty],
+                   [IntrNoMem]>;
+  def int_ppc_fnmadd
+      : GCCBuiltin<"__builtin_ppc_fnmadd">,
+        Intrinsic <[llvm_double_ty],
+                   [llvm_double_ty, llvm_double_ty, llvm_double_ty],
+                   [IntrNoMem]>;
+  def int_ppc_fnmadds
+      : GCCBuiltin<"__builtin_ppc_fnmadds">,
+        Intrinsic <[llvm_float_ty],
+                   [llvm_float_ty, llvm_float_ty, llvm_float_ty],
+                   [IntrNoMem]>;
+  def int_ppc_fnmsub
+      : GCCBuiltin<"__builtin_ppc_fnmsub">,
+        Intrinsic <[llvm_double_ty],
+                   [llvm_double_ty, llvm_double_ty, llvm_double_ty],
+                   [IntrNoMem]>;
+  def int_ppc_fnmsubs
+      : GCCBuiltin<"__builtin_ppc_fnmsubs">,
+        Intrinsic <[llvm_float_ty],
+                   [llvm_float_ty, llvm_float_ty, llvm_float_ty],
+                   [IntrNoMem]>;
+  def int_ppc_fre
+      : GCCBuiltin<"__builtin_ppc_fre">,
+        Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
+  def int_ppc_fres
+      : GCCBuiltin<"__builtin_ppc_fres">,
+        Intrinsic <[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
 }
 
 //===----------------------------------------------------------------------===//
 // PowerPC Atomic Intrinsic Definitions.
 let TargetPrefix = "ppc" in {
   class AtomicRMW128Intrinsic
     : Intrinsic<[llvm_i64_ty, llvm_i64_ty],
                 [llvm_ptr_ty, llvm_i64_ty, llvm_i64_ty],

llvm/lib/Target/PowerPC/PPCInstrInfo.td

def FADDrtz: PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
                       [(set f64:$FRT, (PPCany_faddrtz f64:$FRA, f64:$FRB))]>;
 }
 
 // The above pseudo gets expanded to make use of the following instructions
 // to manipulate FPSCR.  Note that FPSCR is not modeled at the DAG level.
 
 // When FM is 30/31, we are setting the 62/63 bit of FPSCR, the implicit-def
 // RM should be set.
+let hasSideEffects = 1 in {
 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
-                      "mtfsb0 $FM", IIC_IntMTFSB0, []>,
+                      "mtfsb0 $FM", IIC_IntMTFSB0,
+                      [(int_ppc_mtfsb0 timm:$FM)]>,
              PPC970_DGroup_Single, PPC970_Unit_FPU;
 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
-                      "mtfsb1 $FM", IIC_IntMTFSB0, []>,
+                      "mtfsb1 $FM", IIC_IntMTFSB0,
+                      [(int_ppc_mtfsb1 timm:$FM)]>,
              PPC970_DGroup_Single, PPC970_Unit_FPU;
+}
 
 let Defs = [RM] in {
   let isCodeGenOnly = 1 in
   def MTFSFb  : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
                         "mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
                 PPC970_DGroup_Single, PPC970_Unit_FPU;
 }
 let Uses = [RM] in {

 
 // FCOPYSIGN's operand types need not agree.
 def : Pat<(fcopysign f64:$frB, f32:$frA),
           (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
 def : Pat<(fcopysign f32:$frB, f64:$frA),
           (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
 }
 
+// XL Compat intrinsics.
+def : Pat<(int_ppc_fmsub f64:$A, f64:$B, f64:$C), (FMSUB $A, $B, $C)>;
+def : Pat<(int_ppc_fmsubs f32:$A, f32:$B, f32:$C), (FMSUBS $A, $B, $C)>;
+def : Pat<(int_ppc_fnmsub f64:$A, f64:$B, f64:$C), (FNMSUB $A, $B, $C)>;
+def : Pat<(int_ppc_fnmsubs f32:$A, f32:$B, f32:$C), (FNMSUBS $A, $B, $C)>;
+def : Pat<(int_ppc_fnmadd f64:$A, f64:$B, f64:$C), (FNMADD $A, $B, $C)>;
+def : Pat<(int_ppc_fnmadds f32:$A, f32:$B, f32:$C), (FNMADDS $A, $B, $C)>;
+def : Pat<(int_ppc_fre f64:$A), (FRE $A)>;
+def : Pat<(int_ppc_fres f32:$A), (FRES $A)>;
+
 include "PPCInstrAltivec.td"
 include "PPCInstrSPE.td"
 include "PPCInstr64Bit.td"
 include "PPCInstrVSX.td"
 include "PPCInstrHTM.td"
 
 def crnot : OutPatFrag<(ops node:$in),
                        (CRNOR $in, $in)>;

llvm/lib/Target/PowerPC/PPCInstrVSX.td

let Predicates = [HasVSX, HasP9Vector] in {
   def XSRQPXP  : Z23_VT5_R1_VB5_RMC2_EX1<63, 37, 0, "xsrqpxp", []>;
   }
 
   //===--------------------------------------------------------------------===//
   // Insert/Extract Instructions
 
   // Insert Exponent DP/QP
   // XT NOTE: XT.dword[1] = 0xUUUU_UUUU_UUUU_UUUU
-  // FIXME: Setting the hasSideEffects flag here to match current behaviour.
-  let hasSideEffects = 1 in {
-    def XSIEXPDP : XX1Form <60, 918, (outs vsrc:$XT), (ins g8rc:$rA, g8rc:$rB),
-                            "xsiexpdp $XT, $rA, $rB", IIC_VecFP, []>;
+  // FIXME: Setting the hasSideEffects flag here to match current behaviour.
+  let hasSideEffects = 1 in {
     // vB NOTE: only vB.dword[0] is used, that's why we don't use
     //          X_VT5_VA5_VB5 form
     def XSIEXPQP : XForm_18<63, 868, (outs vrrc:$vT), (ins vrrc:$vA, vsfrc:$vB),
                             "xsiexpqp $vT, $vA, $vB", IIC_VecFP, []>;
   }
 
   // Extract Exponent/Significand DP/QP
-  // FIXME: Setting the hasSideEffects flag here to match current behaviour.
-  let hasSideEffects = 1 in {
-    def XSXEXPDP : XX2_RT5_XO5_XB6<60,  0, 347, "xsxexpdp", []>;
-    def XSXSIGDP : XX2_RT5_XO5_XB6<60,  1, 347, "xsxsigdp", []>;
 
+  // FIXME: Setting the hasSideEffects flag here to match current behaviour.
+  let hasSideEffects = 1 in {
     def XSXEXPQP : X_VT5_XO5_VB5  <63,  2, 804, "xsxexpqp", []>;
     def XSXSIGQP : X_VT5_XO5_VB5  <63, 18, 804, "xsxsigqp", []>;
   }
 
   // Vector Insert Word
   // XB NOTE: Only XB.dword[1] is used, but we use vsrc on XB.
   def XXINSERTW   :
     XX2_RD6_UIM5_RS6<60, 181, (outs vsrc:$XT),

 let AddedComplexity = 0 in {
 def : Pat<(v2i64 (PPCvcmp_rec v2i64:$vA, v2i64:$vB, 967)),
           (VCMPGTUB_rec DblwdCmp.MRGSGT, (v2i64 (XXLXORz)))>;
 def : Pat<(v2i64 (PPCvcmp_rec v2i64:$vA, v2i64:$vB, 711)),
           (VCMPGTUB_rec DblwdCmp.MRGUGT, (v2i64 (XXLXORz)))>;
 def : Pat<(v2i64 (PPCvcmp_rec v2i64:$vA, v2i64:$vB, 199)),
           (VCMPGTUB_rec DblwdCmp.MRGEQ, (v2i64 (XXLXORz)))>;
 } // AddedComplexity = 0
+
+// XL Compat builtins.
+def : Pat<(int_ppc_fmsub f64:$A, f64:$B, f64:$C), (XSMSUBMDP $A, $B, $C)>;
+def : Pat<(int_ppc_fnmsub f64:$A, f64:$B, f64:$C), (XSNMSUBMDP $A, $B, $C)>;
+def : Pat<(int_ppc_fnmadd f64:$A, f64:$B, f64:$C), (XSNMADDMDP $A, $B, $C)>;
+def : Pat<(int_ppc_fre f64:$A), (XSREDP $A)>;
 } // HasVSX
 
 // Any big endian VSX subtarget.
 let Predicates = [HasVSX, IsBigEndian] in {
 def : Pat<(v2f64 (scalar_to_vector f64:$A)),
           (v2f64 (SUBREG_TO_REG (i64 1), $A, sub_64))>;
 
 def : Pat<(f64 (extractelt v2f64:$S, 0)),

 def : Pat<(v1i128 (bitconvert (v16i8 immAllOnesV))),
           (v1i128 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
 def : Pat<(v2i64 (bitconvert (v16i8 immAllOnesV))),
           (v2i64 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
 def : Pat<(v8i16 (bitconvert (v16i8 immAllOnesV))),
           (v8i16 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
 def : Pat<(v16i8 (bitconvert (v16i8 immAllOnesV))),
           (v16i8 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
+
+// XL Compat builtins.
+def : Pat<(int_ppc_fmsubs f32:$A, f32:$B, f32:$C), (XSMSUBMSP $A, $B, $C)>;
+def : Pat<(int_ppc_fnmsubs f32:$A, f32:$B, f32:$C), (XSNMSUBMSP $A, $B, $C)>;
+def : Pat<(int_ppc_fnmadds f32:$A, f32:$B, f32:$C), (XSNMADDMSP $A, $B, $C)>;
+def : Pat<(int_ppc_fres f32:$A), (XSRESP $A)>;
+def : Pat<(i32 (int_ppc_extract_exp f64:$A)),
+          (EXTRACT_SUBREG (XSXEXPDP (COPY_TO_REGCLASS $A, VSFRC)), sub_32)>;
+def : Pat<(int_ppc_extract_sig f64:$A),
+          (XSXSIGDP (COPY_TO_REGCLASS $A, VSFRC))>;
+def : Pat<(f64 (int_ppc_insert_exp f64:$A, i64:$B)),
+          (COPY_TO_REGCLASS (XSIEXPDP (COPY_TO_REGCLASS $A, G8RC), $B), F8RC)>;
 } // HasVSX, HasP8Vector
 
 // Any big endian Power8 VSX subtarget.
 let Predicates = [HasVSX, HasP8Vector, IsBigEndian] in {
 def : Pat<DWToSPExtractConv.El0SS1,
           (f32 (XSCVSXDSP (COPY_TO_REGCLASS $S1, VSFRC)))>;
 def : Pat<DWToSPExtractConv.El1SS1,
           (f32 (XSCVSXDSP (COPY_TO_REGCLASS (XXPERMDI $S1, $S1, 2), VSFRC)))>;

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s |\
+; RUN:   FileCheck %s --check-prefix=CHECK-PWR8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr7 \
+; RUN:   < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix -mcpu=pwr8 < %s |\
+; RUN:   FileCheck %s --check-prefix=CHECK-PWR8
+
+define dso_local void @mtfsb0() {
+; CHECK-PWR8-LABEL: mtfsb0:
+; CHECK-PWR8:       # %bb.0: # %entry
+; CHECK-PWR8-NEXT:    mtfsb0 10
+; CHECK-PWR8-NEXT:    blr
+;
+; CHECK-NOVSX-LABEL: mtfsb0:
+; CHECK-NOVSX:       # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:    mtfsb0 10
+; CHECK-NOVSX-NEXT:    blr
+;
+; CHECK-PWR7-LABEL: mtfsb0:
+; CHECK-PWR7:       # %bb.0: # %entry
+; CHECK-PWR7-NEXT:    mtfsb0 10
+; CHECK-PWR7-NEXT:    blr
+entry:
+  tail call void @llvm.ppc.mtfsb0(i32 10)
+  ret void
+}
+
+declare void @llvm.ppc.mtfsb0(i32 immarg) #1
+
+define dso_local void @mtfsb1() {
+; CHECK-PWR8-LABEL: mtfsb1:
+; CHECK-PWR8:       # %bb.0: # %entry
+; CHECK-PWR8-NEXT:    mtfsb1 0
+; CHECK-PWR8-NEXT:    blr
+;
+; CHECK-NOVSX-LABEL: mtfsb1:
+; CHECK-NOVSX:       # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:    mtfsb1 0
+; CHECK-NOVSX-NEXT:    blr
+;
+; CHECK-PWR7-LABEL: mtfsb1:
+; CHECK-PWR7:       # %bb.0: # %entry
+; CHECK-PWR7-NEXT:    mtfsb1 0
+; CHECK-PWR7-NEXT:    blr
+entry:
+  tail call void @llvm.ppc.mtfsb1(i32 0)
+  ret void
+}
+
+declare void @llvm.ppc.mtfsb1(i32 immarg) #1
+
+define dso_local double @fmsub_t0(double %d, double %d2, double %d3) {
+; CHECK-PWR8-LABEL: fmsub_t0:
+; CHECK-PWR8:       # %bb.0: # %entry
+; CHECK-PWR8-NEXT:    xsmsubmdp 1, 2, 3
+; CHECK-PWR8-NEXT:    blr
+;
+; CHECK-NOVSX-LABEL: fmsub_t0:
+; CHECK-NOVSX:       # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:    fmsub 1, 1, 2, 3
+; CHECK-NOVSX-NEXT:    blr
+;
+; CHECK-PWR7-LABEL: fmsub_t0:
+; CHECK-PWR7:       # %bb.0: # %entry
+; CHECK-PWR7-NEXT:    xsmsubmdp 1, 2, 3
+; CHECK-PWR7-NEXT:    blr
+entry:
+  %0 = tail call double @llvm.ppc.fmsub(double %d, double %d2, double %d3)
+  ret double %0
+}
+
+declare double @llvm.ppc.fmsub(double, double, double)
+
+define dso_local float @fmsubs_t0(float %f, float %f2, float %f3) {
+; CHECK-PWR8-LABEL: fmsubs_t0:
+; CHECK-PWR8:       # %bb.0: # %entry
+; CHECK-PWR8-NEXT:    xsmsubmsp 1, 2, 3
+; CHECK-PWR8-NEXT:    blr
+;
+; CHECK-NOVSX-LABEL: fmsubs_t0:
+; CHECK-NOVSX:       # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:    fmsubs 1, 1, 2, 3
+; CHECK-NOVSX-NEXT:    blr
+;
+; CHECK-PWR7-LABEL: fmsubs_t0:
+; CHECK-PWR7:       # %bb.0: # %entry
+; CHECK-PWR7-NEXT:    fmsubs 1, 1, 2, 3
+; CHECK-PWR7-NEXT:    blr
+entry:
+  %0 = tail call float @llvm.ppc.fmsubs(float %f, float %f2, float %f3)
+  ret float %0
+}
+
+declare float @llvm.ppc.fmsubs(float, float, float)
+
+define dso_local double @fnmadd_t0(double %d, double %d2, double %d3) {
+; CHECK-PWR8-LABEL: fnmadd_t0:
+; CHECK-PWR8:       # %bb.0: # %entry
+; CHECK-PWR8-NEXT:    xsnmaddmdp 1, 2, 3
+; CHECK-PWR8-NEXT:    blr
+;
+; CHECK-NOVSX-LABEL: fnmadd_t0:
+; CHECK-NOVSX:       # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:    fnmadd 1, 1, 2, 3
+; CHECK-NOVSX-NEXT:    blr
+;
+; CHECK-PWR7-LABEL: fnmadd_t0:
+; CHECK-PWR7:       # %bb.0: # %entry
+; CHECK-PWR7-NEXT:    xsnmaddmdp 1, 2, 3
+; CHECK-PWR7-NEXT:    blr
+entry:
+  %0 = tail call double @llvm.ppc.fnmadd(double %d, double %d2, double %d3)
+  ret double %0
+}
+
+declare double @llvm.ppc.fnmadd(double, double, double)
+
+define dso_local float @fnmadds_t0(float %f, float %f2, float %f3) {
+; CHECK-PWR8-LABEL: fnmadds_t0:
+; CHECK-PWR8:       # %bb.0: # %entry
+; CHECK-PWR8-NEXT:    xsnmaddmsp 1, 2, 3
+; CHECK-PWR8-NEXT:    blr
+;
+; CHECK-NOVSX-LABEL: fnmadds_t0:
+; CHECK-NOVSX:       # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:    fnmadds 1, 1, 2, 3
+; CHECK-NOVSX-NEXT:    blr
+;
+; CHECK-PWR7-LABEL: fnmadds_t0:
+; CHECK-PWR7:       # %bb.0: # %entry
+; CHECK-PWR7-NEXT:    fnmadds 1, 1, 2, 3
+; CHECK-PWR7-NEXT:    blr
+entry:
+  %0 = tail call float @llvm.ppc.fnmadds(float %f, float %f2, float %f3)
+  ret float %0
+}
+
+declare float @llvm.ppc.fnmadds(float, float, float)
+
+define dso_local double @fnmsub_t0(double %d, double %d2, double %d3) {
+; CHECK-PWR8-LABEL: fnmsub_t0:
+; CHECK-PWR8:       # %bb.0: # %entry
+; CHECK-PWR8-NEXT:    xsnmsubmdp 1, 2, 3
+; CHECK-PWR8-NEXT:    blr
+;
+; CHECK-NOVSX-LABEL: fnmsub_t0:
+; CHECK-NOVSX:       # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:    fnmsub 1, 1, 2, 3
+; CHECK-NOVSX-NEXT:    blr
+;
+; CHECK-PWR7-LABEL: fnmsub_t0:
+; CHECK-PWR7:       # %bb.0: # %entry
+; CHECK-PWR7-NEXT:    xsnmsubmdp 1, 2, 3
+; CHECK-PWR7-NEXT:    blr
+entry:
+  %0 = tail call double @llvm.ppc.fnmsub(double %d, double %d2, double %d3)
+  ret double %0
+}
+
+declare double @llvm.ppc.fnmsub(double, double, double)
+
+define dso_local float @fnmsubs_t0(float %f, float %f2, float %f3) {
+; CHECK-PWR8-LABEL: fnmsubs_t0:
+; CHECK-PWR8:       # %bb.0: # %entry
+; CHECK-PWR8-NEXT:    xsnmsubmsp 1, 2, 3
+; CHECK-PWR8-NEXT:    blr
+;
+; CHECK-NOVSX-LABEL: fnmsubs_t0:
+; CHECK-NOVSX:       # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:    fnmsubs 1, 1, 2, 3
+; CHECK-NOVSX-NEXT:    blr
+;
+; CHECK-PWR7-LABEL: fnmsubs_t0:
+; CHECK-PWR7:       # %bb.0: # %entry
+; CHECK-PWR7-NEXT:    fnmsubs 1, 1, 2, 3
+; CHECK-PWR7-NEXT:    blr
+entry:
+  %0 = tail call float @llvm.ppc.fnmsubs(float %f, float %f2, float %f3)
+  ret float %0
+}
+
+declare float @llvm.ppc.fnmsubs(float, float, float)
+
+define dso_local double @fre(double %d) {
+; CHECK-PWR8-LABEL: fre:
+; CHECK-PWR8:       # %bb.0: # %entry
+; CHECK-PWR8-NEXT:    xsredp 1, 1
+; CHECK-PWR8-NEXT:    blr
+;
+; CHECK-NOVSX-LABEL: fre:
+; CHECK-NOVSX:       # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:    fre 1, 1
+; CHECK-NOVSX-NEXT:    blr
+;
+; CHECK-PWR7-LABEL: fre:
+; CHECK-PWR7:       # %bb.0: # %entry
+; CHECK-PWR7-NEXT:    xsredp 1, 1
+; CHECK-PWR7-NEXT:    blr
+entry:
+  %0 = tail call double @llvm.ppc.fre(double %d)
+  ret double %0
+}
+
+declare double @llvm.ppc.fre(double)
+
+define dso_local float @fres(float %f) {
+; CHECK-PWR8-LABEL: fres:
+; CHECK-PWR8:       # %bb.0: # %entry
+; CHECK-PWR8-NEXT:    xsresp 1, 1
+; CHECK-PWR8-NEXT:    blr
+;
+; CHECK-NOVSX-LABEL: fres:
+; CHECK-NOVSX:       # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:    fres 1, 1
+; CHECK-NOVSX-NEXT:    blr
+;
+; CHECK-PWR7-LABEL: fres:
+; CHECK-PWR7:       # %bb.0: # %entry
+; CHECK-PWR7-NEXT:    fres 1, 1
+; CHECK-PWR7-NEXT:    blr
+entry:
+  %0 = tail call float @llvm.ppc.fres(float %f)
+  ret float %0
+}
+
+declare float @llvm.ppc.fres(float)

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+define dso_local i64 @extract_sig(double %d) {
+; CHECK-LABEL: extract_sig:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xsxsigdp 3, 1
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call i64 @llvm.ppc.extract.sig(double %d)
+  ret i64 %0
+}
+declare i64 @llvm.ppc.extract.sig(double)
+
+define dso_local double @insert_exp(double %d, i64 %ull) {
+; CHECK-LABEL: insert_exp:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mffprd 3, 1
+; CHECK-NEXT:    xsiexpdp 1, 3, 4
+; CHECK-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call double @llvm.ppc.insert.exp(double %d, i64 %ull)
+  ret double %0
+}
+declare double @llvm.ppc.insert.exp(double, i64)

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-32BIT
+
+define dso_local zeroext i32 @extract_exp(double %d) {
+; CHECK-LABEL: extract_exp:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xsxexpdp 3, 1
+; CHECK-NEXT:    clrldi 3, 3, 32
+; CHECK-NEXT:    blr
+;
+; CHECK-32BIT-LABEL: extract_exp:
+; CHECK-32BIT:       # %bb.0: # %entry
+; CHECK-32BIT-NEXT:    xsxexpdp 3, 1
+; CHECK-32BIT-NEXT:    # kill: def $r3 killed $r3 killed $x3
+; CHECK-32BIT-NEXT:    blr
+entry:
+  %0 = tail call i32 @llvm.ppc.extract.exp(double %d)
+  ret i32 %0
+}
+declare i32 @llvm.ppc.extract.exp(double)