Page MenuHomePhabricator

shchenz (ChenZheng)
User

Projects

User does not belong to any projects.

User Details

User Since
Jun 28 2018, 9:57 PM (185 w, 6 d)

Recent Activity

Today

shchenz accepted D117006: [PowerPC] Add custom lowering for SELECT_CC fp128 using xsmaxcqp.

LGTM. Please hold on some days for other reviewers. Thanks for adding this support.

Thu, Jan 20, 12:53 AM · Restricted Project
shchenz accepted D117459: [PowerPC] Change CTR clobber estimation for 128-bit floating types.

Thanks for fixing this. LGTM

Thu, Jan 20, 12:50 AM · Restricted Project

Yesterday

shchenz added inline comments to D117642: [XCOFF][llvm-objdump] ignore the default .text symbol during dissembling..
Wed, Jan 19, 9:11 PM · Restricted Project
shchenz added inline comments to D117459: [PowerPC] Change CTR clobber estimation for 128-bit floating types.
Wed, Jan 19, 7:41 PM · Restricted Project
shchenz added inline comments to D117006: [PowerPC] Add custom lowering for SELECT_CC fp128 using xsmaxcqp.
Wed, Jan 19, 12:35 AM · Restricted Project

Mon, Jan 17

shchenz added inline comments to D117006: [PowerPC] Add custom lowering for SELECT_CC fp128 using xsmaxcqp.
Mon, Jan 17, 6:50 PM · Restricted Project

Sun, Jan 16

shchenz added a comment to D115419: [PowerPC] Allow absolute expressions in relocations.

Maybe I am misunderstanding the relocation fixups and DQ form instructions, if so, please ignore my comments. : )

Sun, Jan 16, 6:09 PM · Restricted Project

Wed, Jan 12

shchenz added a comment to D109676: [HardwareLoops] put +1 for loop count before zero extension.

gentle ping

Wed, Jan 12, 5:35 PM · Restricted Project

Mon, Jan 10

shchenz added inline comments to D116801: [PowerPC] Avoid perfect shuffle when mask has multiple uses.
Mon, Jan 10, 12:31 AM · Restricted Project

Sun, Jan 9

shchenz added inline comments to D116801: [PowerPC] Avoid perfect shuffle when mask has multiple uses.
Sun, Jan 9, 6:44 PM · Restricted Project
shchenz committed rG2c46ca96e242: [PowerPC] fast isel can lower intrinsics call on AIX. (authored by shchenz).
[PowerPC] fast isel can lower intrinsics call on AIX.
Sun, Jan 9, 6:32 PM
shchenz closed D114778: [XCOFF][FastISel] make fast isel can lower general intrinsics.
Sun, Jan 9, 6:32 PM · Restricted Project

Thu, Jan 6

shchenz added a comment to D114778: [XCOFF][FastISel] make fast isel can lower general intrinsics.

nit: Rename debug-label-fast-isel.ll to debug-label-fast-isel-xcoff.ll?

Thu, Jan 6, 10:42 PM · Restricted Project
shchenz updated the diff for D114778: [XCOFF][FastISel] make fast isel can lower general intrinsics.

comment address

Thu, Jan 6, 10:32 PM · Restricted Project
shchenz added a comment to D114778: [XCOFF][FastISel] make fast isel can lower general intrinsics.

gentle ping

Thu, Jan 6, 5:22 PM · Restricted Project
shchenz accepted D113049: [AIX] Disable tests that fail because of no 64-bit XCOFF object file support.

LGTM. Thanks for the explanation.

Thu, Jan 6, 5:21 PM · Restricted Project, Restricted Project

Wed, Dec 29

shchenz added a comment to D113741: [RFC][DwarfDebug][AsmPrinter] Support emitting function-local declaration for a lexical block.

If to apply all the reverted patches (D114705, D113741, and D113743) I believe you should see a correct DWARF compiled for your example.

Wed, Dec 29, 1:24 AM · debug-info, Restricted Project

Mon, Dec 27

shchenz added a comment to D113741: [RFC][DwarfDebug][AsmPrinter] Support emitting function-local declaration for a lexical block.

To continue with a more accurate fix, one example for your reference. (The behavior is changed with/without this reversion):

Sorry, I'm not following this comment ^ (& the rest) - could you rephrase if there's a question/concern you have I can help clarify/describe/work with you on?

Mon, Dec 27, 10:09 PM · debug-info, Restricted Project

Sun, Dec 26

shchenz added a comment to D113741: [RFC][DwarfDebug][AsmPrinter] Support emitting function-local declaration for a lexical block.

To continue with a more accurate fix, one example for your reference. (The behavior is changed with/without this reversion):

int main() {      // <====== function scope
  int x = 3;
  int num = 6;
  printf("%d\n", x);
  if (num) {   // <======= lexical block 1
    static int x = 45;
    printf("%d\n", x);
    if (x) {   // <======= lexical block 2
      int x = 145;
      printf("%d\n", x);
    }
  }
  return 0;
}
Sun, Dec 26, 7:02 PM · debug-info, Restricted Project

Wed, Dec 22

shchenz added a comment to D113049: [AIX] Disable tests that fail because of no 64-bit XCOFF object file support.

Look almost good! Thanks for doing this.

Wed, Dec 22, 7:39 PM · Restricted Project, Restricted Project

Tue, Dec 21

shchenz added inline comments to D113049: [AIX] Disable tests that fail because of no 64-bit XCOFF object file support.
Tue, Dec 21, 6:38 PM · Restricted Project, Restricted Project

Dec 21 2021

shchenz added a comment to D116053: [MachineSink] Allow sinking of constant or ignorable physreg uses.

I am not sure I can prove to myself this is legal. For example you are sinking a def into a loop with divergent condition and this def is used after the loop. Can this happen?

Dec 21 2021, 1:24 AM · Restricted Project
shchenz added a comment to D114778: [XCOFF][FastISel] make fast isel can lower general intrinsics.

gentle ping

Dec 21 2021, 12:53 AM · Restricted Project
shchenz updated the diff for D114419: [XCOFF] change default program code csect alignment to 32.

rebase for D116092

Dec 21 2021, 12:52 AM · Restricted Project
shchenz requested review of D116092: [XCOFF] make sure same number of paddings are added.
Dec 21 2021, 12:47 AM · Restricted Project

Dec 18 2021

shchenz added inline comments to D114419: [XCOFF] change default program code csect alignment to 32.
Dec 18 2021, 5:03 AM · Restricted Project

Dec 17 2021

shchenz added a comment to D115503: [DebugInfo][Clang] record the access flag for class/struct/union types..

Ah, cool - could you include % growth on those rows

Thanks, I edited the table in the previous comment.

(hmm, .debug_line and .debug_str shouldn't be changing in size with this change, right? If you use the same clang version to test the two cases (if you're using a bootstrap with/without the patch applied, then the patch changes itself would show up as changes here))

Hmm...it's a little strange. I got these data by:

  1. pull a base llvm-project branch --> source codes
  2. build the source --> clang1
  3. build the codes after applying the patch --> clang2
  4. use clang1 to build the source (no patch) --> clang-before
  5. use clang2 to build the source (no patch) --> clang-after
  6. compare the size between clang-before and clang-after

I reproduced these steps on another base branch, and saw similar changes (i.e. .debug_line and .debug_str changed in size)...
But I think the change is so small as to be negligible?

& if you could include this table in the commit message, that'd be great!

(can you commit this yourself, or do you need someone to do that for you?)

I will include this table when committing, thanks!

Dec 17 2021, 2:41 AM · Restricted Project, Restricted Project
shchenz accepted D114492: [PowerPC][llvm-objdump] enable --symbolize-operands for PowerPC ELF/XCOFF..

LGTM. Thanks for adding this support.

Dec 17 2021, 12:43 AM · Restricted Project

Dec 16 2021

shchenz added a comment to D114419: [XCOFF] change default program code csect alignment to 32.

Can you try adding a testcase for Os or Oz to see what happens? I suspect that this change might override the pref alignment settings in Lowering.

There is a case test_minsize() in file test/CodeGen/PowerPC/code-align.ll, there is no change for that case, so I think there should be no change for the loop alignment after this patch?

Dec 16 2021, 11:15 PM · Restricted Project

Dec 15 2021

shchenz added inline comments to D113049: [AIX] Disable tests that fail because of no 64-bit XCOFF object file support.
Dec 15 2021, 5:20 PM · Restricted Project, Restricted Project
shchenz added inline comments to D114492: [PowerPC][llvm-objdump] enable --symbolize-operands for PowerPC ELF/XCOFF..
Dec 15 2021, 5:06 AM · Restricted Project

Dec 14 2021

shchenz accepted D115695: Adapt test to be compatible with AIX.

LGTM. Thanks

Dec 14 2021, 4:14 PM · Restricted Project

Dec 13 2021

shchenz added inline comments to D115695: Adapt test to be compatible with AIX.
Dec 13 2021, 8:45 PM · Restricted Project
shchenz committed rG062d9b7d43a7: [LegalizeVectorOps] code refactor for LegalizeOp; NFC (authored by shchenz).
[LegalizeVectorOps] code refactor for LegalizeOp; NFC
Dec 13 2021, 7:59 PM
shchenz closed D115636: [LegalizeVectorOps] code refactor for LegalizeOp - NFC.
Dec 13 2021, 7:59 PM · Restricted Project
shchenz added a comment to D114419: [XCOFF] change default program code csect alignment to 32.

Do we have any data about the *size* change due to alignment change? especially for code with lots of small functions, like perlbench?

Dec 13 2021, 6:25 PM · Restricted Project
shchenz updated the diff for D115636: [LegalizeVectorOps] code refactor for LegalizeOp - NFC.

address comments

Dec 13 2021, 4:40 PM · Restricted Project
shchenz committed rG8c107bee702f: [LegalizeVectorOps] fix a typo (authored by shchenz).
[LegalizeVectorOps] fix a typo
Dec 13 2021, 4:31 PM
shchenz closed D115637: [LegalizeVectorOps] typo fix .
Dec 13 2021, 4:31 PM · Restricted Project
shchenz updated the summary of D115636: [LegalizeVectorOps] code refactor for LegalizeOp - NFC.
Dec 13 2021, 7:09 AM · Restricted Project
shchenz requested review of D115637: [LegalizeVectorOps] typo fix .
Dec 13 2021, 7:09 AM · Restricted Project
shchenz requested review of D115636: [LegalizeVectorOps] code refactor for LegalizeOp - NFC.
Dec 13 2021, 7:06 AM · Restricted Project

Dec 12 2021

shchenz accepted D115503: [DebugInfo][Clang] record the access flag for class/struct/union types..

Thanks for fixing this. LGTM. Please wait for @dblaikie comments.

Dec 12 2021, 11:23 PM · Restricted Project, Restricted Project
shchenz added inline comments to D115503: [DebugInfo][Clang] record the access flag for class/struct/union types..
Dec 12 2021, 11:19 PM · Restricted Project, Restricted Project
shchenz added inline comments to D115503: [DebugInfo][Clang] record the access flag for class/struct/union types..
Dec 12 2021, 7:32 PM · Restricted Project, Restricted Project
shchenz added a comment to D114778: [XCOFF][FastISel] make fast isel can lower general intrinsics.

gentle ping

Dec 12 2021, 6:29 PM · Restricted Project
shchenz added a comment to D114419: [XCOFF] change default program code csect alignment to 32.

gentle ping

Dec 12 2021, 6:24 PM · Restricted Project

Dec 8 2021

shchenz added inline comments to D114492: [PowerPC][llvm-objdump] enable --symbolize-operands for PowerPC ELF/XCOFF..
Dec 8 2021, 7:04 PM · Restricted Project
shchenz committed rGd0022a7250fa: [PowerPC] copy byval parameter to caller's stack when needed (authored by shchenz).
[PowerPC] copy byval parameter to caller's stack when needed
Dec 8 2021, 5:01 PM
shchenz closed D111485: [Powerpc] store byval parameter to parameter save area when needed.
Dec 8 2021, 5:01 PM · Restricted Project

Dec 7 2021

shchenz committed rGc16c99ab03c6: [Powerpc] testcases for D111485; nfc (authored by shchenz).
[Powerpc] testcases for D111485; nfc
Dec 7 2021, 6:23 PM
shchenz added a comment to D111485: [Powerpc] store byval parameter to parameter save area when needed.

LGTM since you have already double checked the compatiblity.

Dec 7 2021, 6:21 PM · Restricted Project
shchenz committed rG63cd1842a7f3: [PowerPC] use lvx + splat directly for aligned splat load (authored by shchenz).
[PowerPC] use lvx + splat directly for aligned splat load
Dec 7 2021, 6:02 PM
shchenz closed D114062: [PowerPC] use lvx + splat directly for aligned splat load.
Dec 7 2021, 6:02 PM · Restricted Project
shchenz added a comment to D114062: [PowerPC] use lvx + splat directly for aligned splat load.

Thanks for your review @nemanjai

Dec 7 2021, 5:45 PM · Restricted Project

Dec 6 2021

shchenz committed rGd0a8f86667b2: [PowerPC][NFC] add cases for D114062 (authored by shchenz).
[PowerPC][NFC] add cases for D114062
Dec 6 2021, 5:12 PM
shchenz added a comment to D111485: [Powerpc] store byval parameter to parameter save area when needed.

I asked for some help from a GCC developer. He told me GCC only copies byval structure bigger than 64 bytes to the parameter save area instead of 8 bytes for ELF64. So now after the change, clang should have the same logic as GCC.

Dec 6 2021, 4:46 PM · Restricted Project

Dec 5 2021

shchenz added a comment to D114778: [XCOFF][FastISel] make fast isel can lower general intrinsics.

gentle ping

Dec 5 2021, 5:52 PM · Restricted Project
shchenz added a comment to D114062: [PowerPC] use lvx + splat directly for aligned splat load.

gentle ping

Dec 5 2021, 5:52 PM · Restricted Project
shchenz added a comment to D114419: [XCOFF] change default program code csect alignment to 32.

gentle ping

Dec 5 2021, 5:52 PM · Restricted Project

Dec 2 2021

shchenz added a comment to D109676: [HardwareLoops] put +1 for loop count before zero extension.

So for this patch, we need to wait for ARM experts find out the solution for the overflow issue when ExitCount type is same with CountType?

Dec 2 2021, 8:01 PM · Restricted Project

Nov 30 2021

shchenz accepted D114434: [NFC][XCOFF] [llvm-readobj] replace binaries with YAMLs (only tests for Symbols).

LGTM too. Thanks for cleaning up.

Nov 30 2021, 10:46 PM · Restricted Project
shchenz added a comment to D114800: [PowerPC] Replace MFVSRLD with MFVSRD when the vector is symmetrical.

Can we fix this at the place where MFVSRLD is generated? (in DAG-ISEL?)

Nov 30 2021, 5:50 PM · Restricted Project
shchenz added inline comments to D112073: [PowerPC] Emit warning when SP is clobbered by asm.
Nov 30 2021, 5:40 PM · Restricted Project, Restricted Project
shchenz added inline comments to D114778: [XCOFF][FastISel] make fast isel can lower general intrinsics.
Nov 30 2021, 5:13 PM · Restricted Project
shchenz updated the diff for D114778: [XCOFF][FastISel] make fast isel can lower general intrinsics.

address comments

Nov 30 2021, 5:13 PM · Restricted Project
shchenz updated the diff for D114778: [XCOFF][FastISel] make fast isel can lower general intrinsics.
Nov 30 2021, 1:02 AM · Restricted Project
shchenz updated the summary of D114778: [XCOFF][FastISel] make fast isel can lower general intrinsics.
Nov 30 2021, 12:57 AM · Restricted Project
shchenz added a comment to D114686: [AIX] XFAIL test missing inlined argument/local variables for the inlined subroutine.

https://reviews.llvm.org/D114778 is created for the root cause, so I think we can abandon this patch now?

Nov 30 2021, 12:56 AM · Restricted Project
shchenz added a comment to D114685: [AIX] XFAIL test missing DBG_LABEL.

https://reviews.llvm.org/D114778 is created for the root cause, so I think we can abandon this patch now?

Nov 30 2021, 12:55 AM · Restricted Project
shchenz requested review of D114778: [XCOFF][FastISel] make fast isel can lower general intrinsics.
Nov 30 2021, 12:55 AM · Restricted Project

Nov 28 2021

shchenz accepted D114685: [AIX] XFAIL test missing DBG_LABEL.

LGTM. Please be aware that we are working on resolving this in fast-isel for 64-bit XCOFF.

Nov 28 2021, 7:22 PM · Restricted Project
shchenz added a comment to D114062: [PowerPC] use lvx + splat directly for aligned splat load.

gentle ping

Nov 28 2021, 5:53 PM · Restricted Project
shchenz added a comment to D111485: [Powerpc] store byval parameter to parameter save area when needed.

gentle ping

Nov 28 2021, 5:52 PM · Restricted Project

Nov 26 2021

shchenz added a comment to D114419: [XCOFF] change default program code csect alignment to 32.

Just out of curiosity, if the csect that contains a function is aligned at 2 bytes, how do we ensure loops within those functions are aligned at 32 bytes?

Nov 26 2021, 4:45 AM · Restricted Project
shchenz updated the diff for D114419: [XCOFF] change default program code csect alignment to 32.
Nov 26 2021, 4:40 AM · Restricted Project

Nov 24 2021

shchenz accepted D114567: [AIX] Disable empty.ll test using unsupported split dwarf.

LGTM. Thanks

Nov 24 2021, 6:42 PM · Restricted Project

Nov 23 2021

shchenz accepted D110616: [Legalizer] Avoid expansion to BR_CC if illegal.

Thanks. LGTM. Please hold on some days in case other reviewers like @craig.topper have further comments.

Nov 23 2021, 9:24 PM · Restricted Project
shchenz added a comment to D114434: [NFC][XCOFF] [llvm-readobj] replace binaries with YAMLs (only tests for Symbols).

A patch like this should be marked with "NFC" in the title

Nov 23 2021, 6:33 PM · Restricted Project
shchenz added inline comments to D112073: [PowerPC] Emit warning when SP is clobbered by asm.
Nov 23 2021, 6:27 AM · Restricted Project, Restricted Project
shchenz added a comment to D113872: [CGP] Handle select instructions relying on the same condition.

If we make the SimplifyCFG pass keep the statically calculated branch weights(if any) for the select instructions, will our case be optimized like expected in the CGP pass? If so, I think letting SimplifyCFG pass keep the branch weights for the select instructions should make more sense. I saw there are some functions like setBranchWeights in SimplifyCFG pass that will update the branch weights, but not sure why it does not work for our case.

Nov 23 2021, 6:07 AM · Restricted Project
shchenz added inline comments to D114361: [MachineCSE] Add an option to enable global CSE.
Nov 23 2021, 5:14 AM · Restricted Project
shchenz requested review of D114419: [XCOFF] change default program code csect alignment to 32.
Nov 23 2021, 1:27 AM · Restricted Project

Nov 22 2021

shchenz added a comment to D114110: [AIX] Mark tests using DWARF version less than 3 as unsupported because XCOFF64 requires DWARF64.

Dumb question, where is the dwarf version specified?

Nov 22 2021, 4:52 PM · Restricted Project
shchenz added inline comments to D80538: [MachineVerifier] Add a new TiedOpsRewritten flag to fix verify two-address constraint error.
Nov 22 2021, 4:42 PM · Restricted Project

Nov 21 2021

shchenz added a comment to D111485: [Powerpc] store byval parameter to parameter save area when needed.

gentle ping

Nov 21 2021, 5:29 PM · Restricted Project

Nov 18 2021

shchenz committed rG9bda9a39800f: [PowerPC] fix typos in comments, NFC (authored by shchenz).
[PowerPC] fix typos in comments, NFC
Nov 18 2021, 12:56 AM

Nov 16 2021

shchenz updated the diff for D114062: [PowerPC] use lvx + splat directly for aligned splat load.

for power 9, use lxsibzx as it has the same latency with lvx but has more useable registers.

Nov 16 2021, 11:53 PM · Restricted Project
shchenz requested review of D114062: [PowerPC] use lvx + splat directly for aligned splat load.
Nov 16 2021, 11:41 PM · Restricted Project

Nov 15 2021

shchenz accepted D112912: [PowerPC] Implement more fusion types for Power10.

LGTM. Thanks

Nov 15 2021, 12:09 AM · Restricted Project

Nov 14 2021

shchenz accepted D113640: [AIX] XFAIL lto-comp-dir.ll for lack of .file directive support.

LGTM.

Nov 14 2021, 7:11 PM · Restricted Project
shchenz committed rGeec9ca622c2d: [PowerPC] guard update form prepare with non-const increment with option (authored by shchenz).
[PowerPC] guard update form prepare with non-const increment with option
Nov 14 2021, 6:18 PM
shchenz closed D113471: [PowerPC] guard update form prepare with non-const increment with option.
Nov 14 2021, 6:18 PM · Restricted Project

Nov 9 2021

shchenz added a comment to D113535: [PowerPC] Add new TableGen backend for instruction mapping table.

This seems like the same/similar semantic with PPCInstPrinter::getMnemonic()?

Nov 9 2021, 6:25 PM · Restricted Project
shchenz requested review of D113471: [PowerPC] guard update form prepare with non-const increment with option.
Nov 9 2021, 2:05 AM · Restricted Project

Nov 8 2021

shchenz accepted D113407: [AIX] XFAIL 2009-03-29-SoftFloatVectorExtract.ll because of no soft float support.
Nov 8 2021, 4:35 PM · Restricted Project
shchenz added inline comments to D113173: [AsmPrinter][ORE] use correct opcode name.
Nov 8 2021, 4:32 PM · Restricted Project

Nov 7 2021

shchenz abandoned D113178: [PowerPC] use right register class for input operand of XXPERMDIs.

NFC patch 7c6f5950f08d41017536575152fb765ba85a09a1 is committed for the required comments.

Nov 7 2021, 6:24 PM · Restricted Project
shchenz committed rG7c6f5950f08d: [PowerPC] comment for different input register classes; nfc (authored by shchenz).
[PowerPC] comment for different input register classes; nfc
Nov 7 2021, 6:23 PM
shchenz committed rG50acbbe3cd19: [AsmPrinter][ORE] use correct opcode name (authored by shchenz).
[AsmPrinter][ORE] use correct opcode name
Nov 7 2021, 5:55 PM