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shchenz (ChenZheng)
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Jun 28 2018, 9:57 PM (133 w, 1 d)

Recent Activity

Yesterday

shchenz added a comment to D94670: [DebugInfo][NFC] add a new DIE type to represent label + offset.

Thanks for your review @MaskRay
Also thanks Hubert for your good comments. @hubert.reinterpretcast

Fri, Jan 15, 4:53 PM · Restricted Project
shchenz added a comment to D94670: [DebugInfo][NFC] add a new DIE type to represent label + offset.

That is quite interesting, why they designed the feature to work that way. Is it recommended to reference debug sections through the label minus the length field size (4 or 12) or they provide some means to simplify the calculation?

Fri, Jan 15, 5:37 AM · Restricted Project
shchenz added a comment to D94668: [debug-info] [NFC] add isa support for MCStreamer.

I'm not quite sure I understand. What's the issue between xcoff and emission here? Does it not support subtraction? It's been a while and I can't recall.

-eric

Fri, Jan 15, 4:04 AM · Restricted Project
shchenz added a comment to D94670: [DebugInfo][NFC] add a new DIE type to represent label + offset.

Can you provide a little more detail on the motivation here? Thanks!

-eric

Fri, Jan 15, 3:57 AM · Restricted Project
shchenz added a comment to D94668: [debug-info] [NFC] add isa support for MCStreamer.

Added Eric as the owner of debug info.

Fri, Jan 15, 2:03 AM · Restricted Project

Thu, Jan 14

shchenz added inline comments to D94670: [DebugInfo][NFC] add a new DIE type to represent label + offset.
Thu, Jan 14, 9:44 PM · Restricted Project
shchenz updated the diff for D94670: [DebugInfo][NFC] add a new DIE type to represent label + offset.

fix according to comments:
1: unchanged the Offset type
2: fix Lint warnings

Thu, Jan 14, 9:44 PM · Restricted Project
shchenz requested review of D94670: [DebugInfo][NFC] add a new DIE type to represent label + offset.
Thu, Jan 14, 4:12 AM · Restricted Project
shchenz added reviewers for D94668: [debug-info] [NFC] add isa support for MCStreamer: hubert.reinterpretcast, jasonliu.
Thu, Jan 14, 3:50 AM · Restricted Project
shchenz requested review of D94668: [debug-info] [NFC] add isa support for MCStreamer.
Thu, Jan 14, 3:46 AM · Restricted Project

Mon, Jan 11

shchenz added a comment to D92069: [NFC] [TargetRegisterInfo] add one use check to lookThruCopyLike..

gentle ping

Mon, Jan 11, 4:30 PM · Restricted Project

Mon, Jan 4

shchenz added a comment to D92069: [NFC] [TargetRegisterInfo] add one use check to lookThruCopyLike..

gentle ping

Mon, Jan 4, 6:14 PM · Restricted Project
shchenz added a comment to D92071: [PowerPC] support register pressure reduction in machine combiner..

Appreciate your review @jsji . Could you please help to have a look at this patch's patent https://reviews.llvm.org/D92069. Thanks again.

Mon, Jan 4, 6:04 PM · Restricted Project

Wed, Dec 30

shchenz added inline comments to D92071: [PowerPC] support register pressure reduction in machine combiner..
Wed, Dec 30, 6:08 PM · Restricted Project
shchenz updated the diff for D92071: [PowerPC] support register pressure reduction in machine combiner..

1: set the register pressure factor to 1.5

Wed, Dec 30, 6:07 PM · Restricted Project

Sun, Dec 27

shchenz added a comment to D86864: [MachineSinking] sink more profitable loads.

Is it better to have the check before 'if (PDT->dominates(To, BB)) {' ?

Sun, Dec 27, 10:00 PM · Restricted Project
shchenz added a comment to D86864: [MachineSinking] sink more profitable loads.

I can surely do that. But I think the most reasonable solution would be fix the compiling time issue. Since compiling time tests I did before does not expose any regression, your test case must be a little special. Could you find out the special point, for example the function has too many blocks or some/many blocks in the function has too many instructions? Thanks.

I think the increase in compile time is because the function has too many instructions and blocks. The function has Thousands of lines of instructions. Can you add limitation for the number of instructions or the number of blocks so the check for 'store' can end early?

Could you please help to check if the following change can solve your issue?

C
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index 0abdf89..8ca3520 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -79,6 +79,12 @@ static cl::opt<unsigned> SplitEdgeProbabilityThreshold(
         "splitted critical edge"),
     cl::init(40), cl::Hidden);
 
+static cl::opt<unsigned> SinkLoadInstsPerBlockThreshold(
+    "machine-sink-load-instrs-threshold",
+    cl::desc("Do not try to find alias store for a load if there is a in-path "
+             "block whose instruction number is higher than this threshold."),
+    cl::init(2000), cl::Hidden);
+
 STATISTIC(NumSunk,      "Number of machine instructions sunk");
 STATISTIC(NumSplit,     "Number of critical edges split");
 STATISTIC(NumCoalesces, "Number of copies coalesced");
@@ -1036,6 +1042,12 @@ bool MachineSinking::hasStoreBetween(MachineBasicBlock *From,
     HandledBlocks.insert(BB);
     // To post dominates BB, it must be a path from block From.
     if (PDT->dominates(To, BB)) {
+      // If this BB is too big, stop searching to save compiling time.
+      if (BB->size() > SinkLoadInstsPerBlockThreshold) {
+        HasStoreCache[BlockPair] = true;
+        return true;
+      }
+
       for (MachineInstr &I : *BB) {
         // Treat as alias conservatively for a call or an ordered memory
         // operation.

Unfortunately, this patch doesn't work. I don't think the number of blocks is necessarily related to the number of instructions.
For one function, with your default threshold, The time spent on Machine code sinking is 11.2464s, no obvious difference from before. When set the threshold to 1, the time spent on Machine code sinking reduced 0.6937.
I think it would be better if you can limit the number of MIs.
Anyway, this patch provides us with an option. Thanks for your help.

Sun, Dec 27, 8:26 PM · Restricted Project
shchenz committed rG31c2b93d83f6: [MachineSink] add threshold in machinesink pass to reduce compiling time. (authored by shchenz).
[MachineSink] add threshold in machinesink pass to reduce compiling time.
Sun, Dec 27, 8:25 PM
shchenz added a comment to D86864: [MachineSinking] sink more profitable loads.

I can surely do that. But I think the most reasonable solution would be fix the compiling time issue. Since compiling time tests I did before does not expose any regression, your test case must be a little special. Could you find out the special point, for example the function has too many blocks or some/many blocks in the function has too many instructions? Thanks.

I think the increase in compile time is because the function has too many instructions and blocks. The function has Thousands of lines of instructions. Can you add limitation for the number of instructions or the number of blocks so the check for 'store' can end early?

Sun, Dec 27, 5:26 PM · Restricted Project

Wed, Dec 23

shchenz added a comment to D92071: [PowerPC] support register pressure reduction in machine combiner..

gentle ping

Wed, Dec 23, 4:48 PM · Restricted Project
shchenz updated the diff for D92071: [PowerPC] support register pressure reduction in machine combiner..

fix lint warnings

Wed, Dec 23, 4:48 PM · Restricted Project
shchenz added a comment to D86864: [MachineSinking] sink more profitable loads.

Yes, we have been aware that this patch may introduce compiling time degradations. And as you can see in previous comments, I already tested the compiling time on X86 arch. Sadly, the tested benchmarks don't expose any regressions.

Could you please help to send me your regression function/IR? So I can have a look about how to fix it? Thanks.

I am sorry that I can't provide the case to you directly. I am trying making a small reproduce but encountered some problems.
However, can you adding an option to control it?
Thanks.

Wed, Dec 23, 1:39 AM · Restricted Project

Tue, Dec 22

shchenz added a comment to D86864: [MachineSinking] sink more profitable loads.

Hi, @shchenz. Our several opecncl benchmarks have appeared great compile time regression.
For only one function, the time consume on Machine code sinking pass increased form 6.0711s to 366.5713.
According to your algorithm, this patch will obviously increase the compile time for some cases.

Tue, Dec 22, 6:56 PM · Restricted Project

Mon, Dec 21

shchenz added a comment to D90807: [PowerPC] add has side effect for SAT bit clobber intrinsics/instructions.

Thank you so much for fixing this and I'm sorry I didn't get around to going over it sooner.

Mon, Dec 21, 5:53 PM · Restricted Project
shchenz planned changes to D82709: [MachineLICM] don't always hoist rematerializable instructions.

perf test shows some degradations together with some improvements. Plan change for now to get more tuning.

Mon, Dec 21, 4:36 AM · Restricted Project
shchenz retitled D82709: [MachineLICM] don't always hoist rematerializable instructions from [MachineLICM] [PowerPC] hoisting rematerializable cheap instructions based on register pressure. to [MachineLICM] don't always hoist rematerializable instructions.
Mon, Dec 21, 3:46 AM · Restricted Project
shchenz added a comment to D82709: [MachineLICM] don't always hoist rematerializable instructions.

Since @efriedma has concerns about adding more hook in machineLICM pass, and the RA works as expected(@qcolombet please correct me if you find there is any issue in RA process in above comments), I made a new solution for this issue:
instead of hoisting all remat instructions, we now do:

// For remat instructions which are inside current working loop, we should
// always hoist them.
// For remat instructions which intend to be hoisted to outer parent loop, we
// only hoist non-cheap ones as RA can not pull all remat instructions down to
// inner loop as it will first try to split them in outer loop.
Mon, Dec 21, 3:01 AM · Restricted Project
shchenz updated the diff for D82709: [MachineLICM] don't always hoist rematerializable instructions.
Mon, Dec 21, 2:59 AM · Restricted Project
shchenz added a comment to D82709: [MachineLICM] don't always hoist rematerializable instructions.

@qcolombet @efriedma , sorry for the late response and the long main. I made a summary for this issue.

Mon, Dec 21, 2:54 AM · Restricted Project

Sun, Dec 20

shchenz committed rG564066524ad0: [PowerPC] add has side effect for SAT bit clobber intrinsics/instructions (authored by shchenz).
[PowerPC] add has side effect for SAT bit clobber intrinsics/instructions
Sun, Dec 20, 5:05 PM
shchenz closed D90807: [PowerPC] add has side effect for SAT bit clobber intrinsics/instructions.
Sun, Dec 20, 5:05 PM · Restricted Project
shchenz committed rG4dce7c2e2092: [MachineLICM] delete dead flag if the duplicated def outside of loop is dead. (authored by shchenz).
[MachineLICM] delete dead flag if the duplicated def outside of loop is dead.
Sun, Dec 20, 4:47 PM
shchenz closed D92557: [MachineLICM] delete dead flag if the duplicated def outside of loop is dead..
Sun, Dec 20, 4:47 PM · Restricted Project

Fri, Dec 18

shchenz added inline comments to D92557: [MachineLICM] delete dead flag if the duplicated def outside of loop is dead..
Fri, Dec 18, 4:23 PM · Restricted Project
shchenz updated the diff for D92557: [MachineLICM] delete dead flag if the duplicated def outside of loop is dead..

address @arsenm comments:
1: handle the case when hoisted and dup registers are both dead.

Fri, Dec 18, 4:22 PM · Restricted Project
shchenz updated the diff for D92557: [MachineLICM] delete dead flag if the duplicated def outside of loop is dead..

address @arsenm comments:
1: do not use const_cast
2: add comments for the test point in test case.

Fri, Dec 18, 8:16 AM · Restricted Project
shchenz added inline comments to D92557: [MachineLICM] delete dead flag if the duplicated def outside of loop is dead..
Fri, Dec 18, 7:46 AM · Restricted Project
shchenz updated the diff for D92557: [MachineLICM] delete dead flag if the duplicated def outside of loop is dead..

update the comments and gentle ping

Fri, Dec 18, 1:04 AM · Restricted Project

Dec 17 2020

shchenz added a comment to D93370: [PowerPC] Add new infrastructure to select load/store instructions, update P8/P9 load/store patterns..

I should have said this in my first comments. I like this refactor. I just want to make sure I understand this refactoring more clear^_^. Thanks for your detailed explanation. @nemanjai

Dec 17 2020, 7:10 PM · Restricted Project, Restricted Project

Dec 16 2020

shchenz added inline comments to D92071: [PowerPC] support register pressure reduction in machine combiner..
Dec 16 2020, 11:50 PM · Restricted Project
shchenz updated the diff for D92071: [PowerPC] support register pressure reduction in machine combiner..

update according to @jsji comments

Dec 16 2020, 11:50 PM · Restricted Project
shchenz added inline comments to D89855: [PowerPC] Extend folding RLWINM + RLWINM to post-RA..
Dec 16 2020, 7:08 PM · Restricted Project
shchenz added a comment to D93370: [PowerPC] Add new infrastructure to select load/store instructions, update P8/P9 load/store patterns..

The primary motivation is that the current implementation of selecting load/stores is dependent on the ordering of patterns in TableGen.

Dec 16 2020, 6:39 PM · Restricted Project, Restricted Project
shchenz added a comment to D93370: [PowerPC] Add new infrastructure to select load/store instructions, update P8/P9 load/store patterns..

I think it is better to explicitly give some reasons why we need this big refactoring, in other words, what's the disadvantage/limitation of legacy implementation? Thank you for the big effort.

Dec 16 2020, 4:42 PM · Restricted Project, Restricted Project

Dec 15 2020

shchenz added a comment to D93336: [PowerPC][NFC] Cleanup PPCCTRLoopsVerify pass.

Thanks for clean-up. Some minor comments.

Dec 15 2020, 6:45 PM · Restricted Project
shchenz added inline comments to D90807: [PowerPC] add has side effect for SAT bit clobber intrinsics/instructions.
Dec 15 2020, 1:33 AM · Restricted Project
shchenz updated the diff for D90807: [PowerPC] add has side effect for SAT bit clobber intrinsics/instructions.

1: add side effect flag for instructions too.

Dec 15 2020, 1:33 AM · Restricted Project

Dec 13 2020

shchenz added a comment to D92069: [NFC] [TargetRegisterInfo] add one use check to lookThruCopyLike..

gentle ping...

Dec 13 2020, 9:06 PM · Restricted Project
shchenz added a comment to D92068: [MachineCombiner] [NFC]Add MustReduceRegisterPressure goal.

Thank you! @spatel

Dec 13 2020, 9:03 PM · Restricted Project
shchenz committed rG4830d458dd0d: [MachineCombiner][NFC] Add MustReduceRegisterPressure goal (authored by shchenz).
[MachineCombiner][NFC] Add MustReduceRegisterPressure goal
Dec 13 2020, 9:03 PM
shchenz closed D92068: [MachineCombiner] [NFC]Add MustReduceRegisterPressure goal.
Dec 13 2020, 9:03 PM · Restricted Project

Dec 11 2020

shchenz updated the summary of D92557: [MachineLICM] delete dead flag if the duplicated def outside of loop is dead..
Dec 11 2020, 12:15 AM · Restricted Project

Dec 10 2020

shchenz updated the diff for D92071: [PowerPC] support register pressure reduction in machine combiner..

1: update according to parent patch https://reviews.llvm.org/D92068 changes

Dec 10 2020, 11:40 PM · Restricted Project
shchenz added a comment to D92068: [MachineCombiner] [NFC]Add MustReduceRegisterPressure goal.

If this is NFC now, no objections from me - I just noted minor errors.
So we do not need LiveIntervals analysis at all now to reduce pressure, or that will be dealt with separately?

Dec 10 2020, 11:36 PM · Restricted Project
shchenz updated the diff for D92068: [MachineCombiner] [NFC]Add MustReduceRegisterPressure goal.

1: address @spatel comments

Dec 10 2020, 11:28 PM · Restricted Project
shchenz updated the diff for D92071: [PowerPC] support register pressure reduction in machine combiner..

1: don't require LiveIntervals analysis pass to estimate register pressure.

Dec 10 2020, 3:58 AM · Restricted Project
shchenz added a comment to D92068: [MachineCombiner] [NFC]Add MustReduceRegisterPressure goal.

Hi @spatel @lebedev.ri , I changed the patch not requiring LiveIntervals pass. Now this patch is NFC.

Dec 10 2020, 3:55 AM · Restricted Project
shchenz updated the diff for D92068: [MachineCombiner] [NFC]Add MustReduceRegisterPressure goal.

1: don't require LiveIntervals analysis
2: revert the test case change as now this should be NFC

Dec 10 2020, 3:52 AM · Restricted Project

Dec 9 2020

shchenz added a comment to D90807: [PowerPC] add has side effect for SAT bit clobber intrinsics/instructions.

gentle ping...

Dec 9 2020, 9:26 PM · Restricted Project
shchenz added a comment to D92557: [MachineLICM] delete dead flag if the duplicated def outside of loop is dead..

gentle ping...

Dec 9 2020, 9:24 PM · Restricted Project

Dec 8 2020

shchenz committed rG66a03d10220a: [PowerPC] prepare more dq form for P10 pair load/store (authored by shchenz).
[PowerPC] prepare more dq form for P10 pair load/store
Dec 8 2020, 6:10 PM
shchenz closed D92393: [PowerPC] prepare more dq form for P10 pair load/store.
Dec 8 2020, 6:09 PM · Restricted Project

Dec 7 2020

shchenz added a comment to D92068: [MachineCombiner] [NFC]Add MustReduceRegisterPressure goal.

Thanks for your comments @spatel @lebedev.ri

Dec 7 2020, 2:41 AM · Restricted Project

Dec 6 2020

shchenz updated the summary of D92393: [PowerPC] prepare more dq form for P10 pair load/store.
Dec 6 2020, 11:36 PM · Restricted Project
shchenz updated the diff for D92393: [PowerPC] prepare more dq form for P10 pair load/store.

1: fix comments

Dec 6 2020, 11:35 PM · Restricted Project

Dec 4 2020

shchenz added a comment to D92068: [MachineCombiner] [NFC]Add MustReduceRegisterPressure goal.

@spatel Very much appreciate your comments. It is a good start for this patch to move on.

Dec 4 2020, 12:49 AM · Restricted Project

Dec 3 2020

shchenz added a comment to D90807: [PowerPC] add has side effect for SAT bit clobber intrinsics/instructions.

gentle ping

Dec 3 2020, 4:31 AM · Restricted Project
shchenz updated the diff for D92069: [NFC] [TargetRegisterInfo] add one use check to lookThruCopyLike..

lint warning fix

Dec 3 2020, 2:12 AM · Restricted Project
shchenz updated the summary of D92068: [MachineCombiner] [NFC]Add MustReduceRegisterPressure goal.
Dec 3 2020, 2:07 AM · Restricted Project
shchenz updated the diff for D92068: [MachineCombiner] [NFC]Add MustReduceRegisterPressure goal.

1: fix lint warning messages
2: fix x86 CodeGen/X86/coalescer-dce.ll verify error after liveintervals introduced in machine combiner pass

Dec 3 2020, 2:06 AM · Restricted Project
shchenz requested review of D92557: [MachineLICM] delete dead flag if the duplicated def outside of loop is dead..
Dec 3 2020, 2:03 AM · Restricted Project

Dec 1 2020

shchenz committed rG3cb7d6245249: [LSR][NFC] don't collect chains when isNumRegsMajorCostOfLSR is false. (authored by shchenz).
[LSR][NFC] don't collect chains when isNumRegsMajorCostOfLSR is false.
Dec 1 2020, 7:30 PM
shchenz closed D92159: [LSR][NFC] don't collect chains when isNumRegsMajorCostOfLSR is false.
Dec 1 2020, 7:30 PM · Restricted Project
shchenz committed rG95d6042dd440: [NFC][PowerPC] code refactor: split IsReassociable to fma and add. (authored by shchenz).
[NFC][PowerPC] code refactor: split IsReassociable to fma and add.
Dec 1 2020, 6:19 PM
shchenz closed D92070: [PowerPC] [NFC] code refactor: split IsReassociable to fma and add. .
Dec 1 2020, 6:19 PM · Restricted Project
shchenz added a comment to D92070: [PowerPC] [NFC] code refactor: split IsReassociable to fma and add. .

thanks for your review, I will update the lint warning in the commit

Dec 1 2020, 6:18 PM · Restricted Project
shchenz added a comment to D90131: [PowerPC] Add folding patterns for rlwinm + andi_rec..

This is more clear than the previous version. Some implementation comments.

Dec 1 2020, 5:49 PM · Restricted Project
shchenz updated the summary of D92393: [PowerPC] prepare more dq form for P10 pair load/store.
Dec 1 2020, 7:43 AM · Restricted Project
shchenz updated the summary of D92393: [PowerPC] prepare more dq form for P10 pair load/store.
Dec 1 2020, 7:35 AM · Restricted Project
shchenz requested review of D92393: [PowerPC] prepare more dq form for P10 pair load/store.
Dec 1 2020, 7:27 AM · Restricted Project

Nov 26 2020

shchenz edited reviewers for D92068: [MachineCombiner] [NFC]Add MustReduceRegisterPressure goal, added: Restricted Project, efriedma; removed: eli.friedman.
Nov 26 2020, 9:46 PM · Restricted Project
shchenz added a reviewer for D92159: [LSR][NFC] don't collect chains when isNumRegsMajorCostOfLSR is false: Restricted Project.
Nov 26 2020, 9:45 PM · Restricted Project
shchenz added a comment to D90807: [PowerPC] add has side effect for SAT bit clobber intrinsics/instructions.

gentle ping

Nov 26 2020, 2:48 AM · Restricted Project
shchenz updated subscribers of D92159: [LSR][NFC] don't collect chains when isNumRegsMajorCostOfLSR is false.
Nov 26 2020, 2:48 AM · Restricted Project
shchenz requested review of D92159: [LSR][NFC] don't collect chains when isNumRegsMajorCostOfLSR is false.
Nov 26 2020, 1:42 AM · Restricted Project

Nov 24 2020

shchenz updated the summary of D92069: [NFC] [TargetRegisterInfo] add one use check to lookThruCopyLike..
Nov 24 2020, 8:04 PM · Restricted Project
shchenz updated the summary of D92068: [MachineCombiner] [NFC]Add MustReduceRegisterPressure goal.
Nov 24 2020, 8:01 PM · Restricted Project
shchenz updated the summary of D92071: [PowerPC] support register pressure reduction in machine combiner..
Nov 24 2020, 7:59 PM · Restricted Project
shchenz requested review of D92071: [PowerPC] support register pressure reduction in machine combiner..
Nov 24 2020, 7:58 PM · Restricted Project
shchenz requested review of D92070: [PowerPC] [NFC] code refactor: split IsReassociable to fma and add. .
Nov 24 2020, 7:48 PM · Restricted Project
shchenz requested review of D92069: [NFC] [TargetRegisterInfo] add one use check to lookThruCopyLike..
Nov 24 2020, 7:44 PM · Restricted Project
shchenz requested review of D92068: [MachineCombiner] [NFC]Add MustReduceRegisterPressure goal.
Nov 24 2020, 7:40 PM · Restricted Project

Nov 19 2020

shchenz accepted D89855: [PowerPC] Extend folding RLWINM + RLWINM to post-RA..

LGTM. Thanks for the new fix.

Nov 19 2020, 11:12 PM · Restricted Project

Nov 18 2020

shchenz added a comment to D91279: [PowerPC] DForm instructions should be preferred when using zero register.

After a discussion with the group I would like to correct what I said in the previous post.
There already is a plan to do this in ISel in a different patch. The reason we also want to do this optimization here is to try to catch situations where this pattern is not known in ISel and only appears after other optimizations later on. Ideally we do not want to have any situations where the XForm exists in the final binary and having this final check in the PreEmitPeephole should ensure that. Basically, we also want to do this check here to find anything that ISel may have missed.

Nov 18 2020, 5:29 PM · Restricted Project, Restricted Project, Restricted Project

Nov 17 2020

shchenz added a comment to D89855: [PowerPC] Extend folding RLWINM + RLWINM to post-RA..

I saw some testcases are removed compared with your committed version. Is there any reason?

Every specific folding patterns with different masks have been tested in llvm/test/CodeGen/PowerPC/fold-rlwinm.mir
This patch didn't change the patterns, so I supposed it would be clearer to remove some redundant test cases.
Do you think they should be added back?

Nov 17 2020, 4:45 AM · Restricted Project
shchenz added a comment to D89855: [PowerPC] Extend folding RLWINM + RLWINM to post-RA..

I saw some testcases are removed compared with your committed version. Is there any reason?

Nov 17 2020, 1:03 AM · Restricted Project

Nov 15 2020

shchenz added a comment to D90807: [PowerPC] add has side effect for SAT bit clobber intrinsics/instructions.

ping

Nov 15 2020, 4:29 PM · Restricted Project

Nov 11 2020

shchenz added a comment to D91279: [PowerPC] DForm instructions should be preferred when using zero register.

Using dform with offset 0 can save one register r0/X0, this is benefit for register allocation? But adding it in PPCPreEmitPeephole pass which is after register allocation will make the benefit gone.
Maybe we need to do it before register allocation? For example at the place where the x-form with zero register is generated.

Nov 11 2020, 5:14 PM · Restricted Project, Restricted Project, Restricted Project
shchenz committed rG09e34048bf7e: [SelectionDAG] fminnum should be a binary operator (authored by shchenz).
[SelectionDAG] fminnum should be a binary operator
Nov 11 2020, 12:42 AM
shchenz closed D91163: [SelectionDAG] fminnum should be a binary operator.
Nov 11 2020, 12:41 AM · Restricted Project