[PowerPC, test] Fix use of undef FileCheck var

[thopre]

Summary

Commit 6ad3d05b681b36f6ecc98523257d154053e4116d disables the definition
of CSR that a follow-up CHECK-NOT directive depends on. This commit
replaces the undefined CSR variable use by the regex used to define it.

[thopre]

Disable directive since it actually fails with current fix

llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll

682

This CHECK-NOT is way too generic. For instance here it matches align 4 in the .p2align 4 assembly. What are PowerPC's CSR?

Even the following (which enforce the first non whitespace to not be a dot and register to have a least 2 digits) fails:

CHECK-NOT: {{^ [a-z] [0-9][0-9]}}

due to addis 10, 2, .LC3@toc@ha in the function body.

[nemanjai]

Looks like when the original test was disabled, this was just omitted. Thanks for fixing it.

llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll

 ; Store of callee-save register saved by shrink wrapping
 ; FIXME: Test disabled: Improved scheduling needs no spills/reloads any longer!
 ; CHECKXX: std [[CSR:[0-9]+]], -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill
 ;
 ; Reload of callee-save register
 ; CHECKXX: ld [[CSR]], -[[STACK_OFFSET]](1) # 8-byte Folded Reload
 ;
 ; Ensure no subsequent uses of callee-save register before end of function
-; CHECK-NOT: {{[a-z]+}} [[CSR]]
+; CHECKXX-NOT: {{[a-z]+}} [[CSR]]
 ; CHECK: blr
 define signext i32 @transpose() {
 entry:
   %0 = load i32, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @columns, i64 0, i64 1), align 4
   %shl.i = shl i32 %0, 7
   %1 = load i32, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @columns, i64 0, i64 2), align 4
   %or.i = or i32 %shl.i, %1
   %shl1.i = shl i32 %or.i, 7