[X86][AMX] Hoist ldtilecfg

[pengfei]

Summary

The previous code calculated the first ldtilecfg by dominating all AMX registers' def. This may result in the ldtilecfg being inserted into a loop.

This patch try to calculate the nearest point where post dominats all shapes of AMX registers.

[pengfei]

Since D98845 is landed. I'd like to do the ldtilecfg hoist together with this patch. WIP.

[pengfei]

Implement ldtilecfg hoist.

[pengfei]

Minor fix.

[pengfei]

Fix a bug in calculating HasAMXBeforeCall.

[pengfei]

Minor fix.

[LuoYuanke]

llvm/lib/Target/X86/X86PreTileConfig.cpp

13

Since we change the algorithm, we need to update the pass description.

66

We can initialize at the beginning. Maybe at runOnMachineFunction().

70

In line 68 Pos is size_t, but the input is unsigned. Need to align the type?

85

Better to comment on each condition.

call
here we need to reload tile config.
amx instr

88

Does HasAMXBeforeCall mean amx config register live in MBB?

100

PostDominateAllShapes.

101

This looks to represent the tile register live through MBB in the code. Basically we need to reconfig after last call if the config register live out the MBB.

128

Does HasAMXBeforeCall mean amx tile config register live through the MBB?

137

Maybe rename it as "update(MachineBasicBlock *Pred, MachineBasicBlock *MBB)"

[pengfei]

Address Yuanke and Xiang's comments.

llvm/lib/Target/X86/X86PreTileConfig.cpp

101

Yes, But it's equal to requiring instead of describing tile config register live into MBB.

    +----+
BB0 |Cfg |
    +----+
    /    \
+----+  +----+ 
|Call|  |AMX |
|AMX |  |Call|
+----+  +----+
  BB1     BB2

For example, tilecfg lives out BB0 and lives in BB1 and BB2, but we require it lives in for BB2 only. So,

BB1.NeedTileCfgLiveIn = false;
BB2.NeedTileCfgLiveIn = true;

137

How about MBB and Succ, I'd like to use MBB to respect the current node that is operating.
It's more clear to me if we consider UpdateShapeDominators is more independent with DFSPredsUpdater.

[pengfei]

Minor fix.

[LuoYuanke]

Perhaps we need more comments and more test cases (maybe in a sperate file) to cover those scenario.

llvm/lib/Target/X86/X86PreTileConfig.cpp

113

Add comment to explain why the loop is needed, and how to find a position to insert.

115

Add comment to explain why it fails.

117

If possible, better add a test case for it.

118

Better to split the function into 2 function. One is isAMXInstruction(), the other is collectShapeInfo().

129

Is it possible that LastShape is null?

137

Better to add comments to say shape is defined in Succ, so the pred won't postdominate the shape.

139

Here need comments to explain why the except is needed.

[pengfei]

Address Yuanke's comments.

llvm/lib/Target/X86/X86PreTileConfig.cpp

117

Will do later.

129

Yes, compare with MIRef() is allowed. The Pos of it is 0. So the condition is false here.

[pengfei]

Minor fix.
Add a test to verify the sink code.

[pengfei]

llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll

139 ↗

(On Diff #335056)

This seems another bug, I'll investigate it.

[pengfei]

Fix a bug found by test.

[pengfei]

llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll

139 ↗

(On Diff #335056)

Fixed.

[pengfei]

Refactor.

[pengfei]

Fixed the problem when the sink need to be forked. I.e.

     +------+
     |Entry | BB0
     +------+
     /     \
+------+  +------+
|Shape1|  |Shape2| BB2
+------+  +------+
BB1  \       /
     +------+
     | AMX  | BB3
     +------+

If BB1 and BB2 don't have a call, we will try to insert ldtilecfg from BB0.
Since BB0 doesn't dominate all shapes, we will sink the insert point to its successors.
The previous code has limitation that only one of BB0's successors has NeedTileCfgLiveIn = true.
This update fixes the problem without major changes. So I amended it instead of putting into a new revision.

[pengfei]

The algorithm for updating shape postdominate BBs is buggy. For a given ShapeBB, clear all its predecessors flag is not enough since its unreachable BBs are also need to clear.
I have thought out a new method but need major refactor. Stay tuned~

[pengfei]

The algorithm for updating shape postdominate BBs is buggy. For a given ShapeBB, clear all its predecessors flag is not enough since its unreachable BBs are also need to clear.

I have thought out a new method but need major refactor. Stay tuned~

Worked it out.

[pengfei]

A litter format & comments refactor.

[pengfei]

Fix a bug in collectShapeInfo.

[LuoYuanke]

llvm/lib/Target/X86/X86PreTileConfig.cpp

27

Do you mean all tile registers are caller saved?

211

Do we need to recursively handle phi instruction? In below example, record "def shape" instruction?

def shape

\
phi
  \
 phi

292

So we would try to insert ldtilecfg at the entry if there is not shape dependency issue?

325

May update the comments. All shapes are reachable.

336

Can we sink the ldtilecfg in below case? We need insert ldtilecfg to B4.

     Entry
   /         \
 B1         B2
call        call
   \           /
       B3
         |
    B4 shape defs
         |
      AMX

353

Is this semicolon necessary?

[pengfei]

Address Yuanke's comments.

llvm/lib/Target/X86/X86PreTileConfig.cpp

27

No, tile registers are visible to RA, we don't need to restore them ourselves.
We are mainly doing the restore for the shape register in this pass.

211

I don't think so. Each phi will be iterated once. So we just need to peek its latest level and ignore the phi in it.

s1 s2
 \ /
  p1  s3  ...
   \  /   /
    p2   p3
     \  /
      p4

For exampe, if we meet p4 firstly, we find all its defs are phis, we don't do anything. Then, we meet p2 in another iteration and record s3. Then p1 etc. The order doesn't metter, you can see all the real shape defs will be recorded without recursion.

292

Yes. Here the insert points are candidates. We will sink them based on the shape defs. We will insert at the entry if shape dependency satisfies.

336

Yes. We will sink two candidates from B1 anf B2. (If there's no call in B2, the candidates are B1 and Entry) We avoid BB being multi visited. So the second sink will stop at B3. This first sink will cross B3 and reach B4.

353

Good catch. It's residue from previous lambda expression.

[xiangzhangllvm]

llvm/lib/Target/X86/X86PreTileConfig.cpp

60

use C++ comments // between line 54,55

72

use getMI() or directly p->MI is more readable.

77

I suggest use tile operand to judge if a MI is AMX Instruction or not. and spilt the collection of shape to another special function.

206

here may be a constant imm in PHI's incomings.

211

1. MI2->isMoveImmediate() may need to be handled, because the imm may always keep in a register after PHI.

In other wards, if AMX MI use the imm shape, they must use the register after PHI.

2. the recursive PHI case is very rare, we can let it easy, not handle it, there is not correction problem.

[xiangzhangllvm]

llvm/lib/Target/X86/X86PreTileConfig.cpp

324

Not sure the non-bottom BBs in loop can both with "fall through + continue".

[pengfei]

Address Xiang's comments.

llvm/lib/Target/X86/X86PreTileConfig.cpp

77

But we still need to judge if it is PHI. I don't know if there're other exceptions.
We have split it to collectShapeInfo.

206

Seems IR parser will normalize this case, so we don't need to handle it.

211

1. The PostRA pass can handle this case.
2. We have covered this case here.

[pengfei]

llvm/lib/Target/X86/X86PreTileConfig.cpp

324

non-bottom BBs can propagate until the bottom BB.

[xiangzhangllvm]

llvm/lib/Target/X86/X86PreTileConfig.cpp

77

Yes, PHI is exception, the exceptions is very few, more better than list all the AMX opcodes.

211

I don't think "Each phi will be iterated once."

MRI->def_operands(ShapeReg) only contains the shape reg used in AMX MI

s1 s2
 \ /
  p1  s3  ...
   \  /   /
    p2   p3
     \  /
      p4
 then AMX MI use p4 as this shape,

only p4 in def_operands(ShapeReg).

211

But here missed the def shape BB, it is not meet the following logic of use "shapeBBNumber == ShapeReachedCount" to judge the BB is all shape def reachable.

   reg=imm        ...
   /     \         / 
amx          phi
              |
             BB

[pengfei]

llvm/lib/Target/X86/X86PreTileConfig.cpp

211

You are right, I excluded phi at first. I'll refactor for it. Thanks!

[xiangzhangllvm]

llvm/lib/Target/X86/X86PreTileConfig.cpp

355

I am a little puzzle here, The I.MBB is all shape def reachable, but how can we make sure the BBVisitedInfo[I.MBB].LastShape is shape def reachable ? They may be not same BB.

[pengfei]

llvm/lib/Target/X86/X86PreTileConfig.cpp

355

LastShape is the last shape def in a BB. It is only used when its BB is all shape def reachable. I.e. insert ldtilecfg after it. But it can be null if the BB has no shape def, which means we can insert at the begining of the BB.

[pengfei]

Address Xiang's comment.
Iterate all PHIs recursively to find all shapes.

[LuoYuanke]

llvm/lib/Target/X86/X86PreTileConfig.cpp

208

Better to add test case to cover the logic.

322

Better to add test case for it.

[pengfei]

Address Yuanke's comments.

Add test5 for checking shape peek's loop break.
Add test6 for checking shape reachability's loop break.

[pengfei]

Fix a silly bug that uses != in case == and a bug when records shape for phi.

This is found by work with PostRA implementation. This should be found by case amx-ldtilecfg-insert.ll:, but happened to get expected output with these 2 bugs.

[pengfei]

Fix crush when build with -g.

[pengfei]

Add back a condition deleted last time by mistaken.

[LuoYuanke]

llvm/lib/Target/X86/X86PreTileConfig.cpp

82

!MI.isPseudo()?

[xiangzhangllvm]

llvm/lib/Target/X86/X86PreTileConfig.cpp

172

This should be calculated in ShapeNum, for AMX always use reg as its shape after PHI.

[pengfei]

Refactor for excluding DBG_VALUE case.

llvm/lib/Target/X86/X86PreTileConfig.cpp

82

Yeah, I meant to. Surprisingly, we didn't set this flag when we define PseudoI. So the tests happened to pass. :)

172

The immediate value is specially handled in PostRA pass. Since the immediate value is always defined adjoining its use, we cannot calculate it as shape def. Otherwise, they will intersect with other AMX instructions.

[LuoYuanke]

LGTM. Thanks!

llvm/lib/Target/X86/X86PreTileConfig.cpp

 //===-- X86PreTileConfig.cpp - Tile Register Pre-configure-----------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 /// \file Pass to pre-config the shape of AMX register
 /// AMX register need to be configured before use. The shape of AMX register
 /// is encoded in the 1st and 2nd machine operand of AMX pseudo instructions.
 /// The pldtilecfg is to config tile registers. It should dominator all AMX
 /// instructions. The pldtilecfg produce a virtual cfg register and the cfg
 /// register is used by all AMX instructions.
 /// This pass is to find the common dominator of all AMX instructions and
 /// insert the pldtilecfg instruction. Besides the cfg register that pldtilecfg
 /// produces is inserted as the last operand of each AMX instruction. We use
 /// this scheme to model the def-use relationship between AMX config instruction
 /// and other AMX instructions. Below is an example.
 ///
 ///                        ----B1----
 ///                       /           \
 ///                      /             \
 ///                    B2               B3
 ///    %1:tile = PTILELOADDV        %2:tile = PTILELOADDV
 ///
 ///  is transformed to
 ///
 ///                            B1
 ///                 %25:tilecfg = PLDTILECFG
 ///                       /           \
 ///                      /             \
 ///  %1:tile = PTILELOADDV %25    %2:tile = PTILELOADDV %25
 //
 //===----------------------------------------------------------------------===//

 
 #define DEBUG_TYPE "tile-pre-config"
 
 namespace {
 
 class X86PreTileConfig : public MachineFunctionPass {
   // context
   MachineFunction *MF = nullptr;
   const X86Subtarget *ST = nullptr;
   const TargetRegisterInfo *TRI;
   const TargetInstrInfo *TII;
   MachineDominatorTree *DomTree = nullptr;
   MachineRegisterInfo *MRI = nullptr;
 
   MachineInstr *getTileConfigPoint();
 
 public:
   X86PreTileConfig() : MachineFunctionPass(ID) {}
 
   /// Return the pass name.
   StringRef getPassName() const override {
     return "Tile Register Pre-configure";
   }
 
   /// X86PreTileConfig analysis usage.
   void getAnalysisUsage(AnalysisUsage &AU) const override;
 
   /// Perform register allocation.
   bool runOnMachineFunction(MachineFunction &mf) override;
 
   static char ID;
 };
 
 } // end anonymous namespace
 
 char X86PreTileConfig::ID = 0;
 
 INITIALIZE_PASS_BEGIN(X86PreTileConfig, "tilepreconfig",
                       "Tile Register Pre-configure", false, false)
 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
 INITIALIZE_PASS_END(X86PreTileConfig, "tilepreconfig",
                     "Tile Register Pre-configure", false, false)
 
 void X86PreTileConfig::getAnalysisUsage(AnalysisUsage &AU) const {
   AU.setPreservesAll();
   AU.addRequired<MachineDominatorTree>();
   MachineFunctionPass::getAnalysisUsage(AU);
 }
 
 static void buildConfigMI(MachineBasicBlock::iterator MI, int FrameIdx,
                           const TargetInstrInfo *TII, MachineRegisterInfo *MRI,
                           const X86Subtarget *ST) {
   auto *MBB = MI->getParent();
 
   // Zero stack slot.
   if (ST->hasAVX512()) {
     Register Zmm = MRI->createVirtualRegister(&X86::VR512RegClass);
     BuildMI(*MBB, MI, DebugLoc(), TII->get(X86::VPXORDZrr), Zmm)
         .addReg(Zmm, RegState::Undef)
         .addReg(Zmm, RegState::Undef);
     addFrameReference(BuildMI(*MBB, MI, DebugLoc(), TII->get(X86::VMOVUPSZmr)),
                       FrameIdx)
         .addReg(Zmm);
   } else if (ST->hasAVX2()) {
     Register Ymm = MRI->createVirtualRegister(&X86::VR256RegClass);
     BuildMI(*MBB, MI, DebugLoc(), TII->get(X86::VPXORYrr), Ymm)
         .addReg(Ymm, RegState::Undef)
         .addReg(Ymm, RegState::Undef);
     addFrameReference(BuildMI(*MBB, MI, DebugLoc(), TII->get(X86::VMOVUPSYmr)),
                       FrameIdx)
         .addReg(Ymm);
     addFrameReference(BuildMI(*MBB, MI, DebugLoc(), TII->get(X86::VMOVUPSYmr)),
                       FrameIdx, 32)
         .addReg(Ymm);
   } else {
     assert(ST->hasSSE2() && "AMX should assume SSE2 enabled");
     Register Xmm = MRI->createVirtualRegister(&X86::VR128RegClass);
     BuildMI(*MBB, MI, DebugLoc(), TII->get(X86::PXORrr), Xmm)
         .addReg(Xmm, RegState::Undef)
         .addReg(Xmm, RegState::Undef);
     addFrameReference(BuildMI(*MBB, MI, DebugLoc(), TII->get(X86::MOVUPSmr)),
                       FrameIdx)
         .addReg(Xmm);
     addFrameReference(BuildMI(*MBB, MI, DebugLoc(), TII->get(X86::MOVUPSmr)),
                       FrameIdx, 16)
         .addReg(Xmm);
     addFrameReference(BuildMI(*MBB, MI, DebugLoc(), TII->get(X86::MOVUPSmr)),
                       FrameIdx, 32)
         .addReg(Xmm);
     addFrameReference(BuildMI(*MBB, MI, DebugLoc(), TII->get(X86::MOVUPSmr)),
                       FrameIdx, 48)
         .addReg(Xmm);
   }
 
   // build psuedo ldtilecfg
   addFrameReference(BuildMI(*MBB, MI, DebugLoc(), TII->get(X86::LDTILECFG)),
case X86::PTDPBF16PSV:
     MachineOperand &MO2 = const_cast<MachineOperand &>(MI.getOperand(2));
     ShapeT Shape(&MO1, &MO2, MRI);
     return Shape;
   }
 }
 
 MachineInstr *X86PreTileConfig::getTileConfigPoint() {
   DenseMap<Register, ShapeT> PhysShapeInfo;
   MachineBasicBlock *MBB = nullptr;
   DenseSet<const MachineInstr *> MIs;
   for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
     Register VirtReg = Register::index2VirtReg(i);
     if (MRI->reg_nodbg_empty(VirtReg))
       continue;
     const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
     if (RC.getID() != X86::TILERegClassID)
       continue;
for (const MachineOperand &MO : MRI->def_operands(VirtReg)) {
       std::array<MachineOperand *, 2> ShapeMOs = {Shape.getRow(),
                                                   Shape.getCol()};
       for (auto *ShapeMO : ShapeMOs) {
         Register ShapeReg = ShapeMO->getReg();
         for (const MachineOperand &MO : MRI->def_operands(ShapeReg)) {
           const auto *ShapeMI = MO.getParent();
           MIs.insert(ShapeMI);
         }
       }
     }
   }
   if (!MBB)
     return nullptr;
   // This pass is before the pass of eliminating PHI node, so it
   // is in SSA form.
   assert(MRI->isSSA() && "Not SSA form in pre-tile config");
   // Shape def should dominate tile config MBB.
   //    def s           s1    s2
   //     / \             \   /
   //    /   \             \ /
   //  conf               s3=phi(s1,s2)
   //                       |
static bool isAMXInstruction(MachineBasicBlock::iterator MII) {
   case X86::PTDPBUUDV:
   case X86::PTILEZEROV:
   case X86::PTDPBF16PSV:
     return true;
   }
 }
 
 struct BBInfo {
-  bool HasAMX = false;
-  bool HasCallBeforeAMX = false;
-  bool HasAMXBeforeCallInSuccs = false;
+  // Note: This is true only when there's no call instructions between the end
+  // of current BB and the AMX instructions.
+  bool HasAMXInSuccs = false;
+  bool PropagateToPred = false;
   MachineInstr *LastCall = nullptr;
 
   BBInfo() = default;
   BBInfo(SmallSet<MachineInstr *, 8> &CfgNeedInsert, MachineBasicBlock *MBB,
          MachineInstr *MI = nullptr) {
     MachineBasicBlock::iterator MII = MI ? MI->getIterator() : MBB->begin();
     for (auto E = MBB->end(); MII != E; ++MII) {
       if (isAMXInstruction(MII)) {
-        HasAMX = true;
         if (LastCall)
           CfgNeedInsert.insert(LastCall);
+        else
+          PropagateToPred = true;
       } else if (MII->isCall()) {
         LastCall = &*MII;
-        if (!HasAMX)
-          HasCallBeforeAMX = true;
       }
     }
   }
 };
 
 static void reloadTileConfig(MachineInstr *MI, int FI,
                              const TargetInstrInfo *TII,
                              const TargetRegisterInfo *TRI) {
   SmallSet<MachineInstr *, 8> CfgNeedInsert;
   SmallVector<MachineBasicBlock *, 8> WorkList;
   DenseMap<MachineBasicBlock *, BBInfo> BBVisitedInfo;
 
   MachineBasicBlock *MBB = MI->getParent();
   BBVisitedInfo[MBB] = BBInfo(CfgNeedInsert, MBB, MI);
 
+  // The entry BB is special, since it always has a ldtilecfg before AMX
+  // instruction. We don't need to insert another ldtilecfg even if its
+  // predecessor BBs have calls.
+  // FIXME: This case happens only when the entry BB is in a loop. We need to
+  // hoist the first ldtilecfg out of the loop in future.
+  BBVisitedInfo[MBB].PropagateToPred = false;
+
   WorkList.push_back(MBB);
   while (!WorkList.empty()) {
     MBB = WorkList.pop_back_val();
     for (auto I = MBB->succ_begin(), E = MBB->succ_end(); I != E; ++I) {
       if (!BBVisitedInfo.count(*I)) {
         BBVisitedInfo[*I] = BBInfo(CfgNeedInsert, *I);
         WorkList.push_back(*I);
       }
     }
   }
 
   WorkList.clear();
   for (auto I : BBVisitedInfo) {
     WorkList.push_back(I.first);
     while (!WorkList.empty()) {
       MBB = WorkList.pop_back_val();
-      if (BBVisitedInfo[MBB].HasCallBeforeAMX ||
-          (!BBVisitedInfo[MBB].HasAMX &&
-           !BBVisitedInfo[MBB].HasAMXBeforeCallInSuccs))
-        continue;
+      if (BBVisitedInfo[MBB].PropagateToPred) {
         for (auto I = MBB->pred_begin(), E = MBB->pred_end(); I != E; ++I) {
-        if (!BBVisitedInfo.count(*I) ||
-            BBVisitedInfo[*I].HasAMXBeforeCallInSuccs)
+          if (!BBVisitedInfo.count(*I) || BBVisitedInfo[*I].HasAMXInSuccs)
             continue;
-        if (BBVisitedInfo[*I].LastCall)
+          BBVisitedInfo[*I].HasAMXInSuccs = true;
+          if (BBVisitedInfo[*I].LastCall) {
             CfgNeedInsert.insert(BBVisitedInfo[*I].LastCall);
-        BBVisitedInfo[*I].HasAMXBeforeCallInSuccs = true;
+            if (!BBVisitedInfo[*I].PropagateToPred)
+              continue;
+          }
+          BBVisitedInfo[*I].PropagateToPred = true;
           WorkList.push_back(*I);
         }
       }
     }
+  }
 
   for (auto *I : CfgNeedInsert) {
     BitVector UsableRegs(TRI->getNumRegs());
     const TargetRegisterClass *RC = TRI->getRegClass(X86::TILERegClassID);
     for (unsigned J = 0; J < RC->getNumRegs(); J++)
       UsableRegs.set(X86::TMM0 + J);
     for (MachineOperand &CallMO : I->operands()) {
       if (CallMO.isRegMask())
         UsableRegs.clearBitsInMask(CallMO.getRegMask());
     }
     if (!UsableRegs.none())
       addFrameReference(BuildMI(*I->getParent(), ++I->getIterator(), DebugLoc(),
                                 TII->get(X86::LDTILECFG)),
                         FI);
   }
 }
 
 bool X86PreTileConfig::runOnMachineFunction(MachineFunction &mf) {
   MF = &mf;
   MRI = &mf.getRegInfo();
   ST = &mf.getSubtarget<X86Subtarget>();
   TRI = ST->getRegisterInfo();
   TII = mf.getSubtarget().getInstrInfo();
   DomTree = &getAnalysis<MachineDominatorTree>();
 
   MachineInstr *MI = getTileConfigPoint();

llvm/test/CodeGen/X86/AMX/amx-across-func.ll

 ; CHECK-NEXT:    movl %edi, %ebx
 ; CHECK-NEXT:    movl $buf, %r14d
 ; CHECK-NEXT:    movl $32, %r15d
 ; CHECK-NEXT:    movw $8, %bp
 ; CHECK-NEXT:    movl $buf+2048, %r12d
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  .LBB3_1: # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    callq foo
-; CHECK-NEXT:    movb $1, {{[0-9]+}}(%rsp)
-; CHECK-NEXT:    movb $8, {{[0-9]+}}(%rsp)
-; CHECK-NEXT:    movw $8, {{[0-9]+}}(%rsp)
-; CHECK-NEXT:    ldtilecfg {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    testl %ebx, %ebx
 ; CHECK-NEXT:    jle .LBB3_3
 ; CHECK-NEXT:  # %bb.2: # in Loop: Header=BB3_1 Depth=1
 ; CHECK-NEXT:    vpxord %zmm0, %zmm0, %zmm0
 ; CHECK-NEXT:    vmovdqu64 %zmm0, {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    movb $1, {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    movb $8, {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    movw $8, {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    ldtilecfg {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    tileloadd (%r14,%r15), %tmm0
 ; CHECK-NEXT:    movabsq $64, %rax
 ; CHECK-NEXT:    tilestored %tmm0, 1024(%rsp,%rax) # 1024-byte Folded Spill
 ; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    callq foo
 ; CHECK-NEXT:    ldtilecfg {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    movabsq $64, %rax