[RISCV] Don't emit #undef BUILTIN from RISCVVEmitter.cpp

[Jim]

Summary

In BuiltinsRISCV.def, other extension 's intrinsics need to be defined by using macro BUILTIN.
So, it shouldn't undefine macro BUILTIN in the end of declaration for V intrinsics.

[craig.topper]

clang/include/clang/Basic/BuiltinsRISCV.def

20

Can you undef TARGET_BUILTIN here too? I missed that when I added it on line 15.

[Jim]

Address @craig.topper 's comment.

[craig.topper]

LGTM thanks!

clang/include/clang/Basic/BuiltinsRISCV.def

 //===----------------------------------------------------------------------===//
 
 #if defined(BUILTIN) && !defined(TARGET_BUILTIN)
 #   define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS)
 #endif
 
 #include "clang/Basic/riscv_vector_builtins.inc"
 
+#undef BUILTIN
+#undef TARGET_BUILTIN

clang/utils/TableGen/RISCVVEmitter.cpp

void RVVEmitter::createBuiltins(raw_ostream &OS) {
   for (auto &Def : Defs) {
     OS << "RISCVV_BUILTIN(__builtin_rvv_" << Def->getName() << ",\""
        << Def->getBuiltinTypeStr() << "\", ";
     if (!Def->hasSideEffects())
       OS << "\"n\")\n";
     else
       OS << "\"\")\n";
   }
-  OS << "\n#undef BUILTIN\n";
   OS << "#undef RISCVV_BUILTIN\n";
 }
 
 void RVVEmitter::createCodeGen(raw_ostream &OS) {
   std::vector<std::unique_ptr<RVVIntrinsic>> Defs;
   createRVVIntrinsics(Defs);
 
   // The same intrinsic IR name has the same switch body.