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Differential D98550

[AMDGPU] Fix getAlignedAGPRClassID
ClosedPublic

Authored by rampitec on Mar 12 2021, 1:33 PM.

Details

Reviewers
arsenm
Commits
rG315ebe0df33d: [AMDGPU] Fix getAlignedAGPRClassID
Summary

Not all register classes were listed.

Diff Detail

Event Timeline

rampitec created this revision.Mar 12 2021, 1:33 PM
Herald added subscribers: kerbowa, hiraditya, t-tye and 6 others. · View Herald TranscriptMar 12 2021, 1:33 PM
rampitec requested review of this revision.Mar 12 2021, 1:33 PM
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arsenm accepted this revision.Mar 12 2021, 2:12 PM
This revision is now accepted and ready to land.Mar 12 2021, 2:12 PM
This revision was landed with ongoing or failed builds.Mar 12 2021, 2:42 PM
Closed by commit rG315ebe0df33d: [AMDGPU] Fix getAlignedAGPRClassID (authored by rampitec). · Explain Why
This revision was automatically updated to reflect the committed changes.
rampitec added a commit: rG315ebe0df33d: [AMDGPU] Fix getAlignedAGPRClassID.
Harbormaster completed remote builds in B93592: Diff 330358.Mar 12 2021, 3:39 PM

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
10 lines

Diff 330376

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

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static int getAlignedAGPRClassID(unsigned UnalignedClassID) { static int getAlignedAGPRClassID(unsigned UnalignedClassID) {
switch (UnalignedClassID) { switch (UnalignedClassID) {
case AMDGPU::VReg_64RegClassID: case AMDGPU::VReg_64RegClassID:
return AMDGPU::VReg_64_Align2RegClassID; return AMDGPU::VReg_64_Align2RegClassID;
case AMDGPU::VReg_96RegClassID: case AMDGPU::VReg_96RegClassID:
return AMDGPU::VReg_96_Align2RegClassID; return AMDGPU::VReg_96_Align2RegClassID;
case AMDGPU::VReg_128RegClassID: case AMDGPU::VReg_128RegClassID:
return AMDGPU::VReg_128_Align2RegClassID; return AMDGPU::VReg_128_Align2RegClassID;
case AMDGPU::VReg_160RegClassID:
return AMDGPU::VReg_160_Align2RegClassID;
case AMDGPU::VReg_192RegClassID:
return AMDGPU::VReg_192_Align2RegClassID;
case AMDGPU::VReg_256RegClassID: case AMDGPU::VReg_256RegClassID:
return AMDGPU::VReg_256_Align2RegClassID; return AMDGPU::VReg_256_Align2RegClassID;
case AMDGPU::VReg_512RegClassID: case AMDGPU::VReg_512RegClassID:
return AMDGPU::VReg_512_Align2RegClassID; return AMDGPU::VReg_512_Align2RegClassID;
case AMDGPU::VReg_1024RegClassID:
return AMDGPU::VReg_1024_Align2RegClassID;
case AMDGPU::AReg_64RegClassID: case AMDGPU::AReg_64RegClassID:
return AMDGPU::AReg_64_Align2RegClassID; return AMDGPU::AReg_64_Align2RegClassID;
case AMDGPU::AReg_96RegClassID: case AMDGPU::AReg_96RegClassID:
return AMDGPU::AReg_96_Align2RegClassID; return AMDGPU::AReg_96_Align2RegClassID;
case AMDGPU::AReg_128RegClassID: case AMDGPU::AReg_128RegClassID:
return AMDGPU::AReg_128_Align2RegClassID; return AMDGPU::AReg_128_Align2RegClassID;
case AMDGPU::AReg_160RegClassID:
return AMDGPU::AReg_160_Align2RegClassID;
case AMDGPU::AReg_192RegClassID:
return AMDGPU::AReg_192_Align2RegClassID;
case AMDGPU::AReg_256RegClassID: case AMDGPU::AReg_256RegClassID:
return AMDGPU::AReg_256_Align2RegClassID; return AMDGPU::AReg_256_Align2RegClassID;
case AMDGPU::AReg_512RegClassID: case AMDGPU::AReg_512RegClassID:
return AMDGPU::AReg_512_Align2RegClassID; return AMDGPU::AReg_512_Align2RegClassID;
case AMDGPU::AReg_1024RegClassID: case AMDGPU::AReg_1024RegClassID:
return AMDGPU::AReg_1024_Align2RegClassID; return AMDGPU::AReg_1024_Align2RegClassID;
default: default:
return -1; return -1;
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