[AMDGPU] Refactor AMDGPUTargetStreamer::EmitCodeEnd

[foad]

Summary

Refactor and add comments to explain where the magic numbers come from
in terms of the instruction cache line size. NFC.

[rampitec]

LGTM, but could you please add comment that FillSize is in bytes before submitting?

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp

bool AMDGPUTargetAsmStreamer::EmitHSAMetadata(
   OS << '\t' << HSAMD::V3::AssemblerDirectiveEnd << '\n';
   return true;
 }
 
 bool AMDGPUTargetAsmStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) {
   const uint32_t Encoded_s_code_end = 0xbf9f0000;
   const uint32_t Encoded_s_nop = 0xbf800000;
   uint32_t Encoded_pad = Encoded_s_code_end;
-  unsigned FillSize = 48;
+
+  // Instruction cache line size in bytes.
+  const unsigned Log2CacheLineSize = 6;
+  const unsigned CacheLineSize = 1u << Log2CacheLineSize;
+
+  // Extra padding amount in bytes to support prefetch mode 3.
+  unsigned FillSize = 3 * CacheLineSize;
 
   if (AMDGPU::isGFX90A(STI)) {
     Encoded_pad = Encoded_s_nop;
-    FillSize = 256;
+    FillSize = 16 * CacheLineSize;
   }
 
-  OS << "\t.p2alignl 6, " << Encoded_pad << '\n';
-  OS << "\t.fill " << FillSize << ", 4, " << Encoded_pad << '\n';
+  OS << "\t.p2alignl " << Log2CacheLineSize << ", " << Encoded_pad << '\n';
+  OS << "\t.fill " << (FillSize / 4) << ", 4, " << Encoded_pad << '\n';
   return true;
 }
 
 void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(
     const MCSubtargetInfo &STI, StringRef KernelName,
     const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR,
     bool ReserveVCC, bool ReserveFlatScr, bool ReserveXNACK) {
   IsaVersion IVersion = getIsaVersion(STI.getCPU());
EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_AMDGPU_HSA_METADATA,
            });
   return true;
 }
 
 bool AMDGPUTargetELFStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) {
   const uint32_t Encoded_s_code_end = 0xbf9f0000;
   const uint32_t Encoded_s_nop = 0xbf800000;
   uint32_t Encoded_pad = Encoded_s_code_end;
-  unsigned FillSize = 48;
+
+  // Instruction cache line size in bytes.
+  const unsigned Log2CacheLineSize = 6;
+  const unsigned CacheLineSize = 1u << Log2CacheLineSize;
+
+  // Extra padding amount in bytes to support prefetch mode 3.
+  unsigned FillSize = 3 * CacheLineSize;
 
   if (AMDGPU::isGFX90A(STI)) {
     Encoded_pad = Encoded_s_nop;
-    FillSize = 256;
+    FillSize = 16 * CacheLineSize;
   }
 
   MCStreamer &OS = getStreamer();
   OS.PushSection();
-  OS.emitValueToAlignment(64, Encoded_pad, 4);
-  for (unsigned I = 0; I < FillSize; ++I)
+  OS.emitValueToAlignment(CacheLineSize, Encoded_pad, 4);
+  for (unsigned I = 0; I < FillSize; I += 4)
     OS.emitInt32(Encoded_pad);
   OS.PopSection();
   return true;
 }
 
 void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor(
     const MCSubtargetInfo &STI, StringRef KernelName,
     const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR,