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Differential D98133

[SelectionDAG] Add computeKnownBits support for ISD::USUBSAT.
ClosedPublic

Authored by craig.topper on Mar 6 2021, 6:38 PM.

Details

Reviewers
RKSimon
spatel
lebedev.ri
Commits
rG0eb405c3b8e2: [SelectionDAG] Add computeKnownBits support for ISD::USUBSAT.
Summary

The result of ISD::USUBSAT will never be larger than the LHS. We
can use this to put a bound on the number of leading zeros.

Diff Detail

Event Timeline

craig.topper created this revision.Mar 6 2021, 6:38 PM
Herald added subscribers: frasercrmck, ecnelises, kerbowa and 24 others. · View Herald TranscriptMar 6 2021, 6:38 PM
craig.topper requested review of this revision.Mar 6 2021, 6:38 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 6 2021, 6:38 PM
Herald added a subscriber: MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B92526: Diff 328829.Mar 6 2021, 6:39 PM
craig.topper added inline comments.Mar 6 2021, 6:42 PM
llvm/test/CodeGen/X86/usub_sat_plus.ll
135

This is still less than optimal. The movzbl at line 133 is really an any_extend. The other operand of the cmovbl is 0. Had we used a zero_extend at 133 this movzbl wouldn't be needed.

RKSimon accepted this revision.Mar 7 2021, 3:03 AM

LGTM

llvm/test/CodeGen/X86/usub_sat_plus.ll
135

Its sort of related to PR40881 - which complains about a similar thing resulting in ZEXTLOAD vs EXTLOAD.

This revision is now accepted and ready to land.Mar 7 2021, 3:03 AM
This revision was landed with ongoing or failed builds.Mar 7 2021, 9:54 AM
Closed by commit rG0eb405c3b8e2: [SelectionDAG] Add computeKnownBits support for ISD::USUBSAT. (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG0eb405c3b8e2: [SelectionDAG] Add computeKnownBits support for ISD::USUBSAT..

Revision Contents

PathSize
llvm/
lib/
CodeGen/
SelectionDAG/
6 lines
test/
CodeGen/
AMDGPU/
63 lines
ARM/
14 lines
13 lines
RISCV/
62 lines
X86/
7 lines
10 lines
4 lines

Diff 328829

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
//===- SelectionDAG.cpp - Implement the SelectionDAG data structures ------===// //===- SelectionDAG.cpp - Implement the SelectionDAG data structures ------===//
Lint: Lint
Inline Actions

clang-format not found in user's PATH; not linting file.

Lint: Lint: clang-format not found in user's PATH; not linting file.
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
▲ Show 20 Lines • Show All 3,361 Lines • ▼ Show 20 Lines case ISD::BSWAP: {
Known = Known2.byteSwap(); Known = Known2.byteSwap();
break; break;
} }
case ISD::ABS: { case ISD::ABS: {
Known2 = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1); Known2 = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
Known = Known2.abs(); Known = Known2.abs();
break; break;
} }
case ISD::USUBSAT: {
// The result of usubsat will never be larger than the LHS.
Known2 = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
Known.Zero.setHighBits(Known2.countMinLeadingZeros());
break;
}
case ISD::UMIN: { case ISD::UMIN: {
Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1); Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1); Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
Known = KnownBits::umin(Known, Known2); Known = KnownBits::umin(Known, Known2);
break; break;
} }
case ISD::UMAX: { case ISD::UMAX: {
Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1); Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
▲ Show 20 Lines • Show All 6,884 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/usubsat.ll

Show First 20 Lines • Show All 77 Lines • ▼ Show 20 Lines; GFX9-NEXT: s_setpc_b64 s[30:31]
ret i32 %result ret i32 %result
} }
define <2 x i16> @v_usubsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) { define <2 x i16> @v_usubsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX6-LABEL: v_usubsat_v2i16: ; GFX6-LABEL: v_usubsat_v2i16:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s4, 0xffff ; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_and_b32_e32 v4, s4, v2 ; GFX6-NEXT: v_and_b32_e32 v4, s4, v3
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_and_b32_e32 v5, s4, v3
; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 ; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_max_u32_e32 v1, v1, v5 ; GFX6-NEXT: v_max_u32_e32 v1, v1, v4
; GFX6-NEXT: v_max_u32_e32 v0, v0, v4 ; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_max_u32_e32 v0, v0, v2
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v3 ; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v3
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0 ; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX6-NEXT: s_setpc_b64 s[30:31] ; GFX6-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-LABEL: v_usubsat_v2i16: ; GFX8-LABEL: v_usubsat_v2i16:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_sub_u16_sdwa v2, v0, v1 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; GFX8-NEXT: v_sub_u16_sdwa v2, v0, v1 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
Show All 10 Lines; GFX9-NEXT: s_setpc_b64 s[30:31]
ret <2 x i16> %result ret <2 x i16> %result
} }
define <3 x i16> @v_usubsat_v3i16(<3 x i16> %lhs, <3 x i16> %rhs) { define <3 x i16> @v_usubsat_v3i16(<3 x i16> %lhs, <3 x i16> %rhs) {
; GFX6-LABEL: v_usubsat_v3i16: ; GFX6-LABEL: v_usubsat_v3i16:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s4, 0xffff ; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_and_b32_e32 v6, s4, v3 ; GFX6-NEXT: v_and_b32_e32 v6, s4, v4
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_and_b32_e32 v7, s4, v4
; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 ; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_max_u32_e32 v1, v1, v7 ; GFX6-NEXT: v_max_u32_e32 v1, v1, v6
; GFX6-NEXT: v_max_u32_e32 v0, v0, v6 ; GFX6-NEXT: v_and_b32_e32 v3, s4, v3
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_max_u32_e32 v0, v0, v3
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v4
; GFX6-NEXT: v_and_b32_e32 v5, s4, v5 ; GFX6-NEXT: v_and_b32_e32 v5, s4, v5
; GFX6-NEXT: v_and_b32_e32 v2, s4, v2 ; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v4
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v3 ; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
; GFX6-NEXT: v_max_u32_e32 v2, v2, v5
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v2, v5
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_and_b32_e32 v2, s4, v3 ; GFX6-NEXT: v_max_u32_e32 v1, v2, v5
; GFX6-NEXT: v_alignbit_b32 v1, v3, v1, 16 ; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v1, v5
; GFX6-NEXT: v_alignbit_b32 v1, v2, v0, 16
; GFX6-NEXT: s_setpc_b64 s[30:31] ; GFX6-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-LABEL: v_usubsat_v3i16: ; GFX8-LABEL: v_usubsat_v3i16:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_sub_u16_sdwa v4, v0, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; GFX8-NEXT: v_sub_u16_sdwa v4, v0, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX8-NEXT: v_sub_u16_e64 v0, v0, v2 clamp ; GFX8-NEXT: v_sub_u16_e64 v0, v0, v2 clamp
; GFX8-NEXT: v_sub_u16_e64 v1, v1, v3 clamp ; GFX8-NEXT: v_sub_u16_e64 v1, v1, v3 clamp
Show All 10 Lines; GFX9-NEXT: s_setpc_b64 s[30:31]
ret <3 x i16> %result ret <3 x i16> %result
} }
define <2 x float> @v_usubsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) { define <2 x float> @v_usubsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
; GFX6-LABEL: v_usubsat_v4i16: ; GFX6-LABEL: v_usubsat_v4i16:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s4, 0xffff ; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_and_b32_e32 v10, s4, v4 ; GFX6-NEXT: v_and_b32_e32 v9, s4, v5
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_and_b32_e32 v11, s4, v5
; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 ; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_max_u32_e32 v1, v1, v11 ; GFX6-NEXT: v_max_u32_e32 v1, v1, v9
; GFX6-NEXT: v_max_u32_e32 v0, v0, v10 ; GFX6-NEXT: v_and_b32_e32 v4, s4, v4
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_max_u32_e32 v0, v0, v4
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v5 ; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v5
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v4 ; GFX6-NEXT: v_and_b32_e32 v8, s4, v7
; GFX6-NEXT: v_and_b32_e32 v8, s4, v6
; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
; GFX6-NEXT: v_and_b32_e32 v9, s4, v7
; GFX6-NEXT: v_and_b32_e32 v3, s4, v3 ; GFX6-NEXT: v_and_b32_e32 v3, s4, v3
; GFX6-NEXT: v_and_b32_e32 v6, s4, v6
; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_max_u32_e32 v2, v2, v8
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_max_u32_e32 v1, v3, v9 ; GFX6-NEXT: v_max_u32_e32 v1, v2, v6
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v7 ; GFX6-NEXT: v_max_u32_e32 v2, v3, v8
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v6 ; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v7
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v6
; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_or_b32_e32 v1, v2, v1 ; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: s_setpc_b64 s[30:31] ; GFX6-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-LABEL: v_usubsat_v4i16: ; GFX8-LABEL: v_usubsat_v4i16:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_sub_u16_sdwa v4, v0, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; GFX8-NEXT: v_sub_u16_sdwa v4, v0, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX8-NEXT: v_sub_u16_e64 v0, v0, v2 clamp ; GFX8-NEXT: v_sub_u16_e64 v0, v0, v2 clamp
; GFX8-NEXT: v_sub_u16_sdwa v2, v1, v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; GFX8-NEXT: v_sub_u16_sdwa v2, v1, v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
▲ Show 20 Lines • Show All 292 Lines • Show Last 20 Lines

llvm/test/CodeGen/ARM/usub_sat.ll

Show First 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y) nounwind { define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y) nounwind {
; CHECK-T1-LABEL: func16: ; CHECK-T1-LABEL: func16:
; CHECK-T1: @ %bb.0: ; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, r0, r1 ; CHECK-T1-NEXT: subs r0, r0, r1
; CHECK-T1-NEXT: bhs .LBB2_2 ; CHECK-T1-NEXT: bhs .LBB2_2
; CHECK-T1-NEXT: @ %bb.1: ; CHECK-T1-NEXT: @ %bb.1:
; CHECK-T1-NEXT: movs r0, #0 ; CHECK-T1-NEXT: movs r0, #0
; CHECK-T1-NEXT: .LBB2_2: ; CHECK-T1-NEXT: .LBB2_2:
; CHECK-T1-NEXT: uxth r0, r0
; CHECK-T1-NEXT: bx lr ; CHECK-T1-NEXT: bx lr
; ;
; CHECK-T2-LABEL: func16: ; CHECK-T2-LABEL: func16:
; CHECK-T2: @ %bb.0: ; CHECK-T2: @ %bb.0:
; CHECK-T2-NEXT: subs r0, r0, r1 ; CHECK-T2-NEXT: subs r0, r0, r1
; CHECK-T2-NEXT: it lo ; CHECK-T2-NEXT: it lo
; CHECK-T2-NEXT: movlo r0, #0 ; CHECK-T2-NEXT: movlo r0, #0
; CHECK-T2-NEXT: uxth r0, r0
; CHECK-T2-NEXT: bx lr ; CHECK-T2-NEXT: bx lr
; ;
; CHECK-ARM-LABEL: func16: ; CHECK-ARM-LABEL: func16:
; CHECK-ARM: @ %bb.0: ; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: subs r0, r0, r1 ; CHECK-ARM-NEXT: subs r0, r0, r1
; CHECK-ARM-NEXT: movlo r0, #0 ; CHECK-ARM-NEXT: movlo r0, #0
; CHECK-ARM-NEXT: uxth r0, r0
; CHECK-ARM-NEXT: bx lr ; CHECK-ARM-NEXT: bx lr
%tmp = call i16 @llvm.usub.sat.i16(i16 %x, i16 %y) %tmp = call i16 @llvm.usub.sat.i16(i16 %x, i16 %y)
ret i16 %tmp ret i16 %tmp
} }
define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y) nounwind { define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y) nounwind {
; CHECK-T1-LABEL: func8: ; CHECK-T1-LABEL: func8:
; CHECK-T1: @ %bb.0: ; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, r0, r1 ; CHECK-T1-NEXT: subs r0, r0, r1
; CHECK-T1-NEXT: bhs .LBB3_2 ; CHECK-T1-NEXT: bhs .LBB3_2
; CHECK-T1-NEXT: @ %bb.1: ; CHECK-T1-NEXT: @ %bb.1:
; CHECK-T1-NEXT: movs r0, #0 ; CHECK-T1-NEXT: movs r0, #0
; CHECK-T1-NEXT: .LBB3_2: ; CHECK-T1-NEXT: .LBB3_2:
; CHECK-T1-NEXT: uxtb r0, r0
; CHECK-T1-NEXT: bx lr ; CHECK-T1-NEXT: bx lr
; ;
; CHECK-T2-LABEL: func8: ; CHECK-T2-LABEL: func8:
; CHECK-T2: @ %bb.0: ; CHECK-T2: @ %bb.0:
; CHECK-T2-NEXT: subs r0, r0, r1 ; CHECK-T2-NEXT: subs r0, r0, r1
; CHECK-T2-NEXT: it lo ; CHECK-T2-NEXT: it lo
; CHECK-T2-NEXT: movlo r0, #0 ; CHECK-T2-NEXT: movlo r0, #0
; CHECK-T2-NEXT: uxtb r0, r0
; CHECK-T2-NEXT: bx lr ; CHECK-T2-NEXT: bx lr
; ;
; CHECK-ARM-LABEL: func8: ; CHECK-ARM-LABEL: func8:
; CHECK-ARM: @ %bb.0: ; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: subs r0, r0, r1 ; CHECK-ARM-NEXT: subs r0, r0, r1
; CHECK-ARM-NEXT: movlo r0, #0 ; CHECK-ARM-NEXT: movlo r0, #0
; CHECK-ARM-NEXT: uxtb r0, r0
; CHECK-ARM-NEXT: bx lr ; CHECK-ARM-NEXT: bx lr
%tmp = call i8 @llvm.usub.sat.i8(i8 %x, i8 %y) %tmp = call i8 @llvm.usub.sat.i8(i8 %x, i8 %y)
ret i8 %tmp ret i8 %tmp
} }
define zeroext i4 @func3(i4 zeroext %x, i4 zeroext %y) nounwind { define zeroext i4 @func3(i4 zeroext %x, i4 zeroext %y) nounwind {
; CHECK-T1-LABEL: func3: ; CHECK-T1-LABEL: func3:
; CHECK-T1: @ %bb.0: ; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r1, r0, r1 ; CHECK-T1-NEXT: subs r0, r0, r1
; CHECK-T1-NEXT: bhs .LBB4_2 ; CHECK-T1-NEXT: bhs .LBB4_2
; CHECK-T1-NEXT: @ %bb.1: ; CHECK-T1-NEXT: @ %bb.1:
; CHECK-T1-NEXT: movs r1, #0 ; CHECK-T1-NEXT: movs r0, #0
; CHECK-T1-NEXT: .LBB4_2: ; CHECK-T1-NEXT: .LBB4_2:
; CHECK-T1-NEXT: movs r0, #15
; CHECK-T1-NEXT: ands r0, r1
; CHECK-T1-NEXT: bx lr ; CHECK-T1-NEXT: bx lr
; ;
; CHECK-T2-LABEL: func3: ; CHECK-T2-LABEL: func3:
; CHECK-T2: @ %bb.0: ; CHECK-T2: @ %bb.0:
; CHECK-T2-NEXT: subs r0, r0, r1 ; CHECK-T2-NEXT: subs r0, r0, r1
; CHECK-T2-NEXT: it lo ; CHECK-T2-NEXT: it lo
; CHECK-T2-NEXT: movlo r0, #0 ; CHECK-T2-NEXT: movlo r0, #0
; CHECK-T2-NEXT: and r0, r0, #15
; CHECK-T2-NEXT: bx lr ; CHECK-T2-NEXT: bx lr
; ;
; CHECK-ARM-LABEL: func3: ; CHECK-ARM-LABEL: func3:
; CHECK-ARM: @ %bb.0: ; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: subs r0, r0, r1 ; CHECK-ARM-NEXT: subs r0, r0, r1
; CHECK-ARM-NEXT: movlo r0, #0 ; CHECK-ARM-NEXT: movlo r0, #0
; CHECK-ARM-NEXT: and r0, r0, #15
; CHECK-ARM-NEXT: bx lr ; CHECK-ARM-NEXT: bx lr
%tmp = call i4 @llvm.usub.sat.i4(i4 %x, i4 %y) %tmp = call i4 @llvm.usub.sat.i4(i4 %x, i4 %y)
ret i4 %tmp ret i4 %tmp
} }

llvm/test/CodeGen/ARM/usub_sat_plus.ll

Show First 20 Lines • Show All 104 Lines • ▼ Show 20 Lines
; CHECK-T1: @ %bb.0: ; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: muls r1, r2, r1 ; CHECK-T1-NEXT: muls r1, r2, r1
; CHECK-T1-NEXT: uxth r1, r1 ; CHECK-T1-NEXT: uxth r1, r1
; CHECK-T1-NEXT: subs r0, r0, r1 ; CHECK-T1-NEXT: subs r0, r0, r1
; CHECK-T1-NEXT: bhs .LBB2_2 ; CHECK-T1-NEXT: bhs .LBB2_2
; CHECK-T1-NEXT: @ %bb.1: ; CHECK-T1-NEXT: @ %bb.1:
; CHECK-T1-NEXT: movs r0, #0 ; CHECK-T1-NEXT: movs r0, #0
; CHECK-T1-NEXT: .LBB2_2: ; CHECK-T1-NEXT: .LBB2_2:
; CHECK-T1-NEXT: uxth r0, r0
; CHECK-T1-NEXT: bx lr ; CHECK-T1-NEXT: bx lr
; ;
; CHECK-T2-LABEL: func16: ; CHECK-T2-LABEL: func16:
; CHECK-T2: @ %bb.0: ; CHECK-T2: @ %bb.0:
; CHECK-T2-NEXT: muls r1, r2, r1 ; CHECK-T2-NEXT: muls r1, r2, r1
; CHECK-T2-NEXT: uxth r1, r1 ; CHECK-T2-NEXT: uxth r1, r1
; CHECK-T2-NEXT: subs r0, r0, r1 ; CHECK-T2-NEXT: subs r0, r0, r1
; CHECK-T2-NEXT: it lo ; CHECK-T2-NEXT: it lo
; CHECK-T2-NEXT: movlo r0, #0 ; CHECK-T2-NEXT: movlo r0, #0
; CHECK-T2-NEXT: uxth r0, r0
; CHECK-T2-NEXT: bx lr ; CHECK-T2-NEXT: bx lr
; ;
; CHECK-ARM-LABEL: func16: ; CHECK-ARM-LABEL: func16:
; CHECK-ARM: @ %bb.0: ; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: mul r1, r1, r2 ; CHECK-ARM-NEXT: mul r1, r1, r2
; CHECK-ARM-NEXT: uxth r1, r1 ; CHECK-ARM-NEXT: uxth r1, r1
; CHECK-ARM-NEXT: subs r0, r0, r1 ; CHECK-ARM-NEXT: subs r0, r0, r1
; CHECK-ARM-NEXT: movlo r0, #0 ; CHECK-ARM-NEXT: movlo r0, #0
; CHECK-ARM-NEXT: uxth r0, r0
; CHECK-ARM-NEXT: bx lr ; CHECK-ARM-NEXT: bx lr
%a = mul i16 %y, %z %a = mul i16 %y, %z
%tmp = call i16 @llvm.usub.sat.i16(i16 %x, i16 %a) %tmp = call i16 @llvm.usub.sat.i16(i16 %x, i16 %a)
ret i16 %tmp ret i16 %tmp
} }
define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y, i8 zeroext %z) nounwind { define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y, i8 zeroext %z) nounwind {
; CHECK-T1-LABEL: func8: ; CHECK-T1-LABEL: func8:
; CHECK-T1: @ %bb.0: ; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: muls r1, r2, r1 ; CHECK-T1-NEXT: muls r1, r2, r1
; CHECK-T1-NEXT: uxtb r1, r1 ; CHECK-T1-NEXT: uxtb r1, r1
; CHECK-T1-NEXT: subs r0, r0, r1 ; CHECK-T1-NEXT: subs r0, r0, r1
; CHECK-T1-NEXT: bhs .LBB3_2 ; CHECK-T1-NEXT: bhs .LBB3_2
; CHECK-T1-NEXT: @ %bb.1: ; CHECK-T1-NEXT: @ %bb.1:
; CHECK-T1-NEXT: movs r0, #0 ; CHECK-T1-NEXT: movs r0, #0
; CHECK-T1-NEXT: .LBB3_2: ; CHECK-T1-NEXT: .LBB3_2:
; CHECK-T1-NEXT: uxtb r0, r0
; CHECK-T1-NEXT: bx lr ; CHECK-T1-NEXT: bx lr
; ;
; CHECK-T2-LABEL: func8: ; CHECK-T2-LABEL: func8:
; CHECK-T2: @ %bb.0: ; CHECK-T2: @ %bb.0:
; CHECK-T2-NEXT: muls r1, r2, r1 ; CHECK-T2-NEXT: muls r1, r2, r1
; CHECK-T2-NEXT: uxtb r1, r1 ; CHECK-T2-NEXT: uxtb r1, r1
; CHECK-T2-NEXT: subs r0, r0, r1 ; CHECK-T2-NEXT: subs r0, r0, r1
; CHECK-T2-NEXT: it lo ; CHECK-T2-NEXT: it lo
; CHECK-T2-NEXT: movlo r0, #0 ; CHECK-T2-NEXT: movlo r0, #0
; CHECK-T2-NEXT: uxtb r0, r0
; CHECK-T2-NEXT: bx lr ; CHECK-T2-NEXT: bx lr
; ;
; CHECK-ARM-LABEL: func8: ; CHECK-ARM-LABEL: func8:
; CHECK-ARM: @ %bb.0: ; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: smulbb r1, r1, r2 ; CHECK-ARM-NEXT: smulbb r1, r1, r2
; CHECK-ARM-NEXT: uxtb r1, r1 ; CHECK-ARM-NEXT: uxtb r1, r1
; CHECK-ARM-NEXT: subs r0, r0, r1 ; CHECK-ARM-NEXT: subs r0, r0, r1
; CHECK-ARM-NEXT: movlo r0, #0 ; CHECK-ARM-NEXT: movlo r0, #0
; CHECK-ARM-NEXT: uxtb r0, r0
; CHECK-ARM-NEXT: bx lr ; CHECK-ARM-NEXT: bx lr
%a = mul i8 %y, %z %a = mul i8 %y, %z
%tmp = call i8 @llvm.usub.sat.i8(i8 %x, i8 %a) %tmp = call i8 @llvm.usub.sat.i8(i8 %x, i8 %a)
ret i8 %tmp ret i8 %tmp
} }
define zeroext i4 @func4(i4 zeroext %x, i4 zeroext %y, i4 zeroext %z) nounwind { define zeroext i4 @func4(i4 zeroext %x, i4 zeroext %y, i4 zeroext %z) nounwind {
; CHECK-T1-LABEL: func4: ; CHECK-T1-LABEL: func4:
; CHECK-T1: @ %bb.0: ; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: muls r1, r2, r1 ; CHECK-T1-NEXT: muls r1, r2, r1
; CHECK-T1-NEXT: movs r2, #15 ; CHECK-T1-NEXT: movs r2, #15
; CHECK-T1-NEXT: ands r1, r2 ; CHECK-T1-NEXT: ands r2, r1
; CHECK-T1-NEXT: subs r0, r0, r1 ; CHECK-T1-NEXT: subs r0, r0, r2
; CHECK-T1-NEXT: bhs .LBB4_2 ; CHECK-T1-NEXT: bhs .LBB4_2
; CHECK-T1-NEXT: @ %bb.1: ; CHECK-T1-NEXT: @ %bb.1:
; CHECK-T1-NEXT: movs r0, #0 ; CHECK-T1-NEXT: movs r0, #0
; CHECK-T1-NEXT: .LBB4_2: ; CHECK-T1-NEXT: .LBB4_2:
; CHECK-T1-NEXT: ands r0, r2
; CHECK-T1-NEXT: bx lr ; CHECK-T1-NEXT: bx lr
; ;
; CHECK-T2-LABEL: func4: ; CHECK-T2-LABEL: func4:
; CHECK-T2: @ %bb.0: ; CHECK-T2: @ %bb.0:
; CHECK-T2-NEXT: muls r1, r2, r1 ; CHECK-T2-NEXT: muls r1, r2, r1
; CHECK-T2-NEXT: and r1, r1, #15 ; CHECK-T2-NEXT: and r1, r1, #15
; CHECK-T2-NEXT: subs r0, r0, r1 ; CHECK-T2-NEXT: subs r0, r0, r1
; CHECK-T2-NEXT: it lo ; CHECK-T2-NEXT: it lo
; CHECK-T2-NEXT: movlo r0, #0 ; CHECK-T2-NEXT: movlo r0, #0
; CHECK-T2-NEXT: and r0, r0, #15
; CHECK-T2-NEXT: bx lr ; CHECK-T2-NEXT: bx lr
; ;
; CHECK-ARM-LABEL: func4: ; CHECK-ARM-LABEL: func4:
; CHECK-ARM: @ %bb.0: ; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: smulbb r1, r1, r2 ; CHECK-ARM-NEXT: smulbb r1, r1, r2
; CHECK-ARM-NEXT: and r1, r1, #15 ; CHECK-ARM-NEXT: and r1, r1, #15
; CHECK-ARM-NEXT: subs r0, r0, r1 ; CHECK-ARM-NEXT: subs r0, r0, r1
; CHECK-ARM-NEXT: movlo r0, #0 ; CHECK-ARM-NEXT: movlo r0, #0
; CHECK-ARM-NEXT: and r0, r0, #15
; CHECK-ARM-NEXT: bx lr ; CHECK-ARM-NEXT: bx lr
%a = mul i4 %y, %z %a = mul i4 %y, %z
%tmp = call i4 @llvm.usub.sat.i4(i4 %x, i4 %a) %tmp = call i4 @llvm.usub.sat.i4(i4 %x, i4 %a)
ret i4 %tmp ret i4 %tmp
} }

llvm/test/CodeGen/RISCV/usub_sat.ll

Show First 20 Lines • Show All 118 Lines • ▼ Show 20 Lines
; RV64IZbb-NEXT: ret ; RV64IZbb-NEXT: ret
%tmp = call i64 @llvm.usub.sat.i64(i64 %x, i64 %y); %tmp = call i64 @llvm.usub.sat.i64(i64 %x, i64 %y);
ret i64 %tmp; ret i64 %tmp;
} }
define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y) nounwind { define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y) nounwind {
; RV32I-LABEL: func16: ; RV32I-LABEL: func16:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: sub a2, a0, a1 ; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: sub a1, a0, a1
; RV32I-NEXT: bltu a0, a2, .LBB2_2 ; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: bltu a2, a1, .LBB2_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a1, a2 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: .LBB2_2: ; RV32I-NEXT: .LBB2_2:
; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: func16: ; RV64I-LABEL: func16:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: sub a2, a0, a1 ; RV64I-NEXT: mv a2, a0
; RV64I-NEXT: mv a1, zero ; RV64I-NEXT: sub a1, a0, a1
; RV64I-NEXT: bltu a0, a2, .LBB2_2 ; RV64I-NEXT: mv a0, zero
; RV64I-NEXT: bltu a2, a1, .LBB2_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a1, a2 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: .LBB2_2: ; RV64I-NEXT: .LBB2_2:
; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw a0, a0, -1
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32IZbb-LABEL: func16: ; RV32IZbb-LABEL: func16:
; RV32IZbb: # %bb.0: ; RV32IZbb: # %bb.0:
; RV32IZbb-NEXT: maxu a0, a0, a1 ; RV32IZbb-NEXT: maxu a0, a0, a1
; RV32IZbb-NEXT: sub a0, a0, a1 ; RV32IZbb-NEXT: sub a0, a0, a1
; RV32IZbb-NEXT: zext.h a0, a0
; RV32IZbb-NEXT: ret ; RV32IZbb-NEXT: ret
; ;
; RV64IZbb-LABEL: func16: ; RV64IZbb-LABEL: func16:
; RV64IZbb: # %bb.0: ; RV64IZbb: # %bb.0:
; RV64IZbb-NEXT: maxu a0, a0, a1 ; RV64IZbb-NEXT: maxu a0, a0, a1
; RV64IZbb-NEXT: sub a0, a0, a1 ; RV64IZbb-NEXT: sub a0, a0, a1
; RV64IZbb-NEXT: zext.h a0, a0
; RV64IZbb-NEXT: ret ; RV64IZbb-NEXT: ret
%tmp = call i16 @llvm.usub.sat.i16(i16 %x, i16 %y); %tmp = call i16 @llvm.usub.sat.i16(i16 %x, i16 %y);
ret i16 %tmp; ret i16 %tmp;
} }
define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y) nounwind { define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y) nounwind {
; RV32I-LABEL: func8: ; RV32I-LABEL: func8:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: sub a1, a0, a1 ; RV32I-NEXT: sub a1, a0, a1
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: bltu a0, a1, .LBB3_2 ; RV32I-NEXT: bltu a2, a1, .LBB3_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: .LBB3_2: ; RV32I-NEXT: .LBB3_2:
; RV32I-NEXT: andi a0, a2, 255
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: func8: ; RV64I-LABEL: func8:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv a2, a0
; RV64I-NEXT: sub a1, a0, a1 ; RV64I-NEXT: sub a1, a0, a1
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a0, zero
; RV64I-NEXT: bltu a0, a1, .LBB3_2 ; RV64I-NEXT: bltu a2, a1, .LBB3_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: .LBB3_2: ; RV64I-NEXT: .LBB3_2:
; RV64I-NEXT: andi a0, a2, 255
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32IZbb-LABEL: func8: ; RV32IZbb-LABEL: func8:
; RV32IZbb: # %bb.0: ; RV32IZbb: # %bb.0:
; RV32IZbb-NEXT: maxu a0, a0, a1 ; RV32IZbb-NEXT: maxu a0, a0, a1
; RV32IZbb-NEXT: sub a0, a0, a1 ; RV32IZbb-NEXT: sub a0, a0, a1
; RV32IZbb-NEXT: andi a0, a0, 255
; RV32IZbb-NEXT: ret ; RV32IZbb-NEXT: ret
; ;
; RV64IZbb-LABEL: func8: ; RV64IZbb-LABEL: func8:
; RV64IZbb: # %bb.0: ; RV64IZbb: # %bb.0:
; RV64IZbb-NEXT: maxu a0, a0, a1 ; RV64IZbb-NEXT: maxu a0, a0, a1
; RV64IZbb-NEXT: sub a0, a0, a1 ; RV64IZbb-NEXT: sub a0, a0, a1
; RV64IZbb-NEXT: andi a0, a0, 255
; RV64IZbb-NEXT: ret ; RV64IZbb-NEXT: ret
%tmp = call i8 @llvm.usub.sat.i8(i8 %x, i8 %y); %tmp = call i8 @llvm.usub.sat.i8(i8 %x, i8 %y);
ret i8 %tmp; ret i8 %tmp;
} }
define zeroext i4 @func3(i4 zeroext %x, i4 zeroext %y) nounwind { define zeroext i4 @func3(i4 zeroext %x, i4 zeroext %y) nounwind {
; RV32I-LABEL: func3: ; RV32I-LABEL: func3:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: sub a1, a0, a1 ; RV32I-NEXT: sub a1, a0, a1
; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: bltu a0, a1, .LBB4_2 ; RV32I-NEXT: bltu a2, a1, .LBB4_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: .LBB4_2: ; RV32I-NEXT: .LBB4_2:
; RV32I-NEXT: andi a0, a2, 15
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: func3: ; RV64I-LABEL: func3:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv a2, a0
; RV64I-NEXT: sub a1, a0, a1 ; RV64I-NEXT: sub a1, a0, a1
; RV64I-NEXT: mv a2, zero ; RV64I-NEXT: mv a0, zero
; RV64I-NEXT: bltu a0, a1, .LBB4_2 ; RV64I-NEXT: bltu a2, a1, .LBB4_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: .LBB4_2: ; RV64I-NEXT: .LBB4_2:
; RV64I-NEXT: andi a0, a2, 15
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32IZbb-LABEL: func3: ; RV32IZbb-LABEL: func3:
; RV32IZbb: # %bb.0: ; RV32IZbb: # %bb.0:
; RV32IZbb-NEXT: maxu a0, a0, a1 ; RV32IZbb-NEXT: maxu a0, a0, a1
; RV32IZbb-NEXT: sub a0, a0, a1 ; RV32IZbb-NEXT: sub a0, a0, a1
; RV32IZbb-NEXT: andi a0, a0, 15
; RV32IZbb-NEXT: ret ; RV32IZbb-NEXT: ret
; ;
; RV64IZbb-LABEL: func3: ; RV64IZbb-LABEL: func3:
; RV64IZbb: # %bb.0: ; RV64IZbb: # %bb.0:
; RV64IZbb-NEXT: maxu a0, a0, a1 ; RV64IZbb-NEXT: maxu a0, a0, a1
; RV64IZbb-NEXT: sub a0, a0, a1 ; RV64IZbb-NEXT: sub a0, a0, a1
; RV64IZbb-NEXT: andi a0, a0, 15
; RV64IZbb-NEXT: ret ; RV64IZbb-NEXT: ret
%tmp = call i4 @llvm.usub.sat.i4(i4 %x, i4 %y); %tmp = call i4 @llvm.usub.sat.i4(i4 %x, i4 %y);
ret i4 %tmp; ret i4 %tmp;
} }

llvm/test/CodeGen/X86/combine-sub-usat.ll

Show First 20 Lines • Show All 132 Lines • ▼ Show 20 Lines
} }
define <8 x i8> @combine_trunc_v8i16_v8i8(<8 x i8> %a0, <8 x i16> %a1) { define <8 x i8> @combine_trunc_v8i16_v8i8(<8 x i8> %a0, <8 x i16> %a1) {
; SSE2-LABEL: combine_trunc_v8i16_v8i8: ; SSE2-LABEL: combine_trunc_v8i16_v8i8:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: pxor %xmm2, %xmm2 ; SSE2-NEXT: pxor %xmm2, %xmm2
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
; SSE2-NEXT: psubusw %xmm1, %xmm0 ; SSE2-NEXT: psubusw %xmm1, %xmm0
; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0 ; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: combine_trunc_v8i16_v8i8: ; SSE41-LABEL: combine_trunc_v8i16_v8i8:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: pmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; SSE41-NEXT: pmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; SSE41-NEXT: psubusw %xmm1, %xmm0 ; SSE41-NEXT: psubusw %xmm1, %xmm0
; SSE41-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u] ; SSE41-NEXT: packuswb %xmm0, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; SSE42-LABEL: combine_trunc_v8i16_v8i8: ; SSE42-LABEL: combine_trunc_v8i16_v8i8:
; SSE42: # %bb.0: ; SSE42: # %bb.0:
; SSE42-NEXT: pmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; SSE42-NEXT: pmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; SSE42-NEXT: psubusw %xmm1, %xmm0 ; SSE42-NEXT: psubusw %xmm1, %xmm0
; SSE42-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u] ; SSE42-NEXT: packuswb %xmm0, %xmm0
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX-LABEL: combine_trunc_v8i16_v8i8: ; AVX-LABEL: combine_trunc_v8i16_v8i8:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; AVX-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX-NEXT: vpsubusw %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpsubusw %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u] ; AVX-NEXT: vpackuswb %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = zext <8 x i8> %a0 to <8 x i16> %1 = zext <8 x i8> %a0 to <8 x i16>
%2 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %1, <8 x i16> %a1) %2 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %1, <8 x i16> %a1)
%3 = trunc <8 x i16> %2 to <8 x i8> %3 = trunc <8 x i16> %2 to <8 x i8>
ret <8 x i8> %3 ret <8 x i8> %3
} }
define <8 x i16> @combine_trunc_v8i32_v8i16(<8 x i16> %a0, <8 x i32> %a1) { define <8 x i16> @combine_trunc_v8i32_v8i16(<8 x i16> %a0, <8 x i32> %a1) {
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llvm/test/CodeGen/X86/usub_sat.ll

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define zeroext i4 @func3(i4 zeroext %x, i4 zeroext %y) nounwind { define zeroext i4 @func3(i4 zeroext %x, i4 zeroext %y) nounwind {
; X86-LABEL: func3: ; X86-LABEL: func3:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: movb {{[0-9]+}}(%esp), %al ; X86-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-NEXT: xorl %ecx, %ecx ; X86-NEXT: xorl %ecx, %ecx
; X86-NEXT: subb {{[0-9]+}}(%esp), %al ; X86-NEXT: subb {{[0-9]+}}(%esp), %al
; X86-NEXT: movzbl %al, %eax ; X86-NEXT: movzbl %al, %eax
; X86-NEXT: cmovbl %ecx, %eax ; X86-NEXT: cmovbl %ecx, %eax
; X86-NEXT: andl $15, %eax ; X86-NEXT: movzbl %al, %eax
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: func3: ; X64-LABEL: func3:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: xorl %ecx, %ecx ; X64-NEXT: xorl %eax, %eax
; X64-NEXT: subb %sil, %dil ; X64-NEXT: subb %sil, %dil
; X64-NEXT: movzbl %dil, %eax ; X64-NEXT: movzbl %dil, %ecx
; X64-NEXT: cmovbl %ecx, %eax ; X64-NEXT: cmovbl %eax, %ecx
; X64-NEXT: andl $15, %eax ; X64-NEXT: movzbl %cl, %eax
; X64-NEXT: retq ; X64-NEXT: retq
%tmp = call i4 @llvm.usub.sat.i4(i4 %x, i4 %y) %tmp = call i4 @llvm.usub.sat.i4(i4 %x, i4 %y)
ret i4 %tmp ret i4 %tmp
} }
define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind { define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
; X86-LABEL: vec: ; X86-LABEL: vec:
; X86: # %bb.0: ; X86: # %bb.0:
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llvm/test/CodeGen/X86/usub_sat_plus.ll

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; X86-NEXT: movb {{[0-9]+}}(%esp), %cl ; X86-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NEXT: movb {{[0-9]+}}(%esp), %al ; X86-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-NEXT: mulb {{[0-9]+}}(%esp) ; X86-NEXT: mulb {{[0-9]+}}(%esp)
; X86-NEXT: andb $15, %al ; X86-NEXT: andb $15, %al
; X86-NEXT: xorl %edx, %edx ; X86-NEXT: xorl %edx, %edx
; X86-NEXT: subb %al, %cl ; X86-NEXT: subb %al, %cl
; X86-NEXT: movzbl %cl, %eax ; X86-NEXT: movzbl %cl, %eax
; X86-NEXT: cmovbl %edx, %eax ; X86-NEXT: cmovbl %edx, %eax
; X86-NEXT: andl $15, %eax ; X86-NEXT: movzbl %al, %eax
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: func4: ; X64-LABEL: func4:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movl %esi, %eax ; X64-NEXT: movl %esi, %eax
; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: # kill: def $al killed $al killed $eax
; X64-NEXT: mulb %dl ; X64-NEXT: mulb %dl
; X64-NEXT: andb $15, %al ; X64-NEXT: andb $15, %al
; X64-NEXT: xorl %ecx, %ecx ; X64-NEXT: xorl %ecx, %ecx
; X64-NEXT: subb %al, %dil ; X64-NEXT: subb %al, %dil
; X64-NEXT: movzbl %dil, %eax ; X64-NEXT: movzbl %dil, %eax
; X64-NEXT: cmovbl %ecx, %eax ; X64-NEXT: cmovbl %ecx, %eax
; X64-NEXT: andl $15, %eax ; X64-NEXT: movzbl %al, %eax
craig.topperAuthorUnsubmitted
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This is still less than optimal. The movzbl at line 133 is really an any_extend. The other operand of the cmovbl is 0. Had we used a zero_extend at 133 this movzbl wouldn't be needed.

craig.topper: This is still less than optimal. The movzbl at line 133 is really an any_extend. The other…
RKSimonUnsubmitted
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Its sort of related to PR40881 - which complains about a similar thing resulting in ZEXTLOAD vs EXTLOAD.

RKSimon: Its sort of related to PR40881 - which complains about a similar thing resulting in ZEXTLOAD vs…
; X64-NEXT: retq ; X64-NEXT: retq
%a = mul i4 %y, %z %a = mul i4 %y, %z
%tmp = call i4 @llvm.usub.sat.i4(i4 %x, i4 %a) %tmp = call i4 @llvm.usub.sat.i4(i4 %x, i4 %a)
ret i4 %tmp ret i4 %tmp
} }