This is an archive of the discontinued LLVM Phabricator instance.

Differential D97859

[LegalizeDAG] Implement promotion rules for SELECT_CC
ClosedPublic

Authored by LemonBoy on Mar 3 2021, 7:25 AM.

Details

Reviewers
fhahn
david-arm
craig.topper
Commits
rG2ec43e416734: [LegalizeDAG] Implement promotion rules for SELECT_CC
Summary

Implement the promotion rule for SELECT_CC nodes by upcasting all the parameters and downcasting the result.
The AArch64 target makes use of this rule and, since it was not implemented, in some cases the instruction selector would hit an assertion upon encountering the illegal node.

This patch requires D97840, the included test cases hit both problems.

Diff Detail

Event Timeline

LemonBoy created this revision.Mar 3 2021, 7:25 AM
Herald added subscribers: hiraditya, kristof.beyls. · View Herald TranscriptMar 3 2021, 7:25 AM
LemonBoy requested review of this revision.Mar 3 2021, 7:25 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 3 2021, 7:25 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
LemonBoy added a parent revision: D97840: [AArch64] Legalize horizontal fmax/fmin reductions on f16 vectors.Mar 3 2021, 7:25 AM
craig.topper added a subscriber: craig.topper.Mar 3 2021, 9:57 AM
craig.topper added inline comments.
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
4729

I believe ISD::SELECT_CC can have integer operands for the compare and FP operands for the result and true/false value.

LemonBoy added inline comments.Mar 3 2021, 10:03 AM
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
4729

I actually tried to do so but hit an assertion when the previous node is RAUW'd.
The assert message is "Cannot replace uses of with self", some brief testing showed it complains after the SELECT_CC is promoted for the second time.

craig.topper added inline comments.Mar 3 2021, 10:41 AM
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
4729

Sorry, what exactly did you try to do? My point was only that you can't assume the same extend opcode is valid for all operands or that all operands want to be promoted to NVT.

LemonBoy added inline comments.Mar 3 2021, 10:57 AM
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
4729

Sorry, I misread your previous comment. I now get there are two possibly different types at play here.

Given the Promote rule kicks in according to the true/false type can we assume the comparison operands are already legalized? Should I try to expand those as well? And if so, is there a way to check if the comparison itself is legal?

Harbormaster completed remote builds in B91816: Diff 327788.Mar 3 2021, 1:43 PM
craig.topper added inline comments.Mar 3 2021, 2:03 PM
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
4729

My best idea is to promote them if they happen to have the same type and leave them alone otherwise. I don't think there's a way to check that the comparison is legal.

LemonBoy updated this revision to Diff 328099.Mar 4 2021, 3:25 AM

Properly handle cases where the true/false operand have different types than the comparison ones.

craig.topper added inline comments.Mar 4 2021, 9:09 AM
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
4727

If NVT is Integer, but operand 0 and 1 are floating point, I'm not sure we should be calling isSignedIntSetCC. The floating point and integer condition codes are shared. So SETGT, SETLT, SETLE, SETGE are also valid for floating point, but they wouldn't mean anything for determining if you should SIGN_EXTEND or ZERO_EXTEND the true/false values of the SELECT_CC.

But I guess since this hasn't worked properly before now maybe this doesn't happen and it doesn't matter.

LemonBoy updated this revision to Diff 328223.Mar 4 2021, 10:09 AM

Assert all the operand types are the same.

llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
4727

I see, this is trickier than anticipated. I'll simply assert that both types are equal and carry on, this promotion rule is rarely used and the only instances I could produce fall into this category.

craig.topper accepted this revision.Mar 4 2021, 10:43 AM

LGTM

This revision is now accepted and ready to land.Mar 4 2021, 10:43 AM
Harbormaster completed remote builds in B92022: Diff 328099.Mar 4 2021, 1:02 PM
Harbormaster completed remote builds in B92114: Diff 328223.Mar 5 2021, 12:33 AM
This revision was landed with ongoing or failed builds.Mar 5 2021, 9:23 AM
Closed by commit rG2ec43e416734: [LegalizeDAG] Implement promotion rules for SELECT_CC (authored by LemonBoy). · Explain Why
This revision was automatically updated to reflect the committed changes.
LemonBoy added a commit: rG2ec43e416734: [LegalizeDAG] Implement promotion rules for SELECT_CC.

Revision Contents

PathSize
llvm/
lib/
CodeGen/
SelectionDAG/
44 lines
test/
CodeGen/
AArch64/
216 lines
216 lines

Diff 328554

llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Show First 20 Lines • Show All 4,512 Lines • ▼ Show 20 Lines if (Node->getOpcode() == ISD::UINT_TO_FP ||
Node->getOpcode() == ISD::INSERT_VECTOR_ELT) { Node->getOpcode() == ISD::INSERT_VECTOR_ELT) {
OVT = Node->getOperand(0).getSimpleValueType(); OVT = Node->getOperand(0).getSimpleValueType();
} }
if (Node->getOpcode() == ISD::STRICT_UINT_TO_FP || if (Node->getOpcode() == ISD::STRICT_UINT_TO_FP ||
Node->getOpcode() == ISD::STRICT_SINT_TO_FP || Node->getOpcode() == ISD::STRICT_SINT_TO_FP ||
Node->getOpcode() == ISD::STRICT_FSETCC || Node->getOpcode() == ISD::STRICT_FSETCC ||
Node->getOpcode() == ISD::STRICT_FSETCCS) Node->getOpcode() == ISD::STRICT_FSETCCS)
OVT = Node->getOperand(1).getSimpleValueType(); OVT = Node->getOperand(1).getSimpleValueType();
if (Node->getOpcode() == ISD::BR_CC) if (Node->getOpcode() == ISD::BR_CC ||
Node->getOpcode() == ISD::SELECT_CC)
OVT = Node->getOperand(2).getSimpleValueType(); OVT = Node->getOperand(2).getSimpleValueType();
MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
SDLoc dl(Node); SDLoc dl(Node);
SDValue Tmp1, Tmp2, Tmp3; SDValue Tmp1, Tmp2, Tmp3, Tmp4;
switch (Node->getOpcode()) { switch (Node->getOpcode()) {
case ISD::CTTZ: case ISD::CTTZ:
case ISD::CTTZ_ZERO_UNDEF: case ISD::CTTZ_ZERO_UNDEF:
case ISD::CTLZ: case ISD::CTLZ:
case ISD::CTLZ_ZERO_UNDEF: case ISD::CTLZ_ZERO_UNDEF:
case ISD::CTPOP: case ISD::CTPOP:
// Zero extend the argument unless its cttz, then use any_extend. // Zero extend the argument unless its cttz, then use any_extend.
if (Node->getOpcode() == ISD::CTTZ || if (Node->getOpcode() == ISD::CTTZ ||
▲ Show 20 Lines • Show All 175 Lines • ▼ Show 20 Lines case ISD::VECTOR_SHUFFLE: {
Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1)); Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
// Convert the shuffle mask to the right # elements. // Convert the shuffle mask to the right # elements.
Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask); Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1); Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
Results.push_back(Tmp1); Results.push_back(Tmp1);
break; break;
} }
case ISD::SELECT_CC: {
SDValue Cond = Node->getOperand(4);
ISD::CondCode CCCode = cast<CondCodeSDNode>(Cond)->get();
// Type of the comparison operands.
MVT CVT = Node->getSimpleValueType(0);
assert(CVT == OVT && "not handled");
unsigned ExtOp = ISD::FP_EXTEND;
if (NVT.isInteger()) {
craig.topperUnsubmitted
Not Done
ReplyInline Actions

If NVT is Integer, but operand 0 and 1 are floating point, I'm not sure we should be calling isSignedIntSetCC. The floating point and integer condition codes are shared. So SETGT, SETLT, SETLE, SETGE are also valid for floating point, but they wouldn't mean anything for determining if you should SIGN_EXTEND or ZERO_EXTEND the true/false values of the SELECT_CC.

But I guess since this hasn't worked properly before now maybe this doesn't happen and it doesn't matter.

craig.topper: If NVT is Integer, but operand 0 and 1 are floating point, I'm not sure we should be calling…
LemonBoyAuthorUnsubmitted
Done
ReplyInline Actions

I see, this is trickier than anticipated. I'll simply assert that both types are equal and carry on, this promotion rule is rarely used and the only instances I could produce fall into this category.

LemonBoy: I see, this is trickier than anticipated. I'll simply assert that both types are equal and…
ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
}
craig.topperUnsubmitted
Not Done
ReplyInline Actions

I believe ISD::SELECT_CC can have integer operands for the compare and FP operands for the result and true/false value.

craig.topper: I believe ISD::SELECT_CC can have integer operands for the compare and FP operands for the…
LemonBoyAuthorUnsubmitted
Done
ReplyInline Actions

I actually tried to do so but hit an assertion when the previous node is RAUW'd.
The assert message is "Cannot replace uses of with self", some brief testing showed it complains after the SELECT_CC is promoted for the second time.

LemonBoy: I actually tried to do so but hit an assertion when the previous node is RAUW'd. The assert…
craig.topperUnsubmitted
Not Done
ReplyInline Actions

Sorry, what exactly did you try to do? My point was only that you can't assume the same extend opcode is valid for all operands or that all operands want to be promoted to NVT.

craig.topper: Sorry, what exactly did you try to do? My point was only that you can't assume the same…
LemonBoyAuthorUnsubmitted
Done
ReplyInline Actions

Sorry, I misread your previous comment. I now get there are two possibly different types at play here.

Given the Promote rule kicks in according to the true/false type can we assume the comparison operands are already legalized? Should I try to expand those as well? And if so, is there a way to check if the comparison itself is legal?

LemonBoy: Sorry, I misread your previous comment. I now get there are two possibly different types at…
craig.topperUnsubmitted
Not Done
ReplyInline Actions

My best idea is to promote them if they happen to have the same type and leave them alone otherwise. I don't think there's a way to check that the comparison is legal.

craig.topper: My best idea is to promote them if they happen to have the same type and leave them alone…
// Promote the comparison operands, if needed.
if (TLI.isCondCodeLegal(CCCode, CVT)) {
Tmp1 = Node->getOperand(0);
Tmp2 = Node->getOperand(1);
} else {
Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
}
// Cast the true/false operands.
Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
Tmp4 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(3));
Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, NVT, {Tmp1, Tmp2, Tmp3, Tmp4, Cond},
Node->getFlags());
// Cast the result back to the original type.
if (ExtOp != ISD::FP_EXTEND)
Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1);
else
Tmp1 = DAG.getNode(ISD::FP_ROUND, dl, OVT, Tmp1,
DAG.getIntPtrConstant(0, dl));
Results.push_back(Tmp1);
break;
}
case ISD::SETCC: case ISD::SETCC:
case ISD::STRICT_FSETCC: case ISD::STRICT_FSETCC:
case ISD::STRICT_FSETCCS: { case ISD::STRICT_FSETCCS: {
unsigned ExtOp = ISD::FP_EXTEND; unsigned ExtOp = ISD::FP_EXTEND;
if (NVT.isInteger()) { if (NVT.isInteger()) {
ISD::CondCode CCCode = cast<CondCodeSDNode>(Node->getOperand(2))->get(); ISD::CondCode CCCode = cast<CondCodeSDNode>(Node->getOperand(2))->get();
ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
} }
▲ Show 20 Lines • Show All 368 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP ; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP
; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon,+fullfp16 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP ; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon,+fullfp16 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP
declare half @llvm.vector.reduce.fmax.v1f16(<1 x half> %a) declare half @llvm.vector.reduce.fmax.v1f16(<1 x half> %a)
declare float @llvm.vector.reduce.fmax.v1f32(<1 x float> %a) declare float @llvm.vector.reduce.fmax.v1f32(<1 x float> %a)
declare double @llvm.vector.reduce.fmax.v1f64(<1 x double> %a) declare double @llvm.vector.reduce.fmax.v1f64(<1 x double> %a)
declare fp128 @llvm.vector.reduce.fmax.v1f128(<1 x fp128> %a) declare fp128 @llvm.vector.reduce.fmax.v1f128(<1 x fp128> %a)
declare half @llvm.vector.reduce.fmax.v4f16(<4 x half> %a) declare half @llvm.vector.reduce.fmax.v4f16(<4 x half> %a)
declare half @llvm.vector.reduce.fmax.v11f16(<11 x half> %a)
declare float @llvm.vector.reduce.fmax.v3f32(<3 x float> %a) declare float @llvm.vector.reduce.fmax.v3f32(<3 x float> %a)
declare fp128 @llvm.vector.reduce.fmax.v2f128(<2 x fp128> %a) declare fp128 @llvm.vector.reduce.fmax.v2f128(<2 x fp128> %a)
declare float @llvm.vector.reduce.fmax.v16f32(<16 x float> %a) declare float @llvm.vector.reduce.fmax.v16f32(<16 x float> %a)
define half @test_v1f16(<1 x half> %a) nounwind { define half @test_v1f16(<1 x half> %a) nounwind {
; CHECK-LABEL: test_v1f16: ; CHECK-LABEL: test_v1f16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
; CHECK-FP-LABEL: test_v4f16_ninf: ; CHECK-FP-LABEL: test_v4f16_ninf:
; CHECK-FP: // %bb.0: ; CHECK-FP: // %bb.0:
; CHECK-FP-NEXT: fmaxnmv h0, v0.4h ; CHECK-FP-NEXT: fmaxnmv h0, v0.4h
; CHECK-FP-NEXT: ret ; CHECK-FP-NEXT: ret
%b = call nnan ninf half @llvm.vector.reduce.fmax.v4f16(<4 x half> %a) %b = call nnan ninf half @llvm.vector.reduce.fmax.v4f16(<4 x half> %a)
ret half %b ret half %b
} }
define half @test_v11f16(<11 x half> %a) nounwind {
; CHECK-NOFP-LABEL: test_v11f16:
; CHECK-NOFP: // %bb.0:
; CHECK-NOFP-NEXT: ldr h18, [sp, #8]
; CHECK-NOFP-NEXT: ldr h17, [sp]
; CHECK-NOFP-NEXT: ldr h16, [sp, #16]
; CHECK-NOFP-NEXT: fcvt s1, h1
; CHECK-NOFP-NEXT: fcvt s18, h18
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fcmp s1, s18
; CHECK-NOFP-NEXT: fcvt s17, h17
; CHECK-NOFP-NEXT: adrp x8, .LCPI6_0
; CHECK-NOFP-NEXT: fcsel s1, s1, s18, gt
; CHECK-NOFP-NEXT: fcmp s0, s17
; CHECK-NOFP-NEXT: ldr h18, [x8, :lo12:.LCPI6_0]
; CHECK-NOFP-NEXT: fcsel s0, s0, s17, gt
; CHECK-NOFP-NEXT: fcvt s2, h2
; CHECK-NOFP-NEXT: fcvt s16, h16
; CHECK-NOFP-NEXT: fcvt h1, s1
; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: fcmp s2, s16
; CHECK-NOFP-NEXT: fcvt s1, h1
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fcsel s2, s2, s16, gt
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
; CHECK-NOFP-NEXT: fcvt s3, h3
; CHECK-NOFP-NEXT: mov w8, #-8388608
; CHECK-NOFP-NEXT: fcvt s18, h18
; CHECK-NOFP-NEXT: fcvt h2, s2
; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: fmov s17, w8
; CHECK-NOFP-NEXT: fcmp s3, s18
; CHECK-NOFP-NEXT: fcvt s1, h2
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fcsel s3, s3, s17, gt
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
; CHECK-NOFP-NEXT: fcvt s4, h4
; CHECK-NOFP-NEXT: fcvt h2, s3
; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: fcmp s4, s18
; CHECK-NOFP-NEXT: fcvt s2, h2
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fcsel s3, s4, s17, gt
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s2
; CHECK-NOFP-NEXT: fcvt s5, h5
; CHECK-NOFP-NEXT: fcvt h3, s3
; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: fcmp s5, s18
; CHECK-NOFP-NEXT: fcvt s3, h3
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fcsel s4, s5, s17, gt
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s3
; CHECK-NOFP-NEXT: fcvt s6, h6
; CHECK-NOFP-NEXT: fcvt h4, s4
; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: fcmp s6, s18
; CHECK-NOFP-NEXT: fcvt s1, h4
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fcsel s5, s6, s17, gt
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
; CHECK-NOFP-NEXT: fcvt s7, h7
; CHECK-NOFP-NEXT: fcvt h4, s5
; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: fcmp s7, s18
; CHECK-NOFP-NEXT: fcvt s4, h4
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fcsel s5, s7, s17, gt
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s4
; CHECK-NOFP-NEXT: fcvt h5, s5
; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fcvt s1, h5
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: ret
;
; CHECK-FP-LABEL: test_v11f16:
; CHECK-FP: // %bb.0:
; CHECK-FP-NEXT: movi v16.8h, #252, lsl #8
; CHECK-FP-NEXT: mov x8, sp
; CHECK-FP-NEXT: ld1 { v16.h }[0], [x8]
; CHECK-FP-NEXT: add x8, sp, #8 // =8
; CHECK-FP-NEXT: // kill: def $h0 killed $h0 def $q0
; CHECK-FP-NEXT: // kill: def $h1 killed $h1 def $q1
; CHECK-FP-NEXT: // kill: def $h2 killed $h2 def $q2
; CHECK-FP-NEXT: // kill: def $h3 killed $h3 def $q3
; CHECK-FP-NEXT: // kill: def $h4 killed $h4 def $q4
; CHECK-FP-NEXT: // kill: def $h5 killed $h5 def $q5
; CHECK-FP-NEXT: // kill: def $h6 killed $h6 def $q6
; CHECK-FP-NEXT: // kill: def $h7 killed $h7 def $q7
; CHECK-FP-NEXT: mov v0.h[1], v1.h[0]
; CHECK-FP-NEXT: ld1 { v16.h }[1], [x8]
; CHECK-FP-NEXT: mov v0.h[2], v2.h[0]
; CHECK-FP-NEXT: mov v0.h[3], v3.h[0]
; CHECK-FP-NEXT: add x8, sp, #16 // =16
; CHECK-FP-NEXT: mov v0.h[4], v4.h[0]
; CHECK-FP-NEXT: ld1 { v16.h }[2], [x8]
; CHECK-FP-NEXT: mov v0.h[5], v5.h[0]
; CHECK-FP-NEXT: mov v0.h[6], v6.h[0]
; CHECK-FP-NEXT: mov v0.h[7], v7.h[0]
; CHECK-FP-NEXT: fmaxnm v0.8h, v0.8h, v16.8h
; CHECK-FP-NEXT: fmaxnmv h0, v0.8h
; CHECK-FP-NEXT: ret
%b = call nnan half @llvm.vector.reduce.fmax.v11f16(<11 x half> %a)
ret half %b
}
define half @test_v11f16_ninf(<11 x half> %a) nounwind {
; CHECK-NOFP-LABEL: test_v11f16_ninf:
; CHECK-NOFP: // %bb.0:
; CHECK-NOFP-NEXT: ldr h18, [sp, #8]
; CHECK-NOFP-NEXT: ldr h17, [sp]
; CHECK-NOFP-NEXT: ldr h16, [sp, #16]
; CHECK-NOFP-NEXT: fcvt s1, h1
; CHECK-NOFP-NEXT: fcvt s18, h18
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fcmp s1, s18
; CHECK-NOFP-NEXT: fcvt s17, h17
; CHECK-NOFP-NEXT: adrp x8, .LCPI7_0
; CHECK-NOFP-NEXT: fcsel s1, s1, s18, gt
; CHECK-NOFP-NEXT: fcmp s0, s17
; CHECK-NOFP-NEXT: ldr h18, [x8, :lo12:.LCPI7_0]
; CHECK-NOFP-NEXT: fcsel s0, s0, s17, gt
; CHECK-NOFP-NEXT: fcvt s2, h2
; CHECK-NOFP-NEXT: fcvt s16, h16
; CHECK-NOFP-NEXT: fcvt h1, s1
; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: fcmp s2, s16
; CHECK-NOFP-NEXT: fcvt s1, h1
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: mov w8, #57344
; CHECK-NOFP-NEXT: fcsel s2, s2, s16, gt
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
; CHECK-NOFP-NEXT: fcvt s3, h3
; CHECK-NOFP-NEXT: movk w8, #51071, lsl #16
; CHECK-NOFP-NEXT: fcvt s18, h18
; CHECK-NOFP-NEXT: fcvt h2, s2
; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: fmov s17, w8
; CHECK-NOFP-NEXT: fcmp s3, s18
; CHECK-NOFP-NEXT: fcvt s1, h2
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fcsel s3, s3, s17, gt
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
; CHECK-NOFP-NEXT: fcvt s4, h4
; CHECK-NOFP-NEXT: fcvt h2, s3
; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: fcmp s4, s18
; CHECK-NOFP-NEXT: fcvt s2, h2
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fcsel s3, s4, s17, gt
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s2
; CHECK-NOFP-NEXT: fcvt s5, h5
; CHECK-NOFP-NEXT: fcvt h3, s3
; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: fcmp s5, s18
; CHECK-NOFP-NEXT: fcvt s3, h3
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fcsel s4, s5, s17, gt
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s3
; CHECK-NOFP-NEXT: fcvt s6, h6
; CHECK-NOFP-NEXT: fcvt h4, s4
; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: fcmp s6, s18
; CHECK-NOFP-NEXT: fcvt s1, h4
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fcsel s5, s6, s17, gt
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
; CHECK-NOFP-NEXT: fcvt s7, h7
; CHECK-NOFP-NEXT: fcvt h4, s5
; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: fcmp s7, s18
; CHECK-NOFP-NEXT: fcvt s4, h4
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fcsel s5, s7, s17, gt
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s4
; CHECK-NOFP-NEXT: fcvt h5, s5
; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fcvt s1, h5
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: ret
;
; CHECK-FP-LABEL: test_v11f16_ninf:
; CHECK-FP: // %bb.0:
; CHECK-FP-NEXT: mvni v16.8h, #4, lsl #8
; CHECK-FP-NEXT: mov x8, sp
; CHECK-FP-NEXT: ld1 { v16.h }[0], [x8]
; CHECK-FP-NEXT: add x8, sp, #8 // =8
; CHECK-FP-NEXT: // kill: def $h0 killed $h0 def $q0
; CHECK-FP-NEXT: // kill: def $h1 killed $h1 def $q1
; CHECK-FP-NEXT: // kill: def $h2 killed $h2 def $q2
; CHECK-FP-NEXT: // kill: def $h3 killed $h3 def $q3
; CHECK-FP-NEXT: // kill: def $h4 killed $h4 def $q4
; CHECK-FP-NEXT: // kill: def $h5 killed $h5 def $q5
; CHECK-FP-NEXT: // kill: def $h6 killed $h6 def $q6
; CHECK-FP-NEXT: // kill: def $h7 killed $h7 def $q7
; CHECK-FP-NEXT: mov v0.h[1], v1.h[0]
; CHECK-FP-NEXT: ld1 { v16.h }[1], [x8]
; CHECK-FP-NEXT: mov v0.h[2], v2.h[0]
; CHECK-FP-NEXT: mov v0.h[3], v3.h[0]
; CHECK-FP-NEXT: add x8, sp, #16 // =16
; CHECK-FP-NEXT: mov v0.h[4], v4.h[0]
; CHECK-FP-NEXT: ld1 { v16.h }[2], [x8]
; CHECK-FP-NEXT: mov v0.h[5], v5.h[0]
; CHECK-FP-NEXT: mov v0.h[6], v6.h[0]
; CHECK-FP-NEXT: mov v0.h[7], v7.h[0]
; CHECK-FP-NEXT: fmaxnm v0.8h, v0.8h, v16.8h
; CHECK-FP-NEXT: fmaxnmv h0, v0.8h
; CHECK-FP-NEXT: ret
%b = call nnan ninf half @llvm.vector.reduce.fmax.v11f16(<11 x half> %a)
ret half %b
}
define float @test_v3f32(<3 x float> %a) nounwind { define float @test_v3f32(<3 x float> %a) nounwind {
; CHECK-LABEL: test_v3f32: ; CHECK-LABEL: test_v3f32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #-8388608 ; CHECK-NEXT: mov w8, #-8388608
; CHECK-NEXT: fmov s1, w8 ; CHECK-NEXT: fmov s1, w8
; CHECK-NEXT: mov v0.s[3], v1.s[0] ; CHECK-NEXT: mov v0.s[3], v1.s[0]
; CHECK-NEXT: fmaxnmv s0, v0.4s ; CHECK-NEXT: fmaxnmv s0, v0.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
Show All 35 Lines

llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP ; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP
; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon,+fullfp16 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP ; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon,+fullfp16 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP
declare half @llvm.vector.reduce.fmin.v1f16(<1 x half> %a) declare half @llvm.vector.reduce.fmin.v1f16(<1 x half> %a)
declare float @llvm.vector.reduce.fmin.v1f32(<1 x float> %a) declare float @llvm.vector.reduce.fmin.v1f32(<1 x float> %a)
declare double @llvm.vector.reduce.fmin.v1f64(<1 x double> %a) declare double @llvm.vector.reduce.fmin.v1f64(<1 x double> %a)
declare fp128 @llvm.vector.reduce.fmin.v1f128(<1 x fp128> %a) declare fp128 @llvm.vector.reduce.fmin.v1f128(<1 x fp128> %a)
declare half @llvm.vector.reduce.fmin.v4f16(<4 x half> %a) declare half @llvm.vector.reduce.fmin.v4f16(<4 x half> %a)
declare half @llvm.vector.reduce.fmin.v11f16(<11 x half> %a)
declare float @llvm.vector.reduce.fmin.v3f32(<3 x float> %a) declare float @llvm.vector.reduce.fmin.v3f32(<3 x float> %a)
declare fp128 @llvm.vector.reduce.fmin.v2f128(<2 x fp128> %a) declare fp128 @llvm.vector.reduce.fmin.v2f128(<2 x fp128> %a)
declare float @llvm.vector.reduce.fmin.v16f32(<16 x float> %a) declare float @llvm.vector.reduce.fmin.v16f32(<16 x float> %a)
define half @test_v1f16(<1 x half> %a) nounwind { define half @test_v1f16(<1 x half> %a) nounwind {
; CHECK-LABEL: test_v1f16: ; CHECK-LABEL: test_v1f16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
; CHECK-FP-LABEL: test_v4f16_ninf: ; CHECK-FP-LABEL: test_v4f16_ninf:
; CHECK-FP: // %bb.0: ; CHECK-FP: // %bb.0:
; CHECK-FP-NEXT: fminnmv h0, v0.4h ; CHECK-FP-NEXT: fminnmv h0, v0.4h
; CHECK-FP-NEXT: ret ; CHECK-FP-NEXT: ret
%b = call nnan ninf half @llvm.vector.reduce.fmin.v4f16(<4 x half> %a) %b = call nnan ninf half @llvm.vector.reduce.fmin.v4f16(<4 x half> %a)
ret half %b ret half %b
} }
define half @test_v11f16(<11 x half> %a) nounwind {
; CHECK-NOFP-LABEL: test_v11f16:
; CHECK-NOFP: // %bb.0:
; CHECK-NOFP-NEXT: ldr h18, [sp, #8]
; CHECK-NOFP-NEXT: ldr h17, [sp]
; CHECK-NOFP-NEXT: ldr h16, [sp, #16]
; CHECK-NOFP-NEXT: fcvt s1, h1
; CHECK-NOFP-NEXT: fcvt s18, h18
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fcmp s1, s18
; CHECK-NOFP-NEXT: fcvt s17, h17
; CHECK-NOFP-NEXT: adrp x8, .LCPI6_0
; CHECK-NOFP-NEXT: fcsel s1, s1, s18, lt
; CHECK-NOFP-NEXT: fcmp s0, s17
; CHECK-NOFP-NEXT: ldr h18, [x8, :lo12:.LCPI6_0]
; CHECK-NOFP-NEXT: fcsel s0, s0, s17, lt
; CHECK-NOFP-NEXT: fcvt s2, h2
; CHECK-NOFP-NEXT: fcvt s16, h16
; CHECK-NOFP-NEXT: fcvt h1, s1
; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: fcmp s2, s16
; CHECK-NOFP-NEXT: fcvt s1, h1
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fcsel s2, s2, s16, lt
; CHECK-NOFP-NEXT: fminnm s0, s0, s1
; CHECK-NOFP-NEXT: fcvt s3, h3
; CHECK-NOFP-NEXT: mov w8, #2139095040
; CHECK-NOFP-NEXT: fcvt s18, h18
; CHECK-NOFP-NEXT: fcvt h2, s2
; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: fmov s17, w8
; CHECK-NOFP-NEXT: fcmp s3, s18
; CHECK-NOFP-NEXT: fcvt s1, h2
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fcsel s3, s3, s17, lt
; CHECK-NOFP-NEXT: fminnm s0, s0, s1
; CHECK-NOFP-NEXT: fcvt s4, h4
; CHECK-NOFP-NEXT: fcvt h2, s3
; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: fcmp s4, s18
; CHECK-NOFP-NEXT: fcvt s2, h2
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fcsel s3, s4, s17, lt
; CHECK-NOFP-NEXT: fminnm s0, s0, s2
; CHECK-NOFP-NEXT: fcvt s5, h5
; CHECK-NOFP-NEXT: fcvt h3, s3
; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: fcmp s5, s18
; CHECK-NOFP-NEXT: fcvt s3, h3
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fcsel s4, s5, s17, lt
; CHECK-NOFP-NEXT: fminnm s0, s0, s3
; CHECK-NOFP-NEXT: fcvt s6, h6
; CHECK-NOFP-NEXT: fcvt h4, s4
; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: fcmp s6, s18
; CHECK-NOFP-NEXT: fcvt s1, h4
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fcsel s5, s6, s17, lt
; CHECK-NOFP-NEXT: fminnm s0, s0, s1
; CHECK-NOFP-NEXT: fcvt s7, h7
; CHECK-NOFP-NEXT: fcvt h4, s5
; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: fcmp s7, s18
; CHECK-NOFP-NEXT: fcvt s4, h4
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fcsel s5, s7, s17, lt
; CHECK-NOFP-NEXT: fminnm s0, s0, s4
; CHECK-NOFP-NEXT: fcvt h5, s5
; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fcvt s1, h5
; CHECK-NOFP-NEXT: fminnm s0, s0, s1
; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: ret
;
; CHECK-FP-LABEL: test_v11f16:
; CHECK-FP: // %bb.0:
; CHECK-FP-NEXT: movi v16.8h, #124, lsl #8
; CHECK-FP-NEXT: mov x8, sp
; CHECK-FP-NEXT: ld1 { v16.h }[0], [x8]
; CHECK-FP-NEXT: add x8, sp, #8 // =8
; CHECK-FP-NEXT: // kill: def $h0 killed $h0 def $q0
; CHECK-FP-NEXT: // kill: def $h1 killed $h1 def $q1
; CHECK-FP-NEXT: // kill: def $h2 killed $h2 def $q2
; CHECK-FP-NEXT: // kill: def $h3 killed $h3 def $q3
; CHECK-FP-NEXT: // kill: def $h4 killed $h4 def $q4
; CHECK-FP-NEXT: // kill: def $h5 killed $h5 def $q5
; CHECK-FP-NEXT: // kill: def $h6 killed $h6 def $q6
; CHECK-FP-NEXT: // kill: def $h7 killed $h7 def $q7
; CHECK-FP-NEXT: mov v0.h[1], v1.h[0]
; CHECK-FP-NEXT: ld1 { v16.h }[1], [x8]
; CHECK-FP-NEXT: mov v0.h[2], v2.h[0]
; CHECK-FP-NEXT: mov v0.h[3], v3.h[0]
; CHECK-FP-NEXT: add x8, sp, #16 // =16
; CHECK-FP-NEXT: mov v0.h[4], v4.h[0]
; CHECK-FP-NEXT: ld1 { v16.h }[2], [x8]
; CHECK-FP-NEXT: mov v0.h[5], v5.h[0]
; CHECK-FP-NEXT: mov v0.h[6], v6.h[0]
; CHECK-FP-NEXT: mov v0.h[7], v7.h[0]
; CHECK-FP-NEXT: fminnm v0.8h, v0.8h, v16.8h
; CHECK-FP-NEXT: fminnmv h0, v0.8h
; CHECK-FP-NEXT: ret
%b = call nnan half @llvm.vector.reduce.fmin.v11f16(<11 x half> %a)
ret half %b
}
define half @test_v11f16_ninf(<11 x half> %a) nounwind {
; CHECK-NOFP-LABEL: test_v11f16_ninf:
; CHECK-NOFP: // %bb.0:
; CHECK-NOFP-NEXT: ldr h18, [sp, #8]
; CHECK-NOFP-NEXT: ldr h17, [sp]
; CHECK-NOFP-NEXT: ldr h16, [sp, #16]
; CHECK-NOFP-NEXT: fcvt s1, h1
; CHECK-NOFP-NEXT: fcvt s18, h18
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fcmp s1, s18
; CHECK-NOFP-NEXT: fcvt s17, h17
; CHECK-NOFP-NEXT: adrp x8, .LCPI7_0
; CHECK-NOFP-NEXT: fcsel s1, s1, s18, lt
; CHECK-NOFP-NEXT: fcmp s0, s17
; CHECK-NOFP-NEXT: ldr h18, [x8, :lo12:.LCPI7_0]
; CHECK-NOFP-NEXT: fcsel s0, s0, s17, lt
; CHECK-NOFP-NEXT: fcvt s2, h2
; CHECK-NOFP-NEXT: fcvt s16, h16
; CHECK-NOFP-NEXT: fcvt h1, s1
; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: fcmp s2, s16
; CHECK-NOFP-NEXT: fcvt s1, h1
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: mov w8, #57344
; CHECK-NOFP-NEXT: fcsel s2, s2, s16, lt
; CHECK-NOFP-NEXT: fminnm s0, s0, s1
; CHECK-NOFP-NEXT: fcvt s3, h3
; CHECK-NOFP-NEXT: movk w8, #18303, lsl #16
; CHECK-NOFP-NEXT: fcvt s18, h18
; CHECK-NOFP-NEXT: fcvt h2, s2
; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: fmov s17, w8
; CHECK-NOFP-NEXT: fcmp s3, s18
; CHECK-NOFP-NEXT: fcvt s1, h2
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fcsel s3, s3, s17, lt
; CHECK-NOFP-NEXT: fminnm s0, s0, s1
; CHECK-NOFP-NEXT: fcvt s4, h4
; CHECK-NOFP-NEXT: fcvt h2, s3
; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: fcmp s4, s18
; CHECK-NOFP-NEXT: fcvt s2, h2
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fcsel s3, s4, s17, lt
; CHECK-NOFP-NEXT: fminnm s0, s0, s2
; CHECK-NOFP-NEXT: fcvt s5, h5
; CHECK-NOFP-NEXT: fcvt h3, s3
; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: fcmp s5, s18
; CHECK-NOFP-NEXT: fcvt s3, h3
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fcsel s4, s5, s17, lt
; CHECK-NOFP-NEXT: fminnm s0, s0, s3
; CHECK-NOFP-NEXT: fcvt s6, h6
; CHECK-NOFP-NEXT: fcvt h4, s4
; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: fcmp s6, s18
; CHECK-NOFP-NEXT: fcvt s1, h4
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fcsel s5, s6, s17, lt
; CHECK-NOFP-NEXT: fminnm s0, s0, s1
; CHECK-NOFP-NEXT: fcvt s7, h7
; CHECK-NOFP-NEXT: fcvt h4, s5
; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: fcmp s7, s18
; CHECK-NOFP-NEXT: fcvt s4, h4
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fcsel s5, s7, s17, lt
; CHECK-NOFP-NEXT: fminnm s0, s0, s4
; CHECK-NOFP-NEXT: fcvt h5, s5
; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: fcvt s0, h0
; CHECK-NOFP-NEXT: fcvt s1, h5
; CHECK-NOFP-NEXT: fminnm s0, s0, s1
; CHECK-NOFP-NEXT: fcvt h0, s0
; CHECK-NOFP-NEXT: ret
;
; CHECK-FP-LABEL: test_v11f16_ninf:
; CHECK-FP: // %bb.0:
; CHECK-FP-NEXT: mvni v16.8h, #132, lsl #8
; CHECK-FP-NEXT: mov x8, sp
; CHECK-FP-NEXT: ld1 { v16.h }[0], [x8]
; CHECK-FP-NEXT: add x8, sp, #8 // =8
; CHECK-FP-NEXT: // kill: def $h0 killed $h0 def $q0
; CHECK-FP-NEXT: // kill: def $h1 killed $h1 def $q1
; CHECK-FP-NEXT: // kill: def $h2 killed $h2 def $q2
; CHECK-FP-NEXT: // kill: def $h3 killed $h3 def $q3
; CHECK-FP-NEXT: // kill: def $h4 killed $h4 def $q4
; CHECK-FP-NEXT: // kill: def $h5 killed $h5 def $q5
; CHECK-FP-NEXT: // kill: def $h6 killed $h6 def $q6
; CHECK-FP-NEXT: // kill: def $h7 killed $h7 def $q7
; CHECK-FP-NEXT: mov v0.h[1], v1.h[0]
; CHECK-FP-NEXT: ld1 { v16.h }[1], [x8]
; CHECK-FP-NEXT: mov v0.h[2], v2.h[0]
; CHECK-FP-NEXT: mov v0.h[3], v3.h[0]
; CHECK-FP-NEXT: add x8, sp, #16 // =16
; CHECK-FP-NEXT: mov v0.h[4], v4.h[0]
; CHECK-FP-NEXT: ld1 { v16.h }[2], [x8]
; CHECK-FP-NEXT: mov v0.h[5], v5.h[0]
; CHECK-FP-NEXT: mov v0.h[6], v6.h[0]
; CHECK-FP-NEXT: mov v0.h[7], v7.h[0]
; CHECK-FP-NEXT: fminnm v0.8h, v0.8h, v16.8h
; CHECK-FP-NEXT: fminnmv h0, v0.8h
; CHECK-FP-NEXT: ret
%b = call nnan ninf half @llvm.vector.reduce.fmin.v11f16(<11 x half> %a)
ret half %b
}
define float @test_v3f32(<3 x float> %a) nounwind { define float @test_v3f32(<3 x float> %a) nounwind {
; CHECK-LABEL: test_v3f32: ; CHECK-LABEL: test_v3f32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #2139095040 ; CHECK-NEXT: mov w8, #2139095040
; CHECK-NEXT: fmov s1, w8 ; CHECK-NEXT: fmov s1, w8
; CHECK-NEXT: mov v0.s[3], v1.s[0] ; CHECK-NEXT: mov v0.s[3], v1.s[0]
; CHECK-NEXT: fminnmv s0, v0.4s ; CHECK-NEXT: fminnmv s0, v0.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
Show All 35 Lines