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Differential D97827

GlobalISel: Add default implementation of assignValueToReg
ClosedPublic

Authored by arsenm on Mar 2 2021, 6:39 PM.

Details

Reviewers
paquette
aemerson
bogner
aditya_nandakumar
Summary

Refactor insertion of the asserting ops. This enables using them for
AMDGPU.

This code should essentially be the same for every target. Mips, X86
and ARM all have different code there now, but this seems to be an
accident. The assignment functions are called with different types
than they would be in the DAG, so this is all likely an assortment of
hacks to get around that.

Diff Detail

Event Timeline

arsenm created this revision.Mar 2 2021, 6:39 PM
Herald added subscribers: kerbowa, pengfei, atanasyan and 8 others. · View Herald TranscriptMar 2 2021, 6:39 PM
arsenm requested review of this revision.Mar 2 2021, 6:39 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 2 2021, 6:39 PM
Herald added a subscriber: wdng. · View Herald Transcript
aemerson accepted this revision.Mar 2 2021, 9:56 PM
aemerson added inline comments.
llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
214

Should say "based on \p VA" since that has the information needed.

This revision is now accepted and ready to land.Mar 2 2021, 9:56 PM
foad added a subscriber: foad.Mar 2 2021, 10:26 PM
foad added inline comments.
llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
213

One of those ZEXT should be SEXT?

Harbormaster completed remote builds in B91715: Diff 327647.Mar 2 2021, 11:27 PM
arsenm closed this revision.Mar 3 2021, 6:34 AM
arsenm marked 2 inline comments as done.

78dcff484120d6e162bc139e0198b59ec08568b0

Revision Contents

PathSize
llvm/
include/
llvm/
CodeGen/
GlobalISel/
8 lines
lib/
CodeGen/
GlobalISel/
38 lines
Target/
AArch64/
GISel/
29 lines
AMDGPU/
63 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
48 lines
5 lines

Diff 327647

llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h

Show First 20 Lines • Show All 203 Lines • ▼ Show 20 Lines private:
bool IsIncomingArgumentHandler; bool IsIncomingArgumentHandler;
virtual void anchor(); virtual void anchor();
}; };
struct IncomingValueHandler : public ValueHandler { struct IncomingValueHandler : public ValueHandler {
IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
CCAssignFn *AssignFn) CCAssignFn *AssignFn)
: ValueHandler(true, MIRBuilder, MRI, AssignFn) {} : ValueHandler(true, MIRBuilder, MRI, AssignFn) {}
/// Insert G_ASSERT_ZEXT/G_ASSERT_ZEXT or other hint instruction based on \p
foadUnsubmitted
Done
ReplyInline Actions

One of those ZEXT should be SEXT?

foad: One of those ZEXT should be SEXT?
/// SrcReg, returning the new register if a hint was inserted.
aemersonUnsubmitted
Done
ReplyInline Actions

Should say "based on \p VA" since that has the information needed.

aemerson: Should say "based on \p VA" since that has the information needed.
Register buildExtensionHint(CCValAssign &VA, Register SrcReg, LLT NarrowTy);
/// Provides a default implementation for argument handling.
void assignValueToReg(Register ValVReg, Register PhysReg,
CCValAssign &VA) override;
}; };
struct OutgoingValueHandler : public ValueHandler { struct OutgoingValueHandler : public ValueHandler {
OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
CCAssignFn *AssignFn) CCAssignFn *AssignFn)
: ValueHandler(false, MIRBuilder, MRI, AssignFn) {} : ValueHandler(false, MIRBuilder, MRI, AssignFn) {}
}; };
▲ Show 20 Lines • Show All 247 Lines • Show Last 20 Lines

llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

Show First 20 Lines • Show All 979 Lines • ▼ Show 20 Lines case CCValAssign::ZExt: {
MIRBuilder.buildZExt(NewReg, ValReg); MIRBuilder.buildZExt(NewReg, ValReg);
return NewReg; return NewReg;
} }
} }
llvm_unreachable("unable to extend register"); llvm_unreachable("unable to extend register");
} }
void CallLowering::ValueHandler::anchor() {} void CallLowering::ValueHandler::anchor() {}
Register CallLowering::IncomingValueHandler::buildExtensionHint(CCValAssign &VA,
Register SrcReg,
LLT NarrowTy) {
switch (VA.getLocInfo()) {
case CCValAssign::LocInfo::ZExt: {
return MIRBuilder
.buildAssertZExt(MRI.cloneVirtualRegister(SrcReg), SrcReg,
NarrowTy.getScalarSizeInBits())
.getReg(0);
}
case CCValAssign::LocInfo::SExt: {
return MIRBuilder
.buildAssertSExt(MRI.cloneVirtualRegister(SrcReg), SrcReg,
NarrowTy.getScalarSizeInBits())
.getReg(0);
break;
}
default:
return SrcReg;
}
}
void CallLowering::IncomingValueHandler::assignValueToReg(Register ValVReg,
Register PhysReg,
CCValAssign &VA) {
const LLT LocTy(VA.getLocVT());
const LLT ValTy = MRI.getType(ValVReg);
if (ValTy.getSizeInBits() == LocTy.getSizeInBits()) {
MIRBuilder.buildCopy(ValVReg, PhysReg);
return;
}
auto Copy = MIRBuilder.buildCopy(LocTy, PhysReg);
auto Hint = buildExtensionHint(VA, Copy.getReg(0), ValTy);
MIRBuilder.buildTrunc(ValVReg, Hint);
}

llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp

Show First 20 Lines • Show All 64 Lines • ▼ Show 20 Lines Register getStackAddress(uint64_t Size, int64_t Offset,
auto AddrReg = MIRBuilder.buildFrameIndex(LLT::pointer(0, 64), FI); auto AddrReg = MIRBuilder.buildFrameIndex(LLT::pointer(0, 64), FI);
StackUsed = std::max(StackUsed, Size + Offset); StackUsed = std::max(StackUsed, Size + Offset);
return AddrReg.getReg(0); return AddrReg.getReg(0);
} }
void assignValueToReg(Register ValVReg, Register PhysReg, void assignValueToReg(Register ValVReg, Register PhysReg,
CCValAssign &VA) override { CCValAssign &VA) override {
markPhysRegUsed(PhysReg); markPhysRegUsed(PhysReg);
switch (VA.getLocInfo()) { IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
default:
MIRBuilder.buildCopy(ValVReg, PhysReg);
break;
case CCValAssign::LocInfo::ZExt: {
auto WideTy = LLT{VA.getLocVT()};
auto NarrowTy = MRI.getType(ValVReg);
MIRBuilder.buildTrunc(ValVReg,
MIRBuilder.buildAssertZExt(
WideTy, MIRBuilder.buildCopy(WideTy, PhysReg),
NarrowTy.getSizeInBits()));
break;
}
case CCValAssign::LocInfo::SExt: {
auto WideTy = LLT{VA.getLocVT()};
auto NarrowTy = MRI.getType(ValVReg);
MIRBuilder.buildTrunc(ValVReg,
MIRBuilder.buildAssertSExt(
WideTy, MIRBuilder.buildCopy(WideTy, PhysReg),
NarrowTy.getSizeInBits()));
break;
}
case CCValAssign::LocInfo::AExt: {
auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
MIRBuilder.buildTrunc(ValVReg, Copy);
break;
}
}
} }
void assignValueToAddress(Register ValVReg, Register Addr, uint64_t MemSize, void assignValueToAddress(Register ValVReg, Register Addr, uint64_t MemSize,
MachinePointerInfo &MPO, CCValAssign &VA) override { MachinePointerInfo &MPO, CCValAssign &VA) override {
MachineFunction &MF = MIRBuilder.getMF(); MachineFunction &MF = MIRBuilder.getMF();
// The reported memory location may be wider than the value. // The reported memory location may be wider than the value.
const LLT RegTy = MRI.getType(ValVReg); const LLT RegTy = MRI.getType(ValVReg);
▲ Show 20 Lines • Show All 955 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp

Show All 23 Lines
#include "llvm/IR/IntrinsicsAMDGPU.h" #include "llvm/IR/IntrinsicsAMDGPU.h"
#define DEBUG_TYPE "amdgpu-call-lowering" #define DEBUG_TYPE "amdgpu-call-lowering"
using namespace llvm; using namespace llvm;
namespace { namespace {
struct AMDGPUValueHandler : public CallLowering::ValueHandler { /// Wrapper around extendRegister to ensure we extend to a full 32-bit register.
AMDGPUValueHandler(bool IsIncoming, MachineIRBuilder &B, static Register extendRegisterMin32(CallLowering::ValueHandler &Handler,
MachineRegisterInfo &MRI, CCAssignFn *AssignFn) Register ValVReg, CCValAssign &VA) {
: ValueHandler(IsIncoming, B, MRI, AssignFn) {}
/// Wrapper around extendRegister to ensure we extend to a full 32-bit
/// register.
Register extendRegisterMin32(Register ValVReg, CCValAssign &VA) {
if (VA.getLocVT().getSizeInBits() < 32) { if (VA.getLocVT().getSizeInBits() < 32) {
// 16-bit types are reported as legal for 32-bit registers. We need to // 16-bit types are reported as legal for 32-bit registers. We need to
// extend and do a 32-bit copy to avoid the verifier complaining about it. // extend and do a 32-bit copy to avoid the verifier complaining about it.
return MIRBuilder.buildAnyExt(LLT::scalar(32), ValVReg).getReg(0); return Handler.MIRBuilder.buildAnyExt(LLT::scalar(32), ValVReg).getReg(0);
} }
return extendRegister(ValVReg, VA); return Handler.extendRegister(ValVReg, VA);
} }
};
struct AMDGPUOutgoingValueHandler : public AMDGPUValueHandler { struct AMDGPUOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
AMDGPUOutgoingValueHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI, AMDGPUOutgoingValueHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI,
MachineInstrBuilder MIB, CCAssignFn *AssignFn) MachineInstrBuilder MIB, CCAssignFn *AssignFn)
: AMDGPUValueHandler(false, B, MRI, AssignFn), MIB(MIB) {} : OutgoingValueHandler(B, MRI, AssignFn), MIB(MIB) {}
MachineInstrBuilder MIB; MachineInstrBuilder MIB;
Register getStackAddress(uint64_t Size, int64_t Offset, Register getStackAddress(uint64_t Size, int64_t Offset,
MachinePointerInfo &MPO) override { MachinePointerInfo &MPO) override {
llvm_unreachable("not implemented"); llvm_unreachable("not implemented");
} }
void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size, void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
MachinePointerInfo &MPO, CCValAssign &VA) override { MachinePointerInfo &MPO, CCValAssign &VA) override {
llvm_unreachable("not implemented"); llvm_unreachable("not implemented");
} }
void assignValueToReg(Register ValVReg, Register PhysReg, void assignValueToReg(Register ValVReg, Register PhysReg,
CCValAssign &VA) override { CCValAssign &VA) override {
Register ExtReg = extendRegisterMin32(ValVReg, VA); Register ExtReg = extendRegisterMin32(*this, ValVReg, VA);
// If this is a scalar return, insert a readfirstlane just in case the value // If this is a scalar return, insert a readfirstlane just in case the value
// ends up in a VGPR. // ends up in a VGPR.
// FIXME: Assert this is a shader return. // FIXME: Assert this is a shader return.
const SIRegisterInfo *TRI const SIRegisterInfo *TRI
= static_cast<const SIRegisterInfo *>(MRI.getTargetRegisterInfo()); = static_cast<const SIRegisterInfo *>(MRI.getTargetRegisterInfo());
if (TRI->isSGPRReg(MRI, PhysReg)) { if (TRI->isSGPRReg(MRI, PhysReg)) {
auto ToSGPR = MIRBuilder.buildIntrinsic(Intrinsic::amdgcn_readfirstlane, auto ToSGPR = MIRBuilder.buildIntrinsic(Intrinsic::amdgcn_readfirstlane,
Show All 10 Lines bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
CCValAssign::LocInfo LocInfo, CCValAssign::LocInfo LocInfo,
const CallLowering::ArgInfo &Info, const CallLowering::ArgInfo &Info,
ISD::ArgFlagsTy Flags, ISD::ArgFlagsTy Flags,
CCState &State) override { CCState &State) override {
return AssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State); return AssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State);
} }
}; };
struct AMDGPUIncomingArgHandler : public AMDGPUValueHandler { struct AMDGPUIncomingArgHandler : public CallLowering::IncomingValueHandler {
uint64_t StackUsed = 0; uint64_t StackUsed = 0;
AMDGPUIncomingArgHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI, AMDGPUIncomingArgHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI,
CCAssignFn *AssignFn) CCAssignFn *AssignFn)
: AMDGPUValueHandler(true, B, MRI, AssignFn) {} : IncomingValueHandler(B, MRI, AssignFn) {}
Register getStackAddress(uint64_t Size, int64_t Offset, Register getStackAddress(uint64_t Size, int64_t Offset,
MachinePointerInfo &MPO) override { MachinePointerInfo &MPO) override {
auto &MFI = MIRBuilder.getMF().getFrameInfo(); auto &MFI = MIRBuilder.getMF().getFrameInfo();
int FI = MFI.CreateFixedObject(Size, Offset, true); int FI = MFI.CreateFixedObject(Size, Offset, true);
MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI); MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
auto AddrReg = MIRBuilder.buildFrameIndex( auto AddrReg = MIRBuilder.buildFrameIndex(
LLT::pointer(AMDGPUAS::PRIVATE_ADDRESS, 32), FI); LLT::pointer(AMDGPUAS::PRIVATE_ADDRESS, 32), FI);
StackUsed = std::max(StackUsed, Size + Offset); StackUsed = std::max(StackUsed, Size + Offset);
return AddrReg.getReg(0); return AddrReg.getReg(0);
} }
void assignValueToReg(Register ValVReg, Register PhysReg, void assignValueToReg(Register ValVReg, Register PhysReg,
CCValAssign &VA) override { CCValAssign &VA) override {
markPhysRegUsed(PhysReg); markPhysRegUsed(PhysReg);
if (VA.getLocVT().getSizeInBits() < 32) { if (VA.getLocVT().getSizeInBits() < 32) {
// 16-bit types are reported as legal for 32-bit registers. We need to do // 16-bit types are reported as legal for 32-bit registers. We need to do
// a 32-bit copy, and truncate to avoid the verifier complaining about it. // a 32-bit copy, and truncate to avoid the verifier complaining about it.
auto Copy = MIRBuilder.buildCopy(LLT::scalar(32), PhysReg); auto Copy = MIRBuilder.buildCopy(LLT::scalar(32), PhysReg);
MIRBuilder.buildTrunc(ValVReg, Copy);
// If we have signext/zeroext, it applies to the whole 32-bit register
// before truncation.
auto Extended =
buildExtensionHint(VA, Copy.getReg(0), LLT(VA.getLocVT()));
MIRBuilder.buildTrunc(ValVReg, Extended);
return; return;
} }
switch (VA.getLocInfo()) { IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
case CCValAssign::LocInfo::SExt:
case CCValAssign::LocInfo::ZExt:
case CCValAssign::LocInfo::AExt: {
auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
MIRBuilder.buildTrunc(ValVReg, Copy);
break;
}
default:
MIRBuilder.buildCopy(ValVReg, PhysReg);
break;
}
} }
void assignValueToAddress(Register ValVReg, Register Addr, uint64_t MemSize, void assignValueToAddress(Register ValVReg, Register Addr, uint64_t MemSize,
MachinePointerInfo &MPO, CCValAssign &VA) override { MachinePointerInfo &MPO, CCValAssign &VA) override {
MachineFunction &MF = MIRBuilder.getMF(); MachineFunction &MF = MIRBuilder.getMF();
// The reported memory location may be wider than the value. // The reported memory location may be wider than the value.
const LLT RegTy = MRI.getType(ValVReg); const LLT RegTy = MRI.getType(ValVReg);
Show All 29 Linesstruct CallReturnHandler : public AMDGPUIncomingArgHandler {
void markPhysRegUsed(unsigned PhysReg) override { void markPhysRegUsed(unsigned PhysReg) override {
MIB.addDef(PhysReg, RegState::Implicit); MIB.addDef(PhysReg, RegState::Implicit);
} }
MachineInstrBuilder MIB; MachineInstrBuilder MIB;
}; };
struct AMDGPUOutgoingArgHandler : public AMDGPUValueHandler { struct AMDGPUOutgoingArgHandler : public AMDGPUOutgoingValueHandler {
MachineInstrBuilder MIB;
CCAssignFn *AssignFnVarArg; CCAssignFn *AssignFnVarArg;
/// For tail calls, the byte offset of the call's argument area from the /// For tail calls, the byte offset of the call's argument area from the
/// callee's. Unused elsewhere. /// callee's. Unused elsewhere.
int FPDiff; int FPDiff;
// Cache the SP register vreg if we need it more than once in this call site. // Cache the SP register vreg if we need it more than once in this call site.
Register SPReg; Register SPReg;
bool IsTailCall; bool IsTailCall;
AMDGPUOutgoingArgHandler(MachineIRBuilder &MIRBuilder, AMDGPUOutgoingArgHandler(MachineIRBuilder &MIRBuilder,
MachineRegisterInfo &MRI, MachineInstrBuilder MIB, MachineRegisterInfo &MRI, MachineInstrBuilder MIB,
CCAssignFn *AssignFn, CCAssignFn *AssignFnVarArg, CCAssignFn *AssignFn, CCAssignFn *AssignFnVarArg,
bool IsTailCall = false, int FPDiff = 0) bool IsTailCall = false, int FPDiff = 0)
: AMDGPUValueHandler(false, MIRBuilder, MRI, AssignFn), MIB(MIB), : AMDGPUOutgoingValueHandler(MIRBuilder, MRI, MIB, AssignFn),
AssignFnVarArg(AssignFnVarArg), FPDiff(FPDiff), IsTailCall(IsTailCall) { AssignFnVarArg(AssignFnVarArg), FPDiff(FPDiff), IsTailCall(IsTailCall) {
} }
Register getStackAddress(uint64_t Size, int64_t Offset, Register getStackAddress(uint64_t Size, int64_t Offset,
MachinePointerInfo &MPO) override { MachinePointerInfo &MPO) override {
MachineFunction &MF = MIRBuilder.getMF(); MachineFunction &MF = MIRBuilder.getMF();
const LLT PtrTy = LLT::pointer(AMDGPUAS::PRIVATE_ADDRESS, 32); const LLT PtrTy = LLT::pointer(AMDGPUAS::PRIVATE_ADDRESS, 32);
const LLT S32 = LLT::scalar(32); const LLT S32 = LLT::scalar(32);
Show All 12 Lines Register getStackAddress(uint64_t Size, int64_t Offset,
auto AddrReg = MIRBuilder.buildPtrAdd(PtrTy, SPReg, OffsetReg); auto AddrReg = MIRBuilder.buildPtrAdd(PtrTy, SPReg, OffsetReg);
MPO = MachinePointerInfo::getStack(MF, Offset); MPO = MachinePointerInfo::getStack(MF, Offset);
return AddrReg.getReg(0); return AddrReg.getReg(0);
} }
void assignValueToReg(Register ValVReg, Register PhysReg, void assignValueToReg(Register ValVReg, Register PhysReg,
CCValAssign &VA) override { CCValAssign &VA) override {
MIB.addUse(PhysReg, RegState::Implicit); MIB.addUse(PhysReg, RegState::Implicit);
Register ExtReg = extendRegisterMin32(ValVReg, VA); Register ExtReg = extendRegisterMin32(*this, ValVReg, VA);
MIRBuilder.buildCopy(PhysReg, ExtReg); MIRBuilder.buildCopy(PhysReg, ExtReg);
} }
void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size, void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
MachinePointerInfo &MPO, CCValAssign &VA) override { MachinePointerInfo &MPO, CCValAssign &VA) override {
MachineFunction &MF = MIRBuilder.getMF(); MachineFunction &MF = MIRBuilder.getMF();
uint64_t LocMemOffset = VA.getLocMemOffset(); uint64_t LocMemOffset = VA.getLocMemOffset();
const auto &ST = MF.getSubtarget<GCNSubtarget>(); const auto &ST = MF.getSubtarget<GCNSubtarget>();
▲ Show 20 Lines • Show All 850 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Linesdefine void @void_func_i1(i1 %arg0) #0 {
ret void ret void
} }
define void @void_func_i1_zeroext(i1 zeroext %arg0) #0 { define void @void_func_i1_zeroext(i1 zeroext %arg0) #0 {
; CHECK-LABEL: name: void_func_i1_zeroext ; CHECK-LABEL: name: void_func_i1_zeroext
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $vgpr0, $sgpr30_sgpr31 ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32) ; CHECK: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 1
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ASSERT_ZEXT]](s32)
; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s1) ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s1)
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ZEXT]], [[C]] ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ZEXT]], [[C]]
; CHECK: G_STORE [[ADD]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1) ; CHECK: G_STORE [[ADD]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]] ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
; CHECK: S_SETPC_B64_return [[COPY2]] ; CHECK: S_SETPC_B64_return [[COPY2]]
%ext = zext i1 %arg0 to i32 %ext = zext i1 %arg0 to i32
%add = add i32 %ext, 12 %add = add i32 %ext, 12
store i32 %add, i32 addrspace(1)* undef store i32 %add, i32 addrspace(1)* undef
ret void ret void
} }
define void @void_func_i1_signext(i1 signext %arg0) #0 { define void @void_func_i1_signext(i1 signext %arg0) #0 {
; CHECK-LABEL: name: void_func_i1_signext ; CHECK-LABEL: name: void_func_i1_signext
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $vgpr0, $sgpr30_sgpr31 ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32) ; CHECK: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 1
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ASSERT_SEXT]](s32)
; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC]](s1) ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC]](s1)
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT]], [[C]] ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT]], [[C]]
; CHECK: G_STORE [[ADD]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1) ; CHECK: G_STORE [[ADD]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]] ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
; CHECK: S_SETPC_B64_return [[COPY2]] ; CHECK: S_SETPC_B64_return [[COPY2]]
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Linesdefine void @void_func_i8(i8 %arg0) #0 {
ret void ret void
} }
define void @void_func_i8_zeroext(i8 zeroext %arg0) #0 { define void @void_func_i8_zeroext(i8 zeroext %arg0) #0 {
; CHECK-LABEL: name: void_func_i8_zeroext ; CHECK-LABEL: name: void_func_i8_zeroext
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $vgpr0, $sgpr30_sgpr31 ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) ; CHECK: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 8
; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_ZEXT]](s32)
; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s8) ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s8)
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ZEXT]], [[C]] ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ZEXT]], [[C]]
; CHECK: G_STORE [[ADD]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1) ; CHECK: G_STORE [[ADD]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]] ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
; CHECK: S_SETPC_B64_return [[COPY2]] ; CHECK: S_SETPC_B64_return [[COPY2]]
%ext = zext i8 %arg0 to i32 %ext = zext i8 %arg0 to i32
%add = add i32 %ext, 12 %add = add i32 %ext, 12
store i32 %add, i32 addrspace(1)* undef store i32 %add, i32 addrspace(1)* undef
ret void ret void
} }
define void @void_func_i8_signext(i8 signext %arg0) #0 { define void @void_func_i8_signext(i8 signext %arg0) #0 {
; CHECK-LABEL: name: void_func_i8_signext ; CHECK-LABEL: name: void_func_i8_signext
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $vgpr0, $sgpr30_sgpr31 ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) ; CHECK: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 8
; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_SEXT]](s32)
; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC]](s8) ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC]](s8)
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT]], [[C]] ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT]], [[C]]
; CHECK: G_STORE [[ADD]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1) ; CHECK: G_STORE [[ADD]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]] ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
; CHECK: S_SETPC_B64_return [[COPY2]] ; CHECK: S_SETPC_B64_return [[COPY2]]
Show All 18 Linesdefine void @void_func_i16(i16 %arg0) #0 {
ret void ret void
} }
define void @void_func_i16_zeroext(i16 zeroext %arg0) #0 { define void @void_func_i16_zeroext(i16 zeroext %arg0) #0 {
; CHECK-LABEL: name: void_func_i16_zeroext ; CHECK-LABEL: name: void_func_i16_zeroext
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $vgpr0, $sgpr30_sgpr31 ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; CHECK: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_ZEXT]](s32)
; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16) ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16)
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ZEXT]], [[C]] ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ZEXT]], [[C]]
; CHECK: G_STORE [[ADD]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1) ; CHECK: G_STORE [[ADD]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]] ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
; CHECK: S_SETPC_B64_return [[COPY2]] ; CHECK: S_SETPC_B64_return [[COPY2]]
%ext = zext i16 %arg0 to i32 %ext = zext i16 %arg0 to i32
%add = add i32 %ext, 12 %add = add i32 %ext, 12
store i32 %add, i32 addrspace(1)* undef store i32 %add, i32 addrspace(1)* undef
ret void ret void
} }
define void @void_func_i16_signext(i16 signext %arg0) #0 { define void @void_func_i16_signext(i16 signext %arg0) #0 {
; CHECK-LABEL: name: void_func_i16_signext ; CHECK-LABEL: name: void_func_i16_signext
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $vgpr0, $sgpr30_sgpr31 ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; CHECK: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 16
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_SEXT]](s32)
; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC]](s16) ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC]](s16)
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT]], [[C]] ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT]], [[C]]
; CHECK: G_STORE [[ADD]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1) ; CHECK: G_STORE [[ADD]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]] ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
; CHECK: S_SETPC_B64_return [[COPY2]] ; CHECK: S_SETPC_B64_return [[COPY2]]
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Linesdefine void @void_func_i32(i32 %arg0) #0 {
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: G_STORE [[COPY]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1) ; CHECK: G_STORE [[COPY]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]] ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
; CHECK: S_SETPC_B64_return [[COPY2]] ; CHECK: S_SETPC_B64_return [[COPY2]]
store i32 %arg0, i32 addrspace(1)* undef store i32 %arg0, i32 addrspace(1)* undef
ret void ret void
} }
; The signext is an no-op
define void @void_func_i32_signext(i32 signext %arg0) #0 {
; CHECK-LABEL: name: void_func_i32_signext
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: G_STORE [[COPY]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
; CHECK: S_SETPC_B64_return [[COPY2]]
store i32 %arg0, i32 addrspace(1)* undef
ret void
}
; The zeroext is an no-op
define void @void_func_i32_zeroext(i32 zeroext %arg0) #0 {
; CHECK-LABEL: name: void_func_i32_zeroext
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: G_STORE [[COPY]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
; CHECK: S_SETPC_B64_return [[COPY2]]
store i32 %arg0, i32 addrspace(1)* undef
ret void
}
define void @void_func_p3i8(i8 addrspace(3)* %arg0) #0 { define void @void_func_p3i8(i8 addrspace(3)* %arg0) #0 {
; CHECK-LABEL: name: void_func_p3i8 ; CHECK-LABEL: name: void_func_p3i8
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $vgpr0, $sgpr30_sgpr31 ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: G_STORE [[COPY]](p3), [[DEF]](p1) :: (store 4 into `i8 addrspace(3)* addrspace(1)* undef`, addrspace 1) ; CHECK: G_STORE [[COPY]](p3), [[DEF]](p1) :: (store 4 into `i8 addrspace(3)* addrspace(1)* undef`, addrspace 1)
▲ Show 20 Lines • Show All 2,321 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll

Show First 20 Lines • Show All 79 Lines • ▼ Show 20 Lines; GFX9-NEXT: ; return to shader part epilog
%result = mul i16 %num, %den %result = mul i16 %num, %den
ret i16 %result ret i16 %result
} }
define zeroext i16 @v_mul_i16_zeroext(i16 zeroext %num, i16 zeroext %den) { define zeroext i16 @v_mul_i16_zeroext(i16 zeroext %num, i16 zeroext %den) {
; GFX7-LABEL: v_mul_i16_zeroext: ; GFX7-LABEL: v_mul_i16_zeroext:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: s_mov_b32 s4, 0xffff
; GFX7-NEXT: v_and_b32_e32 v0, s4, v0
; GFX7-NEXT: v_and_b32_e32 v1, s4, v1
; GFX7-NEXT: v_mul_u32_u24_e32 v0, v0, v1 ; GFX7-NEXT: v_mul_u32_u24_e32 v0, v0, v1
; GFX7-NEXT: v_and_b32_e32 v0, s4, v0 ; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-NEXT: s_setpc_b64 s[30:31] ; GFX7-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-LABEL: v_mul_i16_zeroext: ; GFX8-LABEL: v_mul_i16_zeroext:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mul_lo_u16_e32 v0, v0, v1 ; GFX8-NEXT: v_mul_lo_u16_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-NEXT: s_setpc_b64 s[30:31]
; ;
▲ Show 20 Lines • Show All 2,133 Lines • Show Last 20 Lines