[AMDGPU] Make OMod explicit for V_CVT_{U,I}*

[Joe_Nash]

Summary

Make OMod explicit instead of implied by HasModifiers in the
operand list. Requires explicitly setting HasOMod=1 for
irregular OMod usage in instruction V_CVT_{U,I}*

[Joe_Nash]

remove erroneous addition of OMod to cvt_flr_i32_f32 &
cvt_rpi_i32_f32

[foad]

LGTM since these instructions are documented as supporting OMOD.

llvm/lib/Target/AMDGPU/SIInstrInfo.td

1626–1630

Not really related to your patch, but couldn't we clean up all these nested !ifs by using a big !con of little fragments like !if(HasOMod, (ins omod0:$omod), (ins))?

llvm/lib/Target/AMDGPU/SIInstrInfo.td

class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
   dag ret =
     !if (!eq(NumSrcArgs, 0),
       // VOP1 without input operands (V_NOP, V_CLREXCP)
       (ins),
       /* else */
     !if (!eq(NumSrcArgs, 1),
       !if (HasModifiers,
         // VOP1 with modifiers
+        !if(HasOMod,
+          (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
+               clampmod0:$clamp, omod0:$omod),
           (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
-             clampmod0:$clamp, omod0:$omod)
+               clampmod0:$clamp))
       /* else */,
         // VOP1 without modifiers
         !if (HasClamp,
           (ins Src0RC:$src0, clampmod0:$clamp),
           (ins Src0RC:$src0))
       /* endif */ ),
     !if (!eq(NumSrcArgs, 2),
       !if (HasModifiers,

llvm/lib/Target/AMDGPU/VOP1Instructions.td

class VOPProfileI2F<ValueType dstVt, ValueType srcVt> :
   let HasModifiers = 0;
   let HasClamp = 1;
 }
 
 def VOP1_F64_I32 : VOPProfileI2F <f64, i32>;
 def VOP1_F32_I32 : VOPProfileI2F <f32, i32>;
 def VOP1_F16_I16 : VOPProfileI2F <f16, i16>;
 
+class VOP_SPECIAL_OMOD_PROF<ValueType dstVt, ValueType srcVt> :
+  VOPProfile<[dstVt, srcVt, untyped, untyped]> {
+
+  let HasOMod = 1;
+}
+def VOP_I32_F32_SPECIAL_OMOD : VOP_SPECIAL_OMOD_PROF<i32, f32>;
+def VOP_I32_F64_SPECIAL_OMOD : VOP_SPECIAL_OMOD_PROF<i32, f64>;
+def VOP_I16_F16_SPECIAL_OMOD : VOP_SPECIAL_OMOD_PROF<i16, f16>;
+
 //===----------------------------------------------------------------------===//
 // VOP1 Instructions
 //===----------------------------------------------------------------------===//
 
 let VOPAsmPrefer32Bit = 1 in {
 defm V_NOP : VOP1Inst <"v_nop", VOP_NONE>;
 }
 
def V_READFIRSTLANE_B32 :
 
   let Inst{8-0}   = src0;
   let Inst{16-9}  = 0x2;
   let Inst{24-17} = vdst;
   let Inst{31-25} = 0x3f; //encoding
 }
 
 let SchedRW = [WriteDoubleCvt] in {
-defm V_CVT_I32_F64 : VOP1Inst <"v_cvt_i32_f64", VOP_I32_F64,  fp_to_sint>;
+// OMod clears exceptions when set in this instruction
+defm V_CVT_I32_F64 : VOP1Inst <"v_cvt_i32_f64", VOP_I32_F64_SPECIAL_OMOD,  fp_to_sint>;
 
 let mayRaiseFPException = 0 in {
 defm V_CVT_F64_I32 : VOP1Inst <"v_cvt_f64_i32", VOP1_F64_I32, sint_to_fp>;
 }
 
 defm V_CVT_F32_F64 : VOP1Inst <"v_cvt_f32_f64", VOP_F32_F64,  fpround>;
 defm V_CVT_F64_F32 : VOP1Inst <"v_cvt_f64_f32", VOP_F64_F32,  fpextend>;
-defm V_CVT_U32_F64 : VOP1Inst <"v_cvt_u32_f64", VOP_I32_F64,  fp_to_uint>;
+// OMod clears exceptions when set in this instruction
+defm V_CVT_U32_F64 : VOP1Inst <"v_cvt_u32_f64", VOP_I32_F64_SPECIAL_OMOD,  fp_to_uint>;
 
 let mayRaiseFPException = 0 in {
 defm V_CVT_F64_U32 : VOP1Inst <"v_cvt_f64_u32", VOP1_F64_I32, uint_to_fp>;
 }
 
 } // End SchedRW = [WriteDoubleCvt]
 
 let SchedRW = [WriteFloatCvt] in {
 
 // XXX: Does this really not raise exceptions? The manual claims the
 // 16-bit ones can.
 let mayRaiseFPException = 0 in {
 defm V_CVT_F32_I32 : VOP1Inst <"v_cvt_f32_i32", VOP1_F32_I32, sint_to_fp>;
 defm V_CVT_F32_U32 : VOP1Inst <"v_cvt_f32_u32", VOP1_F32_I32, uint_to_fp>;
 }
 
-defm V_CVT_U32_F32 : VOP1Inst <"v_cvt_u32_f32", VOP_I32_F32, fp_to_uint>;
-defm V_CVT_I32_F32 : VOP1Inst <"v_cvt_i32_f32", VOP_I32_F32, fp_to_sint>;
+// OMod clears exceptions when set in these 2 instructions
+defm V_CVT_U32_F32 : VOP1Inst <"v_cvt_u32_f32", VOP_I32_F32_SPECIAL_OMOD, fp_to_uint>;
+defm V_CVT_I32_F32 : VOP1Inst <"v_cvt_i32_f32", VOP_I32_F32_SPECIAL_OMOD, fp_to_sint>;
 let FPDPRounding = 1 in {
 defm V_CVT_F16_F32 : VOP1Inst <"v_cvt_f16_f32", VOP_F16_F32, fpround>;
 } // End FPDPRounding = 1
 
 defm V_CVT_F32_F16 : VOP1Inst <"v_cvt_f32_f16", VOP_F32_F16, fpextend>;
 
 let ReadsModeReg = 0, mayRaiseFPException = 0 in {
 defm V_CVT_RPI_I32_F32 : VOP1Inst <"v_cvt_rpi_i32_f32", VOP_I32_F32, cvt_rpi_i32_f32>;

 
 defm V_NOT_B32 : VOP1Inst <"v_not_b32", VOP_I32_I32>;
 defm V_BFREV_B32 : VOP1Inst <"v_bfrev_b32", VOP_I32_I32, bitreverse>;
 defm V_FFBH_U32 : VOP1Inst <"v_ffbh_u32", VOP_I32_I32, AMDGPUffbh_u32>;
 defm V_FFBL_B32 : VOP1Inst <"v_ffbl_b32", VOP_I32_I32, AMDGPUffbl_b32>;
 defm V_FFBH_I32 : VOP1Inst <"v_ffbh_i32", VOP_I32_I32, AMDGPUffbh_i32>;
 
 let SchedRW = [WriteDoubleAdd] in {
-defm V_FREXP_EXP_I32_F64 : VOP1Inst <"v_frexp_exp_i32_f64", VOP_I32_F64, int_amdgcn_frexp_exp>;
+defm V_FREXP_EXP_I32_F64 : VOP1Inst <"v_frexp_exp_i32_f64", VOP_I32_F64_SPECIAL_OMOD, int_amdgcn_frexp_exp>;
 defm V_FREXP_MANT_F64 : VOP1Inst <"v_frexp_mant_f64", VOP_F64_F64, int_amdgcn_frexp_mant>;
 let FPDPRounding = 1 in {
 defm V_FRACT_F64 : VOP1Inst <"v_fract_f64", VOP_F64_F64, AMDGPUfract>;
 } // End FPDPRounding = 1
 } // End SchedRW = [WriteDoubleAdd]
 
 defm V_FREXP_EXP_I32_F32 : VOP1Inst <"v_frexp_exp_i32_f32", VOP_I32_F32, int_amdgcn_frexp_exp>;
 defm V_FREXP_MANT_F32 : VOP1Inst <"v_frexp_mant_f32", VOP_F32_F32, int_amdgcn_frexp_mant>;

 } // End SubtargetPredicate = isGFX7Plus
 
 let SubtargetPredicate = Has16BitInsts in {
 
 let FPDPRounding = 1 in {
 defm V_CVT_F16_U16 : VOP1Inst <"v_cvt_f16_u16", VOP1_F16_I16, uint_to_fp>;
 defm V_CVT_F16_I16 : VOP1Inst <"v_cvt_f16_i16", VOP1_F16_I16, sint_to_fp>;
 } // End FPDPRounding = 1
-defm V_CVT_U16_F16 : VOP1Inst <"v_cvt_u16_f16", VOP_I16_F16, fp_to_uint>;
-defm V_CVT_I16_F16 : VOP1Inst <"v_cvt_i16_f16", VOP_I16_F16, fp_to_sint>;
+// OMod clears exceptions when set in these two instructions
+defm V_CVT_U16_F16 : VOP1Inst <"v_cvt_u16_f16", VOP_I16_F16_SPECIAL_OMOD, fp_to_uint>;
+defm V_CVT_I16_F16 : VOP1Inst <"v_cvt_i16_f16", VOP_I16_F16_SPECIAL_OMOD, fp_to_sint>;
 let TRANS = 1, SchedRW = [WriteTrans32] in {
 defm V_RCP_F16 : VOP1Inst <"v_rcp_f16", VOP_F16_F16, AMDGPUrcp>;
 defm V_SQRT_F16 : VOP1Inst <"v_sqrt_f16", VOP_F16_F16, any_amdgcn_sqrt>;
 defm V_RSQ_F16 : VOP1Inst <"v_rsq_f16", VOP_F16_F16, AMDGPUrsq>;
 defm V_LOG_F16 : VOP1Inst <"v_log_f16", VOP_F16_F16, flog2>;
 defm V_EXP_F16 : VOP1Inst <"v_exp_f16", VOP_F16_F16, fexp2>;
 defm V_SIN_F16 : VOP1Inst <"v_sin_f16", VOP_F16_F16, AMDGPUsin>;
 defm V_COS_F16 : VOP1Inst <"v_cos_f16", VOP_F16_F16, AMDGPUcos>;
 } // End TRANS = 1, SchedRW = [WriteTrans32]
 defm V_FREXP_MANT_F16 : VOP1Inst <"v_frexp_mant_f16", VOP_F16_F16, int_amdgcn_frexp_mant>;
-defm V_FREXP_EXP_I16_F16 : VOP1Inst <"v_frexp_exp_i16_f16", VOP_I16_F16, int_amdgcn_frexp_exp>;
+defm V_FREXP_EXP_I16_F16 : VOP1Inst <"v_frexp_exp_i16_f16", VOP_I16_F16_SPECIAL_OMOD, int_amdgcn_frexp_exp>;
 defm V_FLOOR_F16 : VOP1Inst <"v_floor_f16", VOP_F16_F16, ffloor>;
 defm V_CEIL_F16 : VOP1Inst <"v_ceil_f16", VOP_F16_F16, fceil>;
 defm V_TRUNC_F16 : VOP1Inst <"v_trunc_f16", VOP_F16_F16, ftrunc>;
 defm V_RNDNE_F16 : VOP1Inst <"v_rndne_f16", VOP_F16_F16, frint>;
 let FPDPRounding = 1 in {
 defm V_FRACT_F16 : VOP1Inst <"v_fract_f16", VOP_F16_F16, AMDGPUfract>;
 } // End FPDPRounding = 1
 
def V_SWAP_B32 : VOP1_Pseudo<"v_swap_b32", VOP_SWAP_I32, [], 1> {
     let Constraints = "$vdst = $src1, $vdst1 = $src0";
     let DisableEncoding = "$vdst1,$src1";
     let SchedRW = [Write64Bit, Write64Bit];
   }
 
   defm V_SAT_PK_U8_I16    : VOP1Inst<"v_sat_pk_u8_i16", VOP_I32_I32>;
 
   let mayRaiseFPException = 0 in {
-    defm V_CVT_NORM_I16_F16 : VOP1Inst<"v_cvt_norm_i16_f16", VOP_I16_F16>;
-    defm V_CVT_NORM_U16_F16 : VOP1Inst<"v_cvt_norm_u16_f16", VOP_I16_F16>;
+    defm V_CVT_NORM_I16_F16 : VOP1Inst<"v_cvt_norm_i16_f16", VOP_I16_F16_SPECIAL_OMOD>;
+    defm V_CVT_NORM_U16_F16 : VOP1Inst<"v_cvt_norm_u16_f16", VOP_I16_F16_SPECIAL_OMOD>;
   } // End mayRaiseFPException = 0
 } // End SubtargetPredicate = isGFX9Plus
 
 let SubtargetPredicate = isGFX9Only in {
   defm V_SCREEN_PARTITION_4SE_B32 : VOP1Inst <"v_screen_partition_4se_b32", VOP_I32_I32>;
 } // End SubtargetPredicate = isGFX9Only
 
 let SubtargetPredicate = isGFX10Plus in {

llvm/test/MC/AMDGPU/gfx10_asm_vop1.s

 // GFX10: encoding: [0x05,0x00,0x83,0xd5,0x01,0x01,0x00,0x20]
 
 v_cvt_i32_f64_e64 v5, |v[1:2]|
 // GFX10: encoding: [0x05,0x01,0x83,0xd5,0x01,0x01,0x00,0x00]
 
 v_cvt_i32_f64_e64 v5, v[1:2] clamp
 // GFX10: encoding: [0x05,0x80,0x83,0xd5,0x01,0x01,0x00,0x00]
 
+v_cvt_i32_f64_e64 v5, s[4:5] mul:2
+// GFX10: encoding: [0x05,0x00,0x83,0xd5,0x04,0x00,0x00,0x08]
+
+v_cvt_i32_f64_e64 v5, v[1:2] clamp div:2
+// GFX10: encoding: [0x05,0x80,0x83,0xd5,0x01,0x01,0x00,0x18]
+
 v_cvt_f64_i32_e32 v[5:6], v1
 // GFX10: encoding: [0x01,0x09,0x0a,0x7e]
 
 v_cvt_f64_i32_e32 v[254:255], v1
 // GFX10: encoding: [0x01,0x09,0xfc,0x7f]
 
 v_cvt_f64_i32_e32 v[5:6], v255
 // GFX10: encoding: [0xff,0x09,0x0a,0x7e]

 // GFX10: encoding: [0x05,0x00,0x87,0xd5,0x01,0x01,0x00,0x20]
 
 v_cvt_u32_f32_e64 v5, |v1|
 // GFX10: encoding: [0x05,0x01,0x87,0xd5,0x01,0x01,0x00,0x00]
 
 v_cvt_u32_f32_e64 v5, v1 clamp
 // GFX10: encoding: [0x05,0x80,0x87,0xd5,0x01,0x01,0x00,0x00]
 
+v_cvt_u32_f32_e64 v5, s1 mul:2
+// GFX10: encoding: [0x05,0x00,0x87,0xd5,0x01,0x00,0x00,0x08]
+
+v_cvt_u32_f32_e64 v5, v1 clamp div:2
+// GFX10: encoding: [0x05,0x80,0x87,0xd5,0x01,0x01,0x00,0x18]
+
 v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
 // GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x06,0x00]
 
 v_cvt_u32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
 // GFX10: encoding: [0xf9,0x0e,0xfe,0x7f,0x01,0x06,0x06,0x00]
 
 v_cvt_u32_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
 // GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0xff,0x06,0x06,0x00]

 // GFX10: encoding: [0x05,0x00,0x88,0xd5,0x01,0x01,0x00,0x20]
 
 v_cvt_i32_f32_e64 v5, |v1|
 // GFX10: encoding: [0x05,0x01,0x88,0xd5,0x01,0x01,0x00,0x00]
 
 v_cvt_i32_f32_e64 v5, v1 clamp
 // GFX10: encoding: [0x05,0x80,0x88,0xd5,0x01,0x01,0x00,0x00]
 
+v_cvt_i32_f32_e64 v5, v1 mul:2
+// GFX10: encoding: [0x05,0x00,0x88,0xd5,0x01,0x01,0x00,0x08]
+
+v_cvt_i32_f32_e64 v5, v1 clamp div:2
+// GFX10: encoding: [0x05,0x80,0x88,0xd5,0x01,0x01,0x00,0x18]
+
 v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
 // GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x06,0x00]
 
 v_cvt_i32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
 // GFX10: encoding: [0xf9,0x10,0xfe,0x7f,0x01,0x06,0x06,0x00]
 
 v_cvt_i32_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
 // GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0xff,0x06,0x06,0x00]

 // GFX10: encoding: [0x05,0x00,0x95,0xd5,0x01,0x01,0x00,0x20]
 
 v_cvt_u32_f64_e64 v5, |v[1:2]|
 // GFX10: encoding: [0x05,0x01,0x95,0xd5,0x01,0x01,0x00,0x00]
 
 v_cvt_u32_f64_e64 v5, v[1:2] clamp
 // GFX10: encoding: [0x05,0x80,0x95,0xd5,0x01,0x01,0x00,0x00]
 
+v_cvt_u32_f64_e64 v5, s[4:5] mul:2
+// GFX10: encoding: [0x05,0x00,0x95,0xd5,0x04,0x00,0x00,0x08]
+
+v_cvt_u32_f64_e64 v5, v[1:2] clamp div:2
+// GFX10: encoding: [0x05,0x80,0x95,0xd5,0x01,0x01,0x00,0x18]
+
 v_cvt_f64_u32 v[5:6], v1
 // GFX10: encoding: [0x01,0x2d,0x0a,0x7e]
 
 v_cvt_f64_u32 v[254:255], v1
 // GFX10: encoding: [0x01,0x2d,0xfc,0x7f]
 
 v_cvt_f64_u32 v[5:6], v255
 // GFX10: encoding: [0xff,0x2d,0x0a,0x7e]

 // GFX10: encoding: [0x05,0x00,0xd2,0xd5,0x01,0x01,0x00,0x20]
 
 v_cvt_u16_f16_e64 v5, |v1|
 // GFX10: encoding: [0x05,0x01,0xd2,0xd5,0x01,0x01,0x00,0x00]
 
 v_cvt_u16_f16_e64 v5, v1 clamp
 // GFX10: encoding: [0x05,0x80,0xd2,0xd5,0x01,0x01,0x00,0x00]
 
+v_cvt_u16_f16_e64 v5, s1 mul:2
+// GFX10: encoding: [0x05,0x00,0xd2,0xd5,0x01,0x00,0x00,0x08]
+
+v_cvt_u16_f16_e64 v5, v1 clamp div:2
+// GFX10: encoding: [0x05,0x80,0xd2,0xd5,0x01,0x01,0x00,0x18]
+
 v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
 // GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x06,0x06,0x00]
 
 v_cvt_u16_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
 // GFX10: encoding: [0xf9,0xa4,0xfe,0x7f,0x01,0x06,0x06,0x00]
 
 v_cvt_u16_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
 // GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0xff,0x06,0x06,0x00]

 // GFX10: encoding: [0x05,0x00,0xd3,0xd5,0x01,0x01,0x00,0x20]
 
 v_cvt_i16_f16_e64 v5, |v1|
 // GFX10: encoding: [0x05,0x01,0xd3,0xd5,0x01,0x01,0x00,0x00]
 
 v_cvt_i16_f16_e64 v5, v1 clamp
 // GFX10: encoding: [0x05,0x80,0xd3,0xd5,0x01,0x01,0x00,0x00]
 
+v_cvt_i16_f16_e64 v5, v1 mul:2
+// GFX10: encoding: [0x05,0x00,0xd3,0xd5,0x01,0x01,0x00,0x08]
+
+v_cvt_i16_f16_e64 v5, v1 clamp div:2
+// GFX10: encoding: [0x05,0x80,0xd3,0xd5,0x01,0x01,0x00,0x18]
+
 v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
 // GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x06,0x06,0x00]
 
 v_cvt_i16_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
 // GFX10: encoding: [0xf9,0xa6,0xfe,0x7f,0x01,0x06,0x06,0x00]
 
 v_cvt_i16_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
 // GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0xff,0x06,0x06,0x00]

llvm/test/MC/AMDGPU/gfx9_asm_vop3.s

 // CHECK: [0x05,0x00,0x43,0xd1,0x01,0x01,0x00,0x20]
 
 v_cvt_i32_f64_e64 v5, |v[1:2]|
 // CHECK: [0x05,0x01,0x43,0xd1,0x01,0x01,0x00,0x00]
 
 v_cvt_i32_f64_e64 v5, v[1:2] clamp
 // CHECK: [0x05,0x80,0x43,0xd1,0x01,0x01,0x00,0x00]
 
+v_cvt_i32_f64_e64 v5, s[4:5] mul:2
+// CHECK: [0x05,0x00,0x43,0xd1,0x04,0x00,0x00,0x08]
+
+v_cvt_i32_f64_e64 v5, v[1:2] clamp div:2
+// CHECK: [0x05,0x80,0x43,0xd1,0x01,0x01,0x00,0x18]
+
 v_cvt_f64_i32_e64 v[5:6], v1
 // CHECK: [0x05,0x00,0x44,0xd1,0x01,0x01,0x00,0x00]
 
 v_cvt_f64_i32_e64 v[254:255], v1
 // CHECK: [0xfe,0x00,0x44,0xd1,0x01,0x01,0x00,0x00]
 
 v_cvt_f64_i32_e64 v[5:6], v255
 // CHECK: [0x05,0x00,0x44,0xd1,0xff,0x01,0x00,0x00]

 // CHECK: [0x05,0x00,0x47,0xd1,0x01,0x01,0x00,0x20]
 
 v_cvt_u32_f32_e64 v5, |v1|
 // CHECK: [0x05,0x01,0x47,0xd1,0x01,0x01,0x00,0x00]
 
 v_cvt_u32_f32_e64 v5, v1 clamp
 // CHECK: [0x05,0x80,0x47,0xd1,0x01,0x01,0x00,0x00]
 
+v_cvt_u32_f32_e64 v5, s1 mul:2
+// CHECK: [0x05,0x00,0x47,0xd1,0x01,0x00,0x00,0x08]
+
+v_cvt_u32_f32_e64 v5, v1 clamp div:2
+// CHECK: [0x05,0x80,0x47,0xd1,0x01,0x01,0x00,0x18]
+
 v_cvt_i32_f32_e64 v5, v1
 // CHECK: [0x05,0x00,0x48,0xd1,0x01,0x01,0x00,0x00]
 
 v_cvt_i32_f32_e64 v255, v1
 // CHECK: [0xff,0x00,0x48,0xd1,0x01,0x01,0x00,0x00]
 
 v_cvt_i32_f32_e64 v5, v255
 // CHECK: [0x05,0x00,0x48,0xd1,0xff,0x01,0x00,0x00]

 // CHECK: [0x05,0x00,0x48,0xd1,0x01,0x01,0x00,0x20]
 
 v_cvt_i32_f32_e64 v5, |v1|
 // CHECK: [0x05,0x01,0x48,0xd1,0x01,0x01,0x00,0x00]
 
 v_cvt_i32_f32_e64 v5, v1 clamp
 // CHECK: [0x05,0x80,0x48,0xd1,0x01,0x01,0x00,0x00]
 
+v_cvt_i32_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x48,0xd1,0x01,0x01,0x00,0x08]
+
+v_cvt_i32_f32_e64 v5, v1 clamp div:2
+// CHECK: [0x05,0x80,0x48,0xd1,0x01,0x01,0x00,0x18]
+
 v_cvt_f16_f32_e64 v5, v1
 // CHECK: [0x05,0x00,0x4a,0xd1,0x01,0x01,0x00,0x00]
 
 v_cvt_f16_f32_e64 v255, v1
 // CHECK: [0xff,0x00,0x4a,0xd1,0x01,0x01,0x00,0x00]
 
 v_cvt_f16_f32_e64 v5, v255
 // CHECK: [0x05,0x00,0x4a,0xd1,0xff,0x01,0x00,0x00]

 // CHECK: [0x05,0x00,0x55,0xd1,0x01,0x01,0x00,0x20]
 
 v_cvt_u32_f64_e64 v5, |v[1:2]|
 // CHECK: [0x05,0x01,0x55,0xd1,0x01,0x01,0x00,0x00]
 
 v_cvt_u32_f64_e64 v5, v[1:2] clamp
 // CHECK: [0x05,0x80,0x55,0xd1,0x01,0x01,0x00,0x00]
 
+v_cvt_u32_f64_e64 v5, s[4:5] mul:2
+// CHECK: [0x05,0x00,0x55,0xd1,0x04,0x00,0x00,0x08]
+
+v_cvt_u32_f64_e64 v5, v[1:2] clamp div:2
+// CHECK: [0x05,0x80,0x55,0xd1,0x01,0x01,0x00,0x18]
+
 v_cvt_f64_u32_e64 v[5:6], v1
 // CHECK: [0x05,0x00,0x56,0xd1,0x01,0x01,0x00,0x00]
 
 v_cvt_f64_u32_e64 v[254:255], v1
 // CHECK: [0xfe,0x00,0x56,0xd1,0x01,0x01,0x00,0x00]
 
 v_cvt_f64_u32_e64 v[5:6], v255
 // CHECK: [0x05,0x00,0x56,0xd1,0xff,0x01,0x00,0x00]

 // CHECK: [0x05,0x00,0x70,0xd1,0xfd,0x00,0x00,0x00]
 
 v_frexp_exp_i32_f64_e64 v5, -v[1:2]
 // CHECK: [0x05,0x00,0x70,0xd1,0x01,0x01,0x00,0x20]
 
 v_frexp_exp_i32_f64_e64 v5, |v[1:2]|
 // CHECK: [0x05,0x01,0x70,0xd1,0x01,0x01,0x00,0x00]
 
+v_frexp_exp_i32_f64_e64 v5, s[4:5] mul:2
+// CHECK: [0x05,0x00,0x70,0xd1,0x04,0x00,0x00,0x08]
+
 v_frexp_mant_f64_e64 v[5:6], v[1:2]
 // CHECK: [0x05,0x00,0x71,0xd1,0x01,0x01,0x00,0x00]
 
 v_frexp_mant_f64_e64 v[254:255], v[1:2]
 // CHECK: [0xfe,0x00,0x71,0xd1,0x01,0x01,0x00,0x00]
 
 v_frexp_mant_f64_e64 v[5:6], v[254:255]
 // CHECK: [0x05,0x00,0x71,0xd1,0xfe,0x01,0x00,0x00]

 // CHECK: [0x05,0x00,0x7b,0xd1,0x01,0x01,0x00,0x20]
 
 v_cvt_u16_f16_e64 v5, |v1|
 // CHECK: [0x05,0x01,0x7b,0xd1,0x01,0x01,0x00,0x00]
 
 v_cvt_u16_f16_e64 v5, v1 clamp
 // CHECK: [0x05,0x80,0x7b,0xd1,0x01,0x01,0x00,0x00]
 
+v_cvt_u16_f16_e64 v5, s1 mul:2
+// CHECK: [0x05,0x00,0x7b,0xd1,0x01,0x00,0x00,0x08]
+
+v_cvt_u16_f16_e64 v5, v1 clamp div:2
+// CHECK: [0x05,0x80,0x7b,0xd1,0x01,0x01,0x00,0x18]
+
 v_cvt_i16_f16_e64 v5, v1
 // CHECK: [0x05,0x00,0x7c,0xd1,0x01,0x01,0x00,0x00]
 
 v_cvt_i16_f16_e64 v255, v1
 // CHECK: [0xff,0x00,0x7c,0xd1,0x01,0x01,0x00,0x00]
 
 v_cvt_i16_f16_e64 v5, v255
 // CHECK: [0x05,0x00,0x7c,0xd1,0xff,0x01,0x00,0x00]

 // CHECK: [0x05,0x00,0x7c,0xd1,0x01,0x01,0x00,0x20]
 
 v_cvt_i16_f16_e64 v5, |v1|
 // CHECK: [0x05,0x01,0x7c,0xd1,0x01,0x01,0x00,0x00]
 
 v_cvt_i16_f16_e64 v5, v1 clamp
 // CHECK: [0x05,0x80,0x7c,0xd1,0x01,0x01,0x00,0x00]
 
+v_cvt_i16_f16_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x7c,0xd1,0x01,0x01,0x00,0x08]
+
+v_cvt_i16_f16_e64 v5, v1 clamp div:2
+// CHECK: [0x05,0x80,0x7c,0xd1,0x01,0x01,0x00,0x18]
+
 v_rcp_f16_e64 v5, v1
 // CHECK: [0x05,0x00,0x7d,0xd1,0x01,0x01,0x00,0x00]
 
 v_rcp_f16_e64 v255, v1
 // CHECK: [0xff,0x00,0x7d,0xd1,0x01,0x01,0x00,0x00]
 
 v_rcp_f16_e64 v5, v255
 // CHECK: [0x05,0x00,0x7d,0xd1,0xff,0x01,0x00,0x00]

 // CHECK: [0x05,0x00,0x83,0xd1,0xfe,0x00,0x00,0x00]
 
 v_frexp_exp_i16_f16_e64 v5, -v1
 // CHECK: [0x05,0x00,0x83,0xd1,0x01,0x01,0x00,0x20]
 
 v_frexp_exp_i16_f16_e64 v5, |v1|
 // CHECK: [0x05,0x01,0x83,0xd1,0x01,0x01,0x00,0x00]
 
+v_frexp_exp_i16_f16_e64 v5, s1 mul:2
+// CHECK: [0x05,0x00,0x83,0xd1,0x01,0x00,0x00,0x08]
+
 v_floor_f16_e64 v5, v1
 // CHECK: [0x05,0x00,0x84,0xd1,0x01,0x01,0x00,0x00]
 
 v_floor_f16_e64 v255, v1
 // CHECK: [0xff,0x00,0x84,0xd1,0x01,0x01,0x00,0x00]
 
 v_floor_f16_e64 v5, v255
 // CHECK: [0x05,0x00,0x84,0xd1,0xff,0x01,0x00,0x00]

 // CHECK: [0x05,0x00,0x8d,0xd1,0x01,0x01,0x00,0x20]
 
 v_cvt_norm_i16_f16_e64 v5, |v1|
 // CHECK: [0x05,0x01,0x8d,0xd1,0x01,0x01,0x00,0x00]
 
 v_cvt_norm_i16_f16_e64 v5, v1 clamp
 // CHECK: [0x05,0x80,0x8d,0xd1,0x01,0x01,0x00,0x00]
 
+v_cvt_norm_i16_f16_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x8d,0xd1,0x01,0x01,0x00,0x08]
+
 v_cvt_norm_u16_f16_e64 v5, v1
 // CHECK: [0x05,0x00,0x8e,0xd1,0x01,0x01,0x00,0x00]
 
 v_cvt_norm_u16_f16_e64 v255, v1
 // CHECK: [0xff,0x00,0x8e,0xd1,0x01,0x01,0x00,0x00]
 
 v_cvt_norm_u16_f16_e64 v5, v255
 // CHECK: [0x05,0x00,0x8e,0xd1,0xff,0x01,0x00,0x00]

 // CHECK: [0x05,0x00,0x8e,0xd1,0x01,0x01,0x00,0x20]
 
 v_cvt_norm_u16_f16_e64 v5, |v1|
 // CHECK: [0x05,0x01,0x8e,0xd1,0x01,0x01,0x00,0x00]
 
 v_cvt_norm_u16_f16_e64 v5, v1 clamp
 // CHECK: [0x05,0x80,0x8e,0xd1,0x01,0x01,0x00,0x00]
 
+v_cvt_norm_u16_f16_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x8e,0xd1,0x01,0x01,0x00,0x08]
+
 v_sat_pk_u8_i16_e64 v5, v1
 // CHECK: [0x05,0x00,0x8f,0xd1,0x01,0x01,0x00,0x00]
 
 v_sat_pk_u8_i16_e64 v255, v1
 // CHECK: [0xff,0x00,0x8f,0xd1,0x01,0x01,0x00,0x00]
 
 v_sat_pk_u8_i16_e64 v5, v255
 // CHECK: [0x05,0x00,0x8f,0xd1,0xff,0x01,0x00,0x00]

llvm/test/MC/AMDGPU/vop3-errs.s

 // GCN: error: destination must be different than all sources
 
 v_cmp_eq_f32_e64 vcc, v0, v1 mul:2
 // GCN: error: invalid operand for instruction
 
 v_cmp_le_f64_e64 vcc, v0, v1 mul:4
 // GCN: error: invalid operand for instruction
 
-v_cvt_u32_f32_e64 v0, v1 div:2
-// GCN: error: invalid operand for instruction
-
 //
 // mul
 //
 
 v_cvt_f64_i32 v[5:6], s1 mul:3
 // GCN: error: invalid mul value.
 
 //