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Differential D97416

[PowerPC] Update Copy/Paste encodings according to ISA3.1
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Authored by jsji on Feb 24 2021, 2:08 PM.

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nemanjai
steven.zhang
shchenz
Group Reviewers
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rGcc21de678938: [PowerPC] Update Copy/Paste encodings according to ISA3.1
Summary

Copy-paste P9 insns were added back in 2016,
however, looks like the opcodes has changed in ISA3.1.

Diff Detail

Event Timeline

jsji created this revision.Feb 24 2021, 2:08 PM
Herald added subscribers: kbarton, hiraditya. · View Herald TranscriptFeb 24 2021, 2:08 PM
jsji requested review of this revision.Feb 24 2021, 2:08 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 24 2021, 2:08 PM
Herald added a subscriber: llvm-commits. · View Herald Transcript
Harbormaster completed remote builds in B90683: Diff 326201.Feb 24 2021, 4:36 PM
jsji added a comment.Mar 4 2021, 8:58 AM

Ping.

nemanjai accepted this revision.Mar 5 2021, 2:47 AM

LGTM. Thanks for fixing this.

This revision is now accepted and ready to land.Mar 5 2021, 2:47 AM
This revision was landed with ongoing or failed builds.Mar 5 2021, 9:06 AM
Closed by commit rGcc21de678938: [PowerPC] Update Copy/Paste encodings according to ISA3.1 (authored by jsji). · Explain Why
This revision was automatically updated to reflect the committed changes.
jsji added a commit: rGcc21de678938: [PowerPC] Update Copy/Paste encodings according to ISA3.1.

Revision Contents

PathSize
llvm/
lib/
Target/
PowerPC/
AsmParser/
23 lines
1 line
10 lines
14 lines
test/
MC/
Disassembler/
PowerPC/
11 lines
PowerPC/
22 lines
19 lines

Diff 328548

llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp

Show First 20 Lines • Show All 1,126 Lines • ▼ Show 20 Linesvoid PPCAsmParser::ProcessInstruction(MCInst &Inst,
} }
case PPC::MFTB: { case PPC::MFTB: {
if (getSTI().getFeatureBits()[PPC::FeatureMFTB]) { if (getSTI().getFeatureBits()[PPC::FeatureMFTB]) {
assert(Inst.getNumOperands() == 2 && "Expecting two operands"); assert(Inst.getNumOperands() == 2 && "Expecting two operands");
Inst.setOpcode(PPC::MFSPR); Inst.setOpcode(PPC::MFSPR);
} }
break; break;
} }
case PPC::CP_COPYx:
case PPC::CP_COPY_FIRST: {
MCInst TmpInst;
TmpInst.setOpcode(PPC::CP_COPY);
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(1));
TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_COPYx ? 0 : 1));
Inst = TmpInst;
break;
}
case PPC::CP_PASTEx :
case PPC::CP_PASTE_LAST: {
MCInst TmpInst;
TmpInst.setOpcode(Opcode == PPC::CP_PASTEx ? PPC::CP_PASTE
: PPC::CP_PASTE_rec);
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(1));
TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_PASTEx ? 0 : 1));
Inst = TmpInst;
break;
}
} }
} }
static std::string PPCMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, static std::string PPCMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS,
unsigned VariantID = 0); unsigned VariantID = 0);
bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands, OperandVector &Operands,
▲ Show 20 Lines • Show All 616 Lines • Show Last 20 Lines

llvm/lib/Target/PowerPC/P9InstrResources.td

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// 4 Cycle Load uses a single slice. // 4 Cycle Load uses a single slice.
def : InstRW<[P9_LS_4C, IP_AGEN_1C, DISP_1C], def : InstRW<[P9_LS_4C, IP_AGEN_1C, DISP_1C],
(instrs (instrs
(instregex "DCB(F|T|ST)(EP)?$"), (instregex "DCB(F|T|ST)(EP)?$"),
(instregex "DCBZ(L)?(EP)?$"), (instregex "DCBZ(L)?(EP)?$"),
(instregex "DCBTST(EP)?$"), (instregex "DCBTST(EP)?$"),
(instregex "CP_COPY(8)?$"), (instregex "CP_COPY(8)?$"),
(instregex "CP_PASTE(8)?$"),
(instregex "ICBI(EP)?$"), (instregex "ICBI(EP)?$"),
(instregex "ICBT(LS)?$"), (instregex "ICBT(LS)?$"),
(instregex "LBARX(L)?$"), (instregex "LBARX(L)?$"),
(instregex "LBZ(CIX|8|X|X8|XTLS|XTLS_32)?(_)?$"), (instregex "LBZ(CIX|8|X|X8|XTLS|XTLS_32)?(_)?$"),
(instregex "LD(ARX|ARXL|BRX|CIX|X|XTLS)?(_)?$"), (instregex "LD(ARX|ARXL|BRX|CIX|X|XTLS)?(_)?$"),
(instregex "LH(A|B)RX(L)?(8)?$"), (instregex "LH(A|B)RX(L)?(8)?$"),
(instregex "LHZ(8|CIX|X|X8|XTLS|XTLS_32)?(_)?$"), (instregex "LHZ(8|CIX|X|X8|XTLS|XTLS_32)?(_)?$"),
(instregex "LWARX(L)?$"), (instregex "LWARX(L)?$"),
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llvm/lib/Target/PowerPC/PPCInstr64Bit.td

Show First 20 Lines • Show All 1,611 Lines • ▼ Show 20 Lines
let Predicates = [IsISA3_0] in { let Predicates = [IsISA3_0] in {
// DARN (deliver random number) // DARN (deliver random number)
// L=0 for 32-bit, L=1 for conditioned random, L=2 for raw random // L=0 for 32-bit, L=1 for conditioned random, L=2 for raw random
def : Pat<(int_ppc_darn32), (EXTRACT_SUBREG (DARN 0), sub_32)>; def : Pat<(int_ppc_darn32), (EXTRACT_SUBREG (DARN 0), sub_32)>;
def : Pat<(int_ppc_darn), (DARN 1)>; def : Pat<(int_ppc_darn), (DARN 1)>;
def : Pat<(int_ppc_darnraw), (DARN 2)>; def : Pat<(int_ppc_darnraw), (DARN 2)>;
class X_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty,
InstrItinClass itin, list<dag> pattern>
: X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L),
!strconcat(opc, " $rA, $rB"), itin, pattern>{
let L = 1;
}
class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty, class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L), : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L),
!strconcat(opc, " $rA, $rB, $L"), itin, pattern>; !strconcat(opc, " $rA, $rB, $L"), itin, pattern>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in { let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
def CP_COPY8 : X_L1_RA5_RB5<31, 774, "copy" , g8rc, IIC_LdStCOPY, []>; def CP_COPY8 : X_RA5_RB5<31, 774, "copy" , g8rc, IIC_LdStCOPY, []>;
def CP_PASTE8 : X_L1_RA5_RB5<31, 902, "paste" , g8rc, IIC_LdStPASTE, []>;
def CP_PASTE8_rec : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isRecordForm; def CP_PASTE8_rec : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isRecordForm;
} }
// SLB Invalidate Entry Global // SLB Invalidate Entry Global
def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RS, gprc:$RB), def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RS, gprc:$RB),
"slbieg $RS, $RB", IIC_SprSLBIEG, []>; "slbieg $RS, $RB", IIC_SprSLBIEG, []>;
// SLB Synchronize // SLB Synchronize
def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>; def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>;
} // IsISA3_0 } // IsISA3_0

llvm/lib/Target/PowerPC/PPCInstrInfo.td

Show First 20 Lines • Show All 5,150 Lines • ▼ Show 20 Lines
def : Pat<(atomic_store_32 xaddr:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>; def : Pat<(atomic_store_32 xaddr:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>;
let Predicates = [IsISA3_0] in { let Predicates = [IsISA3_0] in {
// Copy-Paste Facility // Copy-Paste Facility
// We prefix 'CP' to COPY due to name conflict in Target.td. We also prefix to // We prefix 'CP' to COPY due to name conflict in Target.td. We also prefix to
// PASTE for naming consistency. // PASTE for naming consistency.
let mayLoad = 1 in let mayLoad = 1 in
def CP_COPY : X_L1_RA5_RB5<31, 774, "copy" , gprc, IIC_LdStCOPY, []>; def CP_COPY : X_RA5_RB5<31, 774, "copy" , gprc, IIC_LdStCOPY, []>;
let mayStore = 1 in
def CP_PASTE : X_L1_RA5_RB5<31, 902, "paste" , gprc, IIC_LdStPASTE, []>;
let mayStore = 1, Defs = [CR0] in let mayStore = 1, Defs = [CR0] in
def CP_PASTE_rec : X_L1_RA5_RB5<31, 902, "paste.", gprc, IIC_LdStPASTE, []>, isRecordForm; def CP_PASTE_rec : X_L1_RA5_RB5<31, 902, "paste.", gprc, IIC_LdStPASTE, []>, isRecordForm;
def CP_COPYx : PPCAsmPseudo<"copy $rA, $rB" , (ins gprc:$rA, gprc:$rB)>; def : InstAlias<"paste. $RA, $RB", (CP_PASTE_rec gprc:$RA, gprc:$RB, 1)>;
def CP_PASTEx : PPCAsmPseudo<"paste $rA, $rB", (ins gprc:$rA, gprc:$rB)>; def CP_ABORT : XForm_0<31, 838, (outs), (ins), "cpabort", IIC_SprABORT, []>;
def CP_COPY_FIRST : PPCAsmPseudo<"copy_first $rA, $rB",
(ins gprc:$rA, gprc:$rB)>;
def CP_PASTE_LAST : PPCAsmPseudo<"paste_last $rA, $rB",
(ins gprc:$rA, gprc:$rB)>;
def CP_ABORT : XForm_0<31, 838, (outs), (ins), "cp_abort", IIC_SprABORT, []>;
// Message Synchronize // Message Synchronize
def MSGSYNC : XForm_0<31, 886, (outs), (ins), "msgsync", IIC_SprMSGSYNC, []>; def MSGSYNC : XForm_0<31, 886, (outs), (ins), "msgsync", IIC_SprMSGSYNC, []>;
// Power-Saving Mode Instruction: // Power-Saving Mode Instruction:
def STOP : XForm_0<19, 370, (outs), (ins), "stop", IIC_SprSTOP, []>; def STOP : XForm_0<19, 370, (outs), (ins), "stop", IIC_SprSTOP, []>;
} // IsISA3_0 } // IsISA3_0
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llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt

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0x7f 0x80 0x04 0x80 0x7f 0x80 0x04 0x80
# CHECK: mtsrin 10, 12 # CHECK: mtsrin 10, 12
0x7d 0x40 0x61 0xe4 0x7d 0x40 0x61 0xe4
# CHECK: mfsrin 10, 12 # CHECK: mfsrin 10, 12
0x7d 0x40 0x65 0x26 0x7d 0x40 0x65 0x26
# CHECK: copy 2, 19, 1 # CHECK: copy 2, 19
0x7c 0x22 0x9e 0x0c 0x7c 0x22 0x9e 0x0c
# CHECK: paste 17, 1, 1 # CHECK: paste. 17, 1, 0
0x7c 0x31 0x0f 0x0c 0x7c 0x11 0x0f 0x0d
# CHECK: cp_abort # CHECK: paste. 17, 1
0x7c 0x31 0x0f 0x0d
# CHECK: cpabort
0x7c 0x00 0x06 0x8c 0x7c 0x00 0x06 0x8c
# CHECK: msgsync # CHECK: msgsync
0x7c 0x00 0x06 0xec 0x7c 0x00 0x06 0xec
# CHECK: slbieg 6, 21 # CHECK: slbieg 6, 21
0x7c 0xc0 0xab 0xa4 0x7c 0xc0 0xab 0xa4
# CHECK: slbsync # CHECK: slbsync
0x7c 0x00 0x02 0xa4 0x7c 0x00 0x02 0xa4
# CHECK: stop # CHECK: stop
0x4c 0x00 0x02 0xe4 0x4c 0x00 0x02 0xe4

llvm/test/MC/PowerPC/ppc64-encoding-ext.s

Show First 20 Lines • Show All 3,695 Lines • ▼ Show 20 Lines# CHECK-LE: stdcix 21, 5, 7 # encoding: [0xea,0x3f,0xa5,0x7e]
stdcix 21, 5, 7 stdcix 21, 5, 7
# Processor-Specific Instructions # Processor-Specific Instructions
# CHECK-BE: attn # encoding: [0x00,0x00,0x02,0x00] # CHECK-BE: attn # encoding: [0x00,0x00,0x02,0x00]
# CHECK-LE: attn # encoding: [0x00,0x02,0x00,0x00] # CHECK-LE: attn # encoding: [0x00,0x02,0x00,0x00]
attn attn
# Copy-Paste Facility (Extended Mnemonics): # Copy-Paste Facility (Extended Mnemonics):
# CHECK-BE: copy 2, 19, 0 # encoding: [0x7c,0x02,0x9e,0x0c] # CHECK-BE: copy 2, 19 # encoding: [0x7c,0x22,0x9e,0x0c]
# CHECK-LE: copy 2, 19, 0 # encoding: [0x0c,0x9e,0x02,0x7c] # CHECK-LE: copy 2, 19 # encoding: [0x0c,0x9e,0x22,0x7c]
copy 2, 19 copy 2, 19
# CHECK-BE: copy 2, 19, 1 # encoding: [0x7c,0x22,0x9e,0x0c] # CHECK-BE: paste. 17, 1, 0 # encoding: [0x7c,0x11,0x0f,0x0d]
# CHECK-LE: copy 2, 19, 1 # encoding: [0x0c,0x9e,0x22,0x7c] # CHECK-LE: paste. 17, 1, 0 # encoding: [0x0d,0x0f,0x11,0x7c]
copy_first 2, 19 paste. 17, 1, 0
# CHECK-BE: paste 17, 1, 0 # encoding: [0x7c,0x11,0x0f,0x0c] # CHECK-BE: paste. 17, 1 # encoding: [0x7c,0x31,0x0f,0x0d]
# CHECK-LE: paste 17, 1, 0 # encoding: [0x0c,0x0f,0x11,0x7c] # CHECK-LE: paste. 17, 1 # encoding: [0x0d,0x0f,0x31,0x7c]
paste 17, 1 paste. 17, 1, 1
# CHECK-BE: paste. 17, 1, 1 # encoding: [0x7c,0x31,0x0f,0x0d] # CHECK-BE: paste. 17, 1 # encoding: [0x7c,0x31,0x0f,0x0d]
# CHECK-LE: paste. 17, 1, 1 # encoding: [0x0d,0x0f,0x31,0x7c] # CHECK-LE: paste. 17, 1 # encoding: [0x0d,0x0f,0x31,0x7c]
paste_last 17, 1 paste. 17, 1

llvm/test/MC/PowerPC/ppc64-encoding.s

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# CHECK-BE: mtsrin 10, 12 # encoding: [0x7d,0x40,0x61,0xe4] # CHECK-BE: mtsrin 10, 12 # encoding: [0x7d,0x40,0x61,0xe4]
# CHECK-LE: mtsrin 10, 12 # encoding: [0xe4,0x61,0x40,0x7d] # CHECK-LE: mtsrin 10, 12 # encoding: [0xe4,0x61,0x40,0x7d]
mtsrin %r10,%r12 mtsrin %r10,%r12
# CHECK-BE: mfsrin 10, 12 # encoding: [0x7d,0x40,0x65,0x26] # CHECK-BE: mfsrin 10, 12 # encoding: [0x7d,0x40,0x65,0x26]
# CHECK-LE: mfsrin 10, 12 # encoding: [0x26,0x65,0x40,0x7d] # CHECK-LE: mfsrin 10, 12 # encoding: [0x26,0x65,0x40,0x7d]
mfsrin %r10,%r12 mfsrin %r10,%r12
# Copy-Paste Facility # Copy-Paste Facility
# CHECK-BE: copy 2, 19, 1 # encoding: [0x7c,0x22,0x9e,0x0c] # CHECK-BE: copy 2, 19 # encoding: [0x7c,0x22,0x9e,0x0c]
# CHECK-LE: copy 2, 19, 1 # encoding: [0x0c,0x9e,0x22,0x7c] # CHECK-LE: copy 2, 19 # encoding: [0x0c,0x9e,0x22,0x7c]
copy 2, 19, 1 copy 2, 19
# CHECK-BE: paste 17, 1, 1 # encoding: [0x7c,0x31,0x0f,0x0c] # CHECK-BE: paste. 17, 1 # encoding: [0x7c,0x31,0x0f,0x0d]
# CHECK-LE: paste 17, 1, 1 # encoding: [0x0c,0x0f,0x31,0x7c] # CHECK-LE: paste. 17, 1 # encoding: [0x0d,0x0f,0x31,0x7c]
paste 17, 1, 1 paste. 17, 1, 1
# CHECK-BE: cp_abort # encoding: [0x7c,0x00,0x06,0x8c] # CHECK-BE: cpabort # encoding: [0x7c,0x00,0x06,0x8c]
# CHECK-LE: cp_abort # encoding: [0x8c,0x06,0x00,0x7c] # CHECK-LE: cpabort # encoding: [0x8c,0x06,0x00,0x7c]
cp_abort cpabort
# Message Synchronize # Message Synchronize
# CHECK-BE: msgsync # encoding: [0x7c,0x00,0x06,0xec] # CHECK-BE: msgsync # encoding: [0x7c,0x00,0x06,0xec]
# CHECK-LE: msgsync # encoding: [0xec,0x06,0x00,0x7c] # CHECK-LE: msgsync # encoding: [0xec,0x06,0x00,0x7c]
msgsync msgsync
# SLB Invalidate Entry Global # SLB Invalidate Entry Global
# CHECK-BE: slbieg 6, 21 # encoding: [0x7c,0xc0,0xab,0xa4] # CHECK-BE: slbieg 6, 21 # encoding: [0x7c,0xc0,0xab,0xa4]
Show All 12 Lines