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Differential D97367

[PowerPC] Allow spilling GPR to VSR on AIX
ClosedPublic

Authored by qiucf on Feb 24 2021, 1:44 AM.

Details

Reviewers
syzaara
nemanjai
jsji
Group Reviewers
Restricted Project
Commits
rG72d4a41ba622: [PowerPC] Allow spilling GPR to VSR on AIX
Summary

This patch enables spilling GPR to VSRs instead of stack (implemented in rGfcd9697) under AIX ABI.

Diff Detail

Event Timeline

qiucf created this revision.Feb 24 2021, 1:44 AM
Herald added subscribers: shchenz, kbarton, hiraditya, qcolombet. · View Herald TranscriptFeb 24 2021, 1:44 AM
qiucf requested review of this revision.Feb 24 2021, 1:44 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 24 2021, 1:44 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
qiucf updated this revision to Diff 326023.Feb 24 2021, 1:45 AM

Update with context

Harbormaster completed remote builds in B90562: Diff 326019.Feb 24 2021, 2:18 AM
Harbormaster completed remote builds in B90564: Diff 326023.Feb 24 2021, 2:20 AM
nemanjai accepted this revision.Feb 24 2021, 5:13 AM

LGTM.

This revision is now accepted and ready to land.Feb 24 2021, 5:13 AM
Closed by commit rG72d4a41ba622: [PowerPC] Allow spilling GPR to VSR on AIX (authored by qiucf). · Explain WhyMar 2 2021, 9:34 PM
This revision was automatically updated to reflect the committed changes.
qiucf added a commit: rG72d4a41ba622: [PowerPC] Allow spilling GPR to VSR on AIX.

Revision Contents

PathSize
llvm/
lib/
Target/
PowerPC/
2 lines
test/
CodeGen/
PowerPC/
2 lines

Diff 327666

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

Show First 20 Lines • Show All 446 Lines • ▼ Show 20 LinesPPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
if (Subtarget.hasVSX()) { if (Subtarget.hasVSX()) {
// With VSX, we can inflate various sub-register classes to the full VSX // With VSX, we can inflate various sub-register classes to the full VSX
// register set. // register set.
// For Power9 we allow the user to enable GPR to vector spills. // For Power9 we allow the user to enable GPR to vector spills.
// FIXME: Currently limited to spilling GP8RC. A follow on patch will add // FIXME: Currently limited to spilling GP8RC. A follow on patch will add
// support to spill GPRC. // support to spill GPRC.
if (TM.isELFv2ABI()) { if (TM.isELFv2ABI() || Subtarget.isAIXABI()) {
if (Subtarget.hasP9Vector() && EnableGPRToVecSpills && if (Subtarget.hasP9Vector() && EnableGPRToVecSpills &&
RC == &PPC::G8RCRegClass) { RC == &PPC::G8RCRegClass) {
InflateGP8RC++; InflateGP8RC++;
return &PPC::SPILLTOVSRRCRegClass; return &PPC::SPILLTOVSRRCRegClass;
} }
if (RC == &PPC::GPRCRegClass && EnableGPRToVecSpills) if (RC == &PPC::GPRCRegClass && EnableGPRToVecSpills)
InflateGPRC++; InflateGPRC++;
} }
▲ Show 20 Lines • Show All 981 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/gpr-vsr-spill.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -ppc-enable-gpr-to-vsr-spills < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -ppc-enable-gpr-to-vsr-spills < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-ibm-aix-xcoff -ppc-enable-gpr-to-vsr-spills -vec-extabi < %s | FileCheck %s
define signext i32 @foo(i32 signext %a, i32 signext %b) { define signext i32 @foo(i32 signext %a, i32 signext %b) {
entry: entry:
%cmp = icmp slt i32 %a, %b %cmp = icmp slt i32 %a, %b
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry if.then: ; preds = %entry
%0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29}"(i32 %a, i32 %b) %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29}"(i32 %a, i32 %b)
%mul = mul nsw i32 %0, %a %mul = mul nsw i32 %0, %a
Show All 15 Lines