[RISCV] Add isel pattern to match X > -1 to bgez.

[craig.topper]

Remove an unnecessary 'the' from comment.

[asb]

LGTM, thanks!

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 // Extra patterns are needed for a brcond without a setcc (i.e. where the
 // condition was calculated elsewhere).
 def : Pat<(brcond GPR:$cond, bb:$imm12), (BNE GPR:$cond, X0, bb:$imm12)>;
 // In this pattern, the `(xor $cond, 1)` functions like (boolean) `not`, as the
 // `brcond` only uses the lowest bit.
 def : Pat<(brcond (XLenVT (xor GPR:$cond, 1)), bb:$imm12),
           (BEQ GPR:$cond, X0, bb:$imm12)>;
 
+// Match X > -1, the canonical form of X >= 0, to the bgez pattern.
+def : Pat<(brcond (XLenVT (setgt GPR:$rs1, -1)), bb:$imm12),
+          (BGE GPR:$rs1, X0, bb:$imm12)>;
+
 let isBarrier = 1, isBranch = 1, isTerminator = 1 in
 def PseudoBR : Pseudo<(outs), (ins simm21_lsb0_jal:$imm20), [(br bb:$imm20)]>,
                PseudoInstExpansion<(JAL X0, simm21_lsb0_jal:$imm20)>;
 
 let isBarrier = 1, isBranch = 1, isIndirectBranch = 1, isTerminator = 1 in
 def PseudoBRIND : Pseudo<(outs), (ins GPR:$rs1, simm12:$imm12), []>,
                   PseudoInstExpansion<(JALR X0, GPR:$rs1, simm12:$imm12)>;
 

llvm/test/CodeGen/RISCV/branch.ll

 ; RV32I-NEXT:    lw a3, 0(a1)
 ; RV32I-NEXT:    bgeu a0, a3, .LBB0_13
 ; RV32I-NEXT:  # %bb.10: # %test11
 ; RV32I-NEXT:    lw a0, 0(a1)
 ; RV32I-NEXT:    andi a0, a2, 1
 ; RV32I-NEXT:    bnez a0, .LBB0_13
 ; RV32I-NEXT:  # %bb.11: # %test12
 ; RV32I-NEXT:    lw a0, 0(a1)
-; RV32I-NEXT:    addi a2, zero, -1
-; RV32I-NEXT:    blt a2, a0, .LBB0_13
+; RV32I-NEXT:    bgez a0, .LBB0_13
 ; RV32I-NEXT:  # %bb.12: # %test13
 ; RV32I-NEXT:    lw a0, 0(a1)
 ; RV32I-NEXT:  .LBB0_13: # %end
 ; RV32I-NEXT:    ret
   %val1 = load volatile i32, i32* %b
   %tst1 = icmp eq i32 %val1, %a
   br i1 %tst1, label %end, label %test2
 

llvm/test/CodeGen/RISCV/xaluo.ll

 ; RV32-NEXT:    add a4, a1, a3
 ; RV32-NEXT:    add a2, a0, a2
 ; RV32-NEXT:    sltu a0, a2, a0
 ; RV32-NEXT:    add a0, a4, a0
 ; RV32-NEXT:    xor a0, a1, a0
 ; RV32-NEXT:    xor a1, a1, a3
 ; RV32-NEXT:    not a1, a1
 ; RV32-NEXT:    and a0, a1, a0
-; RV32-NEXT:    addi a1, zero, -1
-; RV32-NEXT:    blt a1, a0, .LBB47_2
+; RV32-NEXT:    bgez a0, .LBB47_2
 ; RV32-NEXT:  # %bb.1: # %overflow
 ; RV32-NEXT:    mv a0, zero
 ; RV32-NEXT:    ret
 ; RV32-NEXT:  .LBB47_2: # %continue
 ; RV32-NEXT:    addi a0, zero, 1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: saddo.br.i64:

 ; RV32-LABEL: ssubo.br.i64:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    sltu a0, a0, a2
 ; RV32-NEXT:    sub a2, a1, a3
 ; RV32-NEXT:    sub a0, a2, a0
 ; RV32-NEXT:    xor a0, a1, a0
 ; RV32-NEXT:    xor a1, a1, a3
 ; RV32-NEXT:    and a0, a1, a0
-; RV32-NEXT:    addi a1, zero, -1
-; RV32-NEXT:    blt a1, a0, .LBB51_2
+; RV32-NEXT:    bgez a0, .LBB51_2
 ; RV32-NEXT:  # %bb.1: # %overflow
 ; RV32-NEXT:    mv a0, zero
 ; RV32-NEXT:    ret
 ; RV32-NEXT:  .LBB51_2: # %continue
 ; RV32-NEXT:    addi a0, zero, 1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ssubo.br.i64: