Pass the cmdline aapcs bitfield options to cc1

[stuij]

Summary

The following commits added commandline arguments to control following the Arm
Procedure Call Standard for certain volatile bitfield operations:

• https://reviews.llvm.org/D67399
• https://reviews.llvm.org/D72932

This commit fixes the oversight that these args weren't passed from the driver
to cc1 if appropriate.

Where *appropriate* means:

• -faapcs-bitfield-width: is the default, so won't be passed
• -fno-aapcs-bitfield-width: should be passed
• -faapcs-bitfield-load: should be passed

[DavidSpickett]

Looks ok but needs tests. See clang/test/Driver for examples of checking -### output.

clang/lib/Driver/ToolChains/Clang.cpp

1531

Name this AddARMAAPCSVolatileBitfieldArgs to match the other helpers.

[stuij]

added unit tests for the cmdline args

clang/lib/Driver/ToolChains/Clang.cpp

1531

I deliberately didn't add ARM to the name as this function is used by both the Arm and AArch64 targets, and ARM would cause confusion. I figured AAPCS is differentiating enough, as it implies Arm without choosing a specific arch.

[DavidSpickett]

LGTM with /// for the comments in the test.

clang/lib/Driver/ToolChains/Clang.cpp

1531

Good point. At least one of the A's stands for Arm in any case.

clang/test/Driver/arm-aarch64-bitfield-flags.c

3

Nit: Use /// for comments that aren't run/check lines.

clang/lib/Driver/ToolChains/Clang.cpp

static void renderRemarksOptions(const ArgList &Args, ArgStringList &CmdArgs,
   }
 
   if (!Format.empty()) {
     CmdArgs.push_back("-opt-record-format");
     CmdArgs.push_back(Format.data());
   }
 }
 
+void AddAAPCSVolatileBitfieldArgs(const ArgList &Args, ArgStringList &CmdArgs) {
+  if (!Args.hasFlag(options::OPT_faapcs_bitfield_width,
+                    options::OPT_fno_aapcs_bitfield_width, true))
+    CmdArgs.push_back("-fno-aapcs-bitfield-width");
+
+  if (Args.getLastArg(options::OPT_ForceAAPCSBitfieldLoad))
+    CmdArgs.push_back("-faapcs-bitfield-load");
+}
+
 namespace {
 void RenderARMABI(const llvm::Triple &Triple, const ArgList &Args,
                   ArgStringList &CmdArgs) {
   // Select the ABI to use.
   // FIXME: Support -meabi.
   // FIXME: Parts of this are duplicated in the backend, unify this somehow.
   const char *ABIName = nullptr;
   if (Arg *A = Args.getLastArg(options::OPT_mabi_EQ)) {
void Clang::AddARMTargetArgs(const llvm::Triple &Triple, const ArgList &Args,
   }
 
   if (!Args.hasFlag(options::OPT_mimplicit_float,
                     options::OPT_mno_implicit_float, true))
     CmdArgs.push_back("-no-implicit-float");
 
   if (Args.getLastArg(options::OPT_mcmse))
     CmdArgs.push_back("-mcmse");
+
+  AddAAPCSVolatileBitfieldArgs(Args, CmdArgs);
 }
 
 void Clang::RenderTargetOptions(const llvm::Triple &EffectiveTriple,
                                 const ArgList &Args, bool KernelOrKext,
                                 ArgStringList &CmdArgs) const {
   const ToolChain &TC = getToolChain();
 
   // Add the target features
if (Val.equals("128") || Val.equals("256") || Val.equals("512") ||
       CmdArgs.push_back(
           Args.MakeArgString(llvm::Twine("-msve-vector-bits=") + Val));
     // Silently drop requests for vector-length agnostic code as it's implied.
     else if (!Val.equals("scalable"))
       // Handle the unsupported values passed to msve-vector-bits.
       D.Diag(diag::err_drv_unsupported_option_argument)
           << A->getOption().getName() << Val;
   }
+
+  AddAAPCSVolatileBitfieldArgs(Args, CmdArgs);
 }
 
 void Clang::AddMIPSTargetArgs(const ArgList &Args,
                               ArgStringList &CmdArgs) const {
   const Driver &D = getToolChain().getDriver();
   StringRef CPUName;
   StringRef ABIName;
   const llvm::Triple &Triple = getToolChain().getTriple();

clang/test/Driver/arm-aarch64-bitfield-flags.c

+/// check -faapcs-bitfield-width/-fno-aapcs-bitfield-width
+// RUN: %clang -target arm-arm-none-eabi -march=armv8-m.main -faapcs-bitfield-width -### %s 2>&1 | FileCheck --check-prefixes=WIDTH,INVERSE-WIDTH %s
+// RUN: %clang -target aarch64-arm-none-eabi -march=armv8-m.main -faapcs-bitfield-width -### %s 2>&1 | FileCheck --check-prefixes=WIDTH,INVERSE-WIDTH %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8-m.main -fno-aapcs-bitfield-width -### %s 2>&1 | FileCheck --check-prefixes=NO-WIDTH,WIDTH %s
+// RUN: %clang -target aarch64-arm-none-eabi -march=armv8-m.main -fno-aapcs-bitfield-width -### %s 2>&1 | FileCheck --check-prefixes=NO-WIDTH,WIDTH %s
+// WIDTH-NOT: -faapcs-bitfield-width
+// NO-WIDTH: -fno-aapcs-bitfield-width
+
+/// check -faapcs-bitfield-load
+// RUN: %clang -target arm-arm-none-eabi -march=armv8-m.main -faapcs-bitfield-load -### %s 2>&1 | FileCheck --check-prefix=LOAD %s
+// RUN: %clang -target aarch64-arm-none-eabi -march=armv8-m.main -faapcs-bitfield-load -### %s 2>&1 | FileCheck --check-prefix=LOAD %s
+// LOAD: -faapcs-bitfield-load
+
+/// check absence of the above argument when not given
+// RUN: %clang -target arm-arm-none-eabi -march=armv8-m.main -### %s 2>&1 | FileCheck --check-prefixes=INVERSE-WIDTH,INVERSE-LOAD %s
+// RUN: %clang -target aarch64-arm-none-eabi -march=armv8-m.main -### %s 2>&1 | FileCheck --check-prefixes=INVERSE-WIDTH,INVERSE-LOAD %s
+// INVERSE-WIDTH-NOT: -fno-aapcs-bitfield-width
+// INVERSE-LOAD-NOT: -fno-aapcs-bitfield-load