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Differential D96723

[ARM] Use rGPR for writeback vldrs
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Authored by dmgreen on Feb 15 2021, 10:11 AM.

Details

Reviewers
simon_tatham
SjoerdMeijer
efriedma
ostannard
NickGuy
Commits
rG1e007cf43c50: [ARM] Use rGPR for writeback vldrs
Summary

From what I can tell, a writeback is unpredictable with LR for both loads and stores. This changes the operand from a gprnopc to a rGPR in both cases (which I believe is essentially a NOP due to the tied-def already being a rGPR.)

Diff Detail

Event Timeline

dmgreen created this revision.Feb 15 2021, 10:11 AM
Herald added subscribers: danielkiss, hiraditya, kristof.beyls. · View Herald TranscriptFeb 15 2021, 10:11 AM
dmgreen requested review of this revision.Feb 15 2021, 10:11 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 15 2021, 10:11 AM
simon_tatham accepted this revision.Feb 16 2021, 4:44 AM

Oh yes, I must have seen if Rn == '1101' && W == '1' and absentmindedly interpreted the W as a write to memory, not a write back to the register.

This revision is now accepted and ready to land.Feb 16 2021, 4:44 AM
Closed by commit rG1e007cf43c50: [ARM] Use rGPR for writeback vldrs (authored by dmgreen). · Explain WhyFeb 16 2021, 8:45 AM
This revision was automatically updated to reflect the committed changes.
dmgreen added a commit: rG1e007cf43c50: [ARM] Use rGPR for writeback vldrs.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
6 lines
test/
CodeGen/
Thumb2/
LowOverheadLoops/
12 lines
46 lines

Diff 324022

llvm/lib/Target/ARM/ARMInstrMVE.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 6,258 Lines • ▼ Show 20 Lines def _pre : MVE_VLDRSTR_cs<
!con(dir.Iops, (ins t2addrmode_imm7_pre<memsz.shift>:$addr)), !con(dir.Iops, (ins t2addrmode_imm7_pre<memsz.shift>:$addr)),
asm, suffix, IndexModePre, "$Qd, $addr!", "$addr.base = $wb"> { asm, suffix, IndexModePre, "$Qd, $addr!", "$addr.base = $wb"> {
let DecoderMethod = "DecodeMVE_MEM_2_pre<"#memsz.shift#">"; let DecoderMethod = "DecodeMVE_MEM_2_pre<"#memsz.shift#">";
} }
def _post : MVE_VLDRSTR_cs< def _post : MVE_VLDRSTR_cs<
dir, memsz, 0, 1, dir, memsz, 0, 1,
!con((outs rGPR:$wb), dir.Oops), !con((outs rGPR:$wb), dir.Oops),
// We need an !if here to select the base register class, !con(dir.Iops, (ins t2_nosp_addr_offset_none:$Rn,
// because it's legal to write back to SP in a load of this
// type, but not in a store.
!con(dir.Iops, (ins !if(dir.load, t2_addr_offset_none,
t2_nosp_addr_offset_none):$Rn,
t2am_imm7_offset<memsz.shift>:$addr)), t2am_imm7_offset<memsz.shift>:$addr)),
asm, suffix, IndexModePost, "$Qd, $Rn$addr", "$Rn.base = $wb"> { asm, suffix, IndexModePost, "$Qd, $Rn$addr", "$Rn.base = $wb"> {
bits<4> Rn; bits<4> Rn;
let Inst{19-16} = Rn{3-0}; let Inst{19-16} = Rn{3-0};
} }
} }
} }
▲ Show 20 Lines • Show All 1,179 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/count_dominates_start.mir

Show First 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
... ...
--- ---
name: test name: test
alignment: 2 alignment: 2
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: rgpr, preferred-register: '' } - { id: 0, class: rgpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' } - { id: 1, class: gpr, preferred-register: '' }
- { id: 2, class: gprnopc, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
- { id: 3, class: gprnopc, preferred-register: '' } - { id: 3, class: rgpr, preferred-register: '' }
- { id: 4, class: tgpreven, preferred-register: '' } - { id: 4, class: tgpreven, preferred-register: '' }
- { id: 5, class: gprlr, preferred-register: '' } - { id: 5, class: gprlr, preferred-register: '' }
- { id: 6, class: rgpr, preferred-register: '' } - { id: 6, class: rgpr, preferred-register: '' }
- { id: 7, class: gpr, preferred-register: '' } - { id: 7, class: gpr, preferred-register: '' }
- { id: 8, class: gpr, preferred-register: '' } - { id: 8, class: gpr, preferred-register: '' }
- { id: 9, class: gpr, preferred-register: '' } - { id: 9, class: gpr, preferred-register: '' }
- { id: 10, class: gpr, preferred-register: '' } - { id: 10, class: gpr, preferred-register: '' }
- { id: 11, class: gpr, preferred-register: '' } - { id: 11, class: gpr, preferred-register: '' }
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Linesbody: |
; CHECK: [[t2ADDrs:%[0-9]+]]:gprnopc = nuw nsw t2ADDrs [[t2MOVi1]], [[t2SUBri]], 27, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[t2ADDrs:%[0-9]+]]:gprnopc = nuw nsw t2ADDrs [[t2MOVi1]], [[t2SUBri]], 27, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[COPY4:%[0-9]+]]:rgpr = COPY [[t2ADDrs]] ; CHECK: [[COPY4:%[0-9]+]]:rgpr = COPY [[t2ADDrs]]
; CHECK: [[t2MOVi2:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[t2MOVi2:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[COPY5:%[0-9]+]]:gpr = COPY [[t2MOVi2]] ; CHECK: [[COPY5:%[0-9]+]]:gpr = COPY [[t2MOVi2]]
; CHECK: [[COPY6:%[0-9]+]]:rgpr = COPY [[COPY]] ; CHECK: [[COPY6:%[0-9]+]]:rgpr = COPY [[COPY]]
; CHECK: [[t2DoLoopStartTP:%[0-9]+]]:gprlr = t2DoLoopStartTP [[COPY4]], [[COPY6]] ; CHECK: [[t2DoLoopStartTP:%[0-9]+]]:gprlr = t2DoLoopStartTP [[COPY4]], [[COPY6]]
; CHECK: bb.3.vector.body: ; CHECK: bb.3.vector.body:
; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000) ; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000)
; CHECK: [[PHI:%[0-9]+]]:gprnopc = PHI [[COPY2]], %bb.2, %10, %bb.3 ; CHECK: [[PHI:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.2, %10, %bb.3
; CHECK: [[PHI1:%[0-9]+]]:gprnopc = PHI [[COPY1]], %bb.2, %9, %bb.3 ; CHECK: [[PHI1:%[0-9]+]]:rgpr = PHI [[COPY1]], %bb.2, %9, %bb.3
; CHECK: [[PHI2:%[0-9]+]]:tgpreven = PHI [[COPY5]], %bb.2, %8, %bb.3 ; CHECK: [[PHI2:%[0-9]+]]:tgpreven = PHI [[COPY5]], %bb.2, %8, %bb.3
; CHECK: [[PHI3:%[0-9]+]]:gprlr = PHI [[t2DoLoopStartTP]], %bb.2, %33, %bb.3 ; CHECK: [[PHI3:%[0-9]+]]:gprlr = PHI [[t2DoLoopStartTP]], %bb.2, %33, %bb.3
; CHECK: [[PHI4:%[0-9]+]]:rgpr = PHI [[COPY6]], %bb.2, %7, %bb.3 ; CHECK: [[PHI4:%[0-9]+]]:rgpr = PHI [[COPY6]], %bb.2, %7, %bb.3
; CHECK: [[MVE_VCTP16_:%[0-9]+]]:vccr = MVE_VCTP16 [[PHI4]], 0, $noreg ; CHECK: [[MVE_VCTP16_:%[0-9]+]]:vccr = MVE_VCTP16 [[PHI4]], 0, $noreg
; CHECK: [[t2SUBri1:%[0-9]+]]:rgpr = t2SUBri [[PHI4]], 8, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[t2SUBri1:%[0-9]+]]:rgpr = t2SUBri [[PHI4]], 8, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[COPY7:%[0-9]+]]:gpr = COPY [[t2SUBri1]] ; CHECK: [[COPY7:%[0-9]+]]:gpr = COPY [[t2SUBri1]]
; CHECK: [[MVE_VLDRHU16_post:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_post1:%[0-9]+]]:mqpr = MVE_VLDRHU16_post [[PHI]], 16, 1, [[MVE_VCTP16_]] :: (load 16 from %ir.lsr.iv35, align 2) ; CHECK: [[MVE_VLDRHU16_post:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_post1:%[0-9]+]]:mqpr = MVE_VLDRHU16_post [[PHI]], 16, 1, [[MVE_VCTP16_]] :: (load 16 from %ir.lsr.iv35, align 2)
; CHECK: [[MVE_VLDRHU16_post2:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_post3:%[0-9]+]]:mqpr = MVE_VLDRHU16_post [[PHI1]], 16, 1, [[MVE_VCTP16_]] :: (load 16 from %ir.lsr.iv12, align 2) ; CHECK: [[MVE_VLDRHU16_post2:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_post3:%[0-9]+]]:mqpr = MVE_VLDRHU16_post [[PHI1]], 16, 1, [[MVE_VCTP16_]] :: (load 16 from %ir.lsr.iv12, align 2)
Show All 37 Lines bb.1.vector.ph:
%25:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg %25:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
%23:gpr = COPY %25 %23:gpr = COPY %25
%1:gpr = COPY %24 %1:gpr = COPY %24
%35:gprnopc = COPY %15 %35:gprnopc = COPY %15
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
%2:gprnopc = PHI %13, %bb.1, %10, %bb.2 %2:rgpr = PHI %13, %bb.1, %10, %bb.2
%3:gprnopc = PHI %14, %bb.1, %9, %bb.2 %3:rgpr = PHI %14, %bb.1, %9, %bb.2
%4:tgpreven = PHI %23, %bb.1, %8, %bb.2 %4:tgpreven = PHI %23, %bb.1, %8, %bb.2
%5:gprlr = PHI %1, %bb.1, %11, %bb.2 %5:gprlr = PHI %1, %bb.1, %11, %bb.2
%6:rgpr = PHI %35, %bb.1, %7, %bb.2 %6:rgpr = PHI %35, %bb.1, %7, %bb.2
%26:vccr = MVE_VCTP16 %6, 0, $noreg %26:vccr = MVE_VCTP16 %6, 0, $noreg
%27:rgpr = t2SUBri %6, 8, 14 /* CC::al */, $noreg, $noreg %27:rgpr = t2SUBri %6, 8, 14 /* CC::al */, $noreg, $noreg
%7:gpr = COPY %27 %7:gpr = COPY %27
%28:rgpr, %29:mqpr = MVE_VLDRHU16_post %2, 16, 1, %26 :: (load 16 from %ir.lsr.iv35, align 2) %28:rgpr, %29:mqpr = MVE_VLDRHU16_post %2, 16, 1, %26 :: (load 16 from %ir.lsr.iv35, align 2)
%30:rgpr, %31:mqpr = MVE_VLDRHU16_post %3, 16, 1, %26 :: (load 16 from %ir.lsr.iv12, align 2) %30:rgpr, %31:mqpr = MVE_VLDRHU16_post %3, 16, 1, %26 :: (load 16 from %ir.lsr.iv12, align 2)
Show All 15 Lines

llvm/test/CodeGen/Thumb2/mve-postinc-distribute.mir

Show First 20 Lines • Show All 81 Lines • ▼ Show 20 Linesliveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VLDRWU32 ; CHECK-LABEL: name: MVE_VLDRWU32
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8)
; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:gprnopc = COPY $r0 %0:gprnopc = COPY $r0
%1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8) %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8)
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
Show All 10 Linesliveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VLDRHU16 ; CHECK-LABEL: name: MVE_VLDRHU16
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VLDRHU16_post:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_post1:%[0-9]+]]:mqpr = MVE_VLDRHU16_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRHU16_post:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_post1:%[0-9]+]]:mqpr = MVE_VLDRHU16_post [[COPY]], 32, 0, $noreg :: (load 16, align 8)
; CHECK: $r0 = COPY [[MVE_VLDRHU16_post]] ; CHECK: $r0 = COPY [[MVE_VLDRHU16_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:gprnopc = COPY $r0 %0:gprnopc = COPY $r0
%1:mqpr = MVE_VLDRHU16 %0, 0, 0, $noreg :: (load 16, align 8) %1:mqpr = MVE_VLDRHU16 %0, 0, 0, $noreg :: (load 16, align 8)
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
Show All 10 Linesliveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VLDRBU8 ; CHECK-LABEL: name: MVE_VLDRBU8
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VLDRBU8_post:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_post1:%[0-9]+]]:mqpr = MVE_VLDRBU8_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRBU8_post:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_post1:%[0-9]+]]:mqpr = MVE_VLDRBU8_post [[COPY]], 32, 0, $noreg :: (load 16, align 8)
; CHECK: $r0 = COPY [[MVE_VLDRBU8_post]] ; CHECK: $r0 = COPY [[MVE_VLDRBU8_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:gprnopc = COPY $r0 %0:gprnopc = COPY $r0
%1:mqpr = MVE_VLDRBU8 %0, 0, 0, $noreg :: (load 16, align 8) %1:mqpr = MVE_VLDRBU8 %0, 0, 0, $noreg :: (load 16, align 8)
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
▲ Show 20 Lines • Show All 347 Lines • ▼ Show 20 Linesliveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: ld0ld4 ; CHECK-LABEL: name: ld0ld4
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8)
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -28, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -28, 0, $noreg :: (load 16, align 8)
; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:gprnopc = COPY $r0 %0:gprnopc = COPY $r0
%1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8) %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8)
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
%3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8) %3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8)
Show All 13 Linesliveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: ld4ld0 ; CHECK-LABEL: name: ld4ld0
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8)
; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8)
; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:gprnopc = COPY $r0 %0:gprnopc = COPY $r0
%1:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8) %1:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8)
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
%3:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8) %3:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8)
Show All 14 Linesliveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: ld0ld4ld0 ; CHECK-LABEL: name: ld0ld4ld0
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8)
; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8)
; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8)
; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:gprnopc = COPY $r0 %0:gprnopc = COPY $r0
%1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8) %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8)
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
Show All 16 Linesliveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: ld4ld0ld4 ; CHECK-LABEL: name: ld4ld0ld4
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8)
; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8)
; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -28, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -28, 0, $noreg :: (load 16, align 8)
; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:gprnopc = COPY $r0 %0:gprnopc = COPY $r0
%1:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8) %1:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8)
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
Show All 15 Linesliveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: addload ; CHECK-LABEL: name: addload
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8)
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -28, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -28, 0, $noreg :: (load 16, align 8)
; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:gprnopc = COPY $r0 %0:gprnopc = COPY $r0
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
%1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8) %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8)
%3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8) %3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8)
Show All 13 Linesliveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: sub ; CHECK-LABEL: name: sub
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], -32, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], -32, 0, $noreg :: (load 16, align 8)
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], 36, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], 36, 0, $noreg :: (load 16, align 8)
; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:gprnopc = COPY $r0 %0:gprnopc = COPY $r0
%1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8) %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8)
%2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg
%3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8) %3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8)
Show All 33 Lines bb.0:
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: postincUse name: postincUse
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprnopc, preferred-register: '' } - { id: 0, class: rgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
- { id: 3, class: mqpr, preferred-register: '' } - { id: 3, class: mqpr, preferred-register: '' }
- { id: 4, class: rgpr, preferred-register: '' } - { id: 4, class: rgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: postincUse ; CHECK-LABEL: name: postincUse
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8)
; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 4, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 4, 0, $noreg :: (load 16, align 8)
; CHECK: $r0 = COPY [[t2ADDri]] ; CHECK: $r0 = COPY [[t2ADDri]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:gprnopc = COPY $r0 %0:rgpr = COPY $r0
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
%1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8) %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8)
%4:rgpr, %3:mqpr = MVE_VLDRWU32_post %0, 4, 0, $noreg :: (load 16, align 8) %4:rgpr, %3:mqpr = MVE_VLDRWU32_post %0, 4, 0, $noreg :: (load 16, align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Linesliveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: addUseOK ; CHECK-LABEL: name: addUseOK
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], -32, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], -32, 0, $noreg :: (load 16, align 8)
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], 36, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], 36, 0, $noreg :: (load 16, align 8)
; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = nuw t2LSRri [[MVE_VLDRWU32_post]], 2, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = nuw t2LSRri [[MVE_VLDRWU32_post]], 2, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2LSRri]] ; CHECK: $r0 = COPY [[t2LSRri]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:gprnopc = COPY $r0 %0:gprnopc = COPY $r0
%1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8) %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8)
%2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Linesliveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: addUseKilled ; CHECK-LABEL: name: addUseKilled
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], -32, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], -32, 0, $noreg :: (load 16, align 8)
; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = nuw t2LSRri [[MVE_VLDRWU32_post]], 2, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = nuw t2LSRri [[MVE_VLDRWU32_post]], 2, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], 36, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], 36, 0, $noreg :: (load 16, align 8)
; CHECK: $r0 = COPY [[t2LSRri]] ; CHECK: $r0 = COPY [[t2LSRri]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:gprnopc = COPY $r0 %0:gprnopc = COPY $r0
%1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8) %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8)
%2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg
%4:rgpr = nuw t2LSRri killed %2, 2, 14, $noreg, $noreg %4:rgpr = nuw t2LSRri killed %2, 2, 14, $noreg, $noreg
%3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8) %3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8)
$r0 = COPY %4 $r0 = COPY %4
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VLDRWU32_post name: MVE_VLDRWU32_post
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprnopc, preferred-register: '' } - { id: 0, class: rgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VLDRWU32_post ; CHECK-LABEL: name: MVE_VLDRWU32_post
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8)
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -16, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -16, 0, $noreg :: (load 16, align 8)
; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:gprnopc = COPY $r0 %0:rgpr = COPY $r0
%2:rgpr, %1:mqpr = MVE_VLDRWU32_post %0, 32, 0, $noreg :: (load 16, align 8) %2:rgpr, %1:mqpr = MVE_VLDRWU32_post %0, 32, 0, $noreg :: (load 16, align 8)
%1:mqpr = MVE_VLDRWU32 %0, 16, 0, $noreg :: (load 16, align 8) %1:mqpr = MVE_VLDRWU32 %0, 16, 0, $noreg :: (load 16, align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VLDRHU16_post name: MVE_VLDRHU16_post
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprnopc, preferred-register: '' } - { id: 0, class: rgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VLDRHU16_post ; CHECK-LABEL: name: MVE_VLDRHU16_post
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VLDRHU16_post:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_post1:%[0-9]+]]:mqpr = MVE_VLDRHU16_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRHU16_post:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_post1:%[0-9]+]]:mqpr = MVE_VLDRHU16_post [[COPY]], 32, 0, $noreg :: (load 16, align 8)
; CHECK: [[MVE_VLDRHU16_:%[0-9]+]]:mqpr = MVE_VLDRHU16 [[MVE_VLDRHU16_post]], -16, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRHU16_:%[0-9]+]]:mqpr = MVE_VLDRHU16 [[MVE_VLDRHU16_post]], -16, 0, $noreg :: (load 16, align 8)
; CHECK: $r0 = COPY [[MVE_VLDRHU16_post]] ; CHECK: $r0 = COPY [[MVE_VLDRHU16_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:gprnopc = COPY $r0 %0:rgpr = COPY $r0
%2:rgpr, %1:mqpr = MVE_VLDRHU16_post %0, 32, 0, $noreg :: (load 16, align 8) %2:rgpr, %1:mqpr = MVE_VLDRHU16_post %0, 32, 0, $noreg :: (load 16, align 8)
%1:mqpr = MVE_VLDRHU16 %0, 16, 0, $noreg :: (load 16, align 8) %1:mqpr = MVE_VLDRHU16 %0, 16, 0, $noreg :: (load 16, align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VLDRBU8_post name: MVE_VLDRBU8_post
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprnopc, preferred-register: '' } - { id: 0, class: rgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VLDRBU8_post ; CHECK-LABEL: name: MVE_VLDRBU8_post
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VLDRBU8_post:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_post1:%[0-9]+]]:mqpr = MVE_VLDRBU8_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRBU8_post:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_post1:%[0-9]+]]:mqpr = MVE_VLDRBU8_post [[COPY]], 32, 0, $noreg :: (load 16, align 8)
; CHECK: [[MVE_VLDRBU8_:%[0-9]+]]:mqpr = MVE_VLDRBU8 [[MVE_VLDRBU8_post]], -16, 0, $noreg :: (load 16, align 8) ; CHECK: [[MVE_VLDRBU8_:%[0-9]+]]:mqpr = MVE_VLDRBU8 [[MVE_VLDRBU8_post]], -16, 0, $noreg :: (load 16, align 8)
; CHECK: $r0 = COPY [[MVE_VLDRBU8_post]] ; CHECK: $r0 = COPY [[MVE_VLDRBU8_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:gprnopc = COPY $r0 %0:rgpr = COPY $r0
%2:rgpr, %1:mqpr = MVE_VLDRBU8_post %0, 32, 0, $noreg :: (load 16, align 8) %2:rgpr, %1:mqpr = MVE_VLDRBU8_post %0, 32, 0, $noreg :: (load 16, align 8)
%1:mqpr = MVE_VLDRBU8 %0, 16, 0, $noreg :: (load 16, align 8) %1:mqpr = MVE_VLDRBU8 %0, 16, 0, $noreg :: (load 16, align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VLDRBS32_post name: MVE_VLDRBS32_post
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