Address craig.topper 's comment

[StephenFan]

Address craig.topper 's comment

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

OperandMatchResultTy RISCVAsmParser::parseVTypeI(OperandVector &Operands) {
 
   SmallVector<AsmToken, 7> VTypeIElements;
   // Put all the tokens for vtypei operand into VTypeIElements vector.
   while (getLexer().isNot(AsmToken::EndOfStatement)) {
     VTypeIElements.push_back(getLexer().getTok());
     getLexer().Lex();
     if (getLexer().is(AsmToken::EndOfStatement))
       break;
-    if (!getLexer().is(AsmToken::Comma))
+    if (getLexer().isNot(AsmToken::Comma))
       goto MatchFail;
     AsmToken Comma = getLexer().getTok();
     VTypeIElements.push_back(Comma);
     getLexer().Lex();
   }
 
   if (VTypeIElements.size() == 7) {
     // The VTypeIElements layout is:
if (VTypeIElements.size() == 7) {
     unsigned VTypeI =
         RISCVVType::encodeVTYPE(VLMUL, VSEW, TailAgnostic, MaskAgnostic);
     Operands.push_back(RISCVOperand::createVType(VTypeI, S, isRV64()));
     return MatchOperand_Success;
   }
 
 // If NoMatch, unlex all the tokens that comprise a vtypei operand
 MatchFail:
-  while (VTypeIElements.size() > 0)
+  while (!VTypeIElements.empty())
     getLexer().UnLex(VTypeIElements.pop_back_val());
   return MatchOperand_NoMatch;
 }
 
 OperandMatchResultTy RISCVAsmParser::parseMaskReg(OperandVector &Operands) {
   switch (getLexer().getKind()) {
   default:
     return MatchOperand_NoMatch;