[LLDB] Arm64/Linux Add MTE and Pointer Authentication registers

[omjavaid]

Summary

This patch adds two new register sets for MTE and Pointer Authentication feature registers. These register sets are dynamic and will only be available if underlying hardware support either of these features. LLDB will pull in Aux vector information and create register infos based on that information.

A follow up patch will add a test case to test these feature registers.

[DavidSpickett]

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp

82

Should m_pac_mask also be initialised or is it already?

120

I think this should be more defensive:

if (auxv_at_hwcap && (*auxv_at_hwcap & HWCAP_PACA))

Otherwise you'll deference an invalid optional, which might work if its storage happens to be zeroed but it's not intended use.

126

Same here, auxv_at_hwcap2 could be llvm::None.

543

Can you simplify these?

return GetRegisterInfo().IsPAuthReg(reg);

(the others could do that too, but obviously we're ignoring those ones here)

1108

I think m_mte_ctrl_is_valid is missing here.

1209

Just to confirm I understand this logic.

If m_mte_ctrl_is_valid would mean that our cached value of the register is valid. So if something tries to read a new copy of it we fail because they should have used the cached version?

Then if m_mte_ctrl_is_valid is false, our cache is out of date so we do the read.

Seems odd to error on asking for a read of a value that is cached but then again I don't know the surrounding code too well. If that pattern is already established no point disturbing it now.

1227

This is a sanity check that we didn't ask to write this register on a system that doesn't have it?

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h

182

This looks like a mistake.

lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp

323

Can you get this 2 from some list somewhere in this class? E.g. PauthRegs.Size(). Or add a comment if not.

g_register_infos_pauth perhaps?

327

Is it possible at this point that m_dynamic_reg_infos.size() is 0 making m_dynamic_reg_infos[pa_regnum + i - 1] into m_dynamic_reg_infos[0 + 0 - 1] ?

I guess this could happen if SVE wasn't present but maybe you already account for that.

329

Please comment what the [4] is getting.

333

You could simplify this with back (https://www.cplusplus.com/reference/vector/vector/back/) assuming this is a vector-ish type.

339

Same as above

Given that there's only one MTE register you could also remove the for since we'll only ever have i==0. If we want to be nice and handle future expansion some MTERegs.size() would be preferred.

434

return std::find(pauth_regnum_collection.begin(), pauth_regnum_collection.end(),
                reg) != pauth_regnum_collection.end();

440

as above

lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h

537

DEFINE_PAUTH_REGS is an odd name considering we use it for MTE too. DEFINE_EXTENSION_REGS ?

Also I would make it singular "REG"

lldb/source/Plugins/Process/Utility/RegisterInfos_arm64_sve.h

64 ↗

(On Diff #322851)

This seems unrelated

[omjavaid]

Subsequent update will resolve review comments. @DavidSpickett thanks for review. much appreciated

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp

82

Ack. Forgot to do it.

120

Agreed

126

Ack.

1108

Ack.

1209

Status is used to hold error codes and default error code is 'success'. If we have a valid cache value that means we dont need to read and return success thats why returning error without setting the error code.

If we need to read then we call ReadRegisterSet which will set the error code in case of failure.

1227

This may only be relevant for optional regsets where we need to check if registers are readable before writing and registers which need partial modification and we need to have most recent value.

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h

182

yes!!!

lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp

323

k_num_pauth_register already populated and will be used here as well.

327

Its not possible for m_dynamic_reg_infos.size to be zero because it is populated with either g_register_infos_arm64_sve_le or g_register_infos_arm64_le register infos array.

329

Ack.

333

done.

339

Ack.

434

Ack.

440

Ack.

lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h

537

Agreed.

lldb/source/Plugins/Process/Utility/RegisterInfos_arm64_sve.h

64 ↗

(On Diff #322851)

Ack.

[DavidSpickett]

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp

1209

Doh, yes I missed that that "error" will not be a failure at that point.

[omjavaid]

Rebased after updates to parent.

[DavidSpickett]

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp

1127–1146

Indent here

Actually, for these you could just do m_sve_header_is_valid = error.Success(), no if needed. Assuming setting it false here is also fine, which it might not be.

1161

Should be GetPACMaskSize

1164

see above

1218

see above

lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp

276

(like earlier) would it be ok to remove the if?

m_mte_regset_enabled = opt_regsets & eRegsetEnableMTE;

lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h

29

indentation

[omjavaid]

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp

1127–1146

I guess this is inline with rest of the code in this file. Also avoiding write every time may well be a tiny bit faster as we avoid flushing the cache line to which m_sve_header_is_valid belongs.

lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp

276

I think here as well if do write eveytime regardless of true/false we might end up refreshing the whole data set contained in cache against a RegisterInfoPOSIX_arm64 object. What do you think?

[omjavaid]

Ran clang format and fixed typos.

[DavidSpickett]

lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp

276

I assume you mean the cpu cache not any lldb register cache, I don't see a need to care that much about it here.

The reason to always assign is so that there's no implication that there's a 3rd state. Like "false and not enabled" "true and enabled" "false and enabled" (which makes no sense but types wise, it's possible).

Granted it's a drop in the bucket vs the rest of the state we're handling here so I'll leave it up to you.

[omjavaid]

Rebased after changes to parent.

[omjavaid]

Updated after changes in parent. Also removed D96459

[omjavaid]

Rebased after changes to parent D96458

[labath]

This still suffers from the duplication of the auxv reading code from NativeProcessELF. Other than that, it's ok-ish.

[omjavaid]

Pulling GetAuxValue from NativeProcessELF. @labath what do you think.

[labath]

Looks good (and sorry for the delay). Just rebase to main to avoid the cast.

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp

62

After d1486e65a164, this cast should be unnecessary.

[DavidSpickett]

@omjavaid I get some new warnings when compiling this on x86:

[732/1117] Building CXX object too.../RegisterContextDarwin_arm64.cpp.o
In file included from /work/open_source/lldb-cross-compile/llvm-project/lldb/source/Plugins/Process/Utility/RegisterContextDarwin_arm64.cpp:70:
/work/open_source/lldb-cross-compile/llvm-project/lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h:794:35: warning: ‘g_register_infos_mte’ defined but not used [-Wunused-variable]
  794 | static lldb_private::RegisterInfo g_register_infos_mte[] = {
      |                                   ^~~~~~~~~~~~~~~~~~~~
/work/open_source/lldb-cross-compile/llvm-project/lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h:791:35: warning: ‘g_register_infos_pauth’ defined but not used [-Wunused-variable]
  791 | static lldb_private::RegisterInfo g_register_infos_pauth[] = {
      |                                   ^~~~~~~~~~~~~~~~~~~~~~

Makes some sense that they're not used but presumably we could mark them as such? In case it's g++ not seeing the existing macros properly, I'm using:

g++-9 (Ubuntu 9.3.0-23ubuntu1~16.04) 9.3.0

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h

protected:
   void *GetFPRBuffer() override { return &m_fpr; }
 
   size_t GetFPRSize() override { return sizeof(m_fpr); }
 
 private:
   bool m_gpr_is_valid;
   bool m_fpu_is_valid;
   bool m_sve_buffer_is_valid;
+  bool m_mte_ctrl_is_valid;
 
   bool m_sve_header_is_valid;
+  bool m_pac_mask_is_valid;
 
   struct user_pt_regs m_gpr_arm64; // 64-bit general purpose registers.
 
   RegisterInfoPOSIX_arm64::FPU
       m_fpr; // floating-point registers including extended register sets.
 
   SVEState m_sve_state;
   struct user_sve_header m_sve_header;
private:
 
   struct DREG m_hbr_regs[16]; // Arm native linux hardware breakpoints
   struct DREG m_hwp_regs[16]; // Arm native linux hardware watchpoints
 
   uint32_t m_max_hwp_supported;
   uint32_t m_max_hbp_supported;
   bool m_refresh_hwdebug_info;
 
+  struct user_pac_mask {
+    uint64_t data_mask;
+    uint64_t insn_mask;
+  };
+
+  struct user_pac_mask m_pac_mask;
+
+  uint64_t m_mte_ctrl_reg;
+
   bool IsGPR(unsigned reg) const;
 
   bool IsFPR(unsigned reg) const;
 
   Status ReadAllSVE();
 
   Status WriteAllSVE();
 
   Status ReadSVEHeader();
 
   Status WriteSVEHeader();
 
+  Status ReadPAuthMask();
+
+  Status ReadMTEControl();
+
+  Status WriteMTEControl();
+
   bool IsSVE(unsigned reg) const;
+  bool IsPAuth(unsigned reg) const;
+  bool IsMTE(unsigned reg) const;
 
   uint64_t GetSVERegVG() { return m_sve_header.vl / 8; }
 
   void SetSVERegVG(uint64_t vg) { m_sve_header.vl = vg * 8; }
 
   void *GetSVEHeader() { return &m_sve_header; }
 
+  void *GetPACMask() { return &m_pac_mask; }
+
+  void *GetMTEControl() { return &m_mte_ctrl_reg; }
+
   void *GetSVEBuffer();
 
   size_t GetSVEHeaderSize() { return sizeof(m_sve_header); }
 
+  size_t GetPACMaskSize() { return sizeof(m_pac_mask); }
+
   size_t GetSVEBufferSize() { return m_sve_ptrace_payload.size(); }
 
+  size_t GetMTEControlSize() { return sizeof(m_mte_ctrl_reg); }
+
   Status ReadHardwareDebugInfo();
 
   uint32_t QueryAuxvForOptionalRegset();
 
   Status WriteHardwareDebugRegs(int hwbType);
 
   uint32_t CalculateFprOffset(const RegisterInfo *reg_info) const;
 

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp

 #include <sys/socket.h>
 // NT_PRSTATUS and NT_FPREGSET definition
 #include <elf.h>
 
 #ifndef NT_ARM_SVE
 #define NT_ARM_SVE 0x405 /* ARM Scalable Vector Extension */
 #endif
 
+#ifndef NT_ARM_PAC_MASK
+#define NT_ARM_PAC_MASK 0x406 /* Pointer authentication code masks */
+#endif
+
+#ifndef NT_ARM_TAGGED_ADDR_CTRL
+#define NT_ARM_TAGGED_ADDR_CTRL 0x409 /* Tagged address control register */
+#endif
+
+#define HWCAP_PACA (1 << 30)
+#define HWCAP2_MTE (1 << 18)
+
 #define REG_CONTEXT_SIZE (GetGPRSize() + GetFPRSize())
 
 using namespace lldb;
 using namespace lldb_private;
 using namespace lldb_private::process_linux;
 
 std::unique_ptr<NativeRegisterContextLinux>
 NativeRegisterContextLinux::CreateHostNativeRegisterContextLinux(
     const ArchSpec &target_arch, NativeThreadProtocol &native_thread) {
   switch (target_arch.GetMachine()) {
   case llvm::Triple::arm:
     return std::make_unique<NativeRegisterContextLinux_arm>(target_arch,
                                                              native_thread);
   case llvm::Triple::aarch64:
     return std::make_unique<NativeRegisterContextLinux_arm64>(target_arch,
                                                                native_thread);
   default:
     llvm_unreachable("have no register context for architecture");
   }
 }
 
 NativeRegisterContextLinux_arm64::NativeRegisterContextLinux_arm64(
     const ArchSpec &target_arch, NativeThreadProtocol &native_thread)
     : NativeRegisterContextRegisterInfo(
           native_thread, new RegisterInfoPOSIX_arm64(target_arch)) {
   ::memset(&m_fpr, 0, sizeof(m_fpr));
   ::memset(&m_gpr_arm64, 0, sizeof(m_gpr_arm64));
   ::memset(&m_hwp_regs, 0, sizeof(m_hwp_regs));
   ::memset(&m_hbr_regs, 0, sizeof(m_hbr_regs));
   ::memset(&m_sve_header, 0, sizeof(m_sve_header));
+  ::memset(&m_pac_mask, 0, sizeof(m_pac_mask));
+
+  m_mte_ctrl_reg = 0;
 
   // 16 is just a maximum value, query hardware for actual watchpoint count
   m_max_hwp_supported = 16;
   m_max_hbp_supported = 16;
 
   m_refresh_hwdebug_info = true;
 
   m_gpr_is_valid = false;
   m_fpu_is_valid = false;
   m_sve_buffer_is_valid = false;
   m_sve_header_is_valid = false;
+  m_pac_mask_is_valid = false;
+  m_mte_ctrl_is_valid = false;
 
   // At this stage we configure register sets supported by this AArch64 target.
   // ReadSVEHeader is called to check for SVE support.
   Status error = ReadSVEHeader();
   uint32_t opt_regset = QueryAuxvForOptionalRegset();
   if (error.Success()) {
     // SVE is supported, enable its register set.
     // Setting m_sve_state to SVEState::Unknown it will be updated by

 }
 
 RegisterInfoPOSIX_arm64 &
 NativeRegisterContextLinux_arm64::GetRegisterInfo() const {
   return static_cast<RegisterInfoPOSIX_arm64 &>(*m_register_info_interface_up);
 }
 
 uint32_t NativeRegisterContextLinux_arm64::QueryAuxvForOptionalRegset() {
-  return RegisterInfoPOSIX_arm64::eRegsetEnableSVE;
+  NativeProcessProtocol &process = m_thread.GetProcess();
+  auto buffer_or_error = process.GetAuxvData();
+  if (!buffer_or_error)
+    return 0;
+
+  DataExtractor auxv_data(buffer_or_error.get()->getBufferStart(),
+                          buffer_or_error.get()->getBufferSize(),
+                          process.GetByteOrder(), process.GetAddressByteSize());
+
+  std::unique_ptr<AuxVector> aux_vector =
+      std::make_unique<AuxVector>(auxv_data);
+
+  llvm::Optional<uint64_t> auxv_at_hwcap =
+      aux_vector->GetAuxValue(AuxVector::AUXV_AT_HWCAP);
+  uint32_t result = RegisterInfoPOSIX_arm64::eRegsetEnableDefault;
+  if (auxv_at_hwcap && *auxv_at_hwcap & HWCAP_PACA)
+    result |= RegisterInfoPOSIX_arm64::eRegsetEnablePAuth;
+
+  llvm::Optional<uint64_t> auxv_at_hwcap2 =
+      aux_vector->GetAuxValue(AuxVector::AUXV_AT_HWCAP2);
+
+  if (auxv_at_hwcap && *auxv_at_hwcap2 & HWCAP2_MTE)
+    result |= RegisterInfoPOSIX_arm64::eRegsetEnableMTE;
+
+  return result;
 }
 
 uint32_t NativeRegisterContextLinux_arm64::GetRegisterSetCount() const {
   return GetRegisterInfo().GetRegisterSetCount();
 }
 
 const RegisterSet *
 NativeRegisterContextLinux_arm64::GetRegisterSet(uint32_t set_index) const {
if (GetRegisterInfo().IsSVERegVG(reg)) {
                    16);
         }
       } else {
         offset = CalculateSVEOffset(reg_info);
         assert(offset < GetSVEBufferSize());
         src = (uint8_t *)GetSVEBuffer() + offset;
       }
     }
+  } else if (IsPAuth(reg)) {
+    error = ReadPAuthMask();
+    if (error.Fail())
+      return error;
+
+    offset = reg_info->byte_offset - GetRegisterInfo().GetPAuthOffset();
+    assert(offset < GetPACMaskSize());
+    src = (uint8_t *)GetPACMask() + offset;
+  } else if (IsMTE(reg)) {
+    error = ReadMTEControl();
+    if (error.Fail())
+      return error;
+
+    offset = reg_info->byte_offset - GetRegisterInfo().GetMTEOffset();
+    assert(offset < GetMTEControlSize());
+    src = (uint8_t *)GetMTEControl() + offset;
   } else
     return Status("failed - register wasn't recognized to be a GPR or an FPR, "
                   "write strategy unknown");
 
   reg_value.SetFromMemoryData(reg_info, src, reg_info->byte_size,
                               eByteOrderLittle, error);
 
   return error;
else {
       } else {
         offset = CalculateSVEOffset(reg_info);
         assert(offset < GetSVEBufferSize());
         dst = (uint8_t *)GetSVEBuffer() + offset;
         ::memcpy(dst, reg_value.GetBytes(), reg_info->byte_size);
         return WriteAllSVE();
       }
     }
+  } else if (IsMTE(reg)) {
+    error = ReadMTEControl();
+    if (error.Fail())
+      return error;
+
+    offset = reg_info->byte_offset - GetRegisterInfo().GetMTEOffset();
+    assert(offset < GetMTEControlSize());
+    dst = (uint8_t *)GetMTEControl() + offset;
+    ::memcpy(dst, reg_value.GetBytes(), reg_info->byte_size);
+
+    return WriteMTEControl();
   }
 
   return Status("Failed to write register value");
 }
 
 Status NativeRegisterContextLinux_arm64::ReadAllRegisterValues(
     lldb::DataBufferSP &data_sp) {
   Status error;
if (GetRegisterInfo().GetRegisterSetFromRegisterIndex(reg) ==
     return true;
   return false;
 }
 
 bool NativeRegisterContextLinux_arm64::IsSVE(unsigned reg) const {
   return GetRegisterInfo().IsSVEReg(reg);
 }
 
+bool NativeRegisterContextLinux_arm64::IsPAuth(unsigned reg) const {
+  return GetRegisterInfo().IsPAuthReg(reg);
+}
+
+bool NativeRegisterContextLinux_arm64::IsMTE(unsigned reg) const {
+  return GetRegisterInfo().IsMTEReg(reg);
+}
+
 uint32_t NativeRegisterContextLinux_arm64::NumSupportedHardwareBreakpoints() {
   Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_BREAKPOINTS));
 
   LLDB_LOGF(log, "NativeRegisterContextLinux_arm64::%s()", __FUNCTION__);
 
   Status error;
 
   // Read hardware breakpoint and watchpoint information.
Status NativeRegisterContextLinux_arm64::WriteFPR() {
   return WriteRegisterSet(&ioVec, GetFPRSize(), NT_FPREGSET);
 }
 
 void NativeRegisterContextLinux_arm64::InvalidateAllRegisters() {
   m_gpr_is_valid = false;
   m_fpu_is_valid = false;
   m_sve_buffer_is_valid = false;
   m_sve_header_is_valid = false;
+  m_pac_mask_is_valid = false;
+  m_mte_ctrl_is_valid = false;
 
   // Update SVE registers in case there is change in configuration.
   ConfigureRegisterContext();
 }
 
 Status NativeRegisterContextLinux_arm64::ReadSVEHeader() {
   Status error;
 
   if (m_sve_header_is_valid)
     return error;
 
   struct iovec ioVec;
   ioVec.iov_base = GetSVEHeader();
   ioVec.iov_len = GetSVEHeaderSize();
 
   error = ReadRegisterSet(&ioVec, GetSVEHeaderSize(), NT_ARM_SVE);
 
+  if (error.Success())
     m_sve_header_is_valid = true;
 
   return error;
 }
 
+Status NativeRegisterContextLinux_arm64::ReadPAuthMask() {
+  Status error;
+
+  if (m_pac_mask_is_valid)
+    return error;
+
+  struct iovec ioVec;
+  ioVec.iov_base = GetPACMask();
+  ioVec.iov_len = GetPACMaskSize();
+
+  error = ReadRegisterSet(&ioVec, GetPACMaskSize(), NT_ARM_PAC_MASK);
+
+  if (error.Success())
+    m_pac_mask_is_valid = true;
+
+  return error;
+}
+
 Status NativeRegisterContextLinux_arm64::WriteSVEHeader() {
   Status error;
 
   error = ReadSVEHeader();
   if (error.Fail())
     return error;
 
   struct iovec ioVec;
   ioVec.iov_base = GetSVEHeader();
   ioVec.iov_len = GetSVEHeaderSize();
 
   m_sve_buffer_is_valid = false;
   m_sve_header_is_valid = false;
   m_fpu_is_valid = false;
 
   return WriteRegisterSet(&ioVec, GetSVEHeaderSize(), NT_ARM_SVE);
 }
 
 Status NativeRegisterContextLinux_arm64::ReadAllSVE() {
   Status error;
 
   if (m_sve_buffer_is_valid)
Status NativeRegisterContextLinux_arm64::WriteAllSVE() {
 
   m_sve_buffer_is_valid = false;
   m_sve_header_is_valid = false;
   m_fpu_is_valid = false;
 
   return WriteRegisterSet(&ioVec, GetSVEBufferSize(), NT_ARM_SVE);
 }
 
+Status NativeRegisterContextLinux_arm64::ReadMTEControl() {
+  Status error;
+
+  if (m_mte_ctrl_is_valid)
+    return error;
+
+  struct iovec ioVec;
+  ioVec.iov_base = GetMTEControl();
+  ioVec.iov_len = GetMTEControlSize();
+
+  error = ReadRegisterSet(&ioVec, GetMTEControlSize(), NT_ARM_TAGGED_ADDR_CTRL);
+
+  if (error.Success())
+    m_mte_ctrl_is_valid = true;
+
+  return error;
+}
+
+Status NativeRegisterContextLinux_arm64::WriteMTEControl() {
+  Status error;
+
+  error = ReadMTEControl();
+  if (error.Fail())
+    return error;
+
+  struct iovec ioVec;
+  ioVec.iov_base = GetMTEControl();
+  ioVec.iov_len = GetMTEControlSize();
+
+  m_mte_ctrl_is_valid = false;
+
+  return WriteRegisterSet(&ioVec, GetMTEControlSize(), NT_ARM_TAGGED_ADDR_CTRL);
+}
+
 void NativeRegisterContextLinux_arm64::ConfigureRegisterContext() {
   // ConfigureRegisterContext gets called from InvalidateAllRegisters
   // on every stop and configures SVE vector length.
   // If m_sve_state is set to SVEState::Disabled on first stop, code below will
   // be deemed non operational for the lifetime of current process.
   if (!m_sve_header_is_valid && m_sve_state != SVEState::Disabled) {
     Status error = ReadSVEHeader();
     if (error.Success()) {

lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h

class RegisterInfoPOSIX_arm64
     : public lldb_private::RegisterInfoAndSetInterface {
 public:
   enum { GPRegSet = 0, FPRegSet };
 
   // AArch64 register set enable value
   enum {
     eRegsetEnableDefault = 0,
     eRegsetEnableSVE = 1,
+    eRegsetEnablePAuth = 2,
+    eRegsetEnableMTE = 4
   };
 
   // AArch64 Register set FP/SIMD feature configuration
   enum {
     eVectorQuadwordAArch64,
     eVectorQuadwordAArch64SVE,
     eVectorQuadwordAArch64SVEMax = 256
   };
public:
   GetRegisterSet(size_t reg_set) const override;
 
   size_t GetRegisterSetCount() const override;
 
   size_t GetRegisterSetFromRegisterIndex(uint32_t reg_index) const override;
 
   void ConfigureRegisterInfos(uint32_t opt_regsets);
 
+  void AddRegSetPAuth();
+
+  void AddRegSetMTE();
+
   uint32_t ConfigureVectorLength(uint32_t sve_vq);
 
   bool VectorSizeIsValid(uint32_t vq) {
     if (vq >= eVectorQuadwordAArch64 && vq <= eVectorQuadwordAArch64SVEMax)
       return true;
     return false;
   }
 
   bool IsSVEEnabled() const { return m_vector_reg_vq > eVectorQuadwordAArch64; }
 
   bool IsSVEReg(unsigned reg) const;
   bool IsSVEZReg(unsigned reg) const;
   bool IsSVEPReg(unsigned reg) const;
   bool IsSVERegVG(unsigned reg) const;
+  bool IsPAuthReg(unsigned reg) const;
+  bool IsMTEReg(unsigned reg) const;
 
   uint32_t GetRegNumSVEZ0() const;
   uint32_t GetRegNumSVEFFR() const;
   uint32_t GetRegNumFPCR() const;
   uint32_t GetRegNumFPSR() const;
   uint32_t GetRegNumSVEVG() const;
+  uint32_t GetPAuthOffset() const;
+  uint32_t GetMTEOffset() const;
 
 private:
   typedef std::map<uint32_t, std::vector<lldb_private::RegisterInfo>>
       per_vq_register_infos;
 
   per_vq_register_infos m_per_vq_reg_infos;
 
   uint32_t m_vector_reg_vq = eVectorQuadwordAArch64;
 
   const lldb_private::RegisterInfo *m_register_info_p;
   uint32_t m_register_info_count;
 
   const lldb_private::RegisterSet *m_register_set_p;
   uint32_t m_register_set_count;
 
   // Contains pair of (start, end) register numbers of a register set with start
   // and end included.
   std::map<uint32_t, std::pair<uint32_t, uint32_t>> m_per_regset_regnum_range;
 
+  bool m_mte_regset_enabled = false;
+  bool m_pauth_regset_enabled = false;
   bool m_reg_infos_is_dynamic = false;
 
   std::vector<lldb_private::RegisterInfo> m_dynamic_reg_infos;
   std::vector<lldb_private::RegisterSet> m_dynamic_reg_sets;
+
+  std::vector<uint32_t> pauth_regnum_collection;
+  std::vector<uint32_t> m_mte_regnum_collection;
 };
 
 #endif

lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp

GetRegisterInfoPtr(const lldb_private::ArchSpec &target_arch) {
   }
 }
 
 // Number of register sets provided by this context.
 enum {
   k_num_gpr_registers = gpr_w28 - gpr_x0 + 1,
   k_num_fpr_registers = fpu_fpcr - fpu_v0 + 1,
   k_num_sve_registers = sve_ffr - sve_vg + 1,
+  k_num_mte_register = 1,
+  k_num_pauth_register = 2,
   k_num_register_sets = 3
 };
 
 // ARM64 general purpose registers.
 static const uint32_t g_gpr_regnums_arm64[] = {
     gpr_x0,  gpr_x1,   gpr_x2,  gpr_x3,
     gpr_x4,  gpr_x5,   gpr_x6,  gpr_x7,
     gpr_x8,  gpr_x9,   gpr_x10, gpr_x11,

 static const lldb_private::RegisterSet g_reg_sets_arm64[k_num_register_sets] = {
     {"General Purpose Registers", "gpr", k_num_gpr_registers,
      g_gpr_regnums_arm64},
     {"Floating Point Registers", "fpu", k_num_fpr_registers,
      g_fpu_regnums_arm64},
     {"Scalable Vector Extension Registers", "sve", k_num_sve_registers,
      g_sve_regnums_arm64}};
 
+static const lldb_private::RegisterSet g_reg_set_pauth_arm64 = {
+    "Pointer Authentication Registers", "pauth", k_num_pauth_register, NULL};
+
+static const lldb_private::RegisterSet g_reg_set_mte_arm64 = {
+    "MTE Control Register", "mte", k_num_mte_register, NULL};
+
 static uint32_t
 GetRegisterInfoCount(const lldb_private::ArchSpec &target_arch) {
   switch (target_arch.GetMachine()) {
   case llvm::Triple::aarch64:
   case llvm::Triple::aarch64_32:
     return static_cast<uint32_t>(sizeof(g_register_infos_arm64_le) /
                                  sizeof(g_register_infos_arm64_le[0]));
   default:

 
 void RegisterInfoPOSIX_arm64::ConfigureRegisterInfos(uint32_t opt_regsets) {
   // Configures register sets supported by current target. If we have a dynamic
   // register set like MTE, Pointer Authentication regset then we need to
   // create a dynamic register infos and regset array. Push back all optional
   // register infos and regset and calculate register offsets accordingly.
   if (opt_regsets > eRegsetEnableSVE) {
     m_reg_infos_is_dynamic = true;
+    if (opt_regsets & eRegsetEnablePAuth)
+      m_pauth_regset_enabled = true;
+
+    if (opt_regsets & eRegsetEnableMTE)
+      m_mte_regset_enabled = true;
   }
 
   if (m_reg_infos_is_dynamic) {
     const lldb_private::RegisterInfo *reginfo_start, *reginfo_end;
     const lldb_private::RegisterSet *regset_start = g_reg_sets_arm64;
     if (opt_regsets & eRegsetEnableSVE) {
       reginfo_start = g_register_infos_arm64_sve_le;
       reginfo_end = g_register_infos_arm64_sve_le + sve_ffr + 1;
       m_per_regset_regnum_range[m_register_set_count] =
           std::make_pair(sve_vg, sve_ffr);
       m_register_set_count++;
     } else {
       reginfo_start = g_register_infos_arm64_le;
       reginfo_end = g_register_infos_arm64_le + fpu_fpcr + 1;
     }
 
     std::copy(reginfo_start, reginfo_end,
               std::back_inserter(m_dynamic_reg_infos));
     std::copy(regset_start, regset_start + m_register_set_count,
               std::back_inserter(m_dynamic_reg_sets));
 
+    if (m_pauth_regset_enabled)
+      AddRegSetPAuth();
+
+    if (m_mte_regset_enabled)
+      AddRegSetMTE();
+
     m_register_info_count = m_dynamic_reg_infos.size();
     m_register_info_p = m_dynamic_reg_infos.data();
     m_register_set_p = m_dynamic_reg_sets.data();
     m_register_set_count = m_dynamic_reg_sets.size();
   } else {
     if (opt_regsets & eRegsetEnableSVE) {
       m_register_info_p = g_register_infos_arm64_sve_le;
       m_register_info_count =
           static_cast<uint32_t>(sizeof(g_register_infos_arm64_sve_le) /
                                 sizeof(g_register_infos_arm64_sve_le[0]));
       m_per_regset_regnum_range[m_register_set_count] =
           std::make_pair(sve_vg, sve_ffr);
       m_register_set_count++;
     }
   }
 }
 
+void RegisterInfoPOSIX_arm64::AddRegSetPAuth() {
+  uint32_t pa_regnum = m_dynamic_reg_infos.size();
+  for (uint32_t i = 0; i < k_num_pauth_register; i++) {
+    pauth_regnum_collection.push_back(pa_regnum + i);
+    m_dynamic_reg_infos.push_back(g_register_infos_pauth[i]);
+    m_dynamic_reg_infos[pa_regnum + i].byte_offset =
+        m_dynamic_reg_infos[pa_regnum + i - 1].byte_offset +
+        m_dynamic_reg_infos[pa_regnum + i - 1].byte_size;
+    m_dynamic_reg_infos[pa_regnum + i].kinds[lldb::eRegisterKindLLDB] =
+        pa_regnum + i;
+  }
+
+  m_dynamic_reg_sets.push_back(g_reg_set_pauth_arm64);
+  m_dynamic_reg_sets.back().registers = pauth_regnum_collection.data();
+}
+
+void RegisterInfoPOSIX_arm64::AddRegSetMTE() {
+  uint32_t mte_regnum = m_dynamic_reg_infos.size();
+  m_mte_regnum_collection.push_back(mte_regnum);
+  m_dynamic_reg_infos.push_back(g_register_infos_mte[0]);
+  m_dynamic_reg_infos[mte_regnum].byte_offset =
+      m_dynamic_reg_infos[mte_regnum - 1].byte_offset +
+      m_dynamic_reg_infos[mte_regnum - 1].byte_size;
+  m_dynamic_reg_infos[mte_regnum].kinds[lldb::eRegisterKindLLDB] = mte_regnum;
+
+  m_dynamic_reg_sets.push_back(g_reg_set_mte_arm64);
+  m_dynamic_reg_sets.back().registers = m_mte_regnum_collection.data();
+}
+
 uint32_t RegisterInfoPOSIX_arm64::ConfigureVectorLength(uint32_t sve_vq) {
   // sve_vq contains SVE Quad vector length in context of AArch64 SVE.
   // SVE register infos if enabled cannot be disabled by selecting sve_vq = 0.
   // Also if an invalid or previously set vector length is passed to this
   // function then it will exit immediately with previously set vector length.
   if (!VectorSizeIsValid(sve_vq) || m_vector_reg_vq == sve_vq)
     return m_vector_reg_vq;
 

 bool RegisterInfoPOSIX_arm64::IsSVEPReg(unsigned reg) const {
   return (sve_p0 <= reg && reg <= sve_p15);
 }
 
 bool RegisterInfoPOSIX_arm64::IsSVERegVG(unsigned reg) const {
   return sve_vg == reg;
 }
 
+bool RegisterInfoPOSIX_arm64::IsPAuthReg(unsigned reg) const {
+  return std::find(pauth_regnum_collection.begin(),
+                   pauth_regnum_collection.end(),
+                   reg) != pauth_regnum_collection.end();
+}
+
+bool RegisterInfoPOSIX_arm64::IsMTEReg(unsigned reg) const {
+  return std::find(m_mte_regnum_collection.begin(),
+                   m_mte_regnum_collection.end(),
+                   reg) != m_mte_regnum_collection.end();
+}
+
 uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEZ0() const { return sve_z0; }
 
 uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEFFR() const { return sve_ffr; }
 
 uint32_t RegisterInfoPOSIX_arm64::GetRegNumFPCR() const { return fpu_fpcr; }
 
 uint32_t RegisterInfoPOSIX_arm64::GetRegNumFPSR() const { return fpu_fpsr; }
 
 uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEVG() const { return sve_vg; }
+
+uint32_t RegisterInfoPOSIX_arm64::GetPAuthOffset() const {
+  return m_register_info_p[pauth_regnum_collection[0]].byte_offset;
+}
+
+uint32_t RegisterInfoPOSIX_arm64::GetMTEOffset() const {
+  return m_register_info_p[m_mte_regnum_collection[0]].byte_offset;
+}

lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h

 
 // Generates register kinds array for registers with only lldb kind
 #define LLDB_KIND(lldb_kind)                                                   \
   {                                                                            \
     LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,             \
         LLDB_INVALID_REGNUM, lldb_kind                                         \
   }
 
+// Generates register kinds array for registers with only lldb kind
+#define KIND_ALL_INVALID                                                       \
+  {                                                                            \
+    LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,             \
+        LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM                               \
+  }
+
 // Generates register kinds array for vector registers
 #define GPR64_KIND(reg, generic_kind) MISC_KIND(reg, gpr, generic_kind)
 #define VREG_KIND(reg) MISC_KIND(reg, fpu, LLDB_INVALID_REGNUM)
 #define MISC_GPR_KIND(lldb_kind) MISC_KIND(cpsr, gpr, LLDB_REGNUM_GENERIC_FLAGS)
 #define MISC_FPU_KIND(lldb_kind) LLDB_KIND(lldb_kind)
 #define MISC_EXC_KIND(lldb_kind) LLDB_KIND(lldb_kind)
 
 // Defines a 64-bit general purpose register

 // Defines miscellaneous status and control registers like cpsr, fpsr etc
 #define DEFINE_MISC_REGS(reg, size, TYPE, lldb_kind)                           \
   {                                                                            \
     #reg, nullptr, size, TYPE##_OFFSET_NAME(reg), lldb::eEncodingUint,         \
         lldb::eFormatHex, MISC_##TYPE##_KIND(lldb_kind), nullptr, nullptr,     \
         nullptr, 0                                                             \
   }
 
+// Defines pointer authentication mask registers
+#define DEFINE_EXTENSION_REG(reg)                                              \
+  {                                                                            \
+    #reg, nullptr, 8, 0, lldb::eEncodingUint, lldb::eFormatHex,                \
+        KIND_ALL_INVALID, nullptr, nullptr, nullptr, 0                         \
+  }
+
 static lldb_private::RegisterInfo g_register_infos_arm64_le[] = {
     // DEFINE_GPR64(name, GENERIC KIND)
     DEFINE_GPR64(x0, LLDB_REGNUM_GENERIC_ARG1),
     DEFINE_GPR64(x1, LLDB_REGNUM_GENERIC_ARG2),
     DEFINE_GPR64(x2, LLDB_REGNUM_GENERIC_ARG3),
     DEFINE_GPR64(x3, LLDB_REGNUM_GENERIC_ARG4),
     DEFINE_GPR64(x4, LLDB_REGNUM_GENERIC_ARG5),
     DEFINE_GPR64(x5, LLDB_REGNUM_GENERIC_ARG6),
static lldb_private::RegisterInfo g_register_infos_arm64_le[] = {
     {DEFINE_DBG(wcr, 8)},
     {DEFINE_DBG(wcr, 9)},
     {DEFINE_DBG(wcr, 10)},
     {DEFINE_DBG(wcr, 11)},
     {DEFINE_DBG(wcr, 12)},
     {DEFINE_DBG(wcr, 13)},
     {DEFINE_DBG(wcr, 14)},
     {DEFINE_DBG(wcr, 15)}
-    // clang-format on
 };
+// clang-format on
+static lldb_private::RegisterInfo g_register_infos_pauth[] = {
+    DEFINE_EXTENSION_REG(data_mask), DEFINE_EXTENSION_REG(code_mask)};
+
+static lldb_private::RegisterInfo g_register_infos_mte[] = {
+    DEFINE_EXTENSION_REG(mte_ctrl)};
 
 #endif // DECLARE_REGISTER_INFOS_ARM64_STRUCT