[Thumb2] support `movs pc, lr` alias for `subs pc, lr, #0`/`eret`

[nickdesaulniers]

Summary

This is used by the Linux kernel built with CONFIG_THUMB2_KERNEL.

Because different operands are not permitted to movs, the diagnostics now provide multiple suggestions along the lines of using a non-pc destination operand or lr source operand.

Forked from D95586.

Signed-off-by: Nick Desaulniers <[e-mail]>

[nickdesaulniers]

(I should probably add the new notes, so reviewers can see how the diagnostics are changed. Will do so tomorrow.)

[nickdesaulniers]

• add CHECKs for note: diagnostics to tests.

[DavidSpickett]

LGTM with the one comment added.

llvm/lib/Target/ARM/ARMInstrThumb2.td

4147

Here please cite the armarmv7:

B9.3.19 SUBS PC, LR (Thumb)
In the Thumb instruction set, MOVS{<c>}{<q>} PC, LR is a pseudo-instruction for SUBS{<c>}{<q>} PC, LR, #0.

[nickdesaulniers]

• cite armarm

llvm/lib/Target/ARM/ARMInstrThumb2.td

def t2SUBS_PC_LR : T2I <(outs), (ins imm0_255:$imm), NoItinerary,
                         "subs", "\tpc, lr, $imm",
                         [(ARMintretflag imm0_255:$imm)]>,
                    Requires<[IsThumb2,IsNotMClass]> {
   let Inst{31-8} = 0b111100111101111010001111;
 
   bits<8> imm;
   let Inst{7-0} = imm;
 }
 
+// B9.3.19 SUBS PC, LR (Thumb)
+// In the Thumb instruction set, MOVS{<c>}{<q>} PC, LR is a pseudo-instruction
+// for SUBS{<c>}{<q>} PC, LR, #0.
+def : t2InstAlias<"movs${p}\tpc, lr", (t2SUBS_PC_LR 0, pred:$p)>;
+def : t2InstAlias<"movs${p}.w\tpc, lr", (t2SUBS_PC_LR 0, pred:$p)>;
+
+// ERET - Return from exception in Hypervisor mode.
+// B9.3.3, B9.3.20: ERET is an alias for "SUBS PC, LR, #0" in an implementation that
+// includes virtualization extensions.
+def t2ERET : InstAlias<"eret${p}", (t2SUBS_PC_LR 0, pred:$p), 1>,
+             Requires<[IsThumb2, HasVirtualization]>;
+
 // Hypervisor Call is a system instruction.
 let isCall = 1 in {
 def t2HVC : T2XI <(outs), (ins imm0_65535:$imm16), IIC_Br, "hvc.w\t$imm16", []>,
       Requires<[IsThumb2, HasVirtualization]>, Sched<[WriteBr]> {
     bits<16> imm16;
     let Inst{31-20} = 0b111101111110;
     let Inst{19-16} = imm16{15-12};
     let Inst{15-12} = 0b1000;
     let Inst{11-0} = imm16{11-0};
 }
 }
 
 // Alias for HVC without the ".w" optional width specifier
 def : t2InstAlias<"hvc\t$imm16", (t2HVC imm0_65535:$imm16)>;
 
-// ERET - Return from exception in Hypervisor mode.
-// B9.3.3, B9.3.20: ERET is an alias for "SUBS PC, LR, #0" in an implementation that
-// includes virtualization extensions.
-def t2ERET : InstAlias<"eret${p}", (t2SUBS_PC_LR 0, pred:$p), 1>,
-             Requires<[IsThumb2, HasVirtualization]>;
-
 //===----------------------------------------------------------------------===//
 // Non-Instruction Patterns
 //
 
 // 32-bit immediate using movw + movt.
 // This is a single pseudo instruction to make it re-materializable.
 // FIXME: Remove this when we can do generalized remat.
 let isReMaterializable = 1, isMoveImm = 1 in

llvm/test/MC/ARM/lsl-zero-errors.s

 // CHECK-NONARM: note: operand must be an immediate in the range [256,65535]
 
 // CHECK-NONARM: error: invalid instruction, any one of the following would fix this:
 // CHECK-NONARM-NEXT: mov pc, pc, lsl #0
 // CHECK-NONARM: note: operand must be a register in range [r0, r15]
 // CHECK-THUMBV7: note: operand must be a register in range [r0, r12] or r14
 // CHECK-THUMBV8: note: operand must be a register in range [r0, r14]
 
-// CHECK-THUMBV7: error: operand must be a register in range [r0, r12] or r14
-// CHECK-THUMBV8: error: operand must be a register in range [r0, r14]
+// CHECK-NONARM: error: invalid instruction, any one of the following would fix this:
 // CHECK-NONARM-NEXT: movs pc, r0, lsl #0
+// CHECK-THUMBV7: note: operand must be a register in range [r0, r12] or r14
+// CHECK-THUMBV8: note: operand must be a register in range [r0, r14]
+// CHECK-NONARM: note: invalid operand for instruction
 
 // CHECK-NONARM: error: invalid instruction, any one of the following would fix this:
 // CHECK-NONARM-NEXT: movs r0, pc, lsl #0
 // CHECK-NONARM: note: operand must be a register in range [r0, r14]
 // CHECK-NONARM: note: invalid operand for instruction
 // CHECK-NONARM: note: invalid operand for instruction
 
-// CHECK-THUMBV7: error: operand must be a register in range [r0, r12] or r14
-// CHECK-THUMBV8: error: operand must be a register in range [r0, r14]
+// CHECK-NONARM: error: invalid instruction, any one of the following would fix this:
 // CHECK-NONARM-NEXT: movs pc, pc, lsl #0
+// CHECK-THUMBV7: note: operand must be a register in range [r0, r12] or r14
+// CHECK-THUMBV8: note: operand must be a register in range [r0, r14]
+// CHECK-NONARM: note: invalid operand for instruction
 
 // CHECK-ARM: mov pc, r0                @ encoding: [0x00,0xf0,0xa0,0xe1]
 // CHECK-ARM: mov r0, pc                @ encoding: [0x0f,0x00,0xa0,0xe1]
 // CHECK-ARM: mov pc, pc                @ encoding: [0x0f,0xf0,0xa0,0xe1]
 // CHECK-ARM: movs pc, r0               @ encoding: [0x00,0xf0,0xb0,0xe1]
 // CHECK-ARM: movs r0, pc               @ encoding: [0x0f,0x00,0xb0,0xe1]
 // CHECK-ARM: movs pc, pc               @ encoding: [0x0f,0xf0,0xb0,0xe1]
 

llvm/test/MC/ARM/thumb-mov.s

 // RUN: not llvm-mc -triple=thumbv7 -show-encoding < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V7 %s
 // RUN: not llvm-mc -triple=thumbv8 -show-encoding < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V8 %s
 
         // Tests to check handling of sp and pc in thumb mov instructions. We
         // have to be careful about the order of things, as stdout/stderr
         // buffering means the errors appear before the non-error output, so
         // we have to put all the error checks at the top.
 
         // First check instructions that are never valid. These are thumb2
         // instructions that uses pc
 
         // t2MOVr selected because no thumb1 movs that can access high regs
         movs pc, r0
         movs r0, pc
         movs pc, pc
-// CHECK: error: operand must be a register in range [r0, r14]
+// CHECK: error: invalid instruction, any one of the following would fix this:
 // CHECK-NEXT: movs pc, r0
 // CHECK: note: operand must be a register in range [r0, r14]
-// CHECK-NEXT: movs r0, pc
 // CHECK: note: invalid operand for instruction
+// CHECK: error: invalid instruction, any one of the following would fix this:
 // CHECK-NEXT: movs r0, pc
-// CHECK: error: invalid instruction
+// CHECK: note: operand must be a register in range [r0, r14]
+// CHECK: note: invalid operand for instruction
+// CHECK: error: invalid operand for instruction
 // CHECK-NEXT: movs pc, pc
 
         // mov.w selects t2MOVr
         mov.w pc, r0
         mov.w r0, pc
         mov.w pc, pc
 // CHECK: error: operand must be a register in range [r0, r14]
 // CHECK-NEXT: mov.w pc, r0
 // CHECK: note: operand must be a register in range [r0, r14]
 // CHECK-NEXT: mov.w r0, pc
 // CHECK: note: invalid operand for instruction
 // CHECK-NEXT: mov.w r0, pc
 // CHECK: error: invalid instruction
 // CHECK-NEXT: mov.w pc, pc
 
         // movs.w selects t2MOVr
         movs.w pc, r0
         movs.w r0, pc
         movs.w pc, pc
-// CHECK: error: operand must be a register in range [r0, r14]
+// CHECK: error: invalid instruction, any one of the following would fix this:
 // CHECK-NEXT: movs.w pc, r0
 // CHECK: note: operand must be a register in range [r0, r14]
-// CHECK-NEXT: movs.w r0, pc
 // CHECK: note: invalid operand for instruction
+// CHECK: error: invalid instruction, any one of the following would fix this:
 // CHECK-NEXT: movs.w r0, pc
-// CHECK: error: invalid instruction
+// CHECK: note: operand must be a register in range [r0, r14]
+// CHECK: note: invalid operand for instruction
+// CHECK: error: invalid operand for instruction
 // CHECK-NEXT: movs.w pc, pc
 
 
         // Now check instructions that are invalid before ARMv8 due to SP usage
 
         movs sp, r0
         movs r0, sp
         movs sp, sp

 // CHECK: mov r0, pc                  @ encoding: [0x78,0x46]
 // CHECK: mov pc, pc                  @ encoding: [0xff,0x46]
 
         // sp allowed in non-flags-setting t2MOVr
         mov.w sp, r0
         mov.w r0, sp
 // CHECK: mov.w sp, r0                @ encoding: [0x4f,0xea,0x00,0x0d]
 // CHECK: mov.w r0, sp                @ encoding: [0x4f,0xea,0x0d,0x00]
+
+        // `movs pc, lr` is an alias for `subs pc, lr, #0`/`eret`.
+        movs   pc, lr
+        movs.w pc, lr
+// CHECK-V7: subs pc, lr, #0             @ encoding: [0xde,0xf3,0x00,0x8f]
+// CHECK-V7: subs pc, lr, #0             @ encoding: [0xde,0xf3,0x00,0x8f]
+// CHECK-V8: eret                        @ encoding: [0xde,0xf3,0x00,0x8f]
+// CHECK-V8: eret                        @ encoding: [0xde,0xf3,0x00,0x8f]