[WebAssembly] Fix multiclass template parameter types. NFC.

[RKSimon]

Summary

Fixes TableGen parser errors reported by D95874 due to incompatible types being used on multiclass templates.

[aheejin]

llvm/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td

688

llvm/lib/Target/WebAssembly/WebAssemblyInstrMemory.td

70

Why should this be SDPatternOperator? What we put here seems load, which is a subclass of PatFrag. The same question for other LoadPat*** changes.

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

311

This seems to be the same case as StoreLanePatNoOffset, in which your suggestion was Intrinsic..?

916

We seem to supply SDNode in arguments to this class..? (The same question for other SIMDBinary suggestions)

[RKSimon]

Cheers @aheejin - you can review these changes by applying the patch from D95874 against trunk to see the error messages.

llvm/lib/Target/WebAssembly/WebAssemblyInstrMemory.td

70

IIRC this was necessary for some of the uses in WebAssemblyInstrSIMD.td

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

311

A few multiclasses I was to get to work by keeping the more specialized Intrinsic type, in others it was necessary to generalise all the way to SDPatternOperator.

[aheejin]

I see, thanks for taking care of this!

llvm/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td

multiclass BinRMWPatOffsetOnly<ValueType ty, PatFrag kind, string inst> {
   def : Pat<(ty (kind imm:$off, ty:$val)),
             (!cast<NI>(inst#_A32) 0, imm:$off, (CONST_I32 0), ty:$val)>,
         Requires<[HasAddr32, HasAtomics]>;
   def : Pat<(ty (kind imm:$off, ty:$val)),
             (!cast<NI>(inst#_A64) 0, imm:$off, (CONST_I64 0), ty:$val)>,
         Requires<[HasAddr64, HasAtomics]>;
 }
 
-multiclass BinRMWPatGlobalAddrOffOnly<ValueType ty, PatFrag kind, NI inst> {
+multiclass BinRMWPatGlobalAddrOffOnly<ValueType ty, PatFrag kind, string inst> {
   def : Pat<(ty (kind (WebAssemblywrapper tglobaladdr:$off), ty:$val)),
             (!cast<NI>(inst#_A32) 0, tglobaladdr:$off, (CONST_I32 0), ty:$val)>,
         Requires<[HasAddr32, HasAtomics, IsNotPIC]>;
   def : Pat<(ty (kind (WebAssemblywrapper tglobaladdr:$off), ty:$val)),
             (!cast<NI>(inst#_A64) 0, tglobaladdr:$off, (CONST_I64 0), ty:$val)>,
         Requires<[HasAddr64, HasAtomics, IsNotPIC]>;
 }
 
class sext_bin_rmw_8_64<PatFrag kind> :
   PatFrag<(ops node:$addr, node:$val),
           (anyext (i32 (kind node:$addr, (i32 (trunc (i64 node:$val))))))>;
 class sext_bin_rmw_16_64<PatFrag kind> : sext_bin_rmw_8_64<kind>;
 // 32->64 sext RMW gets selected as i32.atomic.rmw.***, i64.extend_i32_s
 
 // Patterns for various addressing modes for truncating-extending binary RMWs.
 multiclass BinRMWTruncExtPattern<
   PatFrag rmw_8, PatFrag rmw_16, PatFrag rmw_32, PatFrag rmw_64,
-  NI inst8_32, NI inst16_32, NI inst8_64, NI inst16_64, NI inst32_64> {
+  string inst8_32, string inst16_32, string inst8_64, string inst16_64, string inst32_64> {
   // Truncating-extending binary RMWs with no constant offset
   defm : BinRMWPatNoOffset<i32, zext_bin_rmw_8_32<rmw_8>, inst8_32>;
   defm : BinRMWPatNoOffset<i32, zext_bin_rmw_16_32<rmw_16>, inst16_32>;
   defm : BinRMWPatNoOffset<i64, zext_bin_rmw_8_64<rmw_8>, inst8_64>;
   defm : BinRMWPatNoOffset<i64, zext_bin_rmw_16_64<rmw_16>, inst16_64>;
   defm : BinRMWPatNoOffset<i64, zext_bin_rmw_32_64<rmw_32>, inst32_64>;
 
   defm : BinRMWPatNoOffset<i32, sext_bin_rmw_8_32<rmw_8>, inst8_32>;

llvm/lib/Target/WebAssembly/WebAssemblyInstrMemory.td

 // FIXME: When we can break syntax compatibility, reorder the fields in the
 // asmstrings to match the binary encoding.
 defm LOAD_I32 : WebAssemblyLoad<I32, "i32.load", 0x28, []>;
 defm LOAD_I64 : WebAssemblyLoad<I64, "i64.load", 0x29, []>;
 defm LOAD_F32 : WebAssemblyLoad<F32, "f32.load", 0x2a, []>;
 defm LOAD_F64 : WebAssemblyLoad<F64, "f64.load", 0x2b, []>;
 
 // Select loads with no constant offset.
-multiclass LoadPatNoOffset<ValueType ty, PatFrag kind, string inst> {
+multiclass LoadPatNoOffset<ValueType ty, SDPatternOperator kind, string inst> {
   def : Pat<(ty (kind I32:$addr)), (!cast<NI>(inst # "_A32") 0, 0, I32:$addr)>,
         Requires<[HasAddr32]>;
   def : Pat<(ty (kind (i64 I64:$addr))), (!cast<NI>(inst # "_A64") 0, 0, I64:$addr)>,
         Requires<[HasAddr64]>;
 }
 
 defm : LoadPatNoOffset<i32, load, "LOAD_I32">;
 defm : LoadPatNoOffset<i64, load, "LOAD_I64">;
 defm : LoadPatNoOffset<f32, load, "LOAD_F32">;
 defm : LoadPatNoOffset<f64, load, "LOAD_F64">;
 
 // Select loads with a constant offset.
 
 // Pattern with address + immediate offset
-multiclass LoadPatImmOff<ValueType ty, PatFrag kind, PatFrag operand,
+multiclass LoadPatImmOff<ValueType ty, SDPatternOperator kind, PatFrag operand,
                          string inst> {
   def : Pat<(ty (kind (operand I32:$addr, imm:$off))),
             (!cast<NI>(inst # "_A32") 0, imm:$off, I32:$addr)>,
         Requires<[HasAddr32]>;
   def : Pat<(ty (kind (operand I64:$addr, imm:$off))),
             (!cast<NI>(inst # "_A64") 0, imm:$off, I64:$addr)>,
         Requires<[HasAddr64]>;
 }
 
 defm : LoadPatImmOff<i32, load, regPlusImm, "LOAD_I32">;
 defm : LoadPatImmOff<i64, load, regPlusImm, "LOAD_I64">;
 defm : LoadPatImmOff<f32, load, regPlusImm, "LOAD_F32">;
 defm : LoadPatImmOff<f64, load, regPlusImm, "LOAD_F64">;
 defm : LoadPatImmOff<i32, load, or_is_add, "LOAD_I32">;
 defm : LoadPatImmOff<i64, load, or_is_add, "LOAD_I64">;
 defm : LoadPatImmOff<f32, load, or_is_add, "LOAD_F32">;
 defm : LoadPatImmOff<f64, load, or_is_add, "LOAD_F64">;
 
 // Select loads with just a constant offset.
-multiclass LoadPatOffsetOnly<ValueType ty, PatFrag kind, string inst> {
+multiclass LoadPatOffsetOnly<ValueType ty, SDPatternOperator kind, string inst> {
   def : Pat<(ty (kind imm:$off)),
             (!cast<NI>(inst # "_A32") 0, imm:$off, (CONST_I32 0))>,
         Requires<[HasAddr32]>;
   def : Pat<(ty (kind imm:$off)),
             (!cast<NI>(inst # "_A64") 0, imm:$off, (CONST_I64 0))>,
         Requires<[HasAddr64]>;
 }
 
 defm : LoadPatOffsetOnly<i32, load, "LOAD_I32">;
 defm : LoadPatOffsetOnly<i64, load, "LOAD_I64">;
 defm : LoadPatOffsetOnly<f32, load, "LOAD_F32">;
 defm : LoadPatOffsetOnly<f64, load, "LOAD_F64">;
 
-multiclass LoadPatGlobalAddrOffOnly<ValueType ty, PatFrag kind, string inst> {
+multiclass LoadPatGlobalAddrOffOnly<ValueType ty, SDPatternOperator kind, string inst> {
   def : Pat<(ty (kind (WebAssemblywrapper tglobaladdr:$off))),
             (!cast<NI>(inst # "_A32") 0, tglobaladdr:$off, (CONST_I32 0))>,
         Requires<[IsNotPIC, HasAddr32]>;
   def : Pat<(ty (kind (WebAssemblywrapper tglobaladdr:$off))),
             (!cast<NI>(inst # "_A64") 0, tglobaladdr:$off, (CONST_I64 0))>,
         Requires<[IsNotPIC, HasAddr64]>;
 }
 

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

 // TODO: Also support v4f32 and v2f64 once the instructions are merged
 // to the proposal
 defm "" : SIMDLoadLane<I8x16, 88>;
 defm "" : SIMDLoadLane<I16x8, 89>;
 defm "" : SIMDLoadLane<I32x4, 90>;
 defm "" : SIMDLoadLane<I64x2, 91>;
 
 // Select loads with no constant offset.
-multiclass LoadLanePatNoOffset<Vec vec, PatFrag kind> {
+multiclass LoadLanePatNoOffset<Vec vec, SDPatternOperator kind> {
   defvar load_lane_a32 = !cast<NI>("LOAD_LANE_"#vec#"_A32");
   defvar load_lane_a64 = !cast<NI>("LOAD_LANE_"#vec#"_A64");
   def : Pat<(vec.vt (kind (i32 I32:$addr),
               (vec.vt V128:$vec), (i32 vec.lane_idx:$idx))),
             (load_lane_a32 0, 0, imm:$idx, $addr, $vec)>,
         Requires<[HasAddr32]>;
   def : Pat<(vec.vt (kind (i64 I64:$addr),
               (vec.vt V128:$vec), (i32 vec.lane_idx:$idx))),

 // TODO: Also support v4f32 and v2f64 once the instructions are merged
 // to the proposal
 defm "" : SIMDStoreLane<I8x16, 92>;
 defm "" : SIMDStoreLane<I16x8, 93>;
 defm "" : SIMDStoreLane<I32x4, 94>;
 defm "" : SIMDStoreLane<I64x2, 95>;
 
 // Select stores with no constant offset.
-multiclass StoreLanePatNoOffset<Vec vec, PatFrag kind> {
+multiclass StoreLanePatNoOffset<Vec vec, Intrinsic kind> {
   def : Pat<(kind (i32 I32:$addr), (vec.vt V128:$vec), (i32 vec.lane_idx:$idx)),
             (!cast<NI>("STORE_LANE_"#vec#"_A32") 0, 0, imm:$idx, $addr, $vec)>,
         Requires<[HasAddr32]>;
   def : Pat<(kind (i64 I64:$addr), (vec.vt V128:$vec), (i32 vec.lane_idx:$idx)),
             (!cast<NI>("STORE_LANE_"#vec#"_A64") 0, 0, imm:$idx, $addr, $vec)>,
         Requires<[HasAddr64]>;
 }
 
SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins),
            (int_wasm_eq (v2i64 V128:$lhs), (v2i64 V128:$rhs)))],
          "i64x2.eq\t$dst, $lhs, $rhs", "i64x2.eq", 192>;
 
 
 //===----------------------------------------------------------------------===//
 // Bitwise operations
 //===----------------------------------------------------------------------===//
 
-multiclass SIMDBinary<Vec vec, SDNode node, string name, bits<32> simdop> {
+multiclass SIMDBinary<Vec vec, SDPatternOperator node, string name, bits<32> simdop> {
   defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
                       (outs), (ins),
                       [(set (vec.vt V128:$dst),
                         (node (vec.vt V128:$lhs), (vec.vt V128:$rhs)))],
                       vec.prefix#"."#name#"\t$dst, $lhs, $rhs",
                       vec.prefix#"."#name, simdop>;
 }
 
-multiclass SIMDBitwise<SDNode node, string name, bits<32> simdop, bit commutable = false> {
+multiclass SIMDBitwise<SDPatternOperator node, string name, bits<32> simdop,
+                       bit commutable = false> {
   let isCommutable = commutable in
   defm "" : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
                    (outs), (ins), [],
                    "v128."#name#"\t$dst, $lhs, $rhs", "v128."#name, simdop>;
   foreach vec = IntVecs in
   def : Pat<(node (vec.vt V128:$lhs), (vec.vt V128:$rhs)),
             (!cast<NI>(NAME) $lhs, $rhs)>;
 }
 
-multiclass SIMDUnary<Vec vec, SDNode node, string name, bits<32> simdop> {
+multiclass SIMDUnary<Vec vec, SDPatternOperator node, string name, bits<32> simdop> {
   defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$v), (outs), (ins),
                       [(set (vec.vt V128:$dst),
                         (vec.vt (node (vec.vt V128:$v))))],
                       vec.prefix#"."#name#"\t$dst, $v",
                       vec.prefix#"."#name, simdop>;
 }
 
 // Bitwise logic: v128.not

 defm : SIMDSignSelect<I16x8, 126>;
 defm : SIMDSignSelect<I32x4, 127>;
 defm : SIMDSignSelect<I64x2, 148>;
 
 //===----------------------------------------------------------------------===//
 // Integer unary arithmetic
 //===----------------------------------------------------------------------===//
 
-multiclass SIMDUnaryInt<SDNode node, string name, bits<32> baseInst> {
+multiclass SIMDUnaryInt<SDPatternOperator node, string name, bits<32> baseInst> {
   defm "" : SIMDUnary<I8x16, node, name, baseInst>;
   defm "" : SIMDUnary<I16x8, node, name, !add(baseInst, 32)>;
   defm "" : SIMDUnary<I32x4, node, name, !add(baseInst, 64)>;
   defm "" : SIMDUnary<I64x2, node, name, !add(baseInst, 96)>;
 }
 
-multiclass SIMDReduceVec<Vec vec, SDNode op, string name, bits<32> simdop> {
+multiclass SIMDReduceVec<Vec vec, SDPatternOperator op, string name, bits<32> simdop> {
   defm _#vec : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins),
                       [(set I32:$dst, (i32 (op (vec.vt V128:$vec))))],
                       vec.prefix#"."#name#"\t$dst, $vec", vec.prefix#"."#name,
                       simdop>;
 }
 
-multiclass SIMDReduce<SDNode op, string name, bits<32> baseInst> {
+multiclass SIMDReduce<SDPatternOperator op, string name, bits<32> baseInst> {
   defm "" : SIMDReduceVec<I8x16, op, name, baseInst>;
   defm "" : SIMDReduceVec<I16x8, op, name, !add(baseInst, 32)>;
   defm "" : SIMDReduceVec<I32x4, op, name, !add(baseInst, 64)>;
   defm "" : SIMDReduceVec<I64x2, op, name, !add(baseInst, 96)>;
 }
 
 // Integer vector negation
 def ivneg : PatFrag<(ops node:$in), (sub immAllZerosV, $in)>;

 // Right shift by scalar: shr_s / shr_u
 defm SHR_S : SIMDShiftInt<wasm_shr_s, "shr_s", 108>;
 defm SHR_U : SIMDShiftInt<wasm_shr_u, "shr_u", 109>;
 
 //===----------------------------------------------------------------------===//
 // Integer binary arithmetic
 //===----------------------------------------------------------------------===//
 
-multiclass SIMDBinaryIntNoI8x16<SDNode node, string name, bits<32> baseInst> {
+multiclass SIMDBinaryIntNoI8x16<SDPatternOperator node, string name, bits<32> baseInst> {
   defm "" : SIMDBinary<I16x8, node, name, !add(baseInst, 32)>;
   defm "" : SIMDBinary<I32x4, node, name, !add(baseInst, 64)>;
   defm "" : SIMDBinary<I64x2, node, name, !add(baseInst, 96)>;
 }
 
-multiclass SIMDBinaryIntSmall<SDNode node, string name, bits<32> baseInst> {
+multiclass SIMDBinaryIntSmall<SDPatternOperator node, string name, bits<32> baseInst> {
   defm "" : SIMDBinary<I8x16, node, name, baseInst>;
   defm "" : SIMDBinary<I16x8, node, name, !add(baseInst, 32)>;
 }
 
-multiclass SIMDBinaryIntNoI64x2<SDNode node, string name, bits<32> baseInst> {
+multiclass SIMDBinaryIntNoI64x2<SDPatternOperator node, string name, bits<32> baseInst> {
   defm "" : SIMDBinaryIntSmall<node, name, baseInst>;
   defm "" : SIMDBinary<I32x4, node, name, !add(baseInst, 64)>;
 }
 
-multiclass SIMDBinaryInt<SDNode node, string name, bits<32> baseInst> {
+multiclass SIMDBinaryInt<SDPatternOperator node, string name, bits<32> baseInst> {
   defm "" : SIMDBinaryIntNoI64x2<node, name, baseInst>;
   defm "" : SIMDBinary<I64x2, node, name, !add(baseInst, 96)>;
 }
 
 // Integer addition: add / add_saturate_s / add_saturate_u
 let isCommutable = 1 in {
 defm ADD : SIMDBinaryInt<add, "add", 110>;
 defm ADD_SAT_S : SIMDBinaryIntSmall<saddsat, "add_saturate_s", 111>;

 // Widening dot product: i32x4.dot_i16x8_s
 let isCommutable = 1 in
 defm DOT : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins),
                   [(set V128:$dst, (int_wasm_dot V128:$lhs, V128:$rhs))],
                   "i32x4.dot_i16x8_s\t$dst, $lhs, $rhs", "i32x4.dot_i16x8_s",
                   186>;
 
 // Extending multiplication: extmul_{low,high}_P, extmul_high
-multiclass SIMDExtBinary<Vec vec, SDNode node, string name, bits<32> simdop> {
+multiclass SIMDExtBinary<Vec vec, Intrinsic node, string name, bits<32> simdop> {
   defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
                       (outs), (ins),
                       [(set (vec.vt V128:$dst), (node
                          (vec.split.vt V128:$lhs),(vec.split.vt V128:$rhs)))],
                       vec.prefix#"."#name#"\t$dst, $lhs, $rhs",
                       vec.prefix#"."#name, simdop>;
 }
 

 defm FLOOR : SIMDUnary<F64x2, int_wasm_floor, "floor", 221>;
 defm TRUNC: SIMDUnary<F64x2, int_wasm_trunc, "trunc", 222>;
 defm NEAREST: SIMDUnary<F64x2, int_wasm_nearest, "nearest", 223>;
 
 //===----------------------------------------------------------------------===//
 // Floating-point binary arithmetic
 //===----------------------------------------------------------------------===//
 
-multiclass SIMDBinaryFP<SDNode node, string name, bits<32> baseInst> {
+multiclass SIMDBinaryFP<SDPatternOperator node, string name, bits<32> baseInst> {
   defm "" : SIMDBinary<F32x4, node, name, baseInst>;
   defm "" : SIMDBinary<F64x2, node, name, !add(baseInst, 12)>;
 }
 
 // Addition: add
 let isCommutable = 1 in
 defm ADD : SIMDBinaryFP<fadd, "add", 228>;
 

 
 // Pseudo-maximum: pmax
 defm PMAX : SIMDBinaryFP<int_wasm_pmax, "pmax", 235>;
 
 //===----------------------------------------------------------------------===//
 // Conversions
 //===----------------------------------------------------------------------===//
 
-multiclass SIMDConvert<Vec vec, Vec arg, SDNode op, string name,
+multiclass SIMDConvert<Vec vec, Vec arg, SDPatternOperator op, string name,
                        bits<32> simdop> {
   defm op#_#vec :
     SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
            [(set (vec.vt V128:$dst), (vec.vt (op (arg.vt V128:$vec))))],
            vec.prefix#"."#name#"\t$dst, $vec", vec.prefix#"."#name, simdop>;
 }
 
 // Floating point to integer with saturation: trunc_sat
SIMD_I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
          "prefetch.nt\t$off$p2align", 0xc6>;
 defm PREFETCH_NT_A64 :
   SIMD_I<(outs), (ins P2Align:$p2align, offset64_op:$off, I64:$addr),
          (outs), (ins P2Align:$p2align, offset64_op:$off), [],
          "prefetch.nt\t${off}(${addr})$p2align",
          "prefetch.nt\t$off$p2align", 0xc6>;
 } // mayLoad, UseNamedOperandTable
 
-multiclass PrefetchPatNoOffset<PatFrag kind, string inst> {
+multiclass PrefetchPatNoOffset<Intrinsic kind, string inst> {
   def : Pat<(kind I32:$addr), (!cast<NI>(inst # "_A32") 0, 0, $addr)>,
         Requires<[HasAddr32]>;
   def : Pat<(kind I64:$addr), (!cast<NI>(inst # "_A64") 0, 0, $addr)>,
         Requires<[HasAddr64]>;
 }
 
 foreach inst = [["PREFETCH_T", "int_wasm_prefetch_t"],
                 ["PREFETCH_NT", "int_wasm_prefetch_nt"]] in {
 defvar node = !cast<Intrinsic>(inst[1]);
 defm : PrefetchPatNoOffset<node, inst[0]>;
 }