[AMDGPU] Clarify calling conv about inactive lanes

[sebastian-ne]

Summary

So far, it was not specified what happens with the VGPRs of inactive
lanes when functions are called. This patch explicitely mentions that
the VGPR values of inactive lanes need to be preserved for all
registers.

This describes the current behavior, as only active lanes of registers
are saved to scratch. Also, as the multi-lane nature of VGPRs is not
properly modeled, we cannot determine the live VGPRs from inactive lanes
at calls. So we cannot save them, even if we intended to do so.

[t-tye]

llvm/docs/AMDGPUUsage.rst

8242–8264

Suggest re-wording to:

` 
    * VGPR40-47
    * VGPR56-63
    * VGPR72-79
    * VGPR88-95
    * VGPR104-111
    * VGPR120-127
    * VGPR136-143
    * VGPR152-159
    * VGPR168-175
    * VGPR184-191
    * VGPR200-207
    * VGPR216-223
    * VGPR232-239
    * VGPR248-255

       .. note::

          Except the argument registers, the VGPR clobbered and the
          preserved registers are intermixed at regular intervals in
          order to keep a similar ratio independent of the number of
          allocated VGPRs.

    * Lanes of all VGPRs that are inactive at the call site.
`

8243–8263

... keep a similar ratio independent of the number of allocated VGPRs.

[sebastian-ne]

Reword as suggested

[t-tye]

In D95610#2530257, @sebastian-ne wrote:

Reword as suggested

I only saw part of the rewording incorporated. Was that intentional? The suggested text would replace the entire VGPR parts.

[sebastian-ne]

I missed the change in the VGPRs, it’s also included now.

[t-tye]

llvm/docs/AMDGPUUsage.rst

8261

the number of

[sebastian-ne]

Fixed

[t-tye]

LGTM Thanks.

[madhur13490]

llvm/docs/AMDGPUUsage.rst

8263

I am confused by the wording "Lanes of all VGPRs". The word "lane" is used in the context of workitems and not VGPRs. Do you mean to say - "All VGPRs of inactive lanes at the call site"?

[t-tye]

llvm/docs/AMDGPUUsage.rst

8263

One view of VGPRs is that that comprises a separate dword for each lane. This sentence is stating that the VGPR lanes corresponding to inactive lanes must be preserved.

llvm/docs/AMDGPUUsage.rst

 1.  VGPR0-31 and SGPR4-29 are used to pass function result arguments as
     described below. Any registers used are considered clobbered registers.
 2.  The following registers are preserved and have the same value as on entry:
 
     * FLAT_SCRATCH
     * EXEC
     * GFX6-GFX8: M0
     * All SGPR registers except the clobbered registers of SGPR4-31.
     * VGPR40-47
-      VGPR56-63
-      VGPR72-79
-      VGPR88-95
-      VGPR104-111
-      VGPR120-127
-      VGPR136-143
-      VGPR152-159
-      VGPR168-175
-      VGPR184-191
-      VGPR200-207
-      VGPR216-223
-      VGPR232-239
-      VGPR248-255
-
-        *Except the argument registers, the VGPR clobbered and the preserved
-        registers are intermixed at regular intervals in order to
-        get a better occupancy.*
+    * VGPR56-63
+    * VGPR72-79
+    * VGPR88-95
+    * VGPR104-111
+    * VGPR120-127
+    * VGPR136-143
+    * VGPR152-159
+    * VGPR168-175
+    * VGPR184-191
+    * VGPR200-207
+    * VGPR216-223
+    * VGPR232-239
+    * VGPR248-255
+
+        .. note::
+
+          Except the argument registers, the VGPRs clobbered and the preserved
+          registers are intermixed at regular intervals in order to keep a
+          similar ratio independent of the number of allocated VGPRs.
+
+    * Lanes of all VGPRs that are inactive at the call site.
 
       For the AMDGPU backend, an inter-procedural register allocation (IPRA)
       optimization may mark some of clobbered SGPR and VGPR registers as
       preserved if it can be determined that the called function does not change
       their value.
 
 2.  The PC is set to the RA provided on entry.
 3.  MODE register: *TBD*.
 4.  All other registers are clobbered.