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Differential D95471

[ARM] VINS f16 pattern
ClosedPublic

Authored by dmgreen on Jan 26 2021, 12:30 PM.

Details

Reviewers
SjoerdMeijer
NickGuy
simon_tatham
ostannard
efriedma
Commits
rG6d9d2049c853: [ARM] VINS f16 pattern
Summary

This adds an extra pattern for inserting an f16 into a odd vector lane via an VINS. If the dual-insert-lane pattern does not happen to apply, this can help with some simple cases.

Diff Detail

Event Timeline

dmgreen created this revision.Jan 26 2021, 12:30 PM
Herald added subscribers: danielkiss, hiraditya, kristof.beyls. · View Herald TranscriptJan 26 2021, 12:30 PM
dmgreen requested review of this revision.Jan 26 2021, 12:30 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 26 2021, 12:30 PM
dmgreen added a parent revision: D95456: [ARM] i16 insert-of-extract to VINS pattern.Jan 26 2021, 12:31 PM
dmgreen added a child revision: D95551: [ARM] One-off identity shuffle.Feb 2 2021, 1:00 AM
ostannard accepted this revision.Feb 11 2021, 2:34 AM

LGTM

This revision is now accepted and ready to land.Feb 11 2021, 2:34 AM
Closed by commit rG6d9d2049c853: [ARM] VINS f16 pattern (authored by dmgreen). · Explain WhyMar 21 2021, 5:00 AM
This revision was automatically updated to reflect the committed changes.
dmgreen added a commit: rG6d9d2049c853: [ARM] VINS f16 pattern.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
7 lines
test/
CodeGen/
Thumb2/
16 lines
24 lines
3 lines
252 lines

Diff 332150

llvm/lib/Target/ARM/ARMInstrMVE.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,894 Lines • ▼ Show 20 Lines def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
(MVE_VMOV_to_lane_32 (v4i32 (IMPLICIT_DEF)), rGPR:$src, (i32 0))>; (MVE_VMOV_to_lane_32 (v4i32 (IMPLICIT_DEF)), rGPR:$src, (i32 0))>;
// Floating point patterns, still enabled under HasMVEInt // Floating point patterns, still enabled under HasMVEInt
def : Pat<(extractelt (v4f32 MQPR:$src), imm:$lane), def : Pat<(extractelt (v4f32 MQPR:$src), imm:$lane),
(COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG MQPR:$src, (SSubReg_f32_reg imm:$lane))), SPR)>; (COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG MQPR:$src, (SSubReg_f32_reg imm:$lane))), SPR)>;
def : Pat<(insertelt (v4f32 MQPR:$src1), (f32 SPR:$src2), imm:$lane), def : Pat<(insertelt (v4f32 MQPR:$src1), (f32 SPR:$src2), imm:$lane),
(INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS MQPR:$src1, MQPR)), SPR:$src2, (SSubReg_f32_reg imm:$lane))>; (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS MQPR:$src1, MQPR)), SPR:$src2, (SSubReg_f32_reg imm:$lane))>;
def : Pat<(insertelt (v8f16 MQPR:$src1), (f16 HPR:$src2), imm:$lane), def : Pat<(insertelt (v8f16 MQPR:$src1), (f16 HPR:$src2), imm_even:$lane),
(MVE_VMOV_to_lane_16 MQPR:$src1, (COPY_TO_REGCLASS (f16 HPR:$src2), rGPR), imm:$lane)>; (MVE_VMOV_to_lane_16 MQPR:$src1, (COPY_TO_REGCLASS (f16 HPR:$src2), rGPR), imm:$lane)>;
def : Pat<(insertelt (v8f16 MQPR:$src1), (f16 HPR:$src2), imm_odd:$lane),
(COPY_TO_REGCLASS (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS MQPR:$src1, MQPR)),
(VINSH (EXTRACT_SUBREG MQPR:$src1, (SSubReg_f16_reg imm_odd:$lane)),
(COPY_TO_REGCLASS HPR:$src2, SPR)),
(SSubReg_f16_reg imm_odd:$lane)), MQPR)>;
def : Pat<(extractelt (v8f16 MQPR:$src), imm_even:$lane), def : Pat<(extractelt (v8f16 MQPR:$src), imm_even:$lane),
(EXTRACT_SUBREG MQPR:$src, (SSubReg_f16_reg imm_even:$lane))>; (EXTRACT_SUBREG MQPR:$src, (SSubReg_f16_reg imm_even:$lane))>;
def : Pat<(extractelt (v8f16 MQPR:$src), imm_odd:$lane), def : Pat<(extractelt (v8f16 MQPR:$src), imm_odd:$lane),
(COPY_TO_REGCLASS (COPY_TO_REGCLASS
(VMOVH (EXTRACT_SUBREG MQPR:$src, (SSubReg_f16_reg imm_odd:$lane))), (VMOVH (EXTRACT_SUBREG MQPR:$src, (SSubReg_f16_reg imm_odd:$lane))),
HPR)>; HPR)>;
def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))), def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
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llvm/test/CodeGen/Thumb2/mve-float16regloops.ll

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; CHECK-NEXT: wls lr, r9, .LBB17_6 ; CHECK-NEXT: wls lr, r9, .LBB17_6
; CHECK-NEXT: @ %bb.4: @ %while.body.preheader ; CHECK-NEXT: @ %bb.4: @ %while.body.preheader
; CHECK-NEXT: @ in Loop: Header=BB17_3 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB17_3 Depth=1
; CHECK-NEXT: mov r5, r2 ; CHECK-NEXT: mov r5, r2
; CHECK-NEXT: .LBB17_5: @ %while.body ; CHECK-NEXT: .LBB17_5: @ %while.body
; CHECK-NEXT: @ Parent Loop BB17_3 Depth=1 ; CHECK-NEXT: @ Parent Loop BB17_3 Depth=1
; CHECK-NEXT: @ => This Inner Loop Header: Depth=2 ; CHECK-NEXT: @ => This Inner Loop Header: Depth=2
; CHECK-NEXT: ldrh r7, [r1], #4 ; CHECK-NEXT: ldrh r7, [r1], #4
; CHECK-NEXT: vmov r4, s4 ; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: vfma.f16 q2, q3, r7 ; CHECK-NEXT: vfma.f16 q2, q3, r7
; CHECK-NEXT: ldrh r3, [r1, #-2] ; CHECK-NEXT: ldrh r4, [r1, #-2]
; CHECK-NEXT: vmov.u16 r7, q2[0] ; CHECK-NEXT: vmov.u16 r7, q2[0]
; CHECK-NEXT: vfma.f16 q2, q4, r7 ; CHECK-NEXT: vfma.f16 q2, q4, r7
; CHECK-NEXT: vmov.16 q2[3], r4 ; CHECK-NEXT: vins.f16 s9, s4
; CHECK-NEXT: vfma.f16 q2, q5, r3 ; CHECK-NEXT: vfma.f16 q2, q5, r4
; CHECK-NEXT: vmov.u16 r3, q2[1] ; CHECK-NEXT: vmov.u16 r4, q2[1]
; CHECK-NEXT: vfma.f16 q2, q6, r3 ; CHECK-NEXT: vfma.f16 q2, q6, r4
; CHECK-NEXT: strh r3, [r5, #2] ; CHECK-NEXT: strh r4, [r5, #2]
; CHECK-NEXT: vmov.f32 s8, s9 ; CHECK-NEXT: vmov.f32 s8, s9
; CHECK-NEXT: strh r7, [r5], #4 ; CHECK-NEXT: strh r7, [r5], #4
; CHECK-NEXT: vmov.16 q2[2], r4 ; CHECK-NEXT: vmov.16 q2[2], r3
; CHECK-NEXT: le lr, .LBB17_5 ; CHECK-NEXT: le lr, .LBB17_5
; CHECK-NEXT: .LBB17_6: @ %while.end ; CHECK-NEXT: .LBB17_6: @ %while.end
; CHECK-NEXT: @ in Loop: Header=BB17_3 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB17_3 Depth=1
; CHECK-NEXT: cmp.w r8, #0 ; CHECK-NEXT: cmp.w r8, #0
; CHECK-NEXT: beq .LBB17_1 ; CHECK-NEXT: beq .LBB17_1
; CHECK-NEXT: @ %bb.7: @ %if.then ; CHECK-NEXT: @ %bb.7: @ %if.then
; CHECK-NEXT: @ in Loop: Header=BB17_3 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB17_3 Depth=1
; CHECK-NEXT: ldrh r1, [r1] ; CHECK-NEXT: ldrh r1, [r1]
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llvm/test/CodeGen/Thumb2/mve-masked-load.ll

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; CHECK-LE-NEXT: strh.w r2, [sp, #28] ; CHECK-LE-NEXT: strh.w r2, [sp, #28]
; CHECK-LE-NEXT: vldr.16 s0, [sp, #28] ; CHECK-LE-NEXT: vldr.16 s0, [sp, #28]
; CHECK-LE-NEXT: lsls r2, r1, #30 ; CHECK-LE-NEXT: lsls r2, r1, #30
; CHECK-LE-NEXT: bpl .LBB45_2 ; CHECK-LE-NEXT: bpl .LBB45_2
; CHECK-LE-NEXT: .LBB45_10: @ %cond.load1 ; CHECK-LE-NEXT: .LBB45_10: @ %cond.load1
; CHECK-LE-NEXT: ldrh r2, [r0, #2] ; CHECK-LE-NEXT: ldrh r2, [r0, #2]
; CHECK-LE-NEXT: strh.w r2, [sp, #24] ; CHECK-LE-NEXT: strh.w r2, [sp, #24]
; CHECK-LE-NEXT: vldr.16 s4, [sp, #24] ; CHECK-LE-NEXT: vldr.16 s4, [sp, #24]
; CHECK-LE-NEXT: vmov r2, s4 ; CHECK-LE-NEXT: vins.f16 s0, s4
; CHECK-LE-NEXT: vmov.16 q0[1], r2
; CHECK-LE-NEXT: lsls r2, r1, #29 ; CHECK-LE-NEXT: lsls r2, r1, #29
; CHECK-LE-NEXT: bpl .LBB45_3 ; CHECK-LE-NEXT: bpl .LBB45_3
; CHECK-LE-NEXT: .LBB45_11: @ %cond.load4 ; CHECK-LE-NEXT: .LBB45_11: @ %cond.load4
; CHECK-LE-NEXT: ldrh r2, [r0, #4] ; CHECK-LE-NEXT: ldrh r2, [r0, #4]
; CHECK-LE-NEXT: strh.w r2, [sp, #20] ; CHECK-LE-NEXT: strh.w r2, [sp, #20]
; CHECK-LE-NEXT: vldr.16 s4, [sp, #20] ; CHECK-LE-NEXT: vldr.16 s4, [sp, #20]
; CHECK-LE-NEXT: vmov r2, s4 ; CHECK-LE-NEXT: vmov r2, s4
; CHECK-LE-NEXT: vmov.16 q0[2], r2 ; CHECK-LE-NEXT: vmov.16 q0[2], r2
; CHECK-LE-NEXT: lsls r2, r1, #28 ; CHECK-LE-NEXT: lsls r2, r1, #28
; CHECK-LE-NEXT: bpl .LBB45_4 ; CHECK-LE-NEXT: bpl .LBB45_4
; CHECK-LE-NEXT: .LBB45_12: @ %cond.load7 ; CHECK-LE-NEXT: .LBB45_12: @ %cond.load7
; CHECK-LE-NEXT: ldrh r2, [r0, #6] ; CHECK-LE-NEXT: ldrh r2, [r0, #6]
; CHECK-LE-NEXT: strh.w r2, [sp, #16] ; CHECK-LE-NEXT: strh.w r2, [sp, #16]
; CHECK-LE-NEXT: vldr.16 s4, [sp, #16] ; CHECK-LE-NEXT: vldr.16 s4, [sp, #16]
; CHECK-LE-NEXT: vmov r2, s4 ; CHECK-LE-NEXT: vins.f16 s1, s4
; CHECK-LE-NEXT: vmov.16 q0[3], r2
; CHECK-LE-NEXT: lsls r2, r1, #27 ; CHECK-LE-NEXT: lsls r2, r1, #27
; CHECK-LE-NEXT: bpl .LBB45_5 ; CHECK-LE-NEXT: bpl .LBB45_5
; CHECK-LE-NEXT: .LBB45_13: @ %cond.load10 ; CHECK-LE-NEXT: .LBB45_13: @ %cond.load10
; CHECK-LE-NEXT: ldrh r2, [r0, #8] ; CHECK-LE-NEXT: ldrh r2, [r0, #8]
; CHECK-LE-NEXT: strh.w r2, [sp, #12] ; CHECK-LE-NEXT: strh.w r2, [sp, #12]
; CHECK-LE-NEXT: vldr.16 s4, [sp, #12] ; CHECK-LE-NEXT: vldr.16 s4, [sp, #12]
; CHECK-LE-NEXT: vmov r2, s4 ; CHECK-LE-NEXT: vmov r2, s4
; CHECK-LE-NEXT: vmov.16 q0[4], r2 ; CHECK-LE-NEXT: vmov.16 q0[4], r2
; CHECK-LE-NEXT: lsls r2, r1, #26 ; CHECK-LE-NEXT: lsls r2, r1, #26
; CHECK-LE-NEXT: bpl .LBB45_6 ; CHECK-LE-NEXT: bpl .LBB45_6
; CHECK-LE-NEXT: .LBB45_14: @ %cond.load13 ; CHECK-LE-NEXT: .LBB45_14: @ %cond.load13
; CHECK-LE-NEXT: ldrh r2, [r0, #10] ; CHECK-LE-NEXT: ldrh r2, [r0, #10]
; CHECK-LE-NEXT: strh.w r2, [sp, #8] ; CHECK-LE-NEXT: strh.w r2, [sp, #8]
; CHECK-LE-NEXT: vldr.16 s4, [sp, #8] ; CHECK-LE-NEXT: vldr.16 s4, [sp, #8]
; CHECK-LE-NEXT: vmov r2, s4 ; CHECK-LE-NEXT: vins.f16 s2, s4
; CHECK-LE-NEXT: vmov.16 q0[5], r2
; CHECK-LE-NEXT: lsls r2, r1, #25 ; CHECK-LE-NEXT: lsls r2, r1, #25
; CHECK-LE-NEXT: bpl .LBB45_7 ; CHECK-LE-NEXT: bpl .LBB45_7
; CHECK-LE-NEXT: .LBB45_15: @ %cond.load16 ; CHECK-LE-NEXT: .LBB45_15: @ %cond.load16
; CHECK-LE-NEXT: ldrh r2, [r0, #12] ; CHECK-LE-NEXT: ldrh r2, [r0, #12]
; CHECK-LE-NEXT: strh.w r2, [sp, #4] ; CHECK-LE-NEXT: strh.w r2, [sp, #4]
; CHECK-LE-NEXT: vldr.16 s4, [sp, #4] ; CHECK-LE-NEXT: vldr.16 s4, [sp, #4]
; CHECK-LE-NEXT: vmov r2, s4 ; CHECK-LE-NEXT: vmov r2, s4
; CHECK-LE-NEXT: vmov.16 q0[6], r2 ; CHECK-LE-NEXT: vmov.16 q0[6], r2
; CHECK-LE-NEXT: lsls r1, r1, #24 ; CHECK-LE-NEXT: lsls r1, r1, #24
; CHECK-LE-NEXT: bpl .LBB45_8 ; CHECK-LE-NEXT: bpl .LBB45_8
; CHECK-LE-NEXT: .LBB45_16: @ %cond.load19 ; CHECK-LE-NEXT: .LBB45_16: @ %cond.load19
; CHECK-LE-NEXT: ldrh r0, [r0, #14] ; CHECK-LE-NEXT: ldrh r0, [r0, #14]
; CHECK-LE-NEXT: strh.w r0, [sp] ; CHECK-LE-NEXT: strh.w r0, [sp]
; CHECK-LE-NEXT: vldr.16 s4, [sp] ; CHECK-LE-NEXT: vldr.16 s4, [sp]
; CHECK-LE-NEXT: vmov r0, s4 ; CHECK-LE-NEXT: vins.f16 s3, s4
; CHECK-LE-NEXT: vmov.16 q0[7], r0
; CHECK-LE-NEXT: add sp, #40 ; CHECK-LE-NEXT: add sp, #40
; CHECK-LE-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
; ;
; CHECK-BE-LABEL: masked_v8f16_align1_undef: ; CHECK-BE-LABEL: masked_v8f16_align1_undef:
; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: .pad #40 ; CHECK-BE-NEXT: .pad #40
; CHECK-BE-NEXT: sub sp, #40 ; CHECK-BE-NEXT: sub sp, #40
; CHECK-BE-NEXT: vrev64.16 q1, q0 ; CHECK-BE-NEXT: vrev64.16 q1, q0
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; CHECK-BE-NEXT: bmi .LBB45_16 ; CHECK-BE-NEXT: bmi .LBB45_16
; CHECK-BE-NEXT: .LBB45_7: @ %else17 ; CHECK-BE-NEXT: .LBB45_7: @ %else17
; CHECK-BE-NEXT: lsls r1, r1, #31 ; CHECK-BE-NEXT: lsls r1, r1, #31
; CHECK-BE-NEXT: beq .LBB45_9 ; CHECK-BE-NEXT: beq .LBB45_9
; CHECK-BE-NEXT: .LBB45_8: @ %cond.load19 ; CHECK-BE-NEXT: .LBB45_8: @ %cond.load19
; CHECK-BE-NEXT: ldrh r0, [r0, #14] ; CHECK-BE-NEXT: ldrh r0, [r0, #14]
; CHECK-BE-NEXT: strh.w r0, [sp] ; CHECK-BE-NEXT: strh.w r0, [sp]
; CHECK-BE-NEXT: vldr.16 s0, [sp] ; CHECK-BE-NEXT: vldr.16 s0, [sp]
; CHECK-BE-NEXT: vmov r0, s0 ; CHECK-BE-NEXT: vins.f16 s7, s0
; CHECK-BE-NEXT: vmov.16 q1[7], r0
; CHECK-BE-NEXT: .LBB45_9: @ %else20 ; CHECK-BE-NEXT: .LBB45_9: @ %else20
; CHECK-BE-NEXT: vrev64.16 q0, q1 ; CHECK-BE-NEXT: vrev64.16 q0, q1
; CHECK-BE-NEXT: add sp, #40 ; CHECK-BE-NEXT: add sp, #40
; CHECK-BE-NEXT: bx lr ; CHECK-BE-NEXT: bx lr
; CHECK-BE-NEXT: .LBB45_10: @ %cond.load ; CHECK-BE-NEXT: .LBB45_10: @ %cond.load
; CHECK-BE-NEXT: ldrh r2, [r0] ; CHECK-BE-NEXT: ldrh r2, [r0]
; CHECK-BE-NEXT: strh.w r2, [sp, #28] ; CHECK-BE-NEXT: strh.w r2, [sp, #28]
; CHECK-BE-NEXT: vldr.16 s4, [sp, #28] ; CHECK-BE-NEXT: vldr.16 s4, [sp, #28]
; CHECK-BE-NEXT: lsls r2, r1, #25 ; CHECK-BE-NEXT: lsls r2, r1, #25
; CHECK-BE-NEXT: bpl .LBB45_2 ; CHECK-BE-NEXT: bpl .LBB45_2
; CHECK-BE-NEXT: .LBB45_11: @ %cond.load1 ; CHECK-BE-NEXT: .LBB45_11: @ %cond.load1
; CHECK-BE-NEXT: ldrh r2, [r0, #2] ; CHECK-BE-NEXT: ldrh r2, [r0, #2]
; CHECK-BE-NEXT: strh.w r2, [sp, #24] ; CHECK-BE-NEXT: strh.w r2, [sp, #24]
; CHECK-BE-NEXT: vldr.16 s0, [sp, #24] ; CHECK-BE-NEXT: vldr.16 s0, [sp, #24]
; CHECK-BE-NEXT: vmov r2, s0 ; CHECK-BE-NEXT: vins.f16 s4, s0
; CHECK-BE-NEXT: vmov.16 q1[1], r2
; CHECK-BE-NEXT: lsls r2, r1, #26 ; CHECK-BE-NEXT: lsls r2, r1, #26
; CHECK-BE-NEXT: bpl .LBB45_3 ; CHECK-BE-NEXT: bpl .LBB45_3
; CHECK-BE-NEXT: .LBB45_12: @ %cond.load4 ; CHECK-BE-NEXT: .LBB45_12: @ %cond.load4
; CHECK-BE-NEXT: ldrh r2, [r0, #4] ; CHECK-BE-NEXT: ldrh r2, [r0, #4]
; CHECK-BE-NEXT: strh.w r2, [sp, #20] ; CHECK-BE-NEXT: strh.w r2, [sp, #20]
; CHECK-BE-NEXT: vldr.16 s0, [sp, #20] ; CHECK-BE-NEXT: vldr.16 s0, [sp, #20]
; CHECK-BE-NEXT: vmov r2, s0 ; CHECK-BE-NEXT: vmov r2, s0
; CHECK-BE-NEXT: vmov.16 q1[2], r2 ; CHECK-BE-NEXT: vmov.16 q1[2], r2
; CHECK-BE-NEXT: lsls r2, r1, #27 ; CHECK-BE-NEXT: lsls r2, r1, #27
; CHECK-BE-NEXT: bpl .LBB45_4 ; CHECK-BE-NEXT: bpl .LBB45_4
; CHECK-BE-NEXT: .LBB45_13: @ %cond.load7 ; CHECK-BE-NEXT: .LBB45_13: @ %cond.load7
; CHECK-BE-NEXT: ldrh r2, [r0, #6] ; CHECK-BE-NEXT: ldrh r2, [r0, #6]
; CHECK-BE-NEXT: strh.w r2, [sp, #16] ; CHECK-BE-NEXT: strh.w r2, [sp, #16]
; CHECK-BE-NEXT: vldr.16 s0, [sp, #16] ; CHECK-BE-NEXT: vldr.16 s0, [sp, #16]
; CHECK-BE-NEXT: vmov r2, s0 ; CHECK-BE-NEXT: vins.f16 s5, s0
; CHECK-BE-NEXT: vmov.16 q1[3], r2
; CHECK-BE-NEXT: lsls r2, r1, #28 ; CHECK-BE-NEXT: lsls r2, r1, #28
; CHECK-BE-NEXT: bpl .LBB45_5 ; CHECK-BE-NEXT: bpl .LBB45_5
; CHECK-BE-NEXT: .LBB45_14: @ %cond.load10 ; CHECK-BE-NEXT: .LBB45_14: @ %cond.load10
; CHECK-BE-NEXT: ldrh r2, [r0, #8] ; CHECK-BE-NEXT: ldrh r2, [r0, #8]
; CHECK-BE-NEXT: strh.w r2, [sp, #12] ; CHECK-BE-NEXT: strh.w r2, [sp, #12]
; CHECK-BE-NEXT: vldr.16 s0, [sp, #12] ; CHECK-BE-NEXT: vldr.16 s0, [sp, #12]
; CHECK-BE-NEXT: vmov r2, s0 ; CHECK-BE-NEXT: vmov r2, s0
; CHECK-BE-NEXT: vmov.16 q1[4], r2 ; CHECK-BE-NEXT: vmov.16 q1[4], r2
; CHECK-BE-NEXT: lsls r2, r1, #29 ; CHECK-BE-NEXT: lsls r2, r1, #29
; CHECK-BE-NEXT: bpl .LBB45_6 ; CHECK-BE-NEXT: bpl .LBB45_6
; CHECK-BE-NEXT: .LBB45_15: @ %cond.load13 ; CHECK-BE-NEXT: .LBB45_15: @ %cond.load13
; CHECK-BE-NEXT: ldrh r2, [r0, #10] ; CHECK-BE-NEXT: ldrh r2, [r0, #10]
; CHECK-BE-NEXT: strh.w r2, [sp, #8] ; CHECK-BE-NEXT: strh.w r2, [sp, #8]
; CHECK-BE-NEXT: vldr.16 s0, [sp, #8] ; CHECK-BE-NEXT: vldr.16 s0, [sp, #8]
; CHECK-BE-NEXT: vmov r2, s0 ; CHECK-BE-NEXT: vins.f16 s6, s0
; CHECK-BE-NEXT: vmov.16 q1[5], r2
; CHECK-BE-NEXT: lsls r2, r1, #30 ; CHECK-BE-NEXT: lsls r2, r1, #30
; CHECK-BE-NEXT: bpl .LBB45_7 ; CHECK-BE-NEXT: bpl .LBB45_7
; CHECK-BE-NEXT: .LBB45_16: @ %cond.load16 ; CHECK-BE-NEXT: .LBB45_16: @ %cond.load16
; CHECK-BE-NEXT: ldrh r2, [r0, #12] ; CHECK-BE-NEXT: ldrh r2, [r0, #12]
; CHECK-BE-NEXT: strh.w r2, [sp, #4] ; CHECK-BE-NEXT: strh.w r2, [sp, #4]
; CHECK-BE-NEXT: vldr.16 s0, [sp, #4] ; CHECK-BE-NEXT: vldr.16 s0, [sp, #4]
; CHECK-BE-NEXT: vmov r2, s0 ; CHECK-BE-NEXT: vmov r2, s0
; CHECK-BE-NEXT: vmov.16 q1[6], r2 ; CHECK-BE-NEXT: vmov.16 q1[6], r2
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llvm/test/CodeGen/Thumb2/mve-shuffle.ll

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entry: entry:
%out = shufflevector <8 x half> %src1, <8 x half> %src2, <8 x i32> <i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %out = shufflevector <8 x half> %src1, <8 x half> %src2, <8 x i32> <i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x half> %out ret <8 x half> %out
} }
define arm_aapcs_vfpcc <8 x half> @oneoff21_f16(<8 x half> %src1, <8 x half> %src2) { define arm_aapcs_vfpcc <8 x half> @oneoff21_f16(<8 x half> %src1, <8 x half> %src2) {
; CHECK-LABEL: oneoff21_f16: ; CHECK-LABEL: oneoff21_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vins.f16 s5, s0
; CHECK-NEXT: vmov.16 q1[3], r0
; CHECK-NEXT: vmov q0, q1 ; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <8 x half> %src1, <8 x half> %src2, <8 x i32> <i32 8, i32 9, i32 10, i32 0, i32 12, i32 13, i32 14, i32 15> %out = shufflevector <8 x half> %src1, <8 x half> %src2, <8 x i32> <i32 8, i32 9, i32 10, i32 0, i32 12, i32 13, i32 14, i32 15>
ret <8 x half> %out ret <8 x half> %out
} }
define arm_aapcs_vfpcc <8 x half> @oneoff22_f16(<8 x half> %src1, <8 x half> %src2) { define arm_aapcs_vfpcc <8 x half> @oneoff22_f16(<8 x half> %src1, <8 x half> %src2) {
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llvm/test/CodeGen/Thumb2/mve-vst3.ll

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ret void ret void
} }
define void @vst3_v8f16(<8 x half> *%src, <24 x half> *%dst) { define void @vst3_v8f16(<8 x half> *%src, <24 x half> *%dst) {
; CHECK-LABEL: vst3_v8f16: ; CHECK-LABEL: vst3_v8f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14}
; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: vldrw.u32 q3, [r0]
; CHECK-NEXT: vldrw.u32 q5, [r0, #16] ; CHECK-NEXT: vldrw.u32 q5, [r0, #16]
; CHECK-NEXT: vmov.f64 d0, d4 ; CHECK-NEXT: vmov.f64 d0, d6
; CHECK-NEXT: vmovx.f16 s6, s20 ; CHECK-NEXT: vmovx.f16 s6, s20
; CHECK-NEXT: vmovx.f16 s12, s8 ; CHECK-NEXT: vmovx.f16 s8, s12
; CHECK-NEXT: vmovx.f16 s24, s23 ; CHECK-NEXT: vmov.f32 s4, s13
; CHECK-NEXT: vmov.f32 s4, s9
; CHECK-NEXT: vins.f16 s0, s20 ; CHECK-NEXT: vins.f16 s0, s20
; CHECK-NEXT: vmov r2, s6 ; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: vins.f16 s4, s21 ; CHECK-NEXT: vins.f16 s4, s21
; CHECK-NEXT: vmov.16 q0[4], r2 ; CHECK-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: vmov.f32 s3, s4 ; CHECK-NEXT: vmov.f32 s3, s4
; CHECK-NEXT: vldrw.u32 q1, [r0, #32] ; CHECK-NEXT: vldrw.u32 q1, [r0, #32]
; CHECK-NEXT: vmov.f32 s1, s8 ; CHECK-NEXT: vmov.f32 s1, s12
; CHECK-NEXT: vmov.f32 s17, s4 ; CHECK-NEXT: vmov.f32 s17, s4
; CHECK-NEXT: vmovx.f16 s26, s6 ; CHECK-NEXT: vmovx.f16 s24, s7
; CHECK-NEXT: vmov.f32 s18, s4 ; CHECK-NEXT: vmov.f32 s18, s4
; CHECK-NEXT: vins.f16 s17, s12 ; CHECK-NEXT: vins.f16 s17, s8
; CHECK-NEXT: vmovx.f16 s12, s18 ; CHECK-NEXT: vmovx.f16 s8, s18
; CHECK-NEXT: vins.f16 s2, s12 ; CHECK-NEXT: vins.f16 s2, s8
; CHECK-NEXT: vmovx.f16 s12, s7 ; CHECK-NEXT: vmovx.f16 s11, s23
; CHECK-NEXT: vins.f16 s24, s12 ; CHECK-NEXT: vins.f16 s11, s24
; CHECK-NEXT: vmovx.f16 s12, s22 ; CHECK-NEXT: vmovx.f16 s24, s6
; CHECK-NEXT: vmov r0, s23 ; CHECK-NEXT: vmovx.f16 s8, s22
; CHECK-NEXT: vins.f16 s12, s26 ; CHECK-NEXT: vmov.f32 s18, s2
; CHECK-NEXT: vmov.16 q3[3], r0 ; CHECK-NEXT: vins.f16 s8, s24
; CHECK-NEXT: vrev32.16 q5, q5 ; CHECK-NEXT: vmov.f32 s25, s15
; CHECK-NEXT: vmov.f32 s15, s24 ; CHECK-NEXT: vins.f16 s9, s23
; CHECK-NEXT: vmov.f32 s25, s11 ; CHECK-NEXT: vmov.f32 s26, s15
; CHECK-NEXT: vmov.f32 s14, s7 ; CHECK-NEXT: vmov.f32 s10, s7
; CHECK-NEXT: vmovx.f16 s28, s13 ; CHECK-NEXT: vmovx.f16 s28, s9
; CHECK-NEXT: vmov.f32 s26, s11
; CHECK-NEXT: vins.f16 s25, s28 ; CHECK-NEXT: vins.f16 s25, s28
; CHECK-NEXT: vmovx.f16 s28, s26 ; CHECK-NEXT: vmovx.f16 s28, s26
; CHECK-NEXT: vins.f16 s14, s28 ; CHECK-NEXT: vins.f16 s10, s28
; CHECK-NEXT: vmovx.f16 s28, s9 ; CHECK-NEXT: vmovx.f16 s28, s13
; CHECK-NEXT: vmov.f32 s4, s5 ; CHECK-NEXT: vmov.f32 s4, s5
; CHECK-NEXT: vrev32.16 q5, q5
; CHECK-NEXT: vins.f16 s4, s28 ; CHECK-NEXT: vins.f16 s4, s28
; CHECK-NEXT: vmovx.f16 s28, s10 ; CHECK-NEXT: vmovx.f16 s28, s14
; CHECK-NEXT: vins.f16 s6, s28 ; CHECK-NEXT: vins.f16 s6, s28
; CHECK-NEXT: vmov.f32 s18, s2 ; CHECK-NEXT: vmov.f32 s26, s10
; CHECK-NEXT: vmov.f32 s7, s6 ; CHECK-NEXT: vmov.f32 s7, s6
; CHECK-NEXT: vmov.f32 s6, s10 ; CHECK-NEXT: vmov.f32 s6, s14
; CHECK-NEXT: vmovx.f16 s8, s5 ; CHECK-NEXT: vmovx.f16 s12, s5
; CHECK-NEXT: vins.f16 s21, s8 ; CHECK-NEXT: vins.f16 s21, s12
; CHECK-NEXT: vmovx.f16 s8, s22 ; CHECK-NEXT: vmovx.f16 s12, s22
; CHECK-NEXT: vins.f16 s6, s8 ; CHECK-NEXT: vins.f16 s6, s12
; CHECK-NEXT: vmov.f32 s26, s14
; CHECK-NEXT: vmov.f32 s22, s6
; CHECK-NEXT: vmov.f32 s1, s17 ; CHECK-NEXT: vmov.f32 s1, s17
; CHECK-NEXT: vmov.f32 s13, s25 ; CHECK-NEXT: vmov.f32 s22, s6
; CHECK-NEXT: vmov.f32 s9, s25
; CHECK-NEXT: vmov.f32 s5, s21 ; CHECK-NEXT: vmov.f32 s5, s21
; CHECK-NEXT: vmov.f32 s2, s18 ; CHECK-NEXT: vmov.f32 s2, s18
; CHECK-NEXT: vmov.f32 s10, s26
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vmov.f32 s14, s26 ; CHECK-NEXT: vstrw.32 q2, [r1, #32]
; CHECK-NEXT: vmov.f32 s6, s22 ; CHECK-NEXT: vmov.f32 s6, s22
; CHECK-NEXT: vstrw.32 q3, [r1, #32]
; CHECK-NEXT: vstrw.32 q1, [r1, #16] ; CHECK-NEXT: vstrw.32 q1, [r1, #16]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <8 x half>, <8 x half>* %src, i32 0 %s1 = getelementptr <8 x half>, <8 x half>* %src, i32 0
%l1 = load <8 x half>, <8 x half>* %s1, align 4 %l1 = load <8 x half>, <8 x half>* %s1, align 4
%s2 = getelementptr <8 x half>, <8 x half>* %src, i32 1 %s2 = getelementptr <8 x half>, <8 x half>* %src, i32 1
%l2 = load <8 x half>, <8 x half>* %s2, align 4 %l2 = load <8 x half>, <8 x half>* %s2, align 4
%s3 = getelementptr <8 x half>, <8 x half>* %src, i32 2 %s3 = getelementptr <8 x half>, <8 x half>* %src, i32 2
%l3 = load <8 x half>, <8 x half>* %s3, align 4 %l3 = load <8 x half>, <8 x half>* %s3, align 4
%t1 = shufflevector <8 x half> %l1, <8 x half> %l2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %t1 = shufflevector <8 x half> %l1, <8 x half> %l2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%t2 = shufflevector <8 x half> %l3, <8 x half> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %t2 = shufflevector <8 x half> %l3, <8 x half> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%s = shufflevector <16 x half> %t1, <16 x half> %t2, <24 x i32> <i32 0, i32 8, i32 16, i32 1, i32 9, i32 17, i32 2, i32 10, i32 18, i32 3, i32 11, i32 19, i32 4, i32 12, i32 20, i32 5, i32 13, i32 21, i32 6, i32 14, i32 22, i32 7, i32 15, i32 23> %s = shufflevector <16 x half> %t1, <16 x half> %t2, <24 x i32> <i32 0, i32 8, i32 16, i32 1, i32 9, i32 17, i32 2, i32 10, i32 18, i32 3, i32 11, i32 19, i32 4, i32 12, i32 20, i32 5, i32 13, i32 21, i32 6, i32 14, i32 22, i32 7, i32 15, i32 23>
store <24 x half> %s, <24 x half> *%dst store <24 x half> %s, <24 x half> *%dst
ret void ret void
} }
define void @vst3_v16f16(<16 x half> *%src, <48 x half> *%dst) { define void @vst3_v16f16(<16 x half> *%src, <48 x half> *%dst) {
; CHECK-LABEL: vst3_v16f16: ; CHECK-LABEL: vst3_v16f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #128 ; CHECK-NEXT: .pad #128
; CHECK-NEXT: sub sp, #128 ; CHECK-NEXT: sub sp, #128
; CHECK-NEXT: vldrw.u32 q3, [r0, #32] ; CHECK-NEXT: vldrw.u32 q1, [r0, #32]
; CHECK-NEXT: vldrw.u32 q7, [r0, #64] ; CHECK-NEXT: vldrw.u32 q7, [r0, #64]
; CHECK-NEXT: vldrw.u32 q4, [r0] ; CHECK-NEXT: vldrw.u32 q5, [r0, #80]
; CHECK-NEXT: vldrw.u32 q5, [r0, #48]
; CHECK-NEXT: vmovx.f16 s0, s31 ; CHECK-NEXT: vmovx.f16 s0, s31
; CHECK-NEXT: vmovx.f16 s2, s15 ; CHECK-NEXT: vmovx.f16 s11, s7
; CHECK-NEXT: vins.f16 s2, s0 ; CHECK-NEXT: vins.f16 s11, s0
; CHECK-NEXT: vmovx.f16 s0, s30 ; CHECK-NEXT: vmovx.f16 s0, s30
; CHECK-NEXT: vmovx.f16 s4, s14 ; CHECK-NEXT: vmovx.f16 s8, s6
; CHECK-NEXT: vmov r2, s15 ; CHECK-NEXT: vmov q4, q1
; CHECK-NEXT: vins.f16 s4, s0 ; CHECK-NEXT: vins.f16 s8, s0
; CHECK-NEXT: vmov q6, q5 ; CHECK-NEXT: vstrw.32 q4, [sp, #48] @ 16-byte Spill
; CHECK-NEXT: vmov.16 q1[3], r2 ; CHECK-NEXT: vins.f16 s9, s7
; CHECK-NEXT: vstrw.32 q3, [sp, #32] @ 16-byte Spill ; CHECK-NEXT: vmov.f32 s10, s31
; CHECK-NEXT: vmov.f32 s7, s2 ; CHECK-NEXT: vmovx.f16 s0, s9
; CHECK-NEXT: vmovx.f16 s2, s20 ; CHECK-NEXT: vmov q3, q2
; CHECK-NEXT: vmov.f32 s6, s31 ; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vmovx.f16 s0, s5 ; CHECK-NEXT: vmov.f32 s5, s11
; CHECK-NEXT: vmov q2, q1 ; CHECK-NEXT: vmov q6, q2
; CHECK-NEXT: vmov.f32 s5, s19 ; CHECK-NEXT: vmov.f32 s6, s11
; CHECK-NEXT: vmov.f32 s6, s19 ; CHECK-NEXT: vldrw.u32 q2, [r0, #48]
; CHECK-NEXT: vstrw.32 q4, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vins.f16 s5, s0 ; CHECK-NEXT: vins.f16 s5, s0
; CHECK-NEXT: vmovx.f16 s0, s6 ; CHECK-NEXT: vmovx.f16 s0, s6
; CHECK-NEXT: vstrw.32 q1, [sp, #64] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q1, [sp, #64] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vins.f16 s10, s0 ; CHECK-NEXT: vins.f16 s14, s0
; CHECK-NEXT: vmov r2, s2 ; CHECK-NEXT: vmovx.f16 s2, s8
; CHECK-NEXT: vstrw.32 q2, [sp, #48] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q3, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vmov.f64 d4, d2 ; CHECK-NEXT: vmov.f64 d6, d2
; CHECK-NEXT: vstrw.32 q1, [sp] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q1, [sp, #80] @ 16-byte Spill
; CHECK-NEXT: vmovx.f16 s2, s12 ; CHECK-NEXT: vstrw.32 q6, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vins.f16 s8, s20 ; CHECK-NEXT: vstrw.32 q2, [sp] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s0, s5 ; CHECK-NEXT: vmov.f32 s0, s5
; CHECK-NEXT: vins.f16 s0, s21 ; CHECK-NEXT: vins.f16 s12, s8
; CHECK-NEXT: vmov.16 q2[4], r2 ; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: vldrw.u32 q5, [r0, #80] ; CHECK-NEXT: vins.f16 s0, s9
; CHECK-NEXT: vmov.f32 s11, s0 ; CHECK-NEXT: vmov.16 q3[4], r2
; CHECK-NEXT: vmov.f32 s9, s4 ; CHECK-NEXT: vmovx.f16 s2, s16
; CHECK-NEXT: vmov.f32 s15, s0
; CHECK-NEXT: vmovx.f16 s0, s4 ; CHECK-NEXT: vmovx.f16 s0, s4
; CHECK-NEXT: vmov.f32 s13, s4
; CHECK-NEXT: vmov.f32 s5, s20 ; CHECK-NEXT: vmov.f32 s5, s20
; CHECK-NEXT: vmov.f32 s6, s20 ; CHECK-NEXT: vmov.f32 s6, s20
; CHECK-NEXT: vins.f16 s5, s0 ; CHECK-NEXT: vins.f16 s5, s0
; CHECK-NEXT: vmovx.f16 s0, s6 ; CHECK-NEXT: vmovx.f16 s0, s6
; CHECK-NEXT: vstrw.32 q1, [sp, #112] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q1, [sp, #112] @ 16-byte Spill
; CHECK-NEXT: vmov.f64 d2, d8 ; CHECK-NEXT: vmov q1, q6
; CHECK-NEXT: vins.f16 s10, s0 ; CHECK-NEXT: vins.f16 s14, s0
; CHECK-NEXT: vstrw.32 q2, [sp, #96] @ 16-byte Spill ; CHECK-NEXT: vmov.f32 s0, s5
; CHECK-NEXT: vmov q2, q6 ; CHECK-NEXT: vins.f16 s24, s16
; CHECK-NEXT: vmovx.f16 s24, s10
; CHECK-NEXT: vmov.f32 s0, s17
; CHECK-NEXT: vins.f16 s4, s12
; CHECK-NEXT: vmov r0, s2 ; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: vins.f16 s0, s13 ; CHECK-NEXT: vins.f16 s0, s17
; CHECK-NEXT: vmov.16 q1[4], r0 ; CHECK-NEXT: vmov.16 q6[4], r0
; CHECK-NEXT: vmov.f32 s13, s28 ; CHECK-NEXT: vmov.f32 s27, s0
; CHECK-NEXT: vmov.f32 s7, s0 ; CHECK-NEXT: vmovx.f16 s0, s4
; CHECK-NEXT: vmovx.f16 s0, s16 ; CHECK-NEXT: vmov.f32 s25, s4
; CHECK-NEXT: vmov.f32 s14, s28 ; CHECK-NEXT: vmov.f32 s5, s28
; CHECK-NEXT: vmovx.f16 s2, s11 ; CHECK-NEXT: vmov.f32 s6, s28
; CHECK-NEXT: vins.f16 s13, s0 ; CHECK-NEXT: vins.f16 s5, s0
; CHECK-NEXT: vmov.f32 s5, s16 ; CHECK-NEXT: vmovx.f16 s0, s6
; CHECK-NEXT: vmovx.f16 s0, s14 ; CHECK-NEXT: vstrw.32 q1, [sp, #96] @ 16-byte Spill
; CHECK-NEXT: vmov r0, s11 ; CHECK-NEXT: vins.f16 s26, s0
; CHECK-NEXT: vins.f16 s6, s0
; CHECK-NEXT: vmovx.f16 s0, s22 ; CHECK-NEXT: vmovx.f16 s0, s22
; CHECK-NEXT: vins.f16 s24, s0 ; CHECK-NEXT: vmovx.f16 s4, s10
; CHECK-NEXT: vstrw.32 q1, [sp, #80] @ 16-byte Spill ; CHECK-NEXT: vins.f16 s4, s0
; CHECK-NEXT: vmov q1, q2
; CHECK-NEXT: vmovx.f16 s0, s23 ; CHECK-NEXT: vmovx.f16 s0, s23
; CHECK-NEXT: vldrw.u32 q2, [sp] @ 16-byte Reload ; CHECK-NEXT: vmovx.f16 s7, s11
; CHECK-NEXT: vins.f16 s2, s0 ; CHECK-NEXT: vmov.f32 s28, s29
; CHECK-NEXT: vmov.16 q6[3], r0 ; CHECK-NEXT: vins.f16 s7, s0
; CHECK-NEXT: vrev32.16 q1, q1 ; CHECK-NEXT: vins.f16 s5, s11
; CHECK-NEXT: vmov.f32 s27, s2 ; CHECK-NEXT: vldrw.u32 q2, [sp, #80] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s6, s23
; CHECK-NEXT: vmovx.f16 s16, s5
; CHECK-NEXT: vmov.f32 s1, s11 ; CHECK-NEXT: vmov.f32 s1, s11
; CHECK-NEXT: vmov.f32 s26, s23
; CHECK-NEXT: vmovx.f16 s16, s25
; CHECK-NEXT: vmov.f32 s2, s11 ; CHECK-NEXT: vmov.f32 s2, s11
; CHECK-NEXT: vins.f16 s1, s16 ; CHECK-NEXT: vins.f16 s1, s16
; CHECK-NEXT: vmovx.f16 s16, s2 ; CHECK-NEXT: vmovx.f16 s16, s2
; CHECK-NEXT: vins.f16 s26, s16 ; CHECK-NEXT: vins.f16 s6, s16
; CHECK-NEXT: vmovx.f16 s16, s9 ; CHECK-NEXT: vmovx.f16 s16, s9
; CHECK-NEXT: vmov.f32 s20, s21 ; CHECK-NEXT: vmov.f32 s20, s21
; CHECK-NEXT: vins.f16 s20, s16 ; CHECK-NEXT: vins.f16 s20, s16
; CHECK-NEXT: vmovx.f16 s16, s10 ; CHECK-NEXT: vmovx.f16 s16, s10
; CHECK-NEXT: vins.f16 s22, s16 ; CHECK-NEXT: vins.f16 s22, s16
; CHECK-NEXT: vmov.f32 s2, s26 ; CHECK-NEXT: vldrw.u32 q2, [sp] @ 16-byte Reload
; CHECK-NEXT: vldrw.u32 q4, [sp, #80] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s23, s22 ; CHECK-NEXT: vmov.f32 s23, s22
; CHECK-NEXT: vmov.f32 s22, s10 ; CHECK-NEXT: vrev32.16 q2, q2
; CHECK-NEXT: vmov.f32 s2, s6
; CHECK-NEXT: vmov.f32 s22, s18
; CHECK-NEXT: vmovx.f16 s16, s21 ; CHECK-NEXT: vmovx.f16 s16, s21
; CHECK-NEXT: vldrw.u32 q2, [sp, #96] @ 16-byte Reload ; CHECK-NEXT: vins.f16 s9, s16
; CHECK-NEXT: vins.f16 s5, s16
; CHECK-NEXT: vldrw.u32 q4, [sp, #112] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q4, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s25, s1 ; CHECK-NEXT: vmov.f32 s18, s14
; CHECK-NEXT: vmov.f32 s18, s10 ; CHECK-NEXT: vstrw.32 q2, [sp, #80] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q2, [sp, #80] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q4, [sp, #112] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q4, [sp, #112] @ 16-byte Spill
; CHECK-NEXT: vmovx.f16 s16, s6 ; CHECK-NEXT: vldrw.u32 q4, [sp, #96] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s14, s10 ; CHECK-NEXT: vmov.f32 s18, s26
; CHECK-NEXT: vstrw.32 q4, [sp, #96] @ 16-byte Spill
; CHECK-NEXT: vmovx.f16 s16, s10
; CHECK-NEXT: vins.f16 s22, s16 ; CHECK-NEXT: vins.f16 s22, s16
; CHECK-NEXT: vldrw.u32 q4, [sp, #16] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q4, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q1, [sp] @ 16-byte Spill ; CHECK-NEXT: vmov.f32 s5, s1
; CHECK-NEXT: vldrw.u32 q1, [sp, #80] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s28, s29
; CHECK-NEXT: vmovx.f16 s8, s17 ; CHECK-NEXT: vmovx.f16 s8, s17
; CHECK-NEXT: vmov.f32 s26, s2 ; CHECK-NEXT: vmov.f32 s6, s2
; CHECK-NEXT: vmov.f32 s5, s13
; CHECK-NEXT: vins.f16 s28, s8 ; CHECK-NEXT: vins.f16 s28, s8
; CHECK-NEXT: vmovx.f16 s0, s18 ; CHECK-NEXT: vmovx.f16 s0, s18
; CHECK-NEXT: vldrw.u32 q2, [sp, #96] @ 16-byte Reload
; CHECK-NEXT: vins.f16 s30, s0 ; CHECK-NEXT: vins.f16 s30, s0
; CHECK-NEXT: vldrw.u32 q0, [sp, #32] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #48] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s6, s14
; CHECK-NEXT: vldrw.u32 q3, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s31, s30 ; CHECK-NEXT: vmov.f32 s31, s30
; CHECK-NEXT: vrev32.16 q0, q0 ; CHECK-NEXT: vldrw.u32 q2, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s30, s18 ; CHECK-NEXT: vmov.f32 s30, s18
; CHECK-NEXT: vmovx.f16 s16, s29 ; CHECK-NEXT: vmovx.f16 s16, s29
; CHECK-NEXT: vmov.f32 s9, s13 ; CHECK-NEXT: vrev32.16 q0, q0
; CHECK-NEXT: vstrw.32 q1, [r1, #80]
; CHECK-NEXT: vins.f16 s1, s16 ; CHECK-NEXT: vins.f16 s1, s16
; CHECK-NEXT: vmov.f32 s10, s14
; CHECK-NEXT: vmovx.f16 s16, s2 ; CHECK-NEXT: vmovx.f16 s16, s2
; CHECK-NEXT: vldrw.u32 q3, [sp, #48] @ 16-byte Reload
; CHECK-NEXT: vins.f16 s30, s16 ; CHECK-NEXT: vins.f16 s30, s16
; CHECK-NEXT: vldrw.u32 q4, [sp, #64] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q4, [sp, #96] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s2, s30 ; CHECK-NEXT: vmov.f32 s2, s30
; CHECK-NEXT: vmov.f32 s18, s14 ; CHECK-NEXT: vmov.f32 s25, s17
; CHECK-NEXT: vstrw.32 q2, [r1, #48] ; CHECK-NEXT: vmov.f32 s26, s18
; CHECK-NEXT: vmov.f32 s13, s17 ; CHECK-NEXT: vldrw.u32 q4, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q6, [r1, #80]
; CHECK-NEXT: vmov.f32 s29, s1 ; CHECK-NEXT: vmov.f32 s29, s1
; CHECK-NEXT: vstrw.32 q1, [r1] ; CHECK-NEXT: vstrw.32 q6, [r1]
; CHECK-NEXT: vmov.f32 s30, s2 ; CHECK-NEXT: vmov.f32 s13, s17
; CHECK-NEXT: vmov.f32 s14, s18 ; CHECK-NEXT: vmov.f32 s14, s18
; CHECK-NEXT: vldrw.u32 q4, [sp] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q4, [sp, #64] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s18, s22 ; CHECK-NEXT: vmov.f32 s18, s10
; CHECK-NEXT: vstrw.32 q3, [r1, #48]
; CHECK-NEXT: vmov.f32 s9, s17
; CHECK-NEXT: vmov.f32 s30, s2
; CHECK-NEXT: vstrw.32 q7, [r1, #16] ; CHECK-NEXT: vstrw.32 q7, [r1, #16]
; CHECK-NEXT: vmov.f32 s10, s18
; CHECK-NEXT: vldrw.u32 q4, [sp, #80] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s18, s22
; CHECK-NEXT: vstrw.32 q2, [r1, #32]
; CHECK-NEXT: vmov.f32 s21, s17 ; CHECK-NEXT: vmov.f32 s21, s17
; CHECK-NEXT: vstrw.32 q3, [r1, #32]
; CHECK-NEXT: vmov.f32 s22, s18 ; CHECK-NEXT: vmov.f32 s22, s18
; CHECK-NEXT: vstrw.32 q5, [r1, #64] ; CHECK-NEXT: vstrw.32 q5, [r1, #64]
; CHECK-NEXT: add sp, #128 ; CHECK-NEXT: add sp, #128
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <16 x half>, <16 x half>* %src, i32 0 %s1 = getelementptr <16 x half>, <16 x half>* %src, i32 0
%l1 = load <16 x half>, <16 x half>* %s1, align 4 %l1 = load <16 x half>, <16 x half>* %s1, align 4
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