This is an archive of the discontinued LLVM Phabricator instance.

Show First 20 Lines • Show All 3,586 Lines • ▼ Show 20 Lines	191:128 8 bytes KERNEL_CODE_ENTRY_BYTE_OFFSET Byte offset (possibly
negative) from base		negative) from base
address of kernel		address of kernel
descriptor to kernel's		descriptor to kernel's
entry point instruction		entry point instruction
which must be 256 byte		which must be 256 byte
aligned.		aligned.
351:272 20 Reserved, must be 0.		351:272 20 Reserved, must be 0.
bytes		bytes
383:352 4 bytes COMPUTE_PGM_RSRC3 GFX6-9		383:352 4 bytes COMPUTE_PGM_RSRC3 GFX6-GFX9
Reserved, must be 0.		Reserved, must be 0.
GFX10		GFX10
Compute Shader (CS)		Compute Shader (CS)
program settings used by		program settings used by
CP to set up		CP to set up
``COMPUTE_PGM_RSRC3``		``COMPUTE_PGM_RSRC3``
configuration		configuration
register. See		register. See
Show All 30 Lines	.. table:: Code Object V3 Kernel Descriptor
>450 1 bit ENABLE_SGPR_QUEUE_PTR		>450 1 bit ENABLE_SGPR_QUEUE_PTR
>451 1 bit ENABLE_SGPR_KERNARG_SEGMENT_PTR		>451 1 bit ENABLE_SGPR_KERNARG_SEGMENT_PTR
>452 1 bit ENABLE_SGPR_DISPATCH_ID		>452 1 bit ENABLE_SGPR_DISPATCH_ID
>453 1 bit ENABLE_SGPR_FLAT_SCRATCH_INIT		>453 1 bit ENABLE_SGPR_FLAT_SCRATCH_INIT

>454 1 bit ENABLE_SGPR_PRIVATE_SEGMENT		>454 1 bit ENABLE_SGPR_PRIVATE_SEGMENT
_SIZE		_SIZE
457:455 3 bits Reserved, must be 0.		457:455 3 bits Reserved, must be 0.
458 1 bit ENABLE_WAVEFRONT_SIZE32 GFX6-9		458 1 bit ENABLE_WAVEFRONT_SIZE32 GFX6-GFX9
Reserved, must be 0.		Reserved, must be 0.
GFX10		GFX10
- If 0 execute in		- If 0 execute in
wavefront size 64 mode.		wavefront size 64 mode.
- If 1 execute in		- If 1 execute in
native wavefront size		native wavefront size
32 mode.		32 mode.
463:459 1 bit Reserved, must be 0.		463:459 1 bit Reserved, must be 0.
▲ Show 20 Lines • Show All 249 Lines • ▼ Show 20 Lines	29 1 bit WGP_MODE GFX6-GFX9
CU wavefront execution mode.		CU wavefront execution mode.
- If 1 execute work-groups on		- If 1 execute work-groups on
in WGP wavefront execution mode.		in WGP wavefront execution mode.

See :ref:`amdgpu-amdhsa-memory-model`.		See :ref:`amdgpu-amdhsa-memory-model`.

Used by CP to set up		Used by CP to set up
``COMPUTE_PGM_RSRC1.WGP_MODE``.		``COMPUTE_PGM_RSRC1.WGP_MODE``.
30 1 bit MEM_ORDERED GFX6-9		30 1 bit MEM_ORDERED GFX6-GFX9
Reserved, must be 0.		Reserved, must be 0.
GFX10		GFX10
Controls the behavior of the		Controls the behavior of the
s_waitcnt's vmcnt and vscnt		s_waitcnt's vmcnt and vscnt
counters.		counters.

- If 0 vmcnt reports completion		- If 0 vmcnt reports completion
of load and atomic with return		of load and atomic with return
out of order with sample		out of order with sample
instructions, and the vscnt		instructions, and the vscnt
reports the completion of		reports the completion of
store and atomic without		store and atomic without
return in order.		return in order.
- If 1 vmcnt reports completion		- If 1 vmcnt reports completion
of load, atomic with return		of load, atomic with return
and sample instructions in		and sample instructions in
order, and the vscnt reports		order, and the vscnt reports
the completion of store and		the completion of store and
atomic without return in order.		atomic without return in order.

Used by CP to set up		Used by CP to set up
``COMPUTE_PGM_RSRC1.MEM_ORDERED``.		``COMPUTE_PGM_RSRC1.MEM_ORDERED``.
31 1 bit FWD_PROGRESS GFX6-9		31 1 bit FWD_PROGRESS GFX6-GFX9
Reserved, must be 0.		Reserved, must be 0.
GFX10		GFX10
- If 0 execute SIMD wavefronts		- If 0 execute SIMD wavefronts
using oldest first policy.		using oldest first policy.
- If 1 execute SIMD wavefronts to		- If 1 execute SIMD wavefronts to
ensure wavefronts will make some		ensure wavefronts will make some
forward progress.		forward progress.

▲ Show 20 Lines • Show All 805 Lines • ▼ Show 20 Lines
The code sequences used to implement the memory model for GFX6-GFX9 are defined		The code sequences used to implement the memory model for GFX6-GFX9 are defined
in table :ref:`amdgpu-amdhsa-memory-model-code-sequences-gfx6-gfx9-table`.		in table :ref:`amdgpu-amdhsa-memory-model-code-sequences-gfx6-gfx9-table`.

.. table:: AMDHSA Memory Model Code Sequences GFX6-GFX9		.. table:: AMDHSA Memory Model Code Sequences GFX6-GFX9
:name: amdgpu-amdhsa-memory-model-code-sequences-gfx6-gfx9-table		:name: amdgpu-amdhsa-memory-model-code-sequences-gfx6-gfx9-table

============ ============ ============== ========== ================================		============ ============ ============== ========== ================================
LLVM Instr LLVM Memory LLVM Memory AMDGPU AMDGPU Machine Code		LLVM Instr LLVM Memory LLVM Memory AMDGPU AMDGPU Machine Code
Ordering Sync Scope Address GFX6-9		Ordering Sync Scope Address GFX6-GFX9
Space		Space
============ ============ ============== ========== ================================		============ ============ ============== ========== ================================
Non-Atomic		Non-Atomic
------------------------------------------------------------------------------------		------------------------------------------------------------------------------------
load none none - global - !volatile & !nontemporal		load none none - global - !volatile & !nontemporal
- generic		- generic
- private 1. buffer/global/flat_load		- private 1. buffer/global/flat_load
- constant		- constant
▲ Show 20 Lines • Show All 3,312 Lines • ▼ Show 20 Lines	.. table:: AMDGPU Trap Handler for AMDHSA OS Code Object V3
reserved ``s_trap 0xff`` Reserved.		reserved ``s_trap 0xff`` Reserved.
=================== =============== =============== =======================================		=================== =============== =============== =======================================

..		..

.. table:: AMDGPU Trap Handler for AMDHSA OS Code Object V4		.. table:: AMDGPU Trap Handler for AMDHSA OS Code Object V4
:name: amdgpu-trap-handler-for-amdhsa-os-v4-table		:name: amdgpu-trap-handler-for-amdhsa-os-v4-table

=================== =============== =============== ============== =======================================		=================== =============== ================ ================= =======================================
Usage Code Sequence GFX6-8 Inputs GFX9-10 Inputs Description		Usage Code Sequence GFX6-GFX8 Inputs GFX9-GFX10 Inputs Description
=================== =============== =============== ============== =======================================		=================== =============== ================ ================= =======================================
reserved ``s_trap 0x00`` Reserved by hardware.		reserved ``s_trap 0x00`` Reserved by hardware.
debugger breakpoint ``s_trap 0x01`` none none Reserved for debugger to use for		debugger breakpoint ``s_trap 0x01`` none none Reserved for debugger to use for
breakpoints. Causes wave to be halted		breakpoints. Causes wave to be halted
with the PC at the trap instruction.		with the PC at the trap instruction.
The debugger is responsible to resume		The debugger is responsible to resume
the wave, including the instruction		the wave, including the instruction
that the breakpoint overwrote.		that the breakpoint overwrote.
``llvm.trap`` ``s_trap 0x02`` ``SGPR0-1``: none Causes wave to be halted with the PC at		``llvm.trap`` ``s_trap 0x02`` ``SGPR0-1``: none Causes wave to be halted with the PC at
``queue_ptr`` the trap instruction. The associated		``queue_ptr`` the trap instruction. The associated
queue is signalled to put it into the		queue is signalled to put it into the
error state. When the queue is put in		error state. When the queue is put in
the error state, the waves executing		the error state, the waves executing
dispatches on the queue will be		dispatches on the queue will be
terminated.		terminated.
``llvm.debugtrap`` ``s_trap 0x03`` none none - If debugger not enabled then behaves		``llvm.debugtrap`` ``s_trap 0x03`` none none - If debugger not enabled then behaves
as a no-operation. The trap handler		as a no-operation. The trap handler
is entered and immediately returns to		is entered and immediately returns to
continue execution of the wavefront.		continue execution of the wavefront.
- If the debugger is enabled, causes		- If the debugger is enabled, causes
the debug trap to be reported by the		the debug trap to be reported by the
debugger and the wavefront is put in		debugger and the wavefront is put in
the halt state with the PC at the		the halt state with the PC at the
instruction. The debugger must		instruction. The debugger must
increment the PC and resume the wave.		increment the PC and resume the wave.
reserved ``s_trap 0x04`` Reserved.		reserved ``s_trap 0x04`` Reserved.
reserved ``s_trap 0x05`` Reserved.		reserved ``s_trap 0x05`` Reserved.
reserved ``s_trap 0x06`` Reserved.		reserved ``s_trap 0x06`` Reserved.
reserved ``s_trap 0x07`` Reserved.		reserved ``s_trap 0x07`` Reserved.
reserved ``s_trap 0x08`` Reserved.		reserved ``s_trap 0x08`` Reserved.
reserved ``s_trap 0xfe`` Reserved.		reserved ``s_trap 0xfe`` Reserved.
reserved ``s_trap 0xff`` Reserved.		reserved ``s_trap 0xff`` Reserved.
=================== =============== =============== ============== =======================================		=================== =============== ================ ================= =======================================

.. _amdgpu-amdhsa-function-call-convention:		.. _amdgpu-amdhsa-function-call-convention:

Call Convention		Call Convention
~~~~~~~~~~~~~~~		~~~~~~~~~~~~~~~

.. note::		.. note::

▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines	1. SGPR0-3 contain a V# with the following properties (see
:ref:`amdgpu-amdhsa-kernel-prolog-private-segment-buffer`):		:ref:`amdgpu-amdhsa-kernel-prolog-private-segment-buffer`):

* Base address pointing to the beginning of the wavefront scratch backing		* Base address pointing to the beginning of the wavefront scratch backing
memory.		memory.
* Swizzled with dword element size and stride of wavefront size elements.		* Swizzled with dword element size and stride of wavefront size elements.

2. The FLAT_SCRATCH register pair is setup. See		2. The FLAT_SCRATCH register pair is setup. See
:ref:`amdgpu-amdhsa-kernel-prolog-flat-scratch`.		:ref:`amdgpu-amdhsa-kernel-prolog-flat-scratch`.
3. GFX6-8: M0 register set to the size of LDS in bytes. See		3. GFX6-GFX8: M0 register set to the size of LDS in bytes. See
:ref:`amdgpu-amdhsa-kernel-prolog-m0`.		:ref:`amdgpu-amdhsa-kernel-prolog-m0`.
4. The EXEC register is set to the lanes active on entry to the function.		4. The EXEC register is set to the lanes active on entry to the function.
5. MODE register: TBD		5. MODE register: TBD
6. VGPR0-31 and SGPR4-29 are used to pass function input arguments as described		6. VGPR0-31 and SGPR4-29 are used to pass function input arguments as described
below.		below.
7. SGPR30-31 return address (RA). The code address that the function must		7. SGPR30-31 return address (RA). The code address that the function must
return to when it completes. The value is undefined if the function is *no		return to when it completes. The value is undefined if the function is *no
return*.		return*.
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On exit from a function:		On exit from a function:

1. VGPR0-31 and SGPR4-29 are used to pass function result arguments as		1. VGPR0-31 and SGPR4-29 are used to pass function result arguments as
described below. Any registers used are considered clobbered registers.		described below. Any registers used are considered clobbered registers.
2. The following registers are preserved and have the same value as on entry:		2. The following registers are preserved and have the same value as on entry:

* FLAT_SCRATCH		* FLAT_SCRATCH
* EXEC		* EXEC
* GFX6-8: M0		* GFX6-GFX8: M0
* All SGPR registers except the clobbered registers of SGPR4-31.		* All SGPR registers except the clobbered registers of SGPR4-31.
* VGPR40-47		* VGPR40-47
VGPR56-63		VGPR56-63
VGPR72-79		VGPR72-79
VGPR88-95		VGPR88-95
VGPR104-111		VGPR104-111
VGPR120-127		VGPR120-127
VGPR136-143		VGPR136-143
▲ Show 20 Lines • Show All 1,285 Lines • Show Last 20 Lines

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[AMDGPU] Write "GFX6-GFX9" instead of "GFX6-9" in docs
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