[RISCV] Add more cmov isel patterns to handle seteq/ne with a small non-zero immediate.

[craig.topper]

Summary

Similar to our free standing setcc patterns, we can use ADDI to
subtract the immediate from the other operand. Then the cmov
can check if the result is zero or non-zero.

[mundaym]

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

725

Out of curiosity do you think it would make sense at some point to have a pass that just removes ADDI x, 0 (and XOR x, 0 etc.) after instruction selection? Then we could presumably delete the two patterns above.

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

 let Predicates = [HasStdExtZbp, IsRV32] in {
 def : Pat<(rotr (riscv_grevi GPR:$rs1, (i32 24)), (i32 16)), (GREVI GPR:$rs1, 8)>;
 def : Pat<(rotl (riscv_grevi GPR:$rs1, (i32 24)), (i32 16)), (GREVI GPR:$rs1, 8)>;
 } // Predicates = [HasStdExtZbp, IsRV32]
 
 let Predicates = [HasStdExtZbt] in {
 def : Pat<(or (and (not GPR:$rs2), GPR:$rs3), (and GPR:$rs2, GPR:$rs1)),
           (CMIX GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+
 def : Pat<(select (XLenVT (setne GPR:$rs2, 0)), GPR:$rs1, GPR:$rs3),
           (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
 def : Pat<(select (XLenVT (seteq GPR:$rs2, 0)), GPR:$rs3, GPR:$rs1),
           (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+def : Pat<(select (XLenVT (setne GPR:$x, simm12_plus1:$y)), GPR:$rs1, GPR:$rs3),
+          (CMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq GPR:$x, simm12_plus1:$y)), GPR:$rs3, GPR:$rs1),
+          (CMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
 def : Pat<(select (XLenVT (setne GPR:$x, GPR:$y)), GPR:$rs1, GPR:$rs3),
           (CMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
 def : Pat<(select (XLenVT (seteq GPR:$x, GPR:$y)), GPR:$rs3, GPR:$rs1),
           (CMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
 def : Pat<(select (XLenVT (setuge GPR:$x, GPR:$y)), GPR:$rs3, GPR:$rs1),
           (CMOV GPR:$rs1, (SLTU GPR:$x, GPR:$y), GPR:$rs3)>;
 def : Pat<(select (XLenVT (setule GPR:$y, GPR:$x)), GPR:$rs3, GPR:$rs1),
           (CMOV GPR:$rs1, (SLTU GPR:$x, GPR:$y), GPR:$rs3)>;

llvm/test/CodeGen/RISCV/select-optimize-multiple.ll

 ; RV32I-NEXT:    mv a2, a4
 ; RV32I-NEXT:  .LBB0_2: # %entry
 ; RV32I-NEXT:    mv a0, a1
 ; RV32I-NEXT:    mv a1, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV32IBT-LABEL: cmovcc64:
 ; RV32IBT:       # %bb.0: # %entry
-; RV32IBT-NEXT:    addi a5, zero, 123
-; RV32IBT-NEXT:    xor a5, a0, a5
+; RV32IBT-NEXT:    addi a5, a0, -123
 ; RV32IBT-NEXT:    cmov a0, a5, a3, a1
 ; RV32IBT-NEXT:    cmov a1, a5, a4, a2
 ; RV32IBT-NEXT:    ret
 ;
 ; RV64I-LABEL: cmovcc64:
 ; RV64I:       # %bb.0: # %entry
 ; RV64I-NEXT:    addi a3, zero, 123
 ; RV64I-NEXT:    beq a0, a3, .LBB0_2
 ; RV64I-NEXT:  # %bb.1: # %entry
 ; RV64I-NEXT:    mv a1, a2
 ; RV64I-NEXT:  .LBB0_2: # %entry
 ; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IBT-LABEL: cmovcc64:
 ; RV64IBT:       # %bb.0: # %entry
-; RV64IBT-NEXT:    addi a3, zero, 123
-; RV64IBT-NEXT:    xor a0, a0, a3
+; RV64IBT-NEXT:    addi a0, a0, -123
 ; RV64IBT-NEXT:    cmov a0, a0, a2, a1
 ; RV64IBT-NEXT:    ret
 entry:
   %cmp = icmp eq i32 %a, 123
   %cond = select i1 %cmp, i64 %b, i64 %c
   ret i64 %cond
 }
 

 ; RV64I-NEXT:    mv a2, a4
 ; RV64I-NEXT:  .LBB1_2: # %entry
 ; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:    mv a1, a2
 ; RV64I-NEXT:    ret
 ;
 ; RV64IBT-LABEL: cmovcc128:
 ; RV64IBT:       # %bb.0: # %entry
-; RV64IBT-NEXT:    addi a5, zero, 123
-; RV64IBT-NEXT:    xor a5, a0, a5
+; RV64IBT-NEXT:    addi a5, a0, -123
 ; RV64IBT-NEXT:    cmov a0, a5, a3, a1
 ; RV64IBT-NEXT:    cmov a1, a5, a4, a2
 ; RV64IBT-NEXT:    ret
 entry:
   %cmp = icmp eq i64 %a, 123
   %cond = select i1 %cmp, i128 %b, i128 %c
   ret i128 %cond
 }

 ; RV32I-NEXT:    beq a0, a4, .LBB6_2
 ; RV32I-NEXT:  .LBB6_4: # %entry
 ; RV32I-NEXT:    mv a2, a3
 ; RV32I-NEXT:    add a0, a1, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV32IBT-LABEL: cmovccdep:
 ; RV32IBT:       # %bb.0: # %entry
-; RV32IBT-NEXT:    addi a4, zero, 123
-; RV32IBT-NEXT:    xor a0, a0, a4
+; RV32IBT-NEXT:    addi a0, a0, -123
 ; RV32IBT-NEXT:    cmov a1, a0, a2, a1
 ; RV32IBT-NEXT:    cmov a0, a0, a3, a1
 ; RV32IBT-NEXT:    add a0, a1, a0
 ; RV32IBT-NEXT:    ret
 ;
 ; RV64I-LABEL: cmovccdep:
 ; RV64I:       # %bb.0: # %entry
 ; RV64I-NEXT:    addi a4, zero, 123

 ; RV64I-NEXT:    beq a0, a4, .LBB6_2
 ; RV64I-NEXT:  .LBB6_4: # %entry
 ; RV64I-NEXT:    mv a2, a3
 ; RV64I-NEXT:    addw a0, a1, a2
 ; RV64I-NEXT:    ret
 ;
 ; RV64IBT-LABEL: cmovccdep:
 ; RV64IBT:       # %bb.0: # %entry
-; RV64IBT-NEXT:    addi a4, zero, 123
-; RV64IBT-NEXT:    xor a0, a0, a4
+; RV64IBT-NEXT:    addi a0, a0, -123
 ; RV64IBT-NEXT:    cmov a1, a0, a2, a1
 ; RV64IBT-NEXT:    cmov a0, a0, a3, a1
 ; RV64IBT-NEXT:    addw a0, a1, a0
 ; RV64IBT-NEXT:    ret
 entry:
   %cmp = icmp eq i32 %a, 123
   %cond1 = select i1 %cmp, i32 %b, i32 %c
   %cond2 = select i1 %cmp, i32 %cond1, i32 %d