Fixes Snapdragon Kryo CPU core detection

[Sonicadvance1]

Summary

All of these families were claiming to be a73 based, which was causing
-mcpu/mtune=native to never use the newer features available to these
cores.

Goes through each and bumps the individual cores to their respective Big
counterparts. Since this code path doesn't support big.little detection,
there was already a precedent set with the Qualcomm line to choose the
big cores only.

Adds a comment on each line for the product's name that the part number
refers to. Confirmed on-device and through Linux header naming
convections.

Additionally newer SoCs mix CPU implementer parts from multiple
implementers. Both 0x41 (ARM) and 0x51 (Qualcomm) in the Snapdragon case

This was causing a desync in information where the scan at the start to
find the implementer would mismatch the part scan later on.
Now scan for both implementer and part at the start so these stay in
sync.

[Sonicadvance1]

This doesn't fully fix the issue on my end.
I'll need to try again, compiling a simple atomic op with -mcpu=native on my Snapdragon 865 board still did loadstore exclusive instead of CAS. while -mcpu=cortex-a77 does.

[Sonicadvance1]

There was a desync between Implementer and Part scans.
Implementer would scan to the end of /proc/cpuinfo, setting the implementer to 0x41 (ARM) but then the StringSwitch loop would return the first definition it would find. Which was CPU part 0x805, which doesn't exist for implementer 0x41 because that was actually a 0x51 implementer part.
Moves the Part scan to the start alongside the Implementer scan so these two values stay in sync across platforms that mix implementers.

[Sonicadvance1]

Whitespace fix on Fujitsu check

[dmgreen]

There are some tests in llvm/unittests/Support/Host.cpp. Can you add test for these cpu's and the multiple infos you were seeing? I suppose it now gets the info from the last one?

[Sonicadvance1]

Adds unit test to ensure it pulls out cortex-a77 from a Snapdragon mixed implementer minimum cpuinfo.

[Sonicadvance1]

In D94954#2508098, @dmgreen wrote:

There are some tests in llvm/unittests/Support/Host.cpp. Can you add test for these cpu's and the multiple infos you were seeing? I suppose it now gets the info from the last one?

Correct. It now pulls that last implementer/part pair from the cpuinfo. Which it was kind of sort of already doing, just in a strange desync'd manner that was broken if you mixed implementers.

[dmgreen]

Thanks. LGTM

[Sonicadvance1]

I don't have commit rights. So someone is going to need to merge this on my behalf.

[MaskRay]

In your commit the message does not include Reviewed by:. Many people agree that both Reviewed by: & Differential Revision: should be present. The Reviewed by: list indicates people who acknowledged the patch. (The Reviewers: list does not necessarily mean all the people on the list have acknowledged the patch so Reviewers: is mostly useless.)

arc amend can fetch the Phabricator summary and amend the local description.

You can install llvm/utils/git/pre-push.py to prevent accidental Summary:, Reviewers:, Subscribers: and Tags: in the presence of Differential Revision:.

[Sonicadvance1]

This has mixed signals to me.
Looking at the recent commits, there is a smattering of commits putting this in the commit message or not.
Additionally they already have the differential review in the commit messages.

If this is to be enforced, it should first be added to the contributor guide which has nothing on the topic. https://llvm.org/docs/Contributing.html
And then there should be additional enforcement as a server-side git hook to block this from missing on the server side.

This is also a minor bugfix that has been merged for nearly a week now. Coming around at this point just to tell me this is just aggressive messaging.

[MaskRay]

In D94954#2523988, @Sonicadvance1 wrote:

This has mixed signals to me.
Looking at the recent commits, there is a smattering of commits putting this in the commit message or not.
Additionally they already have the differential review in the commit messages.

If this is to be enforced, it should first be added to the contributor guide which has nothing on the topic. https://llvm.org/docs/Contributing.html
And then there should be additional enforcement as a server-side git hook to block this from missing on the server side.

Sorry, it was my mistake. The consensus is to have Differential Revision: . Reviewed by: is optional. Reviewers:/Tags:/Subscribers: cannot be added.

This is also a minor bugfix that has been merged for nearly a week now. Coming around at this point just to tell me this is just aggressive messaging.

I reported issues to Reviewed by: patches equally. I just checked - and this commit message is good. But for others, it is not late to tell them to improve for future commits. (And many people may not read relevant sentences https://llvm.org/docs/Contributing.html )

llvm/lib/Support/Host.cpp

StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) {
   // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line
   // in all cases.
   SmallVector<StringRef, 32> Lines;
   ProcCpuinfoContent.split(Lines, "\n");
 
   // Look for the CPU implementer line.
   StringRef Implementer;
   StringRef Hardware;
+  StringRef Part;
   for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
     if (Lines[I].startswith("CPU implementer"))
       Implementer = Lines[I].substr(15).ltrim("\t :");
     if (Lines[I].startswith("Hardware"))
       Hardware = Lines[I].substr(8).ltrim("\t :");
+    if (Lines[I].startswith("CPU part"))
+      Part = Lines[I].substr(8).ltrim("\t :");
   }
 
   if (Implementer == "0x41") { // ARM Ltd.
     // MSM8992/8994 may give cpu part for the core that the kernel is running on,
     // which is undeterministic and wrong. Always return cortex-a53 for these SoC.
     if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996"))
       return "cortex-a53";
 
 
-    // Look for the CPU part line.
-    for (unsigned I = 0, E = Lines.size(); I != E; ++I)
-      if (Lines[I].startswith("CPU part"))
-        // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
-        // values correspond to the "Part number" in the CP15/c0 register. The
-        // contents are specified in the various processor manuals.
-        // This corresponds to the Main ID Register in Technical Reference Manuals.
-        // and is used in programs like sys-utils
-        return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
-            .Case("0x926", "arm926ej-s")
-            .Case("0xb02", "mpcore")
-            .Case("0xb36", "arm1136j-s")
-            .Case("0xb56", "arm1156t2-s")
-            .Case("0xb76", "arm1176jz-s")
-            .Case("0xc08", "cortex-a8")
-            .Case("0xc09", "cortex-a9")
-            .Case("0xc0f", "cortex-a15")
-            .Case("0xc20", "cortex-m0")
-            .Case("0xc23", "cortex-m3")
-            .Case("0xc24", "cortex-m4")
-            .Case("0xd22", "cortex-m55")
-            .Case("0xd02", "cortex-a34")
-            .Case("0xd04", "cortex-a35")
-            .Case("0xd03", "cortex-a53")
-            .Case("0xd07", "cortex-a57")
-            .Case("0xd08", "cortex-a72")
-            .Case("0xd09", "cortex-a73")
-            .Case("0xd0a", "cortex-a75")
-            .Case("0xd0b", "cortex-a76")
-            .Case("0xd0d", "cortex-a77")
-            .Case("0xd41", "cortex-a78")
-            .Case("0xd44", "cortex-x1")
-            .Case("0xd0c", "neoverse-n1")
-            .Case("0xd49", "neoverse-n2")
-            .Default("generic");
+    return StringSwitch<const char *>(Part)
   }
 
   if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium.
-    for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
-      if (Lines[I].startswith("CPU part")) {
-        return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
-          .Case("0x516", "thunderx2t99")
-          .Case("0x0516", "thunderx2t99")
-          .Case("0xaf", "thunderx2t99")
-          .Case("0x0af", "thunderx2t99")
-          .Case("0xa1", "thunderxt88")
-          .Case("0x0a1", "thunderxt88")
-          .Default("generic");
-      }
-    }
-  }
+    return StringSwitch<const char *>(Part)
 
   if (Implementer == "0x46") { // Fujitsu Ltd.
-    for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
-      if (Lines[I].startswith("CPU part")) {
-        return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
-          .Case("0x001", "a64fx")
-          .Default("generic");
-      }
-    }
-  }
+    return StringSwitch<const char *>(Part)
 
   if (Implementer == "0x4e") { // NVIDIA Corporation
-    for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
-      if (Lines[I].startswith("CPU part")) {
-        return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
-            .Case("0x004", "carmel")
-            .Default("generic");
-      }
-    }
-  }
+    return StringSwitch<const char *>(Part)
 
   if (Implementer == "0x48") // HiSilicon Technologies, Inc.
-    // Look for the CPU part line.
-    for (unsigned I = 0, E = Lines.size(); I != E; ++I)
-      if (Lines[I].startswith("CPU part"))
-        // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
-        // values correspond to the "Part number" in the CP15/c0 register. The
-        // contents are specified in the various processor manuals.
-        return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
-          .Case("0xd01", "tsv110")
-          .Default("generic");
+    return StringSwitch<const char *>(Part)
 
   if (Implementer == "0x51") // Qualcomm Technologies, Inc.
-    // Look for the CPU part line.
-    for (unsigned I = 0, E = Lines.size(); I != E; ++I)
-      if (Lines[I].startswith("CPU part"))
-        // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
-        // values correspond to the "Part number" in the CP15/c0 register. The
-        // contents are specified in the various processor manuals.
-        return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
-            .Case("0x06f", "krait") // APQ8064
-            .Case("0x201", "kryo")
-            .Case("0x205", "kryo")
-            .Case("0x211", "kryo")
-            .Case("0x800", "cortex-a73")
-            .Case("0x801", "cortex-a73")
-            .Case("0x802", "cortex-a73")
-            .Case("0x803", "cortex-a73")
-            .Case("0x804", "cortex-a73")
-            .Case("0x805", "cortex-a73")
-            .Case("0xc00", "falkor")
-            .Case("0xc01", "saphira")
-            .Default("generic");
-
+    return StringSwitch<const char *>(Part)
+        .Case("0x800", "cortex-a73") // Kryo 2xx Gold
+        .Case("0x801", "cortex-a73") // Kryo 2xx Silver
+        .Case("0x802", "cortex-a75") // Kryo 3xx Gold
+        .Case("0x803", "cortex-a75") // Kryo 3xx Silver
+        .Case("0x804", "cortex-a76") // Kryo 4xx Gold
+        .Case("0x805", "cortex-a76") // Kryo 4xx/5xx Silver
   if (Implementer == "0x53") { // Samsung Electronics Co., Ltd.
     // The Exynos chips have a convoluted ID scheme that doesn't seem to follow
     // any predictive pattern across variants and parts.
     unsigned Variant = 0, Part = 0;
 
     // Look for the CPU variant line, whose value is a 1 digit hexadecimal
     // number, corresponding to the Variant bits in the CP15/C0 register.
     for (auto I : Lines)

llvm/unittests/Support/Host.cpp

 CPU implementer : 0x4e
 CPU architecture: 8
 CPU variant     : 0x0
 CPU part        : 0x004
 CPU revision    : 0
 )";
 
   EXPECT_EQ(sys::detail::getHostCPUNameForARM(CarmelProcCpuInfo), "carmel");
+
+  // Snapdragon mixed implementer quirk
+  const std::string Snapdragon865ProcCPUInfo = R"(
+processor       : 0
+BogoMIPS        : 38.40
+Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
+CPU implementer : 0x51
+CPU architecture: 8
+CPU variant     : 0xd
+CPU part        : 0x805
+CPU revision    : 14
+processor       : 1
+processor       : 2
+processor       : 3
+processor       : 4
+processor       : 5
+processor       : 6
+BogoMIPS        : 38.40
+Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
+CPU implementer : 0x41
+CPU architecture: 8
+CPU variant     : 0x1
+CPU part        : 0xd0d
+CPU revision    : 0
+)";
+  EXPECT_EQ(sys::detail::getHostCPUNameForARM(Snapdragon865ProcCPUInfo), "cortex-a77");
 }
 
 #if defined(__APPLE__) || defined(_AIX)
 static bool runAndGetCommandOutput(
     const char *ExePath, ArrayRef<llvm::StringRef> argv,
     std::unique_ptr<char[]> &Buffer, off_t &Size) {
   bool Success = false;
   [ExePath, argv, &Buffer, &Size, &Success] {