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Differential D94798

[RISCV][NFC] Increase test coverage of Zbt extension
ClosedPublic

Authored by mundaym on Jan 15 2021, 9:19 AM.

Details

Reviewers
lenary
luismarques
asb
Commits
rGb42ff9fb0382: [RISCV][NFC] Increase test coverage of Zbt extension
Summary

Add Zbt (ternary) extension code generation to the select lowering
tests since it can have a significant impact on how select is
lowered.

While we are here make the neg-abs commands more consistent with
the other tests.

Diff Detail

Event Timeline

mundaym created this revision.Jan 15 2021, 9:19 AM
Herald added subscribers: frasercrmck, NickHung, evandro and 23 others. · View Herald TranscriptJan 15 2021, 9:19 AM
mundaym requested review of this revision.Jan 15 2021, 9:19 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 15 2021, 9:19 AM
Herald added subscribers: llvm-commits, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B85369: Diff 316995.Jan 15 2021, 10:40 AM
mundaym updated this revision to Diff 317246.Jan 17 2021, 3:29 PM

Update MIR test.

Harbormaster completed remote builds in B85541: Diff 317246.Jan 17 2021, 4:03 PM
lenary accepted this revision.Jan 18 2021, 9:09 AM

LGTM. I'll land this for you today.

This revision is now accepted and ready to land.Jan 18 2021, 9:09 AM
Closed by commit rGb42ff9fb0382: [RISCV][NFC] Increase test coverage of Zbt extension (authored by mundaym, committed by lenary). · Explain WhyJan 18 2021, 9:31 AM
This revision was automatically updated to reflect the committed changes.
lenary added a commit: rGb42ff9fb0382: [RISCV][NFC] Increase test coverage of Zbt extension.

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
186 lines
58 lines
select-bare.ll
bare-select.ll
22 lines
56 lines
156 lines
272 lines
90 lines
58 lines

Diff 317379

llvm/test/CodeGen/RISCV/bare-select.ll

  • This file was moved to llvm/test/CodeGen/RISCV/select-bare.ll.

llvm/test/CodeGen/RISCV/neg-abs.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32-unknown-unknown | FileCheck %s --check-prefix=RV32 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: llc < %s -verify-machineinstrs -mtriple=riscv64-unknown-unknown | FileCheck %s --check-prefix=RV64 ; RUN: | FileCheck %s --check-prefix=RV32I
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefix=RV32IBT
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefix=RV64I
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefix=RV64IBT
declare i32 @llvm.abs.i32(i32, i1 immarg) declare i32 @llvm.abs.i32(i32, i1 immarg)
declare i64 @llvm.abs.i64(i64, i1 immarg) declare i64 @llvm.abs.i64(i64, i1 immarg)
define i32 @neg_abs32(i32 %x) { define i32 @neg_abs32(i32 %x) {
; RV32-LABEL: neg_abs32: ; RV32I-LABEL: neg_abs32:
; RV32: # %bb.0: ; RV32I: # %bb.0:
; RV32-NEXT: srai a1, a0, 31 ; RV32I-NEXT: srai a1, a0, 31
; RV32-NEXT: xor a0, a0, a1 ; RV32I-NEXT: xor a0, a0, a1
; RV32-NEXT: sub a0, a1, a0 ; RV32I-NEXT: sub a0, a1, a0
; RV32-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64-LABEL: neg_abs32: ; RV32IBT-LABEL: neg_abs32:
; RV64: # %bb.0: ; RV32IBT: # %bb.0:
; RV64-NEXT: sraiw a1, a0, 31 ; RV32IBT-NEXT: srai a1, a0, 31
; RV64-NEXT: xor a0, a0, a1 ; RV32IBT-NEXT: xor a0, a0, a1
; RV64-NEXT: subw a0, a1, a0 ; RV32IBT-NEXT: sub a0, a1, a0
; RV64-NEXT: ret ; RV32IBT-NEXT: ret
;
; RV64I-LABEL: neg_abs32:
; RV64I: # %bb.0:
; RV64I-NEXT: sraiw a1, a0, 31
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: subw a0, a1, a0
; RV64I-NEXT: ret
;
; RV64IBT-LABEL: neg_abs32:
; RV64IBT: # %bb.0:
; RV64IBT-NEXT: sraiw a1, a0, 31
; RV64IBT-NEXT: xor a0, a0, a1
; RV64IBT-NEXT: subw a0, a1, a0
; RV64IBT-NEXT: ret
%abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true) %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
%neg = sub nsw i32 0, %abs %neg = sub nsw i32 0, %abs
ret i32 %neg ret i32 %neg
} }
define i32 @select_neg_abs32(i32 %x) { define i32 @select_neg_abs32(i32 %x) {
; RV32-LABEL: select_neg_abs32: ; RV32I-LABEL: select_neg_abs32:
; RV32: # %bb.0: ; RV32I: # %bb.0:
; RV32-NEXT: srai a1, a0, 31 ; RV32I-NEXT: srai a1, a0, 31
; RV32-NEXT: xor a0, a0, a1 ; RV32I-NEXT: xor a0, a0, a1
; RV32-NEXT: sub a0, a1, a0 ; RV32I-NEXT: sub a0, a1, a0
; RV32-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64-LABEL: select_neg_abs32: ; RV32IBT-LABEL: select_neg_abs32:
; RV64: # %bb.0: ; RV32IBT: # %bb.0:
; RV64-NEXT: sraiw a1, a0, 31 ; RV32IBT-NEXT: srai a1, a0, 31
; RV64-NEXT: xor a0, a0, a1 ; RV32IBT-NEXT: xor a0, a0, a1
; RV64-NEXT: subw a0, a1, a0 ; RV32IBT-NEXT: sub a0, a1, a0
; RV64-NEXT: ret ; RV32IBT-NEXT: ret
;
; RV64I-LABEL: select_neg_abs32:
; RV64I: # %bb.0:
; RV64I-NEXT: sraiw a1, a0, 31
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: subw a0, a1, a0
; RV64I-NEXT: ret
;
; RV64IBT-LABEL: select_neg_abs32:
; RV64IBT: # %bb.0:
; RV64IBT-NEXT: sraiw a1, a0, 31
; RV64IBT-NEXT: xor a0, a0, a1
; RV64IBT-NEXT: subw a0, a1, a0
; RV64IBT-NEXT: ret
%1 = icmp slt i32 %x, 0 %1 = icmp slt i32 %x, 0
%2 = sub nsw i32 0, %x %2 = sub nsw i32 0, %x
%3 = select i1 %1, i32 %x, i32 %2 %3 = select i1 %1, i32 %x, i32 %2
ret i32 %3 ret i32 %3
} }
define i64 @neg_abs64(i64 %x) { define i64 @neg_abs64(i64 %x) {
; RV32-LABEL: neg_abs64: ; RV32I-LABEL: neg_abs64:
; RV32: # %bb.0: ; RV32I: # %bb.0:
; RV32-NEXT: srai a2, a1, 31 ; RV32I-NEXT: srai a2, a1, 31
; RV32-NEXT: xor a0, a0, a2 ; RV32I-NEXT: xor a0, a0, a2
; RV32-NEXT: sltu a3, a2, a0 ; RV32I-NEXT: sltu a3, a2, a0
; RV32-NEXT: xor a1, a1, a2 ; RV32I-NEXT: xor a1, a1, a2
; RV32-NEXT: sub a1, a2, a1 ; RV32I-NEXT: sub a1, a2, a1
; RV32-NEXT: sub a1, a1, a3 ; RV32I-NEXT: sub a1, a1, a3
; RV32-NEXT: sub a0, a2, a0 ; RV32I-NEXT: sub a0, a2, a0
; RV32-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64-LABEL: neg_abs64: ; RV32IBT-LABEL: neg_abs64:
; RV64: # %bb.0: ; RV32IBT: # %bb.0:
; RV64-NEXT: srai a1, a0, 63 ; RV32IBT-NEXT: srai a2, a1, 31
; RV64-NEXT: xor a0, a0, a1 ; RV32IBT-NEXT: xor a0, a0, a2
; RV64-NEXT: sub a0, a1, a0 ; RV32IBT-NEXT: sltu a3, a2, a0
; RV64-NEXT: ret ; RV32IBT-NEXT: xor a1, a1, a2
; RV32IBT-NEXT: sub a1, a2, a1
; RV32IBT-NEXT: sub a1, a1, a3
; RV32IBT-NEXT: sub a0, a2, a0
; RV32IBT-NEXT: ret
;
; RV64I-LABEL: neg_abs64:
; RV64I: # %bb.0:
; RV64I-NEXT: srai a1, a0, 63
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: sub a0, a1, a0
; RV64I-NEXT: ret
;
; RV64IBT-LABEL: neg_abs64:
; RV64IBT: # %bb.0:
; RV64IBT-NEXT: srai a1, a0, 63
; RV64IBT-NEXT: xor a0, a0, a1
; RV64IBT-NEXT: sub a0, a1, a0
; RV64IBT-NEXT: ret
%abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true) %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
%neg = sub nsw i64 0, %abs %neg = sub nsw i64 0, %abs
ret i64 %neg ret i64 %neg
} }
define i64 @select_neg_abs64(i64 %x) { define i64 @select_neg_abs64(i64 %x) {
; RV32-LABEL: select_neg_abs64: ; RV32I-LABEL: select_neg_abs64:
; RV32: # %bb.0: ; RV32I: # %bb.0:
; RV32-NEXT: srai a2, a1, 31 ; RV32I-NEXT: srai a2, a1, 31
; RV32-NEXT: xor a0, a0, a2 ; RV32I-NEXT: xor a0, a0, a2
; RV32-NEXT: sltu a3, a2, a0 ; RV32I-NEXT: sltu a3, a2, a0
; RV32-NEXT: xor a1, a1, a2 ; RV32I-NEXT: xor a1, a1, a2
; RV32-NEXT: sub a1, a2, a1 ; RV32I-NEXT: sub a1, a2, a1
; RV32-NEXT: sub a1, a1, a3 ; RV32I-NEXT: sub a1, a1, a3
; RV32-NEXT: sub a0, a2, a0 ; RV32I-NEXT: sub a0, a2, a0
; RV32-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64-LABEL: select_neg_abs64: ; RV32IBT-LABEL: select_neg_abs64:
; RV64: # %bb.0: ; RV32IBT: # %bb.0:
; RV64-NEXT: srai a1, a0, 63 ; RV32IBT-NEXT: srai a2, a1, 31
; RV64-NEXT: xor a0, a0, a1 ; RV32IBT-NEXT: xor a0, a0, a2
; RV64-NEXT: sub a0, a1, a0 ; RV32IBT-NEXT: sltu a3, a2, a0
; RV64-NEXT: ret ; RV32IBT-NEXT: xor a1, a1, a2
; RV32IBT-NEXT: sub a1, a2, a1
; RV32IBT-NEXT: sub a1, a1, a3
; RV32IBT-NEXT: sub a0, a2, a0
; RV32IBT-NEXT: ret
;
; RV64I-LABEL: select_neg_abs64:
; RV64I: # %bb.0:
; RV64I-NEXT: srai a1, a0, 63
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: sub a0, a1, a0
; RV64I-NEXT: ret
;
; RV64IBT-LABEL: select_neg_abs64:
; RV64IBT: # %bb.0:
; RV64IBT-NEXT: srai a1, a0, 63
; RV64IBT-NEXT: xor a0, a0, a1
; RV64IBT-NEXT: sub a0, a1, a0
; RV64IBT-NEXT: ret
%1 = icmp slt i64 %x, 0 %1 = icmp slt i64 %x, 0
%2 = sub nsw i64 0, %x %2 = sub nsw i64 0, %x
%3 = select i1 %1, i64 %x, i64 %2 %3 = select i1 %1, i64 %x, i64 %2
ret i64 %3 ret i64 %3
} }

llvm/test/CodeGen/RISCV/select-and.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IBT %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IBT %s
;; There are a few different ways to lower (select (and A, B), X, Y). This test ;; There are a few different ways to lower (select (and A, B), X, Y). This test
;; ensures that we do so with as few branches as possible. ;; ensures that we do so with as few branches as possible.
define signext i32 @select_of_and(i1 zeroext %a, i1 zeroext %b, i32 signext %c, i32 signext %d) nounwind { define signext i32 @select_of_and(i1 zeroext %a, i1 zeroext %b, i32 signext %c, i32 signext %d) nounwind {
; RV32I-LABEL: select_of_and: ; RV32I-LABEL: select_of_and:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: and a1, a0, a1 ; RV32I-NEXT: and a1, a0, a1
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: bnez a1, .LBB0_2 ; RV32I-NEXT: bnez a1, .LBB0_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: .LBB0_2: ; RV32I-NEXT: .LBB0_2:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IBT-LABEL: select_of_and:
; RV32IBT: # %bb.0:
; RV32IBT-NEXT: and a1, a0, a1
; RV32IBT-NEXT: mv a0, a2
; RV32IBT-NEXT: bnez a1, .LBB0_2
; RV32IBT-NEXT: # %bb.1:
; RV32IBT-NEXT: mv a0, a3
; RV32IBT-NEXT: .LBB0_2:
; RV32IBT-NEXT: ret
;
; RV64I-LABEL: select_of_and: ; RV64I-LABEL: select_of_and:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: and a1, a0, a1 ; RV64I-NEXT: and a1, a0, a1
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: bnez a1, .LBB0_2 ; RV64I-NEXT: bnez a1, .LBB0_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB0_2: ; RV64I-NEXT: .LBB0_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV64IBT-LABEL: select_of_and:
; RV64IBT: # %bb.0:
; RV64IBT-NEXT: and a1, a0, a1
; RV64IBT-NEXT: mv a0, a2
; RV64IBT-NEXT: bnez a1, .LBB0_2
; RV64IBT-NEXT: # %bb.1:
; RV64IBT-NEXT: mv a0, a3
; RV64IBT-NEXT: .LBB0_2:
; RV64IBT-NEXT: ret
%1 = and i1 %a, %b %1 = and i1 %a, %b
%2 = select i1 %1, i32 %c, i32 %d %2 = select i1 %1, i32 %c, i32 %d
ret i32 %2 ret i32 %2
} }
declare signext i32 @both() nounwind declare signext i32 @both() nounwind
declare signext i32 @neither() nounwind declare signext i32 @neither() nounwind
Show All 10 Lines
; RV32I-NEXT: j .LBB1_3 ; RV32I-NEXT: j .LBB1_3
; RV32I-NEXT: .LBB1_2: # %if.else ; RV32I-NEXT: .LBB1_2: # %if.else
; RV32I-NEXT: call neither@plt ; RV32I-NEXT: call neither@plt
; RV32I-NEXT: .LBB1_3: # %if.end ; RV32I-NEXT: .LBB1_3: # %if.end
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IBT-LABEL: if_of_and:
; RV32IBT: # %bb.0:
; RV32IBT-NEXT: addi sp, sp, -16
; RV32IBT-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IBT-NEXT: and a0, a0, a1
; RV32IBT-NEXT: addi a1, zero, 1
; RV32IBT-NEXT: bne a0, a1, .LBB1_2
; RV32IBT-NEXT: # %bb.1: # %if.then
; RV32IBT-NEXT: call both@plt
; RV32IBT-NEXT: j .LBB1_3
; RV32IBT-NEXT: .LBB1_2: # %if.else
; RV32IBT-NEXT: call neither@plt
; RV32IBT-NEXT: .LBB1_3: # %if.end
; RV32IBT-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IBT-NEXT: addi sp, sp, 16
; RV32IBT-NEXT: ret
;
; RV64I-LABEL: if_of_and: ; RV64I-LABEL: if_of_and:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: addi a1, zero, 1 ; RV64I-NEXT: addi a1, zero, 1
; RV64I-NEXT: bne a0, a1, .LBB1_2 ; RV64I-NEXT: bne a0, a1, .LBB1_2
; RV64I-NEXT: # %bb.1: # %if.then ; RV64I-NEXT: # %bb.1: # %if.then
; RV64I-NEXT: call both@plt ; RV64I-NEXT: call both@plt
; RV64I-NEXT: j .LBB1_3 ; RV64I-NEXT: j .LBB1_3
; RV64I-NEXT: .LBB1_2: # %if.else ; RV64I-NEXT: .LBB1_2: # %if.else
; RV64I-NEXT: call neither@plt ; RV64I-NEXT: call neither@plt
; RV64I-NEXT: .LBB1_3: # %if.end ; RV64I-NEXT: .LBB1_3: # %if.end
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV64IBT-LABEL: if_of_and:
; RV64IBT: # %bb.0:
; RV64IBT-NEXT: addi sp, sp, -16
; RV64IBT-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IBT-NEXT: and a0, a0, a1
; RV64IBT-NEXT: addi a1, zero, 1
; RV64IBT-NEXT: bne a0, a1, .LBB1_2
; RV64IBT-NEXT: # %bb.1: # %if.then
; RV64IBT-NEXT: call both@plt
; RV64IBT-NEXT: j .LBB1_3
; RV64IBT-NEXT: .LBB1_2: # %if.else
; RV64IBT-NEXT: call neither@plt
; RV64IBT-NEXT: .LBB1_3: # %if.end
; RV64IBT-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IBT-NEXT: addi sp, sp, 16
; RV64IBT-NEXT: ret
%1 = and i1 %a, %b %1 = and i1 %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.then: if.then:
%2 = tail call i32 @both() %2 = tail call i32 @both()
br label %if.end br label %if.end
if.else: if.else:
%3 = tail call i32 @neither() %3 = tail call i32 @neither()
br label %if.end br label %if.end
if.end: if.end:
%4 = phi i32 [%2, %if.then], [%3, %if.else] %4 = phi i32 [%2, %if.then], [%3, %if.else]
ret i32 %4 ret i32 %4
} }

llvm/test/CodeGen/RISCV/select-bare.ll

  • This file was moved from llvm/test/CodeGen/RISCV/bare-select.ll.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I ; RUN: | FileCheck %s -check-prefix=RV32I
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32IBT
define i32 @bare_select(i1 %a, i32 %b, i32 %c) nounwind { define i32 @bare_select(i1 %a, i32 %b, i32 %c) nounwind {
; RV32I-LABEL: bare_select: ; RV32I-LABEL: bare_select:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: andi a3, a0, 1 ; RV32I-NEXT: andi a3, a0, 1
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: bnez a3, .LBB0_2 ; RV32I-NEXT: bnez a3, .LBB0_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB0_2: ; RV32I-NEXT: .LBB0_2:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
;
; RV32IBT-LABEL: bare_select:
; RV32IBT: # %bb.0:
; RV32IBT-NEXT: andi a3, a0, 1
; RV32IBT-NEXT: mv a0, a1
; RV32IBT-NEXT: bnez a3, .LBB0_2
; RV32IBT-NEXT: # %bb.1:
; RV32IBT-NEXT: mv a0, a2
; RV32IBT-NEXT: .LBB0_2:
; RV32IBT-NEXT: ret
%1 = select i1 %a, i32 %b, i32 %c %1 = select i1 %a, i32 %b, i32 %c
ret i32 %1 ret i32 %1
} }
define float @bare_select_float(i1 %a, float %b, float %c) nounwind { define float @bare_select_float(i1 %a, float %b, float %c) nounwind {
; RV32I-LABEL: bare_select_float: ; RV32I-LABEL: bare_select_float:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: andi a3, a0, 1 ; RV32I-NEXT: andi a3, a0, 1
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: bnez a3, .LBB1_2 ; RV32I-NEXT: bnez a3, .LBB1_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB1_2: ; RV32I-NEXT: .LBB1_2:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
;
; RV32IBT-LABEL: bare_select_float:
; RV32IBT: # %bb.0:
; RV32IBT-NEXT: andi a3, a0, 1
; RV32IBT-NEXT: mv a0, a1
; RV32IBT-NEXT: bnez a3, .LBB1_2
; RV32IBT-NEXT: # %bb.1:
; RV32IBT-NEXT: mv a0, a2
; RV32IBT-NEXT: .LBB1_2:
; RV32IBT-NEXT: ret
%1 = select i1 %a, float %b, float %c %1 = select i1 %a, float %b, float %c
ret float %1 ret float %1
} }

llvm/test/CodeGen/RISCV/select-cc.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -disable-block-placement -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -disable-block-placement -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -disable-block-placement -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IBT %s
define i32 @foo(i32 %a, i32 *%b) nounwind { define i32 @foo(i32 %a, i32 *%b) nounwind {
; RV32I-LABEL: foo: ; RV32I-LABEL: foo:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lw a2, 0(a1) ; RV32I-NEXT: lw a2, 0(a1)
; RV32I-NEXT: beq a0, a2, .LBB0_2 ; RV32I-NEXT: beq a0, a2, .LBB0_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
Show All 39 Lines
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB0_18: ; RV32I-NEXT: .LBB0_18:
; RV32I-NEXT: lw a1, 0(a1) ; RV32I-NEXT: lw a1, 0(a1)
; RV32I-NEXT: bge a1, a0, .LBB0_20 ; RV32I-NEXT: bge a1, a0, .LBB0_20
; RV32I-NEXT: # %bb.19: ; RV32I-NEXT: # %bb.19:
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: .LBB0_20: ; RV32I-NEXT: .LBB0_20:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
;
; RV32IBT-LABEL: foo:
; RV32IBT: # %bb.0:
; RV32IBT-NEXT: lw a2, 0(a1)
; RV32IBT-NEXT: beq a0, a2, .LBB0_2
; RV32IBT-NEXT: # %bb.1:
; RV32IBT-NEXT: mv a0, a2
; RV32IBT-NEXT: .LBB0_2:
; RV32IBT-NEXT: lw a2, 0(a1)
; RV32IBT-NEXT: bne a0, a2, .LBB0_4
; RV32IBT-NEXT: # %bb.3:
; RV32IBT-NEXT: mv a0, a2
; RV32IBT-NEXT: .LBB0_4:
; RV32IBT-NEXT: lw a2, 0(a1)
; RV32IBT-NEXT: bltu a2, a0, .LBB0_6
; RV32IBT-NEXT: # %bb.5:
; RV32IBT-NEXT: mv a0, a2
; RV32IBT-NEXT: .LBB0_6:
; RV32IBT-NEXT: lw a2, 0(a1)
; RV32IBT-NEXT: bgeu a0, a2, .LBB0_8
; RV32IBT-NEXT: # %bb.7:
; RV32IBT-NEXT: mv a0, a2
; RV32IBT-NEXT: .LBB0_8:
; RV32IBT-NEXT: lw a2, 0(a1)
; RV32IBT-NEXT: bltu a0, a2, .LBB0_10
; RV32IBT-NEXT: # %bb.9:
; RV32IBT-NEXT: mv a0, a2
; RV32IBT-NEXT: .LBB0_10:
; RV32IBT-NEXT: lw a2, 0(a1)
; RV32IBT-NEXT: bgeu a2, a0, .LBB0_12
; RV32IBT-NEXT: # %bb.11:
; RV32IBT-NEXT: mv a0, a2
; RV32IBT-NEXT: .LBB0_12:
; RV32IBT-NEXT: lw a2, 0(a1)
; RV32IBT-NEXT: blt a2, a0, .LBB0_14
; RV32IBT-NEXT: # %bb.13:
; RV32IBT-NEXT: mv a0, a2
; RV32IBT-NEXT: .LBB0_14:
; RV32IBT-NEXT: lw a2, 0(a1)
; RV32IBT-NEXT: bge a0, a2, .LBB0_16
; RV32IBT-NEXT: # %bb.15:
; RV32IBT-NEXT: mv a0, a2
; RV32IBT-NEXT: .LBB0_16:
; RV32IBT-NEXT: lw a2, 0(a1)
; RV32IBT-NEXT: blt a0, a2, .LBB0_18
; RV32IBT-NEXT: # %bb.17:
; RV32IBT-NEXT: mv a0, a2
; RV32IBT-NEXT: .LBB0_18:
; RV32IBT-NEXT: lw a1, 0(a1)
; RV32IBT-NEXT: bge a1, a0, .LBB0_20
; RV32IBT-NEXT: # %bb.19:
; RV32IBT-NEXT: mv a0, a1
; RV32IBT-NEXT: .LBB0_20:
; RV32IBT-NEXT: ret
%val1 = load volatile i32, i32* %b %val1 = load volatile i32, i32* %b
%tst1 = icmp eq i32 %a, %val1 %tst1 = icmp eq i32 %a, %val1
%val2 = select i1 %tst1, i32 %a, i32 %val1 %val2 = select i1 %tst1, i32 %a, i32 %val1
%val3 = load volatile i32, i32* %b %val3 = load volatile i32, i32* %b
%tst2 = icmp ne i32 %val2, %val3 %tst2 = icmp ne i32 %val2, %val3
%val4 = select i1 %tst2, i32 %val2, i32 %val3 %val4 = select i1 %tst2, i32 %val2, i32 %val3
Show All 34 Lines

llvm/test/CodeGen/RISCV/select-const.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IF %s ; RUN: | FileCheck -check-prefix=RV32IF %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IBT %s
; RUN: llc -mtriple=riscv32 -mattr=+f,+experimental-zbt -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IFBT %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+f,+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+f,+d -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IFD %s ; RUN: | FileCheck -check-prefix=RV64IFD %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IBT %s
; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+experimental-zbt -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IFDBT %s
;; This tests how good we are at materialising constants using `select`. The aim ;; This tests how good we are at materialising constants using `select`. The aim
;; is that we do so without a branch if possible (at the moment our lowering of ;; is that we do so without a branch if possible (at the moment our lowering of
;; select always introduces a branch). ;; select always introduces a branch).
;; ;;
;; Currently the hook `convertSelectOfConstantsToMath` only is useful when the ;; Currently the hook `convertSelectOfConstantsToMath` only is useful when the
;; constants are either 1 away from each other, or one is a power of two and ;; constants are either 1 away from each other, or one is a power of two and
;; the other is zero. ;; the other is zero.
define signext i32 @select_const_int_easy(i1 zeroext %a) nounwind { define signext i32 @select_const_int_easy(i1 zeroext %a) nounwind {
; RV32I-LABEL: select_const_int_easy: ; RV32I-LABEL: select_const_int_easy:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IF-LABEL: select_const_int_easy: ; RV32IF-LABEL: select_const_int_easy:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV32IBT-LABEL: select_const_int_easy:
; RV32IBT: # %bb.0:
; RV32IBT-NEXT: ret
;
; RV32IFBT-LABEL: select_const_int_easy:
; RV32IFBT: # %bb.0:
; RV32IFBT-NEXT: ret
;
; RV64I-LABEL: select_const_int_easy: ; RV64I-LABEL: select_const_int_easy:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IFD-LABEL: select_const_int_easy: ; RV64IFD-LABEL: select_const_int_easy:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV64IBT-LABEL: select_const_int_easy:
; RV64IBT: # %bb.0:
; RV64IBT-NEXT: ret
;
; RV64IFDBT-LABEL: select_const_int_easy:
; RV64IFDBT: # %bb.0:
; RV64IFDBT-NEXT: ret
%1 = select i1 %a, i32 1, i32 0 %1 = select i1 %a, i32 1, i32 0
ret i32 %1 ret i32 %1
} }
define signext i32 @select_const_int_one_away(i1 zeroext %a) nounwind { define signext i32 @select_const_int_one_away(i1 zeroext %a) nounwind {
; RV32I-LABEL: select_const_int_one_away: ; RV32I-LABEL: select_const_int_one_away:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 4 ; RV32I-NEXT: addi a1, zero, 4
; RV32I-NEXT: sub a0, a1, a0 ; RV32I-NEXT: sub a0, a1, a0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IF-LABEL: select_const_int_one_away: ; RV32IF-LABEL: select_const_int_one_away:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi a1, zero, 4 ; RV32IF-NEXT: addi a1, zero, 4
; RV32IF-NEXT: sub a0, a1, a0 ; RV32IF-NEXT: sub a0, a1, a0
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV32IBT-LABEL: select_const_int_one_away:
; RV32IBT: # %bb.0:
; RV32IBT-NEXT: addi a1, zero, 4
; RV32IBT-NEXT: sub a0, a1, a0
; RV32IBT-NEXT: ret
;
; RV32IFBT-LABEL: select_const_int_one_away:
; RV32IFBT: # %bb.0:
; RV32IFBT-NEXT: addi a1, zero, 4
; RV32IFBT-NEXT: sub a0, a1, a0
; RV32IFBT-NEXT: ret
;
; RV64I-LABEL: select_const_int_one_away: ; RV64I-LABEL: select_const_int_one_away:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 4 ; RV64I-NEXT: addi a1, zero, 4
; RV64I-NEXT: sub a0, a1, a0 ; RV64I-NEXT: sub a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IFD-LABEL: select_const_int_one_away: ; RV64IFD-LABEL: select_const_int_one_away:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi a1, zero, 4 ; RV64IFD-NEXT: addi a1, zero, 4
; RV64IFD-NEXT: sub a0, a1, a0 ; RV64IFD-NEXT: sub a0, a1, a0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV64IBT-LABEL: select_const_int_one_away:
; RV64IBT: # %bb.0:
; RV64IBT-NEXT: addi a1, zero, 4
; RV64IBT-NEXT: sub a0, a1, a0
; RV64IBT-NEXT: ret
;
; RV64IFDBT-LABEL: select_const_int_one_away:
; RV64IFDBT: # %bb.0:
; RV64IFDBT-NEXT: addi a1, zero, 4
; RV64IFDBT-NEXT: sub a0, a1, a0
; RV64IFDBT-NEXT: ret
%1 = select i1 %a, i32 3, i32 4 %1 = select i1 %a, i32 3, i32 4
ret i32 %1 ret i32 %1
} }
define signext i32 @select_const_int_pow2_zero(i1 zeroext %a) nounwind { define signext i32 @select_const_int_pow2_zero(i1 zeroext %a) nounwind {
; RV32I-LABEL: select_const_int_pow2_zero: ; RV32I-LABEL: select_const_int_pow2_zero:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 2 ; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IF-LABEL: select_const_int_pow2_zero: ; RV32IF-LABEL: select_const_int_pow2_zero:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: slli a0, a0, 2 ; RV32IF-NEXT: slli a0, a0, 2
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV32IBT-LABEL: select_const_int_pow2_zero:
; RV32IBT: # %bb.0:
; RV32IBT-NEXT: slli a0, a0, 2
; RV32IBT-NEXT: ret
;
; RV32IFBT-LABEL: select_const_int_pow2_zero:
; RV32IFBT: # %bb.0:
; RV32IFBT-NEXT: slli a0, a0, 2
; RV32IFBT-NEXT: ret
;
; RV64I-LABEL: select_const_int_pow2_zero: ; RV64I-LABEL: select_const_int_pow2_zero:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 2 ; RV64I-NEXT: slli a0, a0, 2
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IFD-LABEL: select_const_int_pow2_zero: ; RV64IFD-LABEL: select_const_int_pow2_zero:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: slli a0, a0, 2 ; RV64IFD-NEXT: slli a0, a0, 2
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV64IBT-LABEL: select_const_int_pow2_zero:
; RV64IBT: # %bb.0:
; RV64IBT-NEXT: slli a0, a0, 2
; RV64IBT-NEXT: ret
;
; RV64IFDBT-LABEL: select_const_int_pow2_zero:
; RV64IFDBT: # %bb.0:
; RV64IFDBT-NEXT: slli a0, a0, 2
; RV64IFDBT-NEXT: ret
%1 = select i1 %a, i32 4, i32 0 %1 = select i1 %a, i32 4, i32 0
ret i32 %1 ret i32 %1
} }
define signext i32 @select_const_int_harder(i1 zeroext %a) nounwind { define signext i32 @select_const_int_harder(i1 zeroext %a) nounwind {
; RV32I-LABEL: select_const_int_harder: ; RV32I-LABEL: select_const_int_harder:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
Show All 9 Lines
; RV32IF-NEXT: mv a1, a0 ; RV32IF-NEXT: mv a1, a0
; RV32IF-NEXT: addi a0, zero, 6 ; RV32IF-NEXT: addi a0, zero, 6
; RV32IF-NEXT: bnez a1, .LBB3_2 ; RV32IF-NEXT: bnez a1, .LBB3_2
; RV32IF-NEXT: # %bb.1: ; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: addi a0, zero, 38 ; RV32IF-NEXT: addi a0, zero, 38
; RV32IF-NEXT: .LBB3_2: ; RV32IF-NEXT: .LBB3_2:
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV32IBT-LABEL: select_const_int_harder:
; RV32IBT: # %bb.0:
; RV32IBT-NEXT: mv a1, a0
; RV32IBT-NEXT: addi a0, zero, 6
; RV32IBT-NEXT: bnez a1, .LBB3_2
; RV32IBT-NEXT: # %bb.1:
; RV32IBT-NEXT: addi a0, zero, 38
; RV32IBT-NEXT: .LBB3_2:
; RV32IBT-NEXT: ret
;
; RV32IFBT-LABEL: select_const_int_harder:
; RV32IFBT: # %bb.0:
; RV32IFBT-NEXT: mv a1, a0
; RV32IFBT-NEXT: addi a0, zero, 6
; RV32IFBT-NEXT: bnez a1, .LBB3_2
; RV32IFBT-NEXT: # %bb.1:
; RV32IFBT-NEXT: addi a0, zero, 38
; RV32IFBT-NEXT: .LBB3_2:
; RV32IFBT-NEXT: ret
;
; RV64I-LABEL: select_const_int_harder: ; RV64I-LABEL: select_const_int_harder:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: addi a0, zero, 6 ; RV64I-NEXT: addi a0, zero, 6
; RV64I-NEXT: bnez a1, .LBB3_2 ; RV64I-NEXT: bnez a1, .LBB3_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: addi a0, zero, 38 ; RV64I-NEXT: addi a0, zero, 38
; RV64I-NEXT: .LBB3_2: ; RV64I-NEXT: .LBB3_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IFD-LABEL: select_const_int_harder: ; RV64IFD-LABEL: select_const_int_harder:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: mv a1, a0 ; RV64IFD-NEXT: mv a1, a0
; RV64IFD-NEXT: addi a0, zero, 6 ; RV64IFD-NEXT: addi a0, zero, 6
; RV64IFD-NEXT: bnez a1, .LBB3_2 ; RV64IFD-NEXT: bnez a1, .LBB3_2
; RV64IFD-NEXT: # %bb.1: ; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: addi a0, zero, 38 ; RV64IFD-NEXT: addi a0, zero, 38
; RV64IFD-NEXT: .LBB3_2: ; RV64IFD-NEXT: .LBB3_2:
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV64IBT-LABEL: select_const_int_harder:
; RV64IBT: # %bb.0:
; RV64IBT-NEXT: mv a1, a0
; RV64IBT-NEXT: addi a0, zero, 6
; RV64IBT-NEXT: bnez a1, .LBB3_2
; RV64IBT-NEXT: # %bb.1:
; RV64IBT-NEXT: addi a0, zero, 38
; RV64IBT-NEXT: .LBB3_2:
; RV64IBT-NEXT: ret
;
; RV64IFDBT-LABEL: select_const_int_harder:
; RV64IFDBT: # %bb.0:
; RV64IFDBT-NEXT: mv a1, a0
; RV64IFDBT-NEXT: addi a0, zero, 6
; RV64IFDBT-NEXT: bnez a1, .LBB3_2
; RV64IFDBT-NEXT: # %bb.1:
; RV64IFDBT-NEXT: addi a0, zero, 38
; RV64IFDBT-NEXT: .LBB3_2:
; RV64IFDBT-NEXT: ret
%1 = select i1 %a, i32 6, i32 38 %1 = select i1 %a, i32 6, i32 38
ret i32 %1 ret i32 %1
} }
define float @select_const_fp(i1 zeroext %a) nounwind { define float @select_const_fp(i1 zeroext %a) nounwind {
; RV32I-LABEL: select_const_fp: ; RV32I-LABEL: select_const_fp:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
Show All 13 Lines
; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB4_2: ; RV32IF-NEXT: .LBB4_2:
; RV32IF-NEXT: lui a0, %hi(.LCPI4_1) ; RV32IF-NEXT: lui a0, %hi(.LCPI4_1)
; RV32IF-NEXT: flw ft0, %lo(.LCPI4_1)(a0) ; RV32IF-NEXT: flw ft0, %lo(.LCPI4_1)(a0)
; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV32IBT-LABEL: select_const_fp:
; RV32IBT: # %bb.0:
; RV32IBT-NEXT: mv a1, a0
; RV32IBT-NEXT: lui a0, 263168
; RV32IBT-NEXT: bnez a1, .LBB4_2
; RV32IBT-NEXT: # %bb.1:
; RV32IBT-NEXT: lui a0, 264192
; RV32IBT-NEXT: .LBB4_2:
; RV32IBT-NEXT: ret
;
; RV32IFBT-LABEL: select_const_fp:
; RV32IFBT: # %bb.0:
; RV32IFBT-NEXT: bnez a0, .LBB4_2
; RV32IFBT-NEXT: # %bb.1:
; RV32IFBT-NEXT: lui a0, %hi(.LCPI4_0)
; RV32IFBT-NEXT: flw ft0, %lo(.LCPI4_0)(a0)
; RV32IFBT-NEXT: fmv.x.w a0, ft0
; RV32IFBT-NEXT: ret
; RV32IFBT-NEXT: .LBB4_2:
; RV32IFBT-NEXT: lui a0, %hi(.LCPI4_1)
; RV32IFBT-NEXT: flw ft0, %lo(.LCPI4_1)(a0)
; RV32IFBT-NEXT: fmv.x.w a0, ft0
; RV32IFBT-NEXT: ret
;
; RV64I-LABEL: select_const_fp: ; RV64I-LABEL: select_const_fp:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: lui a0, 263168 ; RV64I-NEXT: lui a0, 263168
; RV64I-NEXT: bnez a1, .LBB4_2 ; RV64I-NEXT: bnez a1, .LBB4_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: lui a0, 264192 ; RV64I-NEXT: lui a0, 264192
; RV64I-NEXT: .LBB4_2: ; RV64I-NEXT: .LBB4_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IFD-LABEL: select_const_fp: ; RV64IFD-LABEL: select_const_fp:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: bnez a0, .LBB4_2 ; RV64IFD-NEXT: bnez a0, .LBB4_2
; RV64IFD-NEXT: # %bb.1: ; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: lui a0, %hi(.LCPI4_0) ; RV64IFD-NEXT: lui a0, %hi(.LCPI4_0)
; RV64IFD-NEXT: flw ft0, %lo(.LCPI4_0)(a0) ; RV64IFD-NEXT: flw ft0, %lo(.LCPI4_0)(a0)
; RV64IFD-NEXT: fmv.x.w a0, ft0 ; RV64IFD-NEXT: fmv.x.w a0, ft0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB4_2: ; RV64IFD-NEXT: .LBB4_2:
; RV64IFD-NEXT: lui a0, %hi(.LCPI4_1) ; RV64IFD-NEXT: lui a0, %hi(.LCPI4_1)
; RV64IFD-NEXT: flw ft0, %lo(.LCPI4_1)(a0) ; RV64IFD-NEXT: flw ft0, %lo(.LCPI4_1)(a0)
; RV64IFD-NEXT: fmv.x.w a0, ft0 ; RV64IFD-NEXT: fmv.x.w a0, ft0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV64IBT-LABEL: select_const_fp:
; RV64IBT: # %bb.0:
; RV64IBT-NEXT: mv a1, a0
; RV64IBT-NEXT: lui a0, 263168
; RV64IBT-NEXT: bnez a1, .LBB4_2
; RV64IBT-NEXT: # %bb.1:
; RV64IBT-NEXT: lui a0, 264192
; RV64IBT-NEXT: .LBB4_2:
; RV64IBT-NEXT: ret
;
; RV64IFDBT-LABEL: select_const_fp:
; RV64IFDBT: # %bb.0:
; RV64IFDBT-NEXT: bnez a0, .LBB4_2
; RV64IFDBT-NEXT: # %bb.1:
; RV64IFDBT-NEXT: lui a0, %hi(.LCPI4_0)
; RV64IFDBT-NEXT: flw ft0, %lo(.LCPI4_0)(a0)
; RV64IFDBT-NEXT: fmv.x.w a0, ft0
; RV64IFDBT-NEXT: ret
; RV64IFDBT-NEXT: .LBB4_2:
; RV64IFDBT-NEXT: lui a0, %hi(.LCPI4_1)
; RV64IFDBT-NEXT: flw ft0, %lo(.LCPI4_1)(a0)
; RV64IFDBT-NEXT: fmv.x.w a0, ft0
; RV64IFDBT-NEXT: ret
%1 = select i1 %a, float 3.0, float 4.0 %1 = select i1 %a, float 3.0, float 4.0
ret float %1 ret float %1
} }

llvm/test/CodeGen/RISCV/select-optimize-multiple.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I ; RUN: | FileCheck %s -check-prefix=RV32I
; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zbt -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32IBT
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I ; RUN: | FileCheck %s -check-prefix=RV64I
; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zbt -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64IBT
; Selects of wide values are split into two selects, which can easily cause ; Selects of wide values are split into two selects, which can easily cause
; unnecessary control flow. Here we check some cases where we can currently ; unnecessary control flow. Here we check some cases where we can currently
; emit a sequence of selects with shared control flow. ; emit a sequence of selects with shared control flow.
define i64 @cmovcc64(i32 signext %a, i64 %b, i64 %c) nounwind { define i64 @cmovcc64(i32 signext %a, i64 %b, i64 %c) nounwind {
; RV32I-LABEL: cmovcc64: ; RV32I-LABEL: cmovcc64:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
; RV32I-NEXT: addi a5, zero, 123 ; RV32I-NEXT: addi a5, zero, 123
; RV32I-NEXT: beq a0, a5, .LBB0_2 ; RV32I-NEXT: beq a0, a5, .LBB0_2
; RV32I-NEXT: # %bb.1: # %entry ; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: mv a1, a3 ; RV32I-NEXT: mv a1, a3
; RV32I-NEXT: mv a2, a4 ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: .LBB0_2: # %entry ; RV32I-NEXT: .LBB0_2: # %entry
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: mv a1, a2 ; RV32I-NEXT: mv a1, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IBT-LABEL: cmovcc64:
; RV32IBT: # %bb.0: # %entry
; RV32IBT-NEXT: addi a5, zero, 123
; RV32IBT-NEXT: beq a0, a5, .LBB0_2
; RV32IBT-NEXT: # %bb.1: # %entry
; RV32IBT-NEXT: mv a1, a3
; RV32IBT-NEXT: mv a2, a4
; RV32IBT-NEXT: .LBB0_2: # %entry
; RV32IBT-NEXT: mv a0, a1
; RV32IBT-NEXT: mv a1, a2
; RV32IBT-NEXT: ret
;
; RV64I-LABEL: cmovcc64: ; RV64I-LABEL: cmovcc64:
; RV64I: # %bb.0: # %entry ; RV64I: # %bb.0: # %entry
; RV64I-NEXT: addi a3, zero, 123 ; RV64I-NEXT: addi a3, zero, 123
; RV64I-NEXT: beq a0, a3, .LBB0_2 ; RV64I-NEXT: beq a0, a3, .LBB0_2
; RV64I-NEXT: # %bb.1: # %entry ; RV64I-NEXT: # %bb.1: # %entry
; RV64I-NEXT: mv a1, a2 ; RV64I-NEXT: mv a1, a2
; RV64I-NEXT: .LBB0_2: # %entry ; RV64I-NEXT: .LBB0_2: # %entry
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV64IBT-LABEL: cmovcc64:
; RV64IBT: # %bb.0: # %entry
; RV64IBT-NEXT: addi a3, zero, 123
; RV64IBT-NEXT: beq a0, a3, .LBB0_2
; RV64IBT-NEXT: # %bb.1: # %entry
; RV64IBT-NEXT: mv a1, a2
; RV64IBT-NEXT: .LBB0_2: # %entry
; RV64IBT-NEXT: mv a0, a1
; RV64IBT-NEXT: ret
entry: entry:
%cmp = icmp eq i32 %a, 123 %cmp = icmp eq i32 %a, 123
%cond = select i1 %cmp, i64 %b, i64 %c %cond = select i1 %cmp, i64 %b, i64 %c
ret i64 %cond ret i64 %cond
} }
define i128 @cmovcc128(i64 signext %a, i128 %b, i128 %c) nounwind { define i128 @cmovcc128(i64 signext %a, i128 %b, i128 %c) nounwind {
; RV32I-LABEL: cmovcc128: ; RV32I-LABEL: cmovcc128:
Show All 30 Lines
; RV32I-NEXT: .LBB1_10: # %entry ; RV32I-NEXT: .LBB1_10: # %entry
; RV32I-NEXT: lw a1, 0(a1) ; RV32I-NEXT: lw a1, 0(a1)
; RV32I-NEXT: sw a1, 12(a0) ; RV32I-NEXT: sw a1, 12(a0)
; RV32I-NEXT: sw a2, 8(a0) ; RV32I-NEXT: sw a2, 8(a0)
; RV32I-NEXT: sw a7, 4(a0) ; RV32I-NEXT: sw a7, 4(a0)
; RV32I-NEXT: sw a6, 0(a0) ; RV32I-NEXT: sw a6, 0(a0)
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IBT-LABEL: cmovcc128:
; RV32IBT: # %bb.0: # %entry
; RV32IBT-NEXT: addi a6, a3, 12
; RV32IBT-NEXT: addi a7, a4, 12
; RV32IBT-NEXT: addi t0, a3, 8
; RV32IBT-NEXT: addi t1, a4, 8
; RV32IBT-NEXT: addi t2, a3, 4
; RV32IBT-NEXT: addi a5, a4, 4
; RV32IBT-NEXT: xori a1, a1, 123
; RV32IBT-NEXT: or a1, a1, a2
; RV32IBT-NEXT: cmov a2, a1, a4, a3
; RV32IBT-NEXT: cmov a3, a1, a5, t2
; RV32IBT-NEXT: cmov a4, a1, t1, t0
; RV32IBT-NEXT: cmov a1, a1, a7, a6
; RV32IBT-NEXT: lw a1, 0(a1)
; RV32IBT-NEXT: lw a4, 0(a4)
; RV32IBT-NEXT: lw a3, 0(a3)
; RV32IBT-NEXT: lw a2, 0(a2)
; RV32IBT-NEXT: sw a1, 12(a0)
; RV32IBT-NEXT: sw a4, 8(a0)
; RV32IBT-NEXT: sw a3, 4(a0)
; RV32IBT-NEXT: sw a2, 0(a0)
; RV32IBT-NEXT: ret
;
; RV64I-LABEL: cmovcc128: ; RV64I-LABEL: cmovcc128:
; RV64I: # %bb.0: # %entry ; RV64I: # %bb.0: # %entry
; RV64I-NEXT: addi a5, zero, 123 ; RV64I-NEXT: addi a5, zero, 123
; RV64I-NEXT: beq a0, a5, .LBB1_2 ; RV64I-NEXT: beq a0, a5, .LBB1_2
; RV64I-NEXT: # %bb.1: # %entry ; RV64I-NEXT: # %bb.1: # %entry
; RV64I-NEXT: mv a1, a3 ; RV64I-NEXT: mv a1, a3
; RV64I-NEXT: mv a2, a4 ; RV64I-NEXT: mv a2, a4
; RV64I-NEXT: .LBB1_2: # %entry ; RV64I-NEXT: .LBB1_2: # %entry
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: mv a1, a2 ; RV64I-NEXT: mv a1, a2
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV64IBT-LABEL: cmovcc128:
; RV64IBT: # %bb.0: # %entry
; RV64IBT-NEXT: addi a5, zero, 123
; RV64IBT-NEXT: beq a0, a5, .LBB1_2
; RV64IBT-NEXT: # %bb.1: # %entry
; RV64IBT-NEXT: mv a1, a3
; RV64IBT-NEXT: mv a2, a4
; RV64IBT-NEXT: .LBB1_2: # %entry
; RV64IBT-NEXT: mv a0, a1
; RV64IBT-NEXT: mv a1, a2
; RV64IBT-NEXT: ret
entry: entry:
%cmp = icmp eq i64 %a, 123 %cmp = icmp eq i64 %a, 123
%cond = select i1 %cmp, i128 %b, i128 %c %cond = select i1 %cmp, i128 %b, i128 %c
ret i128 %cond ret i128 %cond
} }
define i64 @cmov64(i1 %a, i64 %b, i64 %c) nounwind { define i64 @cmov64(i1 %a, i64 %b, i64 %c) nounwind {
; RV32I-LABEL: cmov64: ; RV32I-LABEL: cmov64:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
; RV32I-NEXT: andi a5, a0, 1 ; RV32I-NEXT: andi a5, a0, 1
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: bnez a5, .LBB2_2 ; RV32I-NEXT: bnez a5, .LBB2_2
; RV32I-NEXT: # %bb.1: # %entry ; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: mv a2, a4 ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: .LBB2_2: # %entry ; RV32I-NEXT: .LBB2_2: # %entry
; RV32I-NEXT: mv a1, a2 ; RV32I-NEXT: mv a1, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IBT-LABEL: cmov64:
; RV32IBT: # %bb.0: # %entry
; RV32IBT-NEXT: andi a5, a0, 1
; RV32IBT-NEXT: mv a0, a1
; RV32IBT-NEXT: bnez a5, .LBB2_2
; RV32IBT-NEXT: # %bb.1: # %entry
; RV32IBT-NEXT: mv a0, a3
; RV32IBT-NEXT: mv a2, a4
; RV32IBT-NEXT: .LBB2_2: # %entry
; RV32IBT-NEXT: mv a1, a2
; RV32IBT-NEXT: ret
;
; RV64I-LABEL: cmov64: ; RV64I-LABEL: cmov64:
; RV64I: # %bb.0: # %entry ; RV64I: # %bb.0: # %entry
; RV64I-NEXT: andi a3, a0, 1 ; RV64I-NEXT: andi a3, a0, 1
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: bnez a3, .LBB2_2 ; RV64I-NEXT: bnez a3, .LBB2_2
; RV64I-NEXT: # %bb.1: # %entry ; RV64I-NEXT: # %bb.1: # %entry
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: .LBB2_2: # %entry ; RV64I-NEXT: .LBB2_2: # %entry
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV64IBT-LABEL: cmov64:
; RV64IBT: # %bb.0: # %entry
; RV64IBT-NEXT: andi a3, a0, 1
; RV64IBT-NEXT: mv a0, a1
; RV64IBT-NEXT: bnez a3, .LBB2_2
; RV64IBT-NEXT: # %bb.1: # %entry
; RV64IBT-NEXT: mv a0, a2
; RV64IBT-NEXT: .LBB2_2: # %entry
; RV64IBT-NEXT: ret
entry: entry:
%cond = select i1 %a, i64 %b, i64 %c %cond = select i1 %a, i64 %b, i64 %c
ret i64 %cond ret i64 %cond
} }
define i128 @cmov128(i1 %a, i128 %b, i128 %c) nounwind { define i128 @cmov128(i1 %a, i128 %b, i128 %c) nounwind {
; RV32I-LABEL: cmov128: ; RV32I-LABEL: cmov128:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
Show All 28 Lines
; RV32I-NEXT: .LBB3_10: # %entry ; RV32I-NEXT: .LBB3_10: # %entry
; RV32I-NEXT: lw a1, 0(a1) ; RV32I-NEXT: lw a1, 0(a1)
; RV32I-NEXT: sw a1, 12(a0) ; RV32I-NEXT: sw a1, 12(a0)
; RV32I-NEXT: sw a4, 8(a0) ; RV32I-NEXT: sw a4, 8(a0)
; RV32I-NEXT: sw a7, 4(a0) ; RV32I-NEXT: sw a7, 4(a0)
; RV32I-NEXT: sw a6, 0(a0) ; RV32I-NEXT: sw a6, 0(a0)
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IBT-LABEL: cmov128:
; RV32IBT: # %bb.0: # %entry
; RV32IBT-NEXT: andi a1, a1, 1
; RV32IBT-NEXT: mv a4, a2
; RV32IBT-NEXT: bnez a1, .LBB3_2
; RV32IBT-NEXT: # %bb.1: # %entry
; RV32IBT-NEXT: mv a4, a3
; RV32IBT-NEXT: .LBB3_2: # %entry
; RV32IBT-NEXT: bnez a1, .LBB3_5
; RV32IBT-NEXT: # %bb.3: # %entry
; RV32IBT-NEXT: addi a7, a3, 4
; RV32IBT-NEXT: beqz a1, .LBB3_6
; RV32IBT-NEXT: .LBB3_4:
; RV32IBT-NEXT: addi a5, a2, 8
; RV32IBT-NEXT: j .LBB3_7
; RV32IBT-NEXT: .LBB3_5:
; RV32IBT-NEXT: addi a7, a2, 4
; RV32IBT-NEXT: bnez a1, .LBB3_4
; RV32IBT-NEXT: .LBB3_6: # %entry
; RV32IBT-NEXT: addi a5, a3, 8
; RV32IBT-NEXT: .LBB3_7: # %entry
; RV32IBT-NEXT: lw a6, 0(a4)
; RV32IBT-NEXT: lw a7, 0(a7)
; RV32IBT-NEXT: lw a4, 0(a5)
; RV32IBT-NEXT: bnez a1, .LBB3_9
; RV32IBT-NEXT: # %bb.8: # %entry
; RV32IBT-NEXT: addi a1, a3, 12
; RV32IBT-NEXT: j .LBB3_10
; RV32IBT-NEXT: .LBB3_9:
; RV32IBT-NEXT: addi a1, a2, 12
; RV32IBT-NEXT: .LBB3_10: # %entry
; RV32IBT-NEXT: lw a1, 0(a1)
; RV32IBT-NEXT: sw a1, 12(a0)
; RV32IBT-NEXT: sw a4, 8(a0)
; RV32IBT-NEXT: sw a7, 4(a0)
; RV32IBT-NEXT: sw a6, 0(a0)
; RV32IBT-NEXT: ret
;
; RV64I-LABEL: cmov128: ; RV64I-LABEL: cmov128:
; RV64I: # %bb.0: # %entry ; RV64I: # %bb.0: # %entry
; RV64I-NEXT: andi a5, a0, 1 ; RV64I-NEXT: andi a5, a0, 1
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: bnez a5, .LBB3_2 ; RV64I-NEXT: bnez a5, .LBB3_2
; RV64I-NEXT: # %bb.1: # %entry ; RV64I-NEXT: # %bb.1: # %entry
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: mv a2, a4 ; RV64I-NEXT: mv a2, a4
; RV64I-NEXT: .LBB3_2: # %entry ; RV64I-NEXT: .LBB3_2: # %entry
; RV64I-NEXT: mv a1, a2 ; RV64I-NEXT: mv a1, a2
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV64IBT-LABEL: cmov128:
; RV64IBT: # %bb.0: # %entry
; RV64IBT-NEXT: andi a5, a0, 1
; RV64IBT-NEXT: mv a0, a1
; RV64IBT-NEXT: bnez a5, .LBB3_2
; RV64IBT-NEXT: # %bb.1: # %entry
; RV64IBT-NEXT: mv a0, a3
; RV64IBT-NEXT: mv a2, a4
; RV64IBT-NEXT: .LBB3_2: # %entry
; RV64IBT-NEXT: mv a1, a2
; RV64IBT-NEXT: ret
entry: entry:
%cond = select i1 %a, i128 %b, i128 %c %cond = select i1 %a, i128 %b, i128 %c
ret i128 %cond ret i128 %cond
} }
define float @cmovfloat(i1 %a, float %b, float %c, float %d, float %e) nounwind { define float @cmovfloat(i1 %a, float %b, float %c, float %d, float %e) nounwind {
; RV32I-LABEL: cmovfloat: ; RV32I-LABEL: cmovfloat:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
; RV32I-NEXT: andi a0, a0, 1 ; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: bnez a0, .LBB4_2 ; RV32I-NEXT: bnez a0, .LBB4_2
; RV32I-NEXT: # %bb.1: # %entry ; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: fmv.w.x ft0, a4 ; RV32I-NEXT: fmv.w.x ft0, a4
; RV32I-NEXT: fmv.w.x ft1, a2 ; RV32I-NEXT: fmv.w.x ft1, a2
; RV32I-NEXT: j .LBB4_3 ; RV32I-NEXT: j .LBB4_3
; RV32I-NEXT: .LBB4_2: ; RV32I-NEXT: .LBB4_2:
; RV32I-NEXT: fmv.w.x ft0, a3 ; RV32I-NEXT: fmv.w.x ft0, a3
; RV32I-NEXT: fmv.w.x ft1, a1 ; RV32I-NEXT: fmv.w.x ft1, a1
; RV32I-NEXT: .LBB4_3: # %entry ; RV32I-NEXT: .LBB4_3: # %entry
; RV32I-NEXT: fadd.s ft0, ft1, ft0 ; RV32I-NEXT: fadd.s ft0, ft1, ft0
; RV32I-NEXT: fmv.x.w a0, ft0 ; RV32I-NEXT: fmv.x.w a0, ft0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IBT-LABEL: cmovfloat:
; RV32IBT: # %bb.0: # %entry
; RV32IBT-NEXT: andi a0, a0, 1
; RV32IBT-NEXT: bnez a0, .LBB4_2
; RV32IBT-NEXT: # %bb.1: # %entry
; RV32IBT-NEXT: fmv.w.x ft0, a4
; RV32IBT-NEXT: fmv.w.x ft1, a2
; RV32IBT-NEXT: j .LBB4_3
; RV32IBT-NEXT: .LBB4_2:
; RV32IBT-NEXT: fmv.w.x ft0, a3
; RV32IBT-NEXT: fmv.w.x ft1, a1
; RV32IBT-NEXT: .LBB4_3: # %entry
; RV32IBT-NEXT: fadd.s ft0, ft1, ft0
; RV32IBT-NEXT: fmv.x.w a0, ft0
; RV32IBT-NEXT: ret
;
; RV64I-LABEL: cmovfloat: ; RV64I-LABEL: cmovfloat:
; RV64I: # %bb.0: # %entry ; RV64I: # %bb.0: # %entry
; RV64I-NEXT: andi a0, a0, 1 ; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: bnez a0, .LBB4_2 ; RV64I-NEXT: bnez a0, .LBB4_2
; RV64I-NEXT: # %bb.1: # %entry ; RV64I-NEXT: # %bb.1: # %entry
; RV64I-NEXT: fmv.w.x ft0, a4 ; RV64I-NEXT: fmv.w.x ft0, a4
; RV64I-NEXT: fmv.w.x ft1, a2 ; RV64I-NEXT: fmv.w.x ft1, a2
; RV64I-NEXT: j .LBB4_3 ; RV64I-NEXT: j .LBB4_3
; RV64I-NEXT: .LBB4_2: ; RV64I-NEXT: .LBB4_2:
; RV64I-NEXT: fmv.w.x ft0, a3 ; RV64I-NEXT: fmv.w.x ft0, a3
; RV64I-NEXT: fmv.w.x ft1, a1 ; RV64I-NEXT: fmv.w.x ft1, a1
; RV64I-NEXT: .LBB4_3: # %entry ; RV64I-NEXT: .LBB4_3: # %entry
; RV64I-NEXT: fadd.s ft0, ft1, ft0 ; RV64I-NEXT: fadd.s ft0, ft1, ft0
; RV64I-NEXT: fmv.x.w a0, ft0 ; RV64I-NEXT: fmv.x.w a0, ft0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV64IBT-LABEL: cmovfloat:
; RV64IBT: # %bb.0: # %entry
; RV64IBT-NEXT: andi a0, a0, 1
; RV64IBT-NEXT: bnez a0, .LBB4_2
; RV64IBT-NEXT: # %bb.1: # %entry
; RV64IBT-NEXT: fmv.w.x ft0, a4
; RV64IBT-NEXT: fmv.w.x ft1, a2
; RV64IBT-NEXT: j .LBB4_3
; RV64IBT-NEXT: .LBB4_2:
; RV64IBT-NEXT: fmv.w.x ft0, a3
; RV64IBT-NEXT: fmv.w.x ft1, a1
; RV64IBT-NEXT: .LBB4_3: # %entry
; RV64IBT-NEXT: fadd.s ft0, ft1, ft0
; RV64IBT-NEXT: fmv.x.w a0, ft0
; RV64IBT-NEXT: ret
entry: entry:
%cond1 = select i1 %a, float %b, float %c %cond1 = select i1 %a, float %b, float %c
%cond2 = select i1 %a, float %d, float %e %cond2 = select i1 %a, float %d, float %e
%ret = fadd float %cond1, %cond2 %ret = fadd float %cond1, %cond2
ret float %ret ret float %ret
} }
define double @cmovdouble(i1 %a, double %b, double %c) nounwind { define double @cmovdouble(i1 %a, double %b, double %c) nounwind {
Show All 11 Lines
; RV32I-NEXT: fld ft0, 8(sp) ; RV32I-NEXT: fld ft0, 8(sp)
; RV32I-NEXT: .LBB5_2: # %entry ; RV32I-NEXT: .LBB5_2: # %entry
; RV32I-NEXT: fsd ft0, 8(sp) ; RV32I-NEXT: fsd ft0, 8(sp)
; RV32I-NEXT: lw a0, 8(sp) ; RV32I-NEXT: lw a0, 8(sp)
; RV32I-NEXT: lw a1, 12(sp) ; RV32I-NEXT: lw a1, 12(sp)
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IBT-LABEL: cmovdouble:
; RV32IBT: # %bb.0: # %entry
; RV32IBT-NEXT: addi sp, sp, -16
; RV32IBT-NEXT: sw a3, 8(sp)
; RV32IBT-NEXT: sw a4, 12(sp)
; RV32IBT-NEXT: fld ft0, 8(sp)
; RV32IBT-NEXT: sw a1, 8(sp)
; RV32IBT-NEXT: andi a0, a0, 1
; RV32IBT-NEXT: sw a2, 12(sp)
; RV32IBT-NEXT: beqz a0, .LBB5_2
; RV32IBT-NEXT: # %bb.1:
; RV32IBT-NEXT: fld ft0, 8(sp)
; RV32IBT-NEXT: .LBB5_2: # %entry
; RV32IBT-NEXT: fsd ft0, 8(sp)
; RV32IBT-NEXT: lw a0, 8(sp)
; RV32IBT-NEXT: lw a1, 12(sp)
; RV32IBT-NEXT: addi sp, sp, 16
; RV32IBT-NEXT: ret
;
; RV64I-LABEL: cmovdouble: ; RV64I-LABEL: cmovdouble:
; RV64I: # %bb.0: # %entry ; RV64I: # %bb.0: # %entry
; RV64I-NEXT: andi a0, a0, 1 ; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: bnez a0, .LBB5_2 ; RV64I-NEXT: bnez a0, .LBB5_2
; RV64I-NEXT: # %bb.1: # %entry ; RV64I-NEXT: # %bb.1: # %entry
; RV64I-NEXT: fmv.d.x ft0, a2 ; RV64I-NEXT: fmv.d.x ft0, a2
; RV64I-NEXT: fmv.x.d a0, ft0 ; RV64I-NEXT: fmv.x.d a0, ft0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; RV64I-NEXT: .LBB5_2: ; RV64I-NEXT: .LBB5_2:
; RV64I-NEXT: fmv.d.x ft0, a1 ; RV64I-NEXT: fmv.d.x ft0, a1
; RV64I-NEXT: fmv.x.d a0, ft0 ; RV64I-NEXT: fmv.x.d a0, ft0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV64IBT-LABEL: cmovdouble:
; RV64IBT: # %bb.0: # %entry
; RV64IBT-NEXT: andi a0, a0, 1
; RV64IBT-NEXT: bnez a0, .LBB5_2
; RV64IBT-NEXT: # %bb.1: # %entry
; RV64IBT-NEXT: fmv.d.x ft0, a2
; RV64IBT-NEXT: fmv.x.d a0, ft0
; RV64IBT-NEXT: ret
; RV64IBT-NEXT: .LBB5_2:
; RV64IBT-NEXT: fmv.d.x ft0, a1
; RV64IBT-NEXT: fmv.x.d a0, ft0
; RV64IBT-NEXT: ret
entry: entry:
%cond = select i1 %a, double %b, double %c %cond = select i1 %a, double %b, double %c
ret double %cond ret double %cond
} }
; Check that selects with dependencies on previous ones aren't incorrectly ; Check that selects with dependencies on previous ones aren't incorrectly
; optimized. ; optimized.
Show All 12 Lines
; RV32I-NEXT: mv a1, a2 ; RV32I-NEXT: mv a1, a2
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: beq a0, a4, .LBB6_2 ; RV32I-NEXT: beq a0, a4, .LBB6_2
; RV32I-NEXT: .LBB6_4: # %entry ; RV32I-NEXT: .LBB6_4: # %entry
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: add a0, a1, a2 ; RV32I-NEXT: add a0, a1, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IBT-LABEL: cmovccdep:
; RV32IBT: # %bb.0: # %entry
; RV32IBT-NEXT: addi a4, zero, 123
; RV32IBT-NEXT: bne a0, a4, .LBB6_3
; RV32IBT-NEXT: # %bb.1: # %entry
; RV32IBT-NEXT: mv a2, a1
; RV32IBT-NEXT: bne a0, a4, .LBB6_4
; RV32IBT-NEXT: .LBB6_2: # %entry
; RV32IBT-NEXT: add a0, a1, a2
; RV32IBT-NEXT: ret
; RV32IBT-NEXT: .LBB6_3: # %entry
; RV32IBT-NEXT: mv a1, a2
; RV32IBT-NEXT: mv a2, a1
; RV32IBT-NEXT: beq a0, a4, .LBB6_2
; RV32IBT-NEXT: .LBB6_4: # %entry
; RV32IBT-NEXT: mv a2, a3
; RV32IBT-NEXT: add a0, a1, a2
; RV32IBT-NEXT: ret
;
; RV64I-LABEL: cmovccdep: ; RV64I-LABEL: cmovccdep:
; RV64I: # %bb.0: # %entry ; RV64I: # %bb.0: # %entry
; RV64I-NEXT: addi a4, zero, 123 ; RV64I-NEXT: addi a4, zero, 123
; RV64I-NEXT: bne a0, a4, .LBB6_3 ; RV64I-NEXT: bne a0, a4, .LBB6_3
; RV64I-NEXT: # %bb.1: # %entry ; RV64I-NEXT: # %bb.1: # %entry
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bne a0, a4, .LBB6_4 ; RV64I-NEXT: bne a0, a4, .LBB6_4
; RV64I-NEXT: .LBB6_2: # %entry ; RV64I-NEXT: .LBB6_2: # %entry
; RV64I-NEXT: addw a0, a1, a2 ; RV64I-NEXT: addw a0, a1, a2
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; RV64I-NEXT: .LBB6_3: # %entry ; RV64I-NEXT: .LBB6_3: # %entry
; RV64I-NEXT: mv a1, a2 ; RV64I-NEXT: mv a1, a2
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: beq a0, a4, .LBB6_2 ; RV64I-NEXT: beq a0, a4, .LBB6_2
; RV64I-NEXT: .LBB6_4: # %entry ; RV64I-NEXT: .LBB6_4: # %entry
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: addw a0, a1, a2 ; RV64I-NEXT: addw a0, a1, a2
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV64IBT-LABEL: cmovccdep:
; RV64IBT: # %bb.0: # %entry
; RV64IBT-NEXT: addi a4, zero, 123
; RV64IBT-NEXT: bne a0, a4, .LBB6_3
; RV64IBT-NEXT: # %bb.1: # %entry
; RV64IBT-NEXT: mv a2, a1
; RV64IBT-NEXT: bne a0, a4, .LBB6_4
; RV64IBT-NEXT: .LBB6_2: # %entry
; RV64IBT-NEXT: addw a0, a1, a2
; RV64IBT-NEXT: ret
; RV64IBT-NEXT: .LBB6_3: # %entry
; RV64IBT-NEXT: mv a1, a2
; RV64IBT-NEXT: mv a2, a1
; RV64IBT-NEXT: beq a0, a4, .LBB6_2
; RV64IBT-NEXT: .LBB6_4: # %entry
; RV64IBT-NEXT: mv a2, a3
; RV64IBT-NEXT: addw a0, a1, a2
; RV64IBT-NEXT: ret
entry: entry:
%cmp = icmp eq i32 %a, 123 %cmp = icmp eq i32 %a, 123
%cond1 = select i1 %cmp, i32 %b, i32 %c %cond1 = select i1 %cmp, i32 %b, i32 %c
%cond2 = select i1 %cmp, i32 %cond1, i32 %d %cond2 = select i1 %cmp, i32 %cond1, i32 %d
%ret = add i32 %cond1, %cond2 %ret = add i32 %cond1, %cond2
ret i32 %ret ret i32 %ret
} }
Show All 13 Lines
; RV32I-NEXT: .LBB7_3: # %entry ; RV32I-NEXT: .LBB7_3: # %entry
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bnez a1, .LBB7_2 ; RV32I-NEXT: bnez a1, .LBB7_2
; RV32I-NEXT: .LBB7_4: # %entry ; RV32I-NEXT: .LBB7_4: # %entry
; RV32I-NEXT: mv a4, a5 ; RV32I-NEXT: mv a4, a5
; RV32I-NEXT: add a0, a2, a4 ; RV32I-NEXT: add a0, a2, a4
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IBT-LABEL: cmovdiffcc:
; RV32IBT: # %bb.0: # %entry
; RV32IBT-NEXT: andi a0, a0, 1
; RV32IBT-NEXT: andi a1, a1, 1
; RV32IBT-NEXT: beqz a0, .LBB7_3
; RV32IBT-NEXT: # %bb.1: # %entry
; RV32IBT-NEXT: beqz a1, .LBB7_4
; RV32IBT-NEXT: .LBB7_2: # %entry
; RV32IBT-NEXT: add a0, a2, a4
; RV32IBT-NEXT: ret
; RV32IBT-NEXT: .LBB7_3: # %entry
; RV32IBT-NEXT: mv a2, a3
; RV32IBT-NEXT: bnez a1, .LBB7_2
; RV32IBT-NEXT: .LBB7_4: # %entry
; RV32IBT-NEXT: mv a4, a5
; RV32IBT-NEXT: add a0, a2, a4
; RV32IBT-NEXT: ret
;
; RV64I-LABEL: cmovdiffcc: ; RV64I-LABEL: cmovdiffcc:
; RV64I: # %bb.0: # %entry ; RV64I: # %bb.0: # %entry
; RV64I-NEXT: andi a0, a0, 1 ; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: andi a1, a1, 1 ; RV64I-NEXT: andi a1, a1, 1
; RV64I-NEXT: beqz a0, .LBB7_3 ; RV64I-NEXT: beqz a0, .LBB7_3
; RV64I-NEXT: # %bb.1: # %entry ; RV64I-NEXT: # %bb.1: # %entry
; RV64I-NEXT: beqz a1, .LBB7_4 ; RV64I-NEXT: beqz a1, .LBB7_4
; RV64I-NEXT: .LBB7_2: # %entry ; RV64I-NEXT: .LBB7_2: # %entry
; RV64I-NEXT: addw a0, a2, a4 ; RV64I-NEXT: addw a0, a2, a4
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; RV64I-NEXT: .LBB7_3: # %entry ; RV64I-NEXT: .LBB7_3: # %entry
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bnez a1, .LBB7_2 ; RV64I-NEXT: bnez a1, .LBB7_2
; RV64I-NEXT: .LBB7_4: # %entry ; RV64I-NEXT: .LBB7_4: # %entry
; RV64I-NEXT: mv a4, a5 ; RV64I-NEXT: mv a4, a5
; RV64I-NEXT: addw a0, a2, a4 ; RV64I-NEXT: addw a0, a2, a4
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV64IBT-LABEL: cmovdiffcc:
; RV64IBT: # %bb.0: # %entry
; RV64IBT-NEXT: andi a0, a0, 1
; RV64IBT-NEXT: andi a1, a1, 1
; RV64IBT-NEXT: beqz a0, .LBB7_3
; RV64IBT-NEXT: # %bb.1: # %entry
; RV64IBT-NEXT: beqz a1, .LBB7_4
; RV64IBT-NEXT: .LBB7_2: # %entry
; RV64IBT-NEXT: addw a0, a2, a4
; RV64IBT-NEXT: ret
; RV64IBT-NEXT: .LBB7_3: # %entry
; RV64IBT-NEXT: mv a2, a3
; RV64IBT-NEXT: bnez a1, .LBB7_2
; RV64IBT-NEXT: .LBB7_4: # %entry
; RV64IBT-NEXT: mv a4, a5
; RV64IBT-NEXT: addw a0, a2, a4
; RV64IBT-NEXT: ret
entry: entry:
%cond1 = select i1 %a, i32 %c, i32 %d %cond1 = select i1 %a, i32 %c, i32 %d
%cond2 = select i1 %b, i32 %e, i32 %f %cond2 = select i1 %b, i32 %e, i32 %f
%ret = add i32 %cond1, %cond2 %ret = add i32 %cond1, %cond2
ret i32 %ret ret i32 %ret
} }

llvm/test/CodeGen/RISCV/select-optimize-multiple.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=finalize-isel -simplify-mir -o - %s \ # RUN: llc -mtriple=riscv32 -run-pass=finalize-isel -simplify-mir -o - %s \
# RUN: | FileCheck -check-prefix=RV32I %s # RUN: | FileCheck -check-prefix=RV32I %s
# RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -run-pass=finalize-isel -simplify-mir -o - %s \
# RUN: | FileCheck -check-prefix=RV32IBT %s
# RUN: llc -mtriple=riscv64 -run-pass=finalize-isel -simplify-mir -o - %s \ # RUN: llc -mtriple=riscv64 -run-pass=finalize-isel -simplify-mir -o - %s \
# RUN: | FileCheck -check-prefix=RV64I %s # RUN: | FileCheck -check-prefix=RV64I %s
# RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -run-pass=finalize-isel -simplify-mir -o - %s \
# RUN: | FileCheck -check-prefix=RV64IBT %s
# Provide dummy definitions of functions and just enough metadata to create a # Provide dummy definitions of functions and just enough metadata to create a
# DBG_VALUE. # DBG_VALUE.
--- | --- |
define void @cmov_interleaved_bad() { define void @cmov_interleaved_bad() {
ret void ret void
} }
define void @cmov_interleaved_debug_value() { define void @cmov_interleaved_debug_value() {
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines bb.0:
; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1 ; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
; RV32I: BNE [[ANDI]], [[COPY4]], %bb.4 ; RV32I: BNE [[ANDI]], [[COPY4]], %bb.4
; RV32I: .3: ; RV32I: .3:
; RV32I: .4: ; RV32I: .4:
; RV32I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3 ; RV32I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3
; RV32I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]] ; RV32I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
; RV32I: $x10 = COPY [[ADD]] ; RV32I: $x10 = COPY [[ADD]]
; RV32I: PseudoRET implicit $x10 ; RV32I: PseudoRET implicit $x10
; RV32IBT-LABEL: name: cmov_interleaved_bad
; RV32IBT: successors: %bb.1, %bb.2
; RV32IBT: liveins: $x10, $x11, $x12, $x13
; RV32IBT: [[COPY:%[0-9]+]]:gpr = COPY $x13
; RV32IBT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
; RV32IBT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
; RV32IBT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
; RV32IBT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
; RV32IBT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
; RV32IBT: BNE [[ANDI]], [[COPY4]], %bb.2
; RV32IBT: .1:
; RV32IBT: .2:
; RV32IBT: successors: %bb.3, %bb.4
; RV32IBT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
; RV32IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
; RV32IBT: BNE [[ANDI]], [[COPY4]], %bb.4
; RV32IBT: .3:
; RV32IBT: .4:
; RV32IBT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3
; RV32IBT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
; RV32IBT: $x10 = COPY [[ADD]]
; RV32IBT: PseudoRET implicit $x10
; RV64I-LABEL: name: cmov_interleaved_bad ; RV64I-LABEL: name: cmov_interleaved_bad
; RV64I: successors: %bb.1, %bb.2 ; RV64I: successors: %bb.1, %bb.2
; RV64I: liveins: $x10, $x11, $x12, $x13 ; RV64I: liveins: $x10, $x11, $x12, $x13
; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x13 ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x13
; RV64I: [[COPY1:%[0-9]+]]:gpr = COPY $x12 ; RV64I: [[COPY1:%[0-9]+]]:gpr = COPY $x12
; RV64I: [[COPY2:%[0-9]+]]:gpr = COPY $x11 ; RV64I: [[COPY2:%[0-9]+]]:gpr = COPY $x11
; RV64I: [[COPY3:%[0-9]+]]:gpr = COPY $x10 ; RV64I: [[COPY3:%[0-9]+]]:gpr = COPY $x10
; RV64I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1 ; RV64I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
; RV64I: [[COPY4:%[0-9]+]]:gpr = COPY $x0 ; RV64I: [[COPY4:%[0-9]+]]:gpr = COPY $x0
; RV64I: BNE [[ANDI]], [[COPY4]], %bb.2 ; RV64I: BNE [[ANDI]], [[COPY4]], %bb.2
; RV64I: .1: ; RV64I: .1:
; RV64I: .2: ; RV64I: .2:
; RV64I: successors: %bb.3, %bb.4 ; RV64I: successors: %bb.3, %bb.4
; RV64I: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1 ; RV64I: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1 ; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
; RV64I: BNE [[ANDI]], [[COPY4]], %bb.4 ; RV64I: BNE [[ANDI]], [[COPY4]], %bb.4
; RV64I: .3: ; RV64I: .3:
; RV64I: .4: ; RV64I: .4:
; RV64I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3 ; RV64I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3
; RV64I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]] ; RV64I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
; RV64I: $x10 = COPY [[ADD]] ; RV64I: $x10 = COPY [[ADD]]
; RV64I: PseudoRET implicit $x10 ; RV64I: PseudoRET implicit $x10
; RV64IBT-LABEL: name: cmov_interleaved_bad
; RV64IBT: successors: %bb.1, %bb.2
; RV64IBT: liveins: $x10, $x11, $x12, $x13
; RV64IBT: [[COPY:%[0-9]+]]:gpr = COPY $x13
; RV64IBT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
; RV64IBT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
; RV64IBT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
; RV64IBT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
; RV64IBT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
; RV64IBT: BNE [[ANDI]], [[COPY4]], %bb.2
; RV64IBT: .1:
; RV64IBT: .2:
; RV64IBT: successors: %bb.3, %bb.4
; RV64IBT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
; RV64IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
; RV64IBT: BNE [[ANDI]], [[COPY4]], %bb.4
; RV64IBT: .3:
; RV64IBT: .4:
; RV64IBT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3
; RV64IBT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
; RV64IBT: $x10 = COPY [[ADD]]
; RV64IBT: PseudoRET implicit $x10
%3:gpr = COPY $x13 %3:gpr = COPY $x13
%2:gpr = COPY $x12 %2:gpr = COPY $x12
%1:gpr = COPY $x11 %1:gpr = COPY $x11
%0:gpr = COPY $x10 %0:gpr = COPY $x10
%5:gpr = ANDI %0, 1 %5:gpr = ANDI %0, 1
%6:gpr = COPY $x0 %6:gpr = COPY $x0
%7:gpr = Select_GPR_Using_CC_GPR %5, %6, 22, %1, %2 %7:gpr = Select_GPR_Using_CC_GPR %5, %6, 22, %1, %2
%8:gpr = ADDI %7, 1 %8:gpr = ADDI %7, 1
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines bb.0:
; RV32I: .2: ; RV32I: .2:
; RV32I: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1 ; RV32I: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
; RV32I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1 ; RV32I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
; RV32I: DBG_VALUE [[PHI]], $noreg ; RV32I: DBG_VALUE [[PHI]], $noreg
; RV32I: DBG_VALUE [[PHI1]], $noreg ; RV32I: DBG_VALUE [[PHI1]], $noreg
; RV32I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]] ; RV32I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
; RV32I: $x10 = COPY [[ADD]] ; RV32I: $x10 = COPY [[ADD]]
; RV32I: PseudoRET implicit $x10 ; RV32I: PseudoRET implicit $x10
; RV32IBT-LABEL: name: cmov_interleaved_debug_value
; RV32IBT: successors: %bb.1, %bb.2
; RV32IBT: liveins: $x10, $x11, $x12, $x13
; RV32IBT: [[COPY:%[0-9]+]]:gpr = COPY $x13
; RV32IBT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
; RV32IBT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
; RV32IBT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
; RV32IBT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
; RV32IBT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
; RV32IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
; RV32IBT: DBG_VALUE [[ADDI]], $noreg
; RV32IBT: BNE [[ANDI]], [[COPY4]], %bb.2
; RV32IBT: .1:
; RV32IBT: .2:
; RV32IBT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
; RV32IBT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
; RV32IBT: DBG_VALUE [[PHI]], $noreg
; RV32IBT: DBG_VALUE [[PHI1]], $noreg
; RV32IBT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
; RV32IBT: $x10 = COPY [[ADD]]
; RV32IBT: PseudoRET implicit $x10
; RV64I-LABEL: name: cmov_interleaved_debug_value ; RV64I-LABEL: name: cmov_interleaved_debug_value
; RV64I: successors: %bb.1, %bb.2 ; RV64I: successors: %bb.1, %bb.2
; RV64I: liveins: $x10, $x11, $x12, $x13 ; RV64I: liveins: $x10, $x11, $x12, $x13
; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x13 ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x13
; RV64I: [[COPY1:%[0-9]+]]:gpr = COPY $x12 ; RV64I: [[COPY1:%[0-9]+]]:gpr = COPY $x12
; RV64I: [[COPY2:%[0-9]+]]:gpr = COPY $x11 ; RV64I: [[COPY2:%[0-9]+]]:gpr = COPY $x11
; RV64I: [[COPY3:%[0-9]+]]:gpr = COPY $x10 ; RV64I: [[COPY3:%[0-9]+]]:gpr = COPY $x10
; RV64I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1 ; RV64I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
; RV64I: [[COPY4:%[0-9]+]]:gpr = COPY $x0 ; RV64I: [[COPY4:%[0-9]+]]:gpr = COPY $x0
; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1 ; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
; RV64I: DBG_VALUE [[ADDI]], $noreg ; RV64I: DBG_VALUE [[ADDI]], $noreg
; RV64I: BNE [[ANDI]], [[COPY4]], %bb.2 ; RV64I: BNE [[ANDI]], [[COPY4]], %bb.2
; RV64I: .1: ; RV64I: .1:
; RV64I: .2: ; RV64I: .2:
; RV64I: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1 ; RV64I: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
; RV64I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1 ; RV64I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
; RV64I: DBG_VALUE [[PHI]], $noreg ; RV64I: DBG_VALUE [[PHI]], $noreg
; RV64I: DBG_VALUE [[PHI1]], $noreg ; RV64I: DBG_VALUE [[PHI1]], $noreg
; RV64I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]] ; RV64I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
; RV64I: $x10 = COPY [[ADD]] ; RV64I: $x10 = COPY [[ADD]]
; RV64I: PseudoRET implicit $x10 ; RV64I: PseudoRET implicit $x10
; RV64IBT-LABEL: name: cmov_interleaved_debug_value
; RV64IBT: successors: %bb.1, %bb.2
; RV64IBT: liveins: $x10, $x11, $x12, $x13
; RV64IBT: [[COPY:%[0-9]+]]:gpr = COPY $x13
; RV64IBT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
; RV64IBT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
; RV64IBT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
; RV64IBT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
; RV64IBT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
; RV64IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
; RV64IBT: DBG_VALUE [[ADDI]], $noreg
; RV64IBT: BNE [[ANDI]], [[COPY4]], %bb.2
; RV64IBT: .1:
; RV64IBT: .2:
; RV64IBT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
; RV64IBT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
; RV64IBT: DBG_VALUE [[PHI]], $noreg
; RV64IBT: DBG_VALUE [[PHI1]], $noreg
; RV64IBT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
; RV64IBT: $x10 = COPY [[ADD]]
; RV64IBT: PseudoRET implicit $x10
%3:gpr = COPY $x13 %3:gpr = COPY $x13
%2:gpr = COPY $x12 %2:gpr = COPY $x12
%1:gpr = COPY $x11 %1:gpr = COPY $x11
%0:gpr = COPY $x10 %0:gpr = COPY $x10
%5:gpr = ANDI %0, 1 %5:gpr = ANDI %0, 1
%6:gpr = COPY $x0 %6:gpr = COPY $x0
%7:gpr = Select_GPR_Using_CC_GPR %5, %6, 22, %1, %2 %7:gpr = Select_GPR_Using_CC_GPR %5, %6, 22, %1, %2
DBG_VALUE %7, $noreg DBG_VALUE %7, $noreg
Show All 10 Lines

llvm/test/CodeGen/RISCV/select-or.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IBT %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IBT %s
;; There are a few different ways to lower (select (or A, B), X, Y). This test ;; There are a few different ways to lower (select (or A, B), X, Y). This test
;; ensures that we do so with as few branches as possible. ;; ensures that we do so with as few branches as possible.
define signext i32 @select_of_or(i1 zeroext %a, i1 zeroext %b, i32 signext %c, i32 signext %d) nounwind { define signext i32 @select_of_or(i1 zeroext %a, i1 zeroext %b, i32 signext %c, i32 signext %d) nounwind {
; RV32I-LABEL: select_of_or: ; RV32I-LABEL: select_of_or:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: or a1, a0, a1 ; RV32I-NEXT: or a1, a0, a1
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: bnez a1, .LBB0_2 ; RV32I-NEXT: bnez a1, .LBB0_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: .LBB0_2: ; RV32I-NEXT: .LBB0_2:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IBT-LABEL: select_of_or:
; RV32IBT: # %bb.0:
; RV32IBT-NEXT: or a1, a0, a1
; RV32IBT-NEXT: mv a0, a2
; RV32IBT-NEXT: bnez a1, .LBB0_2
; RV32IBT-NEXT: # %bb.1:
; RV32IBT-NEXT: mv a0, a3
; RV32IBT-NEXT: .LBB0_2:
; RV32IBT-NEXT: ret
;
; RV64I-LABEL: select_of_or: ; RV64I-LABEL: select_of_or:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: or a1, a0, a1 ; RV64I-NEXT: or a1, a0, a1
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: bnez a1, .LBB0_2 ; RV64I-NEXT: bnez a1, .LBB0_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB0_2: ; RV64I-NEXT: .LBB0_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV64IBT-LABEL: select_of_or:
; RV64IBT: # %bb.0:
; RV64IBT-NEXT: or a1, a0, a1
; RV64IBT-NEXT: mv a0, a2
; RV64IBT-NEXT: bnez a1, .LBB0_2
; RV64IBT-NEXT: # %bb.1:
; RV64IBT-NEXT: mv a0, a3
; RV64IBT-NEXT: .LBB0_2:
; RV64IBT-NEXT: ret
%1 = or i1 %a, %b %1 = or i1 %a, %b
%2 = select i1 %1, i32 %c, i32 %d %2 = select i1 %1, i32 %c, i32 %d
ret i32 %2 ret i32 %2
} }
declare signext i32 @either() nounwind declare signext i32 @either() nounwind
declare signext i32 @neither() nounwind declare signext i32 @neither() nounwind
Show All 10 Lines
; RV32I-NEXT: j .LBB1_3 ; RV32I-NEXT: j .LBB1_3
; RV32I-NEXT: .LBB1_2: # %if.else ; RV32I-NEXT: .LBB1_2: # %if.else
; RV32I-NEXT: call neither@plt ; RV32I-NEXT: call neither@plt
; RV32I-NEXT: .LBB1_3: # %if.end ; RV32I-NEXT: .LBB1_3: # %if.end
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IBT-LABEL: if_of_or:
; RV32IBT: # %bb.0:
; RV32IBT-NEXT: addi sp, sp, -16
; RV32IBT-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IBT-NEXT: or a0, a0, a1
; RV32IBT-NEXT: addi a1, zero, 1
; RV32IBT-NEXT: bne a0, a1, .LBB1_2
; RV32IBT-NEXT: # %bb.1: # %if.then
; RV32IBT-NEXT: call either@plt
; RV32IBT-NEXT: j .LBB1_3
; RV32IBT-NEXT: .LBB1_2: # %if.else
; RV32IBT-NEXT: call neither@plt
; RV32IBT-NEXT: .LBB1_3: # %if.end
; RV32IBT-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IBT-NEXT: addi sp, sp, 16
; RV32IBT-NEXT: ret
;
; RV64I-LABEL: if_of_or: ; RV64I-LABEL: if_of_or:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: addi a1, zero, 1 ; RV64I-NEXT: addi a1, zero, 1
; RV64I-NEXT: bne a0, a1, .LBB1_2 ; RV64I-NEXT: bne a0, a1, .LBB1_2
; RV64I-NEXT: # %bb.1: # %if.then ; RV64I-NEXT: # %bb.1: # %if.then
; RV64I-NEXT: call either@plt ; RV64I-NEXT: call either@plt
; RV64I-NEXT: j .LBB1_3 ; RV64I-NEXT: j .LBB1_3
; RV64I-NEXT: .LBB1_2: # %if.else ; RV64I-NEXT: .LBB1_2: # %if.else
; RV64I-NEXT: call neither@plt ; RV64I-NEXT: call neither@plt
; RV64I-NEXT: .LBB1_3: # %if.end ; RV64I-NEXT: .LBB1_3: # %if.end
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV64IBT-LABEL: if_of_or:
; RV64IBT: # %bb.0:
; RV64IBT-NEXT: addi sp, sp, -16
; RV64IBT-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IBT-NEXT: or a0, a0, a1
; RV64IBT-NEXT: addi a1, zero, 1
; RV64IBT-NEXT: bne a0, a1, .LBB1_2
; RV64IBT-NEXT: # %bb.1: # %if.then
; RV64IBT-NEXT: call either@plt
; RV64IBT-NEXT: j .LBB1_3
; RV64IBT-NEXT: .LBB1_2: # %if.else
; RV64IBT-NEXT: call neither@plt
; RV64IBT-NEXT: .LBB1_3: # %if.end
; RV64IBT-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IBT-NEXT: addi sp, sp, 16
; RV64IBT-NEXT: ret
%1 = or i1 %a, %b %1 = or i1 %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.then: if.then:
%2 = tail call i32 @either() %2 = tail call i32 @either()
br label %if.end br label %if.end
if.else: if.else:
%3 = tail call i32 @neither() %3 = tail call i32 @neither()
br label %if.end br label %if.end
if.end: if.end:
%4 = phi i32 [%2, %if.then], [%3, %if.else] %4 = phi i32 [%2, %if.then], [%3, %if.else]
ret i32 %4 ret i32 %4
} }