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Differential D94605

[ARM] Use ResourceUses annotations for Cortex-M7
AbandonedPublic

Authored by dpenry on Jan 13 2021, 8:06 AM.

Details

Reviewers
andreadb
dmgreen
SjoerdMeijer
Summary

ResourceUses annotations give better scheduling results than
repeating a write resource because ResourceUses are parallel
uses instead of serial uses.

Diff Detail

Event Timeline

dpenry created this revision.Jan 13 2021, 8:06 AM
Herald added a reviewer: andreadb. · View Herald TranscriptJan 13 2021, 8:06 AM
Herald added subscribers: danielkiss, gbedwell, hiraditya, kristof.beyls. · View Herald Transcript
dpenry requested review of this revision.Jan 13 2021, 8:06 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 13 2021, 8:06 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
dpenry mentioned this in D94604: [CodeGen] Allow parallel uses of a resource.Jan 13 2021, 8:08 AM
dpenry added reviewers: dmgreen, SjoerdMeijer.Jan 13 2021, 8:10 AM
Harbormaster completed remote builds in B85024: Diff 316404.Jan 13 2021, 8:12 AM
dpenry abandoned this revision.Apr 19 2021, 1:31 PM

Abandoned because was replaced by D98977

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
74 lines
test/
tools/
llvm-mca/
ARM/
90 lines

Diff 316404

llvm/lib/Target/ARM/ARMScheduleM7.td

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def : WriteRes<WriteNoop, []> { let Latency = 0; } def : WriteRes<WriteNoop, []> { let Latency = 0; }
//===---------------------------------------------------------------------===// //===---------------------------------------------------------------------===//
// Sched definitions for floating-point instructions // Sched definitions for floating-point instructions
// //
// Floating point conversions. // Floating point conversions.
def : WriteRes<WriteFPCVT, [M7UnitVFP, M7UnitVPort]> { let Latency = 3; } def : WriteRes<WriteFPCVT, [M7UnitVFP, M7UnitVPort]> { let Latency = 3; }
def : WriteRes<WriteFPMOV, [M7UnitVPort]> { let Latency = 3; } def : WriteRes<WriteFPMOV, [M7UnitVPort]> { let Latency = 3; }
def M7WriteFPMOV64 : SchedWriteRes<[M7UnitVPort]> {
let Latency = 3; let ResourceUses = [2];
}
// The FP pipeline has a latency of 3 cycles. // The FP pipeline has a latency of 3 cycles.
// ALU operations (32/64-bit). These go down the FP pipeline. // ALU operations (32/64-bit). These go down the FP pipeline.
def : WriteRes<WriteFPALU32, [M7UnitVFP, M7UnitVPort]> { let Latency = 3; } def : WriteRes<WriteFPALU32, [M7UnitVFP, M7UnitVPort]> { let Latency = 3; }
def : WriteRes<WriteFPALU64, [M7UnitVFP, M7UnitVPort, M7UnitVPort]> { def : WriteRes<WriteFPALU64, [M7UnitVFP, M7UnitVPort]> {
let ResourceUses = [1,2];
let Latency = 4; let Latency = 4;
let BeginGroup = 1; let BeginGroup = 1;
} }
// Multiplication // Multiplication
def : WriteRes<WriteFPMUL32, [M7UnitVFP, M7UnitVPort]> { let Latency = 3; } def : WriteRes<WriteFPMUL32, [M7UnitVFP, M7UnitVPort]> { let Latency = 3; }
def : WriteRes<WriteFPMUL64, [M7UnitVFP, M7UnitVPort, M7UnitVPort]> { def : WriteRes<WriteFPMUL64, [M7UnitVFP, M7UnitVPort]> {
let ResourceUses = [1,2];
let Latency = 7; let Latency = 7;
let BeginGroup = 1; let BeginGroup = 1;
} }
// Multiply-accumulate. FPMAC goes down the FP Pipeline. // Multiply-accumulate. FPMAC goes down the FP Pipeline.
def : WriteRes<WriteFPMAC32, [M7UnitVFP, M7UnitVPort]> { let Latency = 6; } def : WriteRes<WriteFPMAC32, [M7UnitVFP, M7UnitVPort]> { let Latency = 6; }
def : WriteRes<WriteFPMAC64, [M7UnitVFP, M7UnitVPort, M7UnitVPort]> { def : WriteRes<WriteFPMAC64, [M7UnitVFP, M7UnitVPort]> {
let ResourceUses = [1,2];
let Latency = 11; let Latency = 11;
let BeginGroup = 1; let BeginGroup = 1;
} }
// Division. Effective scheduling latency is 3, though real latency is larger // Division. Effective scheduling latency is 3, though real latency is larger
def : WriteRes<WriteFPDIV32, [M7UnitVFP, M7UnitVPort]> { let Latency = 16; } def : WriteRes<WriteFPDIV32, [M7UnitVFP, M7UnitVPort]> { let Latency = 16; }
def : WriteRes<WriteFPDIV64, [M7UnitVFP, M7UnitVPort, M7UnitVPort]> { def : WriteRes<WriteFPDIV64, [M7UnitVFP, M7UnitVPort]> {
let ResourceUses = [1,2];
let Latency = 30; let Latency = 30;
let BeginGroup = 1; let BeginGroup = 1;
} }
// Square-root. Effective scheduling latency is 3; real latency is larger // Square-root. Effective scheduling latency is 3; real latency is larger
def : WriteRes<WriteFPSQRT32, [M7UnitVFP, M7UnitVPort]> { let Latency = 16; } def : WriteRes<WriteFPSQRT32, [M7UnitVFP, M7UnitVPort]> { let Latency = 16; }
def : WriteRes<WriteFPSQRT64, [M7UnitVFP, M7UnitVPort, M7UnitVPort]> { def : WriteRes<WriteFPSQRT64, [M7UnitVFP, M7UnitVPort]> {
let ResourceUses = [1,2];
let Latency = 30; let Latency = 30;
let BeginGroup = 1; let BeginGroup = 1;
} }
def M7WriteShift2 : SchedWriteRes<[M7UnitALU, M7UnitShift2]> {} def M7WriteShift2 : SchedWriteRes<[M7UnitALU, M7UnitShift2]> {}
// Not used for M7, but needing definitions anyway // Not used for M7, but needing definitions anyway
def : WriteRes<WriteVLD1, []>; def : WriteRes<WriteVLD1, []>;
▲ Show 20 Lines • Show All 129 Lines • ▼ Show 20 Linesdef M7TableLoad : SchedWriteRes<[M7UnitLoad]> {
let SingleIssue = 1; let SingleIssue = 1;
} }
def : InstRW<[M7TableLoad, M7Read_ISS, M7Read_ISS], (instregex "t2TB")>; def : InstRW<[M7TableLoad, M7Read_ISS, M7Read_ISS], (instregex "t2TB")>;
// VFP loads and stores // VFP loads and stores
def M7LoadSP : SchedWriteRes<[M7UnitLoad, M7UnitVPort]> { let Latency = 1; } def M7LoadSP : SchedWriteRes<[M7UnitLoad, M7UnitVPort]> { let Latency = 1; }
def M7LoadDP : SchedWriteRes<[M7UnitLoad, M7UnitVPort, M7UnitVPort]> { def M7LoadDP : SchedWriteRes<[M7UnitLoad, M7UnitVPort]> {
let ResourceUses = [2,2];
let Latency = 2; let Latency = 2;
let SingleIssue = 1; let SingleIssue = 1;
} }
def M7StoreSP : SchedWriteRes<[M7UnitStore, M7UnitVPort]>; def M7StoreSP : SchedWriteRes<[M7UnitStore, M7UnitVPort]>;
def M7StoreDP : SchedWriteRes<[M7UnitStore, M7UnitVPort, M7UnitVPort]> { def M7StoreDP : SchedWriteRes<[M7UnitStore, M7UnitVPort]> {
let ResourceUses = [1,2];
let SingleIssue = 1; let SingleIssue = 1;
} }
def : InstRW<[M7LoadSP, M7Read_ISS], (instregex "VLDR(S|H)$")>; def : InstRW<[M7LoadSP, M7Read_ISS], (instregex "VLDR(S|H)$")>;
def : InstRW<[M7LoadDP, M7Read_ISS], (instregex "VLDRD$")>; def : InstRW<[M7LoadDP, M7Read_ISS], (instregex "VLDRD$")>;
def : InstRW<[M7StoreSP, M7Read_EX3, M7Read_ISS], (instregex "VSTR(S|H)$")>; def : InstRW<[M7StoreSP, M7Read_EX3, M7Read_ISS], (instregex "VSTR(S|H)$")>;
def : InstRW<[M7StoreDP, M7Read_EX3, M7Read_ISS], (instregex "VSTRD$")>; def : InstRW<[M7StoreDP, M7Read_EX3, M7Read_ISS], (instregex "VSTRD$")>;
▲ Show 20 Lines • Show All 99 Lines • ▼ Show 20 Lines
// //
// Effective scheduling latency is really 3 for nearly all FP operations, // Effective scheduling latency is really 3 for nearly all FP operations,
// even if their true latency is higher. // even if their true latency is higher.
def M7WriteVFPLatOverride : SchedWriteRes<[]> { def M7WriteVFPLatOverride : SchedWriteRes<[]> {
let Latency = 3; let Latency = 3;
let NumMicroOps = 0; let NumMicroOps = 0;
} }
def M7WriteVFPExtraVPort : SchedWriteRes<[M7UnitVPort]> { def M7WriteVFPExtra : SchedWriteRes<[]> {
let Latency = 3; let Latency = 3;
let NumMicroOps = 0; let NumMicroOps = 0;
} }
// Instructions which are missing default schedules. // Instructions which are missing default schedules.
def : InstRW<[WriteFPALU32], def : InstRW<[WriteFPALU32],
(instregex "V(ABS|CVT.*|NEG|FP_VMAX.*|FP_VMIN.*|RINT.*)S$")>; (instregex "V(ABS|CVT.*|NEG|FP_VMAX.*|FP_VMIN.*|RINT.*)S$")>;
def : InstRW<[M7WriteVFPLatOverride, WriteFPALU64], def : InstRW<[M7WriteVFPLatOverride, WriteFPALU64],
(instregex "V(ABS|CVT.*|NEG|FP_VMAX.*|FP_VMIN.*|RINT.*)D$")>; (instregex "V(ABS|CVT.*|NEG|FP_VMAX.*|FP_VMIN.*|RINT.*)D$")>;
// VCMP // VCMP
def M7WriteVCMPS : SchedWriteRes<[M7UnitVFP, M7UnitVPort]> { let Latency = 0; } def M7WriteVCMPS : SchedWriteRes<[M7UnitVFP, M7UnitVPort]> { let Latency = 0; }
def M7WriteVCMPD : SchedWriteRes<[M7UnitVFP, M7UnitVPort, M7UnitVPort]> { def M7WriteVCMPD : SchedWriteRes<[M7UnitVFP, M7UnitVPort]> {
let Latency = 0; let Latency = 0;
let BeginGroup = 1; let BeginGroup = 1;
} }
def : InstRW<[M7WriteVCMPS], (instregex "VCMPS$")>; def : InstRW<[M7WriteVCMPS], (instregex "VCMPS$")>;
def : InstRW<[M7WriteVCMPD], (instregex "VCMPD$")>; def : InstRW<[M7WriteVCMPD], (instregex "VCMPD$")>;
// VMRS/VMSR // VMRS/VMSR
def M7VMRS : SchedWriteRes<[M7UnitVFP, M7UnitVPort]> { let SingleIssue = 1; } def M7VMRS : SchedWriteRes<[M7UnitVFP, M7UnitVPort]> { let SingleIssue = 1; }
def M7VMSR : SchedWriteRes<[M7UnitVFP, M7UnitVPort]> { let SingleIssue = 1; } def M7VMSR : SchedWriteRes<[M7UnitVFP, M7UnitVPort]> { let SingleIssue = 1; }
def : InstRW<[M7VMRS], (instregex "FMSTAT")>; def : InstRW<[M7VMRS], (instregex "FMSTAT")>;
def : InstRW<[M7VMSR], (instregex "VMSR")>; def : InstRW<[M7VMSR], (instregex "VMSR")>;
// VSEL cannot bypass in its implied $cpsr operand; model as earlier read // VSEL cannot bypass in its implied $cpsr operand; model as earlier read
def : InstRW<[WriteFPALU32, M7Slot0Only, ReadALU, ReadALU, M7Read_ISS], def : InstRW<[WriteFPALU32, M7Slot0Only, ReadALU, ReadALU, M7Read_ISS],
(instregex "VSEL.*S$")>; (instregex "VSEL.*S$")>;
def : InstRW<[M7WriteVFPLatOverride, WriteFPALU64, M7Slot0Only, def : InstRW<[M7WriteVFPLatOverride, WriteFPALU64, M7Slot0Only,
ReadALU, ReadALU, M7Read_ISS], ReadALU, ReadALU, M7Read_ISS],
(instregex "VSEL.*D$")>; (instregex "VSEL.*D$")>;
// VMOV // VMOV
def : InstRW<[WriteFPMOV], def : InstRW<[WriteFPMOV],
(instregex "VMOV(H|S)$", "FCONST(H|S)")>; (instregex "VMOV(H|S)$", "FCONST(H|S)")>;
def : InstRW<[WriteFPMOV, M7WriteVFPExtraVPort, M7Slot0Only], def : InstRW<[M7WriteFPMOV64, M7Slot0Only],
(instregex "VMOVD$")>; (instregex "VMOVD$")>;
def : InstRW<[WriteFPMOV, M7WriteVFPExtraVPort, M7Slot0Only], def : InstRW<[M7WriteFPMOV64, M7Slot0Only],
(instregex "FCONSTD")>; (instregex "FCONSTD")>;
def : InstRW<[WriteFPMOV, M7WriteVFPExtraVPort, M7SingleIssue], def : InstRW<[M7WriteFPMOV64, M7WriteVFPExtra, M7SingleIssue],
(instregex "VMOV(DRR|RRD|RRS|SRR)")>; (instregex "VMOV(DRR|RRD|RRS|SRR)")>;
// Larger-latency overrides. // Larger-latency overrides.
def : InstRW<[M7WriteVFPLatOverride, WriteFPDIV32], (instregex "VDIVS")>; def : InstRW<[M7WriteVFPLatOverride, WriteFPDIV32], (instregex "VDIVS")>;
def : InstRW<[M7WriteVFPLatOverride, WriteFPDIV64], (instregex "VDIVD")>; def : InstRW<[M7WriteVFPLatOverride, WriteFPDIV64], (instregex "VDIVD")>;
def : InstRW<[M7WriteVFPLatOverride, WriteFPSQRT32], (instregex "VSQRTS")>; def : InstRW<[M7WriteVFPLatOverride, WriteFPSQRT32], (instregex "VSQRTS")>;
def : InstRW<[M7WriteVFPLatOverride, WriteFPSQRT64], (instregex "VSQRTD")>; def : InstRW<[M7WriteVFPLatOverride, WriteFPSQRT64], (instregex "VSQRTD")>;
def : InstRW<[M7WriteVFPLatOverride, WriteFPMUL64], def : InstRW<[M7WriteVFPLatOverride, WriteFPMUL64],
(instregex "V(MUL|NMUL)D")>; (instregex "V(MUL|NMUL)D")>;
def : InstRW<[M7WriteVFPLatOverride, WriteFPALU64], def : InstRW<[M7WriteVFPLatOverride, WriteFPALU64],
(instregex "V(ADD|SUB)D")>; (instregex "V(ADD|SUB)D")>;
// Multiply-accumulate. Chained SP timing is correct; rest need overrides // Multiply-accumulate. Chained SP timing is correct; rest need overrides
// Double-precision chained MAC stalls the pipeline behind it for 3 cycles, // Double-precision chained MAC stalls the pipeline behind it for 3 cycles,
// making it appear to have 3 cycle latency for scheduling. // making it appear to have 3 cycle latency for scheduling. MAC->MAC
// bypassing is advanced by 2/3 cycles (fused/chained), but other bypassing is
// not.
let NumMicroOps = 0 in {
def M7WriteVFPLatOverrideMAC : SchedWriteRes<[]> { let Latency = 3; }
def M7WriteVFPLatOverride5 : SchedWriteRes<[]> { let Latency = 5; }
}
def M7MACBypass3 : SchedReadAdvance<3, [WriteFPMAC32, WriteFPMAC64,
M7WriteVFPLatOverrideMAC,
M7WriteVFPLatOverride5,
]>;
def M7MACBypass2 : SchedReadAdvance<2, [WriteFPMAC32, WriteFPMAC64,
M7WriteVFPLatOverrideMAC,
M7WriteVFPLatOverride5,
]>;
def : InstRW<[M7WriteVFPLatOverride, WriteFPMAC64, def : InstRW<[WriteFPMAC32, M7MACBypass3, ReadFPMUL, ReadFPMUL],
ReadFPMAC, ReadFPMUL, ReadFPMUL], (instregex "V(N)?ML(A|S)S$")>;
(instregex "V(N)?ML(A|S)D$")>;
// Single-precision fused MACs look like latency 5 with advance of 2. def : InstRW<[M7WriteVFPLatOverrideMAC, WriteFPMAC64,
M7MACBypass3, ReadFPMUL, ReadFPMUL],
(instregex "V(N)?ML(A|S)D$")>;
def M7WriteVFPLatOverride5 : SchedWriteRes<[]> { // Single-precision fused MACs look like latency 5.
let Latency = 5;
let NumMicroOps = 0;
}
def M7ReadFPMAC2 : SchedReadAdvance<2>;
def : InstRW<[M7WriteVFPLatOverride5, WriteFPMAC32, def : InstRW<[M7WriteVFPLatOverride5, WriteFPMAC32,
M7ReadFPMAC2, ReadFPMUL, ReadFPMUL], M7MACBypass2, ReadFPMUL, ReadFPMUL],
(instregex "VF(N)?M(A|S)S$")>; (instregex "VF(N)?M(A|S)S$")>;
// Double-precision fused MAC stalls the pipeline behind it for 2 cycles, making // Double-precision fused MAC stalls the pipeline behind it for 2 cycles, making
// it appear to have 3 cycle latency for scheduling. // it appear to have 3 cycle latency for scheduling.
def : InstRW<[M7WriteVFPLatOverride, WriteFPMAC64, def : InstRW<[M7WriteVFPLatOverrideMAC, WriteFPMAC64,
ReadFPMAC, ReadFPMUL, ReadFPMUL], M7MACBypass2, ReadFPMUL, ReadFPMUL],
(instregex "VF(N)?M(A|S)D$")>; (instregex "VF(N)?M(A|S)D$")>;
} // SchedModel = CortexM7Model } // SchedModel = CortexM7Model

llvm/test/tools/llvm-mca/ARM/m7-fp.s

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# CHECK-NEXT: [6] - M7UnitShift2 # CHECK-NEXT: [6] - M7UnitShift2
# CHECK-NEXT: [7] - M7UnitStore # CHECK-NEXT: [7] - M7UnitStore
# CHECK-NEXT: [8] - M7UnitVFP # CHECK-NEXT: [8] - M7UnitVFP
# CHECK-NEXT: [9.0] - M7UnitVPort # CHECK-NEXT: [9.0] - M7UnitVPort
# CHECK-NEXT: [9.1] - M7UnitVPort # CHECK-NEXT: [9.1] - M7UnitVPort
# CHECK: Resource pressure per iteration: # CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0.0] [0.1] [1] [2.0] [2.1] [3] [4] [5] [6] [7] [8] [9.0] [9.1] # CHECK-NEXT: [0.0] [0.1] [1] [2.0] [2.1] [3] [4] [5] [6] [7] [8] [9.0] [9.1]
# CHECK-NEXT: - - - 1.00 1.00 - - - - 2.00 104.00 81.00 81.00 # CHECK-NEXT: - - - 1.00 1.00 - - - - 2.00 104.00 59.00 59.00
# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0.0] [0.1] [1] [2.0] [2.1] [3] [4] [5] [6] [7] [8] [9.0] [9.1] Instructions: # CHECK-NEXT: [0.0] [0.1] [1] [2.0] [2.1] [3] [4] [5] [6] [7] [8] [9.0] [9.1] Instructions:
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vabs.f32 s0, s2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vabs.f32 s0, s2
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vabs.f64 d0, d2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vabs.f64 d0, d2
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vadd.f32 s0, s2, s1 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vadd.f32 s0, s2, s1
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vadd.f64 d0, d2, d1 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vadd.f64 d0, d2, d1
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcmp.f32 s1, s2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcmp.f32 s1, s2
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vcmp.f64 d1, d2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcmp.f64 d1, d2
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vcvt.f32.f64 s1, d2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f32.f64 s1, d2
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f64.f32 d1, s1 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f64.f32 d1, s1
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f32.u16 s1, s1, #8 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f32.u16 s1, s1, #8
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f32.s16 s1, s1, #8 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f32.s16 s1, s1, #8
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f32.u32 s1, s1, #8 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f32.u32 s1, s1, #8
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f32.s32 s1, s1, #8 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f32.s32 s1, s1, #8
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.u16.f32 s1, s1, #8 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.u16.f32 s1, s1, #8
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.s16.f32 s1, s1, #8 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.s16.f32 s1, s1, #8
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.u32.f32 s1, s1, #8 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.u32.f32 s1, s1, #8
Show All 11 Lines
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.u32.f64 s1, d2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.u32.f64 s1, d2
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.s32.f64 s1, d2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.s32.f64 s1, d2
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f32.u32 s1, s2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f32.u32 s1, s2
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f32.s32 s1, s2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f32.s32 s1, s2
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f64.u32 d1, s2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f64.u32 d1, s2
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f64.s32 d1, s2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f64.s32 d1, s2
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvta.u32.f32 s1, s2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvta.u32.f32 s1, s2
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvta.s32.f32 s1, s2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvta.s32.f32 s1, s2
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vcvta.u32.f64 s1, d2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvta.u32.f64 s1, d2
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vcvta.s32.f64 s1, d2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvta.s32.f64 s1, d2
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtm.u32.f32 s1, s2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtm.u32.f32 s1, s2
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtm.s32.f32 s1, s2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtm.s32.f32 s1, s2
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vcvtm.u32.f64 s1, d2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtm.u32.f64 s1, d2
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vcvtm.s32.f64 s1, d2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtm.s32.f64 s1, d2
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtn.u32.f32 s1, s2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtn.u32.f32 s1, s2
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtn.s32.f32 s1, s2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtn.s32.f32 s1, s2
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vcvtn.u32.f64 s1, d2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtn.u32.f64 s1, d2
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vcvtn.s32.f64 s1, d2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtn.s32.f64 s1, d2
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtp.u32.f32 s1, s2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtp.u32.f32 s1, s2
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtp.s32.f32 s1, s2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtp.s32.f32 s1, s2
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vcvtp.u32.f64 s1, d2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtp.u32.f64 s1, d2
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vcvtp.s32.f64 s1, d2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtp.s32.f64 s1, d2
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtb.f32.f16 s1, s2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtb.f32.f16 s1, s2
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtb.f16.f32 s1, s2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtb.f16.f32 s1, s2
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtr.u32.f32 s1, s2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtr.u32.f32 s1, s2
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtr.s32.f32 s1, s2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtr.s32.f32 s1, s2
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtr.u32.f64 s1, d2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtr.u32.f64 s1, d2
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtr.s32.f64 s1, d2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtr.s32.f64 s1, d2
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtt.f16.f32 s1, s2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtt.f16.f32 s1, s2
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtt.f32.f16 s1, s2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtt.f32.f16 s1, s2
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vdiv.f32 s0, s2, s1 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vdiv.f32 s0, s2, s1
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vdiv.f64 d0, d2, d1 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vdiv.f64 d0, d2, d1
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vfma.f32 s0, s2, s1 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vfma.f32 s0, s2, s1
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vfma.f64 d0, d2, d1 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vfma.f64 d0, d2, d1
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vfms.f32 s0, s2, s1 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vfms.f32 s0, s2, s1
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vfms.f64 d0, d2, d1 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vfms.f64 d0, d2, d1
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vfnma.f32 s0, s2, s1 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vfnma.f32 s0, s2, s1
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vfnma.f64 d0, d2, d1 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vfnma.f64 d0, d2, d1
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vfnms.f32 s0, s2, s1 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vfnms.f32 s0, s2, s1
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vfnms.f64 d0, d2, d1 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vfnms.f64 d0, d2, d1
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vmaxnm.f32 s0, s2, s1 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vmaxnm.f32 s0, s2, s1
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vmaxnm.f64 d0, d2, d1 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vmaxnm.f64 d0, d2, d1
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vminnm.f32 s0, s2, s1 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vminnm.f32 s0, s2, s1
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vminnm.f64 d0, d2, d1 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vminnm.f64 d0, d2, d1
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vmla.f32 s0, s2, s1 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vmla.f32 s0, s2, s1
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vmla.f64 d0, d2, d1 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vmla.f64 d0, d2, d1
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vmls.f32 s0, s2, s1 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vmls.f32 s0, s2, s1
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vmls.f64 d0, d2, d1 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vmls.f64 d0, d2, d1
# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vmov s0, r1 # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vmov s0, r1
# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vmov r0, s1 # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vmov r0, s1
# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmov d0, r1, r2 # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vmov d0, r1, r2
# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmov r0, r1, d1 # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vmov r0, r1, d1
# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmov s0, s1, r0, r1 # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vmov s0, s1, r0, r1
# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmov r0, r1, s0, s1 # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vmov r0, r1, s0, s1
# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vmov.f32 s0, #1.000000e+00 # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vmov.f32 s0, #1.000000e+00
# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmov.f64 d0, #1.000000e+00 # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vmov.f64 d0, #1.000000e+00
# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vmov.f32 s0, s1 # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vmov.f32 s0, s1
# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmov.f64 d0, d1 # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vmov.f64 d0, d1
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vmul.f32 s0, s2, s1 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vmul.f32 s0, s2, s1
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vmul.f64 d0, d2, d1 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vmul.f64 d0, d2, d1
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vneg.f32 s0, s2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vneg.f32 s0, s2
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vneg.f64 d0, d2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vneg.f64 d0, d2
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vnmla.f32 s0, s2, s1 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vnmla.f32 s0, s2, s1
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vnmla.f64 d0, d2, d1 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vnmla.f64 d0, d2, d1
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vnmls.f32 s0, s2, s1 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vnmls.f32 s0, s2, s1
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vnmls.f64 d0, d2, d1 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vnmls.f64 d0, d2, d1
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vnmul.f32 s0, s2, s1 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vnmul.f32 s0, s2, s1
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vnmul.f64 d0, d2, d1 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vnmul.f64 d0, d2, d1
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrinta.f32 s0, s2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrinta.f32 s0, s2
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vrinta.f64 d0, d2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrinta.f64 d0, d2
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrintm.f32 s0, s2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrintm.f32 s0, s2
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vrintm.f64 d0, d2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrintm.f64 d0, d2
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrintn.f32 s0, s2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrintn.f32 s0, s2
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vrintn.f64 d0, d2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrintn.f64 d0, d2
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrintp.f32 s0, s2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrintp.f32 s0, s2
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vrintp.f64 d0, d2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrintp.f64 d0, d2
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrintr.f32 s0, s2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrintr.f32 s0, s2
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vrintr.f64 d0, d2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrintr.f64 d0, d2
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrintz.f32 s0, s2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrintz.f32 s0, s2
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vrintz.f64 d0, d2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrintz.f64 d0, d2
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrintx.f32 s0, s2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrintx.f32 s0, s2
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vrintx.f64 d0, d2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrintx.f64 d0, d2
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vseleq.f32 s0, s2, s1 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vseleq.f32 s0, s2, s1
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vseleq.f64 d0, d2, d1 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vseleq.f64 d0, d2, d1
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vsqrt.f32 s0, s2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vsqrt.f32 s0, s2
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vsqrt.f64 d0, d2 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vsqrt.f64 d0, d2
# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vsub.f32 s0, s2, s1 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vsub.f32 s0, s2, s1
# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vsub.f64 d0, d2, d1 # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vsub.f64 d0, d2, d1
# CHECK-NEXT: - - - 0.50 0.50 - - - - - - 1.00 1.00 vldr d0, [r0] # CHECK-NEXT: - - - 0.50 0.50 - - - - - - 0.50 0.50 vldr d0, [r0]
# CHECK-NEXT: - - - 0.50 0.50 - - - - - - 0.50 0.50 vldr s0, [r0] # CHECK-NEXT: - - - 0.50 0.50 - - - - - - 0.50 0.50 vldr s0, [r0]
# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 1.00 vstr d0, [r0] # CHECK-NEXT: - - - - - - - - - 1.00 - 0.50 0.50 vstr d0, [r0]
# CHECK-NEXT: - - - - - - - - - 1.00 - 0.50 0.50 vstr s0, [r0] # CHECK-NEXT: - - - - - - - - - 1.00 - 0.50 0.50 vstr s0, [r0]