[PowerPC][AIX] Support calling convention for IEEE Long Double

[steven.zhang]

Summary

We have supported the calling convention for altivec. As the fp128 is handled by VR register, it should have the same calling convention with vector type.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT,
   const Align PtrAlign = IsPPC64 ? Align(8) : Align(4);
   const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32;
 
   if (ValVT.isVector() && !State.getMachineFunction()
                                .getTarget()
                                .Options.EnableAIXExtendedAltivecABI)
     report_fatal_error("the default Altivec AIX ABI is not yet supported");
 
-  if (ValVT == MVT::f128)
-    report_fatal_error("f128 is unimplemented on AIX.");
-
   if (ArgFlags.isNest())
     report_fatal_error("Nest arguments are unimplemented.");
 
   static const MCPhysReg GPR_32[] = {// 32-bit registers.
                                      PPC::R3, PPC::R4, PPC::R5, PPC::R6,
                                      PPC::R7, PPC::R8, PPC::R9, PPC::R10};
   static const MCPhysReg GPR_64[] = {// 64-bit registers.
                                      PPC::X3, PPC::X4, PPC::X5, PPC::X6,
for (unsigned I = 0; I < StoreSize; I += PtrAlign.value()) {
                                              LocInfo)
                  : CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
         break;
       }
     }
 
     return false;
   }
+  case MVT::f128:
   case MVT::v4f32:
   case MVT::v4i32:
   case MVT::v8i16:
   case MVT::v16i8:
   case MVT::v2i64:
   case MVT::v2f64:
   case MVT::v1i128: {
     if (State.isVarArg())
static const TargetRegisterClass *getRegClassForSVT(MVT::SimpleValueType SVT,
   case MVT::i1:
   case MVT::i32:
   case MVT::i64:
     return IsPPC64 ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
   case MVT::f32:
     return &PPC::F4RCRegClass;
   case MVT::f64:
     return &PPC::F8RCRegClass;
+  case MVT::f128:
   case MVT::v4f32:
   case MVT::v4i32:
   case MVT::v8i16:
   case MVT::v16i8:
   case MVT::v2i64:
   case MVT::v2f64:
   case MVT::v1i128:
     return &PPC::VRRCRegClass;

llvm/test/CodeGen/PowerPC/f128-arith.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs \
 ; RUN:   -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
 ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs \
 ; RUN:   -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -enable-soft-fp128 | FileCheck %s \
 ; RUN:   -check-prefix=CHECK-P8
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs -vec-extabi \
+; RUN:   < %s | FileCheck %s -check-prefix=CHECK-P9-AIX
 
 ; Function Attrs: norecurse nounwind
 define dso_local void @qpAdd(fp128* nocapture readonly %a, fp128* nocapture %res) {
 ; CHECK-LABEL: qpAdd:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv v2, 0(r3)
 ; CHECK-NEXT:    xsaddqp v2, v2, v2
 ; CHECK-NEXT:    stxv v2, 0(r4)

 ; CHECK-P8-NEXT:    bl __addkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    stvx v2, 0, r30
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-AIX-LABEL: qpAdd:
+; CHECK-P9-AIX:       # %bb.0: # %entry
+; CHECK-P9-AIX-NEXT:    lxv 34, 0(3)
+; CHECK-P9-AIX-NEXT:    xsaddqp 2, 2, 2
+; CHECK-P9-AIX-NEXT:    stxv 34, 0(4)
+; CHECK-P9-AIX-NEXT:    blr
 entry:
   %0 = load fp128, fp128* %a, align 16
   %add = fadd fp128 %0, %0
   store fp128 %add, fp128* %res, align 16
   ret void
 }
 
 ; Function Attrs: norecurse nounwind

 ; CHECK-P8-NEXT:    bl __subkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    stvx v2, 0, r30
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-AIX-LABEL: qpSub:
+; CHECK-P9-AIX:       # %bb.0: # %entry
+; CHECK-P9-AIX-NEXT:    lxv 34, 0(3)
+; CHECK-P9-AIX-NEXT:    xssubqp 2, 2, 2
+; CHECK-P9-AIX-NEXT:    stxv 34, 0(4)
+; CHECK-P9-AIX-NEXT:    blr
 entry:
   %0 = load fp128, fp128* %a, align 16
   %sub = fsub fp128 %0, %0
   store fp128 %sub, fp128* %res, align 16
   ret void
 }
 
 ; Function Attrs: norecurse nounwind

 ; CHECK-P8-NEXT:    bl __mulkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    stvx v2, 0, r30
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-AIX-LABEL: qpMul:
+; CHECK-P9-AIX:       # %bb.0: # %entry
+; CHECK-P9-AIX-NEXT:    lxv 34, 0(3)
+; CHECK-P9-AIX-NEXT:    xsmulqp 2, 2, 2
+; CHECK-P9-AIX-NEXT:    stxv 34, 0(4)
+; CHECK-P9-AIX-NEXT:    blr
 entry:
   %0 = load fp128, fp128* %a, align 16
   %mul = fmul fp128 %0, %0
   store fp128 %mul, fp128* %res, align 16
   ret void
 }
 
 ; Function Attrs: norecurse nounwind

 ; CHECK-P8-NEXT:    bl __divkf3
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    stvx v2, 0, r30
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-AIX-LABEL: qpDiv:
+; CHECK-P9-AIX:       # %bb.0: # %entry
+; CHECK-P9-AIX-NEXT:    lxv 34, 0(3)
+; CHECK-P9-AIX-NEXT:    xsdivqp 2, 2, 2
+; CHECK-P9-AIX-NEXT:    stxv 34, 0(4)
+; CHECK-P9-AIX-NEXT:    blr
 entry:
   %0 = load fp128, fp128* %a, align 16
   %div = fdiv fp128 %0, %0
   store fp128 %div, fp128* %res, align 16
   ret void
 }
 
 define dso_local void @testLdNSt(i8* nocapture readonly %PtrC, fp128* nocapture %PtrF) {
 ; CHECK-LABEL: testLdNSt:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addi r3, r3, 4
 ; CHECK-NEXT:    addi r4, r4, 8
 ; CHECK-NEXT:    lxvx vs0, 0, r3
 ; CHECK-NEXT:    stxvx vs0, 0, r4
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: testLdNSt:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    addi r3, r3, 4
 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    addi r3, r4, 8
 ; CHECK-P8-NEXT:    stvx v2, 0, r3
 ; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-AIX-LABEL: testLdNSt:
+; CHECK-P9-AIX:       # %bb.0: # %entry
+; CHECK-P9-AIX-NEXT:    addi 3, 3, 4
+; CHECK-P9-AIX-NEXT:    addi 4, 4, 8
+; CHECK-P9-AIX-NEXT:    lxvx 0, 0, 3
+; CHECK-P9-AIX-NEXT:    stxvx 0, 0, 4
+; CHECK-P9-AIX-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %PtrC, i64 4
   %0 = bitcast i8* %add.ptr to fp128*
   %1 = load fp128, fp128* %0, align 16
   %2 = bitcast fp128* %PtrF to i8*
   %add.ptr1 = getelementptr inbounds i8, i8* %2, i64 8
   %3 = bitcast i8* %add.ptr1 to fp128*
   store fp128 %1, fp128* %3, align 16

 ; CHECK-P8-NEXT:    bl sqrtf128
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    stvx v2, 0, r30
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-AIX-LABEL: qpSqrt:
+; CHECK-P9-AIX:       # %bb.0: # %entry
+; CHECK-P9-AIX-NEXT:    lxv 34, 0(3)
+; CHECK-P9-AIX-NEXT:    xssqrtqp 2, 2
+; CHECK-P9-AIX-NEXT:    stxv 34, 0(4)
+; CHECK-P9-AIX-NEXT:    blr
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = tail call fp128 @llvm.sqrt.f128(fp128 %0)
   store fp128 %1, fp128* %res, align 16
   ret void
 
 }
 declare fp128 @llvm.sqrt.f128(fp128 %Val)

 ; CHECK-P8-NEXT:    stvx v2, 0, r4
 ; CHECK-P8-NEXT:    lbz r3, -1(r1)
 ; CHECK-P8-NEXT:    lbz r6, -17(r1)
 ; CHECK-P8-NEXT:    rlwimi r6, r3, 0, 0, 24
 ; CHECK-P8-NEXT:    stb r6, -17(r1)
 ; CHECK-P8-NEXT:    lvx v2, 0, r4
 ; CHECK-P8-NEXT:    stvx v2, 0, r5
 ; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-AIX-LABEL: qpCpsgn:
+; CHECK-P9-AIX:       # %bb.0: # %entry
+; CHECK-P9-AIX-NEXT:    lxv 34, 0(3)
+; CHECK-P9-AIX-NEXT:    lxv 35, 0(4)
+; CHECK-P9-AIX-NEXT:    xscpsgnqp 2, 3, 2
+; CHECK-P9-AIX-NEXT:    stxv 34, 0(5)
+; CHECK-P9-AIX-NEXT:    blr
                      fp128* nocapture %res) {
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = load fp128, fp128* %b, align 16
   %2 = tail call fp128 @llvm.copysign.f128(fp128 %0, fp128 %1)
   store fp128 %2, fp128* %res, align 16
   ret void
 

 ; CHECK-P8-NEXT:    addi r3, r1, -16
 ; CHECK-P8-NEXT:    stvx v2, 0, r3
 ; CHECK-P8-NEXT:    lbz r5, -1(r1)
 ; CHECK-P8-NEXT:    clrlwi r5, r5, 25
 ; CHECK-P8-NEXT:    stb r5, -1(r1)
 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    stvx v2, 0, r4
 ; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-AIX-LABEL: qpAbs:
+; CHECK-P9-AIX:       # %bb.0: # %entry
+; CHECK-P9-AIX-NEXT:    lxv 34, 0(3)
+; CHECK-P9-AIX-NEXT:    xsabsqp 2, 2
+; CHECK-P9-AIX-NEXT:    stxv 34, 0(4)
+; CHECK-P9-AIX-NEXT:    blr
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = tail call fp128 @llvm.fabs.f128(fp128 %0)
   store fp128 %1, fp128* %res, align 16
   ret void
 
 }
 declare fp128 @llvm.fabs.f128(fp128 %Val)

 ; CHECK-P8-NEXT:    addi r3, r1, -16
 ; CHECK-P8-NEXT:    stvx v2, 0, r3
 ; CHECK-P8-NEXT:    lbz r5, -1(r1)
 ; CHECK-P8-NEXT:    xori r5, r5, 128
 ; CHECK-P8-NEXT:    stb r5, -1(r1)
 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    stvx v2, 0, r4
 ; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-AIX-LABEL: qpNAbs:
+; CHECK-P9-AIX:       # %bb.0: # %entry
+; CHECK-P9-AIX-NEXT:    lxv 34, 0(3)
+; CHECK-P9-AIX-NEXT:    xsnabsqp 2, 2
+; CHECK-P9-AIX-NEXT:    stxv 34, 0(4)
+; CHECK-P9-AIX-NEXT:    blr
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = tail call fp128 @llvm.fabs.f128(fp128 %0)
   %neg = fsub fp128 0xL00000000000000008000000000000000, %1
   store fp128 %neg, fp128* %res, align 16
   ret void
 
 }

 ; CHECK-P8-NEXT:    addi r3, r1, -16
 ; CHECK-P8-NEXT:    stvx v2, 0, r3
 ; CHECK-P8-NEXT:    lbz r5, -1(r1)
 ; CHECK-P8-NEXT:    xori r5, r5, 128
 ; CHECK-P8-NEXT:    stb r5, -1(r1)
 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    stvx v2, 0, r4
 ; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-AIX-LABEL: qpNeg:
+; CHECK-P9-AIX:       # %bb.0: # %entry
+; CHECK-P9-AIX-NEXT:    lxv 34, 0(3)
+; CHECK-P9-AIX-NEXT:    xsnegqp 2, 2
+; CHECK-P9-AIX-NEXT:    stxv 34, 0(4)
+; CHECK-P9-AIX-NEXT:    blr
 entry:
   %0 = load fp128, fp128* %a, align 16
   %sub = fsub fp128 0xL00000000000000008000000000000000, %0
   store fp128 %sub, fp128* %res, align 16
   ret void
 
 }
 

 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    bl sinf128
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-AIX-LABEL: qp_sin:
+; CHECK-P9-AIX:       # %bb.0: # %entry
+; CHECK-P9-AIX-NEXT:    mflr 0
+; CHECK-P9-AIX-NEXT:    stw 0, 8(1)
+; CHECK-P9-AIX-NEXT:    stwu 1, -64(1)
+; CHECK-P9-AIX-NEXT:    lxv 34, 0(3)
+; CHECK-P9-AIX-NEXT:    bl .sinf128[PR]
+; CHECK-P9-AIX-NEXT:    nop
+; CHECK-P9-AIX-NEXT:    addi 1, 1, 64
+; CHECK-P9-AIX-NEXT:    lwz 0, 8(1)
+; CHECK-P9-AIX-NEXT:    mtlr 0
+; CHECK-P9-AIX-NEXT:    blr
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = tail call fp128 @llvm.sin.f128(fp128 %0)
   ret fp128 %1
 }
 declare fp128 @llvm.sin.f128(fp128 %Val)
 
 define fp128 @qp_cos(fp128* nocapture readonly %a) {

 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    bl cosf128
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-AIX-LABEL: qp_cos:
+; CHECK-P9-AIX:       # %bb.0: # %entry
+; CHECK-P9-AIX-NEXT:    mflr 0
+; CHECK-P9-AIX-NEXT:    stw 0, 8(1)
+; CHECK-P9-AIX-NEXT:    stwu 1, -64(1)
+; CHECK-P9-AIX-NEXT:    lxv 34, 0(3)
+; CHECK-P9-AIX-NEXT:    bl .cosf128[PR]
+; CHECK-P9-AIX-NEXT:    nop
+; CHECK-P9-AIX-NEXT:    addi 1, 1, 64
+; CHECK-P9-AIX-NEXT:    lwz 0, 8(1)
+; CHECK-P9-AIX-NEXT:    mtlr 0
+; CHECK-P9-AIX-NEXT:    blr
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = tail call fp128 @llvm.cos.f128(fp128 %0)
   ret fp128 %1
 }
 declare fp128 @llvm.cos.f128(fp128 %Val)
 
 define fp128 @qp_log(fp128* nocapture readonly %a) {

 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    bl logf128
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-AIX-LABEL: qp_log:
+; CHECK-P9-AIX:       # %bb.0: # %entry
+; CHECK-P9-AIX-NEXT:    mflr 0
+; CHECK-P9-AIX-NEXT:    stw 0, 8(1)
+; CHECK-P9-AIX-NEXT:    stwu 1, -64(1)
+; CHECK-P9-AIX-NEXT:    lxv 34, 0(3)
+; CHECK-P9-AIX-NEXT:    bl .logf128[PR]
+; CHECK-P9-AIX-NEXT:    nop
+; CHECK-P9-AIX-NEXT:    addi 1, 1, 64
+; CHECK-P9-AIX-NEXT:    lwz 0, 8(1)
+; CHECK-P9-AIX-NEXT:    mtlr 0
+; CHECK-P9-AIX-NEXT:    blr
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = tail call fp128 @llvm.log.f128(fp128 %0)
   ret fp128 %1
 }
 declare fp128     @llvm.log.f128(fp128 %Val)
 
 define fp128 @qp_log10(fp128* nocapture readonly %a) {

 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    bl log10f128
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-AIX-LABEL: qp_log10:
+; CHECK-P9-AIX:       # %bb.0: # %entry
+; CHECK-P9-AIX-NEXT:    mflr 0
+; CHECK-P9-AIX-NEXT:    stw 0, 8(1)
+; CHECK-P9-AIX-NEXT:    stwu 1, -64(1)
+; CHECK-P9-AIX-NEXT:    lxv 34, 0(3)
+; CHECK-P9-AIX-NEXT:    bl .log10f128[PR]
+; CHECK-P9-AIX-NEXT:    nop
+; CHECK-P9-AIX-NEXT:    addi 1, 1, 64
+; CHECK-P9-AIX-NEXT:    lwz 0, 8(1)
+; CHECK-P9-AIX-NEXT:    mtlr 0
+; CHECK-P9-AIX-NEXT:    blr
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = tail call fp128 @llvm.log10.f128(fp128 %0)
   ret fp128 %1
 }
 declare fp128     @llvm.log10.f128(fp128 %Val)
 
 define fp128 @qp_log2(fp128* nocapture readonly %a) {

 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    bl log2f128
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-AIX-LABEL: qp_log2:
+; CHECK-P9-AIX:       # %bb.0: # %entry
+; CHECK-P9-AIX-NEXT:    mflr 0
+; CHECK-P9-AIX-NEXT:    stw 0, 8(1)
+; CHECK-P9-AIX-NEXT:    stwu 1, -64(1)
+; CHECK-P9-AIX-NEXT:    lxv 34, 0(3)
+; CHECK-P9-AIX-NEXT:    bl .log2f128[PR]
+; CHECK-P9-AIX-NEXT:    nop
+; CHECK-P9-AIX-NEXT:    addi 1, 1, 64
+; CHECK-P9-AIX-NEXT:    lwz 0, 8(1)
+; CHECK-P9-AIX-NEXT:    mtlr 0
+; CHECK-P9-AIX-NEXT:    blr
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = tail call fp128 @llvm.log2.f128(fp128 %0)
   ret fp128 %1
 }
 declare fp128     @llvm.log2.f128(fp128 %Val)
 
 define fp128 @qp_minnum(fp128* nocapture readonly %a,

 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    bl fminf128
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-AIX-LABEL: qp_minnum:
+; CHECK-P9-AIX:       # %bb.0: # %entry
+; CHECK-P9-AIX-NEXT:    mflr 0
+; CHECK-P9-AIX-NEXT:    stw 0, 8(1)
+; CHECK-P9-AIX-NEXT:    stwu 1, -64(1)
+; CHECK-P9-AIX-NEXT:    lxv 34, 0(3)
+; CHECK-P9-AIX-NEXT:    lxv 35, 0(4)
+; CHECK-P9-AIX-NEXT:    bl .fminf128[PR]
+; CHECK-P9-AIX-NEXT:    nop
+; CHECK-P9-AIX-NEXT:    addi 1, 1, 64
+; CHECK-P9-AIX-NEXT:    lwz 0, 8(1)
+; CHECK-P9-AIX-NEXT:    mtlr 0
+; CHECK-P9-AIX-NEXT:    blr
                         fp128* nocapture readonly %b) {
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = load fp128, fp128* %b, align 16
   %2 = tail call fp128 @llvm.minnum.f128(fp128 %0, fp128 %1)
   ret fp128 %2
 }
 declare fp128     @llvm.minnum.f128(fp128 %Val0, fp128 %Val1)

 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    bl fmaxf128
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-AIX-LABEL: qp_maxnum:
+; CHECK-P9-AIX:       # %bb.0: # %entry
+; CHECK-P9-AIX-NEXT:    mflr 0
+; CHECK-P9-AIX-NEXT:    stw 0, 8(1)
+; CHECK-P9-AIX-NEXT:    stwu 1, -64(1)
+; CHECK-P9-AIX-NEXT:    lxv 34, 0(3)
+; CHECK-P9-AIX-NEXT:    lxv 35, 0(4)
+; CHECK-P9-AIX-NEXT:    bl .fmaxf128[PR]
+; CHECK-P9-AIX-NEXT:    nop
+; CHECK-P9-AIX-NEXT:    addi 1, 1, 64
+; CHECK-P9-AIX-NEXT:    lwz 0, 8(1)
+; CHECK-P9-AIX-NEXT:    mtlr 0
+; CHECK-P9-AIX-NEXT:    blr
                         fp128* nocapture readonly %b) {
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = load fp128, fp128* %b, align 16
   %2 = tail call fp128 @llvm.maxnum.f128(fp128 %0, fp128 %1)
   ret fp128 %2
 }
 declare fp128     @llvm.maxnum.f128(fp128 %Val0, fp128 %Val1)

 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    bl powf128
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-AIX-LABEL: qp_pow:
+; CHECK-P9-AIX:       # %bb.0: # %entry
+; CHECK-P9-AIX-NEXT:    mflr 0
+; CHECK-P9-AIX-NEXT:    stw 0, 8(1)
+; CHECK-P9-AIX-NEXT:    stwu 1, -64(1)
+; CHECK-P9-AIX-NEXT:    lxv 34, 0(3)
+; CHECK-P9-AIX-NEXT:    lxv 35, 0(4)
+; CHECK-P9-AIX-NEXT:    bl .powf128[PR]
+; CHECK-P9-AIX-NEXT:    nop
+; CHECK-P9-AIX-NEXT:    addi 1, 1, 64
+; CHECK-P9-AIX-NEXT:    lwz 0, 8(1)
+; CHECK-P9-AIX-NEXT:    mtlr 0
+; CHECK-P9-AIX-NEXT:    blr
                      fp128* nocapture readonly %b) {
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = load fp128, fp128* %b, align 16
   %2 = tail call fp128 @llvm.pow.f128(fp128 %0, fp128 %1)
   ret fp128 %2
 }
 declare fp128 @llvm.pow.f128(fp128 %Val, fp128 %Power)

 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    bl expf128
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-AIX-LABEL: qp_exp:
+; CHECK-P9-AIX:       # %bb.0: # %entry
+; CHECK-P9-AIX-NEXT:    mflr 0
+; CHECK-P9-AIX-NEXT:    stw 0, 8(1)
+; CHECK-P9-AIX-NEXT:    stwu 1, -64(1)
+; CHECK-P9-AIX-NEXT:    lxv 34, 0(3)
+; CHECK-P9-AIX-NEXT:    bl .expf128[PR]
+; CHECK-P9-AIX-NEXT:    nop
+; CHECK-P9-AIX-NEXT:    addi 1, 1, 64
+; CHECK-P9-AIX-NEXT:    lwz 0, 8(1)
+; CHECK-P9-AIX-NEXT:    mtlr 0
+; CHECK-P9-AIX-NEXT:    blr
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = tail call fp128 @llvm.exp.f128(fp128 %0)
   ret fp128 %1
 }
 declare fp128     @llvm.exp.f128(fp128 %Val)
 
 define fp128 @qp_exp2(fp128* nocapture readonly %a) {

 ; CHECK-P8-NEXT:    .cfi_offset lr, 16
 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    bl exp2f128
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-AIX-LABEL: qp_exp2:
+; CHECK-P9-AIX:       # %bb.0: # %entry
+; CHECK-P9-AIX-NEXT:    mflr 0
+; CHECK-P9-AIX-NEXT:    stw 0, 8(1)
+; CHECK-P9-AIX-NEXT:    stwu 1, -64(1)
+; CHECK-P9-AIX-NEXT:    lxv 34, 0(3)
+; CHECK-P9-AIX-NEXT:    bl .exp2f128[PR]
+; CHECK-P9-AIX-NEXT:    nop
+; CHECK-P9-AIX-NEXT:    addi 1, 1, 64
+; CHECK-P9-AIX-NEXT:    lwz 0, 8(1)
+; CHECK-P9-AIX-NEXT:    mtlr 0
+; CHECK-P9-AIX-NEXT:    blr
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = tail call fp128 @llvm.exp2.f128(fp128 %0)
   ret fp128 %1
 }
 declare fp128     @llvm.exp2.f128(fp128 %Val)
 
 define dso_local void @qp_powi(fp128* nocapture readonly %a, i32* nocapture readonly %b,

 ; CHECK-P8-NEXT:    bl __powikf2
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    stvx v2, 0, r30
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-AIX-LABEL: qp_powi:
+; CHECK-P9-AIX:       # %bb.0: # %entry
+; CHECK-P9-AIX-NEXT:    mflr 0
+; CHECK-P9-AIX-NEXT:    stw 0, 8(1)
+; CHECK-P9-AIX-NEXT:    stwu 1, -64(1)
+; CHECK-P9-AIX-NEXT:    lxv 34, 0(3)
+; CHECK-P9-AIX-NEXT:    lwz 3, 0(4)
+; CHECK-P9-AIX-NEXT:    stw 30, 56(1) # 4-byte Folded Spill
+; CHECK-P9-AIX-NEXT:    mr 30, 5
+; CHECK-P9-AIX-NEXT:    bl .__powikf2[PR]
+; CHECK-P9-AIX-NEXT:    nop
+; CHECK-P9-AIX-NEXT:    stxv 34, 0(30)
+; CHECK-P9-AIX-NEXT:    lwz 30, 56(1) # 4-byte Folded Reload
+; CHECK-P9-AIX-NEXT:    addi 1, 1, 64
+; CHECK-P9-AIX-NEXT:    lwz 0, 8(1)
+; CHECK-P9-AIX-NEXT:    mtlr 0
+; CHECK-P9-AIX-NEXT:    blr
                      fp128* nocapture %res) {
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = load i32, i32* %b, align 8
   %2 = tail call fp128 @llvm.powi.f128(fp128 %0, i32 %1)
   store fp128 %2, fp128* %res, align 16
   ret void
 }

 ; CHECK-P8-NEXT:    lvx v2, 0, r3
 ; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    bl fmodf128
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    addi r1, r1, 32
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-AIX-LABEL: qp_frem:
+; CHECK-P9-AIX:       # %bb.0: # %entry
+; CHECK-P9-AIX-NEXT:    mflr 0
+; CHECK-P9-AIX-NEXT:    stw 0, 8(1)
+; CHECK-P9-AIX-NEXT:    stwu 1, -64(1)
+; CHECK-P9-AIX-NEXT:    lwz 3, L..C0(2)
+; CHECK-P9-AIX-NEXT:    lxvx 34, 0, 3
+; CHECK-P9-AIX-NEXT:    lwz 3, L..C1(2)
+; CHECK-P9-AIX-NEXT:    lxvx 35, 0, 3
+; CHECK-P9-AIX-NEXT:    bl .fmodf128[PR]
+; CHECK-P9-AIX-NEXT:    nop
+; CHECK-P9-AIX-NEXT:    addi 1, 1, 64
+; CHECK-P9-AIX-NEXT:    lwz 0, 8(1)
+; CHECK-P9-AIX-NEXT:    mtlr 0
+; CHECK-P9-AIX-NEXT:    blr
 entry:
   %0 = load fp128, fp128* @a, align 16
   %1 = load fp128, fp128* @b, align 16
   %rem = frem fp128 %0, %1
   ret fp128 %rem
 }
 
 define dso_local void @qpCeil(fp128* nocapture readonly %a, fp128* nocapture %res) {

 ; CHECK-P8-NEXT:    bl ceilf128
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    stvx v2, 0, r30
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-AIX-LABEL: qpCeil:
+; CHECK-P9-AIX:       # %bb.0: # %entry
+; CHECK-P9-AIX-NEXT:    lxv 34, 0(3)
+; CHECK-P9-AIX-NEXT:    xsrqpi 1, 2, 2, 2
+; CHECK-P9-AIX-NEXT:    stxv 34, 0(4)
+; CHECK-P9-AIX-NEXT:    blr
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = tail call fp128 @llvm.ceil.f128(fp128 %0)
   store fp128 %1, fp128* %res, align 16
   ret void
 }
 declare fp128 @llvm.ceil.f128(fp128 %Val)
 

 ; CHECK-P8-NEXT:    bl floorf128
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    stvx v2, 0, r30
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-AIX-LABEL: qpFloor:
+; CHECK-P9-AIX:       # %bb.0: # %entry
+; CHECK-P9-AIX-NEXT:    lxv 34, 0(3)
+; CHECK-P9-AIX-NEXT:    xsrqpi 1, 2, 2, 3
+; CHECK-P9-AIX-NEXT:    stxv 34, 0(4)
+; CHECK-P9-AIX-NEXT:    blr
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = tail call fp128 @llvm.floor.f128(fp128 %0)
   store fp128 %1, fp128* %res, align 16
   ret void
 }
 declare fp128 @llvm.floor.f128(fp128 %Val)
 

 ; CHECK-P8-NEXT:    bl truncf128
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    stvx v2, 0, r30
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-AIX-LABEL: qpTrunc:
+; CHECK-P9-AIX:       # %bb.0: # %entry
+; CHECK-P9-AIX-NEXT:    lxv 34, 0(3)
+; CHECK-P9-AIX-NEXT:    xsrqpi 1, 2, 2, 1
+; CHECK-P9-AIX-NEXT:    stxv 34, 0(4)
+; CHECK-P9-AIX-NEXT:    blr
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = tail call fp128 @llvm.trunc.f128(fp128 %0)
   store fp128 %1, fp128* %res, align 16
   ret void
 }
 declare fp128 @llvm.trunc.f128(fp128 %Val)
 

 ; CHECK-P8-NEXT:    bl roundf128
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    stvx v2, 0, r30
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-AIX-LABEL: qpRound:
+; CHECK-P9-AIX:       # %bb.0: # %entry
+; CHECK-P9-AIX-NEXT:    lxv 34, 0(3)
+; CHECK-P9-AIX-NEXT:    xsrqpi 0, 2, 2, 0
+; CHECK-P9-AIX-NEXT:    stxv 34, 0(4)
+; CHECK-P9-AIX-NEXT:    blr
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = tail call fp128 @llvm.round.f128(fp128 %0)
   store fp128 %1, fp128* %res, align 16
   ret void
 }
 declare fp128 @llvm.round.f128(fp128 %Val)
 

 ; CHECK-P8-NEXT:    bl lroundf128
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    stw r3, 0(r30)
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-AIX-LABEL: qpLRound:
+; CHECK-P9-AIX:       # %bb.0: # %entry
+; CHECK-P9-AIX-NEXT:    mflr 0
+; CHECK-P9-AIX-NEXT:    stw 0, 8(1)
+; CHECK-P9-AIX-NEXT:    stwu 1, -64(1)
+; CHECK-P9-AIX-NEXT:    lxv 34, 0(3)
+; CHECK-P9-AIX-NEXT:    stw 30, 56(1) # 4-byte Folded Spill
+; CHECK-P9-AIX-NEXT:    mr 30, 4
+; CHECK-P9-AIX-NEXT:    bl .lroundf128[PR]
+; CHECK-P9-AIX-NEXT:    nop
+; CHECK-P9-AIX-NEXT:    stw 3, 0(30)
+; CHECK-P9-AIX-NEXT:    lwz 30, 56(1) # 4-byte Folded Reload
+; CHECK-P9-AIX-NEXT:    addi 1, 1, 64
+; CHECK-P9-AIX-NEXT:    lwz 0, 8(1)
+; CHECK-P9-AIX-NEXT:    mtlr 0
+; CHECK-P9-AIX-NEXT:    blr
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = tail call i32 @llvm.lround.f128(fp128 %0)
   store i32 %1, i32* %res, align 16
   ret void
 }
 declare i32 @llvm.lround.f128(fp128 %Val)
 

 ; CHECK-P8-NEXT:    bl llroundf128
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    std r3, 0(r30)
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-AIX-LABEL: qpLLRound:
+; CHECK-P9-AIX:       # %bb.0: # %entry
+; CHECK-P9-AIX-NEXT:    mflr 0
+; CHECK-P9-AIX-NEXT:    stw 0, 8(1)
+; CHECK-P9-AIX-NEXT:    stwu 1, -64(1)
+; CHECK-P9-AIX-NEXT:    lxv 34, 0(3)
+; CHECK-P9-AIX-NEXT:    stw 30, 56(1) # 4-byte Folded Spill
+; CHECK-P9-AIX-NEXT:    mr 30, 4
+; CHECK-P9-AIX-NEXT:    bl .llroundf128[PR]
+; CHECK-P9-AIX-NEXT:    nop
+; CHECK-P9-AIX-NEXT:    stw 4, 4(30)
+; CHECK-P9-AIX-NEXT:    stw 3, 0(30)
+; CHECK-P9-AIX-NEXT:    lwz 30, 56(1) # 4-byte Folded Reload
+; CHECK-P9-AIX-NEXT:    addi 1, 1, 64
+; CHECK-P9-AIX-NEXT:    lwz 0, 8(1)
+; CHECK-P9-AIX-NEXT:    mtlr 0
+; CHECK-P9-AIX-NEXT:    blr
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = tail call i64 @llvm.llround.f128(fp128 %0)
   store i64 %1, i64* %res, align 16
   ret void
 }
 declare i64 @llvm.llround.f128(fp128 %Val)
 

 ; CHECK-P8-NEXT:    bl rintf128
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    stvx v2, 0, r30
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-AIX-LABEL: qpRint:
+; CHECK-P9-AIX:       # %bb.0: # %entry
+; CHECK-P9-AIX-NEXT:    lxv 34, 0(3)
+; CHECK-P9-AIX-NEXT:    xsrqpix 0, 2, 2, 3
+; CHECK-P9-AIX-NEXT:    stxv 34, 0(4)
+; CHECK-P9-AIX-NEXT:    blr
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = tail call fp128 @llvm.rint.f128(fp128 %0)
   store fp128 %1, fp128* %res, align 16
   ret void
 }
 declare fp128 @llvm.rint.f128(fp128 %Val)
 

 ; CHECK-P8-NEXT:    bl lrintf128
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    stw r3, 0(r30)
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-AIX-LABEL: qpLRint:
+; CHECK-P9-AIX:       # %bb.0: # %entry
+; CHECK-P9-AIX-NEXT:    mflr 0
+; CHECK-P9-AIX-NEXT:    stw 0, 8(1)
+; CHECK-P9-AIX-NEXT:    stwu 1, -64(1)
+; CHECK-P9-AIX-NEXT:    lxv 34, 0(3)
+; CHECK-P9-AIX-NEXT:    stw 30, 56(1) # 4-byte Folded Spill
+; CHECK-P9-AIX-NEXT:    mr 30, 4
+; CHECK-P9-AIX-NEXT:    bl .lrintf128[PR]
+; CHECK-P9-AIX-NEXT:    nop
+; CHECK-P9-AIX-NEXT:    stw 3, 0(30)
+; CHECK-P9-AIX-NEXT:    lwz 30, 56(1) # 4-byte Folded Reload
+; CHECK-P9-AIX-NEXT:    addi 1, 1, 64
+; CHECK-P9-AIX-NEXT:    lwz 0, 8(1)
+; CHECK-P9-AIX-NEXT:    mtlr 0
+; CHECK-P9-AIX-NEXT:    blr
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = tail call i32 @llvm.lrint.f128(fp128 %0)
   store i32 %1, i32* %res, align 16
   ret void
 }
 declare i32 @llvm.lrint.f128(fp128 %Val)
 

 ; CHECK-P8-NEXT:    bl llrintf128
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    std r3, 0(r30)
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-AIX-LABEL: qpLLRint:
+; CHECK-P9-AIX:       # %bb.0: # %entry
+; CHECK-P9-AIX-NEXT:    mflr 0
+; CHECK-P9-AIX-NEXT:    stw 0, 8(1)
+; CHECK-P9-AIX-NEXT:    stwu 1, -64(1)
+; CHECK-P9-AIX-NEXT:    lxv 34, 0(3)
+; CHECK-P9-AIX-NEXT:    stw 30, 56(1) # 4-byte Folded Spill
+; CHECK-P9-AIX-NEXT:    mr 30, 4
+; CHECK-P9-AIX-NEXT:    bl .llrintf128[PR]
+; CHECK-P9-AIX-NEXT:    nop
+; CHECK-P9-AIX-NEXT:    stw 4, 4(30)
+; CHECK-P9-AIX-NEXT:    stw 3, 0(30)
+; CHECK-P9-AIX-NEXT:    lwz 30, 56(1) # 4-byte Folded Reload
+; CHECK-P9-AIX-NEXT:    addi 1, 1, 64
+; CHECK-P9-AIX-NEXT:    lwz 0, 8(1)
+; CHECK-P9-AIX-NEXT:    mtlr 0
+; CHECK-P9-AIX-NEXT:    blr
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = tail call i64 @llvm.llrint.f128(fp128 %0)
   store i64 %1, i64* %res, align 16
   ret void
 }
 declare i64 @llvm.llrint.f128(fp128 %Val)
 

 ; CHECK-P8-NEXT:    bl nearbyintf128
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    stvx v2, 0, r30
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-AIX-LABEL: qpNearByInt:
+; CHECK-P9-AIX:       # %bb.0: # %entry
+; CHECK-P9-AIX-NEXT:    lxv 34, 0(3)
+; CHECK-P9-AIX-NEXT:    xsrqpi 0, 2, 2, 3
+; CHECK-P9-AIX-NEXT:    stxv 34, 0(4)
+; CHECK-P9-AIX-NEXT:    blr
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = tail call fp128 @llvm.nearbyint.f128(fp128 %0)
   store fp128 %1, fp128* %res, align 16
   ret void
 }
 declare fp128 @llvm.nearbyint.f128(fp128 %Val)
 

 ; CHECK-P8-NEXT:    bl fmaf128
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    stvx v2, 0, r30
 ; CHECK-P8-NEXT:    addi r1, r1, 48
 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
+;
+; CHECK-P9-AIX-LABEL: qpFMA:
+; CHECK-P9-AIX:       # %bb.0: # %entry
+; CHECK-P9-AIX-NEXT:    lxv 34, 0(3)
+; CHECK-P9-AIX-NEXT:    lxv 35, 0(4)
+; CHECK-P9-AIX-NEXT:    lxv 36, 0(5)
+; CHECK-P9-AIX-NEXT:    xsmaddqp 4, 2, 3
+; CHECK-P9-AIX-NEXT:    stxv 36, 0(6)
+; CHECK-P9-AIX-NEXT:    blr
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = load fp128, fp128* %b, align 16
   %2 = load fp128, fp128* %c, align 16
   %3 = tail call fp128 @llvm.fma.f128(fp128 %0, fp128 %1, fp128 %2)
   store fp128 %3, fp128* %res, align 16
   ret void
 }
 declare fp128 @llvm.fma.f128(fp128, fp128, fp128)