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Differential D94459

[RISCV] Use vmerge.vim for llvm.riscv.vfmerge with a 0.0 scalar operand.
ClosedPublic

Authored by craig.topper on Jan 11 2021, 4:07 PM.

Details

Reviewers
evandro
HsiangKai
frasercrmck
Commits
rGa14040bd4d90: [RISCV] Use vmerge.vim for llvm.riscv.vfmerge with a 0.0 scalar operand.
Summary

We can use a 0 immediate to avoid needing to materialize 0 into
an FPR first.

Diff Detail

Event Timeline

craig.topper created this revision.Jan 11 2021, 4:07 PM
Herald added subscribers: NickHung, luismarques, apazos and 24 others. · View Herald TranscriptJan 11 2021, 4:07 PM
craig.topper requested review of this revision.Jan 11 2021, 4:07 PM
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Herald added a subscriber: MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B84774: Diff 315958.Jan 11 2021, 4:39 PM
frasercrmck accepted this revision.Jan 12 2021, 1:13 AM

LGTM.

This revision is now accepted and ready to land.Jan 12 2021, 1:13 AM
Closed by commit rGa14040bd4d90: [RISCV] Use vmerge.vim for llvm.riscv.vfmerge with a 0.0 scalar operand. (authored by craig.topper). · Explain WhyJan 12 2021, 11:10 AM
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rGa14040bd4d90: [RISCV] Use vmerge.vim for llvm.riscv.vfmerge with a 0.0 scalar operand..

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
8 lines
test/
CodeGen/
RISCV/
rvv/
154 lines
210 lines

Diff 316169

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Show First 20 Lines • Show All 3,361 Lines • ▼ Show 20 Lines
// 14.15. Vector Floating-Point Merge Instruction // 14.15. Vector Floating-Point Merge Instruction
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// We can use vmerge.vvm to support vector-vector vfmerge. // We can use vmerge.vvm to support vector-vector vfmerge.
defm "" : VPatBinaryV_VM<"int_riscv_vfmerge", "PseudoVMERGE", defm "" : VPatBinaryV_VM<"int_riscv_vfmerge", "PseudoVMERGE",
/*CarryOut = */0, /*vtilist=*/AllFloatVectors>; /*CarryOut = */0, /*vtilist=*/AllFloatVectors>;
defm "" : VPatBinaryV_XM<"int_riscv_vfmerge", "PseudoVFMERGE", defm "" : VPatBinaryV_XM<"int_riscv_vfmerge", "PseudoVFMERGE",
/*CarryOut = */0, /*vtilist=*/AllFloatVectors>; /*CarryOut = */0, /*vtilist=*/AllFloatVectors>;
foreach fvti = AllFloatVectors in {
defvar instr = !cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX);
def : Pat<(fvti.Vector (int_riscv_vfmerge (fvti.Vector fvti.RegClass:$rs2),
(fvti.Scalar (fpimm0)),
(fvti.Mask V0), (XLenVT GPR:$vl))),
(instr fvti.RegClass:$rs2, 0, (fvti.Mask V0), (NoX0 GPR:$vl), fvti.SEW)>;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 14.16. Vector Floating-Point Move Instruction // 14.16. Vector Floating-Point Move Instruction
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
foreach fvti = AllFloatVectors in { foreach fvti = AllFloatVectors in {
// If we're splatting fpimm0, use vmv.v.x vd, x0. // If we're splatting fpimm0, use vmv.v.x vd, x0.
def : Pat<(fvti.Vector (int_riscv_vfmv_v_f def : Pat<(fvti.Vector (int_riscv_vfmv_v_f
(fvti.Scalar (fpimm0)), GPR:$vl)), (fvti.Scalar (fpimm0)), GPR:$vl)),
(!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX) (!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX)
▲ Show 20 Lines • Show All 231 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll

Show First 20 Lines • Show All 433 Lines • ▼ Show 20 Lines; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0
%a = call <vscale x 16 x float> @llvm.riscv.vfmerge.nxv16f32.f32( %a = call <vscale x 16 x float> @llvm.riscv.vfmerge.nxv16f32.f32(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
float %1, float %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
define <vscale x 1 x half> @intrinsic_vfmerge_vzm_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv1f16_nxv1f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
%a = call <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16(
<vscale x 1 x half> %0,
half zeroinitializer,
<vscale x 1 x i1> %1,
i32 %2)
ret <vscale x 1 x half> %a
}
define <vscale x 2 x half> @intrinsic_vfmerge_vzm_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv2f16_nxv2f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
%a = call <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16(
<vscale x 2 x half> %0,
half zeroinitializer,
<vscale x 2 x i1> %1,
i32 %2)
ret <vscale x 2 x half> %a
}
define <vscale x 4 x half> @intrinsic_vfmerge_vzm_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv4f16_nxv4f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
%a = call <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16(
<vscale x 4 x half> %0,
half zeroinitializer,
<vscale x 4 x i1> %1,
i32 %2)
ret <vscale x 4 x half> %a
}
define <vscale x 8 x half> @intrinsic_vfmerge_vzm_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv8f16_nxv8f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
%a = call <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16(
<vscale x 8 x half> %0,
half zeroinitializer,
<vscale x 8 x i1> %1,
i32 %2)
ret <vscale x 8 x half> %a
}
define <vscale x 16 x half> @intrinsic_vfmerge_vzm_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv16f16_nxv16f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
%a = call <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16(
<vscale x 16 x half> %0,
half zeroinitializer,
<vscale x 16 x i1> %1,
i32 %2)
ret <vscale x 16 x half> %a
}
define <vscale x 32 x half> @intrinsic_vfmerge_vzm_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, <vscale x 32 x i1> %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv32f16_nxv32f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
%a = call <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16(
<vscale x 32 x half> %0,
half zeroinitializer,
<vscale x 32 x i1> %1,
i32 %2)
ret <vscale x 32 x half> %a
}
define <vscale x 1 x float> @intrinsic_vfmerge_vzm_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv1f32_nxv1f32_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
%a = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32(
<vscale x 1 x float> %0,
float zeroinitializer,
<vscale x 1 x i1> %1,
i32 %2)
ret <vscale x 1 x float> %a
}
define <vscale x 2 x float> @intrinsic_vfmerge_vzm_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv2f32_nxv2f32_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
%a = call <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.f32(
<vscale x 2 x float> %0,
float zeroinitializer,
<vscale x 2 x i1> %1,
i32 %2)
ret <vscale x 2 x float> %a
}
define <vscale x 4 x float> @intrinsic_vfmerge_vzm_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv4f32_nxv4f32_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
%a = call <vscale x 4 x float> @llvm.riscv.vfmerge.nxv4f32.f32(
<vscale x 4 x float> %0,
float zeroinitializer,
<vscale x 4 x i1> %1,
i32 %2)
ret <vscale x 4 x float> %a
}
define <vscale x 8 x float> @intrinsic_vfmerge_vzm_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv8f32_nxv8f32_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
%a = call <vscale x 8 x float> @llvm.riscv.vfmerge.nxv8f32.f32(
<vscale x 8 x float> %0,
float zeroinitializer,
<vscale x 8 x i1> %1,
i32 %2)
ret <vscale x 8 x float> %a
}
define <vscale x 16 x float> @intrinsic_vfmerge_vzm_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv16f32_nxv16f32_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
%a = call <vscale x 16 x float> @llvm.riscv.vfmerge.nxv16f32.f32(
<vscale x 16 x float> %0,
float zeroinitializer,
<vscale x 16 x i1> %1,
i32 %2)
ret <vscale x 16 x float> %a
}

llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll

Show First 20 Lines • Show All 593 Lines • ▼ Show 20 Lines; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0
%a = call <vscale x 8 x double> @llvm.riscv.vfmerge.nxv8f64.f64( %a = call <vscale x 8 x double> @llvm.riscv.vfmerge.nxv8f64.f64(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
double %1, double %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
define <vscale x 1 x half> @intrinsic_vfmerge_vzm_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv1f16_nxv1f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
%a = call <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16(
<vscale x 1 x half> %0,
half zeroinitializer,
<vscale x 1 x i1> %1,
i64 %2)
ret <vscale x 1 x half> %a
}
define <vscale x 2 x half> @intrinsic_vfmerge_vzm_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv2f16_nxv2f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
%a = call <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16(
<vscale x 2 x half> %0,
half zeroinitializer,
<vscale x 2 x i1> %1,
i64 %2)
ret <vscale x 2 x half> %a
}
define <vscale x 4 x half> @intrinsic_vfmerge_vzm_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv4f16_nxv4f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
%a = call <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16(
<vscale x 4 x half> %0,
half zeroinitializer,
<vscale x 4 x i1> %1,
i64 %2)
ret <vscale x 4 x half> %a
}
define <vscale x 8 x half> @intrinsic_vfmerge_vzm_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv8f16_nxv8f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
%a = call <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16(
<vscale x 8 x half> %0,
half zeroinitializer,
<vscale x 8 x i1> %1,
i64 %2)
ret <vscale x 8 x half> %a
}
define <vscale x 16 x half> @intrinsic_vfmerge_vzm_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv16f16_nxv16f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
%a = call <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16(
<vscale x 16 x half> %0,
half zeroinitializer,
<vscale x 16 x i1> %1,
i64 %2)
ret <vscale x 16 x half> %a
}
define <vscale x 32 x half> @intrinsic_vfmerge_vzm_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv32f16_nxv32f16_f16
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
%a = call <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16(
<vscale x 32 x half> %0,
half zeroinitializer,
<vscale x 32 x i1> %1,
i64 %2)
ret <vscale x 32 x half> %a
}
define <vscale x 1 x float> @intrinsic_vfmerge_vzm_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv1f32_nxv1f32_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
%a = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32(
<vscale x 1 x float> %0,
float zeroinitializer,
<vscale x 1 x i1> %1,
i64 %2)
ret <vscale x 1 x float> %a
}
define <vscale x 2 x float> @intrinsic_vfmerge_vzm_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv2f32_nxv2f32_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
%a = call <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.f32(
<vscale x 2 x float> %0,
float zeroinitializer,
<vscale x 2 x i1> %1,
i64 %2)
ret <vscale x 2 x float> %a
}
define <vscale x 4 x float> @intrinsic_vfmerge_vzm_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv4f32_nxv4f32_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
%a = call <vscale x 4 x float> @llvm.riscv.vfmerge.nxv4f32.f32(
<vscale x 4 x float> %0,
float zeroinitializer,
<vscale x 4 x i1> %1,
i64 %2)
ret <vscale x 4 x float> %a
}
define <vscale x 8 x float> @intrinsic_vfmerge_vzm_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv8f32_nxv8f32_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
%a = call <vscale x 8 x float> @llvm.riscv.vfmerge.nxv8f32.f32(
<vscale x 8 x float> %0,
float zeroinitializer,
<vscale x 8 x i1> %1,
i64 %2)
ret <vscale x 8 x float> %a
}
define <vscale x 16 x float> @intrinsic_vfmerge_vzm_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv16f32_nxv16f32_f32
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
%a = call <vscale x 16 x float> @llvm.riscv.vfmerge.nxv16f32.f32(
<vscale x 16 x float> %0,
float zeroinitializer,
<vscale x 16 x i1> %1,
i64 %2)
ret <vscale x 16 x float> %a
}
define <vscale x 1 x double> @intrinsic_vfmerge_vzm_nxv1f64_nxv1f64_f64(<vscale x 1 x double> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv1f64_nxv1f64_f64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
%a = call <vscale x 1 x double> @llvm.riscv.vfmerge.nxv1f64.f64(
<vscale x 1 x double> %0,
double zeroinitializer,
<vscale x 1 x i1> %1,
i64 %2)
ret <vscale x 1 x double> %a
}
define <vscale x 2 x double> @intrinsic_vfmerge_vzm_nxv2f64_nxv2f64_f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv2f64_nxv2f64_f64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
%a = call <vscale x 2 x double> @llvm.riscv.vfmerge.nxv2f64.f64(
<vscale x 2 x double> %0,
double zeroinitializer,
<vscale x 2 x i1> %1,
i64 %2)
ret <vscale x 2 x double> %a
}
define <vscale x 4 x double> @intrinsic_vfmerge_vzm_nxv4f64_nxv4f64_f64(<vscale x 4 x double> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv4f64_nxv4f64_f64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
%a = call <vscale x 4 x double> @llvm.riscv.vfmerge.nxv4f64.f64(
<vscale x 4 x double> %0,
double zeroinitializer,
<vscale x 4 x i1> %1,
i64 %2)
ret <vscale x 4 x double> %a
}
define <vscale x 8 x double> @intrinsic_vfmerge_vzm_nxv8f64_nxv8f64_f64(<vscale x 8 x double> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
entry:
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv8f64_nxv8f64_f64
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
%a = call <vscale x 8 x double> @llvm.riscv.vfmerge.nxv8f64.f64(
<vscale x 8 x double> %0,
double zeroinitializer,
<vscale x 8 x i1> %1,
i64 %2)
ret <vscale x 8 x double> %a
}