[AArch64][GlobalISel] Add support for FCONSTANT of FP128 type

[Asif]

Summary

Add support for G_FCONSTANT of FP128 (Quadruple precision) type.
It replaces the constant by emitting a load with a constant pool entry.

[arsenm]

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

2318–2319

Why not just fix this?

2321

You can do isExactlyValue directly on getFPImm

[Asif]

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

2318–2319

I haven't worked with the tablegen before. Please point to the source files so I can look into it and fix it.

[arsenm]

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

2318–2319

I think the way this is working differs from the DAG entirely. I think the DAG is emitting constant pool loads earlier and not directly selecting them

[aemerson]

LGTM with the getFPImm nit fixed.

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

bool AArch64InstructionSelector::select(MachineInstr &I) {
   case TargetOpcode::G_FCONSTANT:
   case TargetOpcode::G_CONSTANT: {
     const bool isFP = Opcode == TargetOpcode::G_FCONSTANT;
 
     const LLT s8 = LLT::scalar(8);
     const LLT s16 = LLT::scalar(16);
     const LLT s32 = LLT::scalar(32);
     const LLT s64 = LLT::scalar(64);
+    const LLT s128 = LLT::scalar(128);
     const LLT p0 = LLT::pointer(0, 64);
 
     const Register DefReg = I.getOperand(0).getReg();
     const LLT DefTy = MRI.getType(DefReg);
     const unsigned DefSize = DefTy.getSizeInBits();
     const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
 
     // FIXME: Redundant check, but even less readable when factored out.
     if (isFP) {
-      if (Ty != s32 && Ty != s64) {
+      if (Ty != s32 && Ty != s64 && Ty != s128) {
         LLVM_DEBUG(dbgs() << "Unable to materialize FP " << Ty
                           << " constant, expected: " << s32 << " or " << s64
-                          << '\n');
+                          << " or " << s128 << '\n');
         return false;
       }
 
       if (RB.getID() != AArch64::FPRRegBankID) {
         LLVM_DEBUG(dbgs() << "Unable to materialize FP " << Ty
                           << " constant on bank: " << RB
                           << ", expected: FPR\n");
         return false;
       }
 
       // The case when we have 0.0 is covered by tablegen. Reject it here so we
       // can be sure tablegen works correctly and isn't rescued by this code.
-      if (I.getOperand(1).getFPImm()->getValueAPF().isExactlyValue(0.0))
+      // 0.0 is not covered by tablegen for FP128. So we will handle this 
+      // scenario in the code here.
+      if (DefSize != 128 && 
+          I.getOperand(1).getFPImm()->getValueAPF().isExactlyValue(0.0))
         return false;
     } else {
       // s32 and s64 are covered by tablegen.
       if (Ty != p0 && Ty != s8 && Ty != s16) {
         LLVM_DEBUG(dbgs() << "Unable to materialize integer " << Ty
                           << " constant, expected: " << s32 << ", " << s64
                           << ", or " << p0 << '\n');
         return false;
case TargetOpcode::G_CONSTANT: {
     // We allow G_CONSTANT of types < 32b.
     const unsigned MovOpc =
         DefSize == 64 ? AArch64::MOVi64imm : AArch64::MOVi32imm;
 
     if (isFP) {
       // Either emit a FMOV, or emit a copy to emit a normal mov.
       const TargetRegisterClass &GPRRC =
           DefSize == 32 ? AArch64::GPR32RegClass : AArch64::GPR64RegClass;
-      const TargetRegisterClass &FPRRC =
-          DefSize == 32 ? AArch64::FPR32RegClass : AArch64::FPR64RegClass;
+      const TargetRegisterClass &FPRRC = 
+          DefSize == 32 ? AArch64::FPR32RegClass 
+                        : (DefSize == 64 ? AArch64::FPR64RegClass 
+                                         : AArch64::FPR128RegClass);
 
       // Can we use a FMOV instruction to represent the immediate?
       if (emitFMovForFConstant(I, MRI))
         return true;
 
       // For 64b values, emit a constant pool load instead.
-      if (DefSize == 64) {
+      if (DefSize == 64 || DefSize == 128) {
         auto *FPImm = I.getOperand(1).getFPImm();
         MachineIRBuilder MIB(I);
         auto *LoadMI = emitLoadFromConstantPool(FPImm, MIB);
         if (!LoadMI) {
           LLVM_DEBUG(dbgs() << "Failed to load double constant pool entry\n");
           return false;
         }
         MIB.buildCopy({DefReg}, {LoadMI->getOperand(0).getReg()});

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

getActionDefinitionsBuilder(G_CONSTANT)
       .legalFor({p0, s8, s16, s32, s64})
       .clampScalar(0, s8, s64)
       .widenScalarToNextPow2(0);
   getActionDefinitionsBuilder(G_FCONSTANT)
       .legalIf([=](const LegalityQuery &Query) {
         const auto &Ty = Query.Types[0];
         if (HasFP16 && Ty == s16)
           return true;
-        return Ty == s32 || Ty == s64;
+        return Ty == s32 || Ty == s64 || Ty == s128;
       })
-      .clampScalar(0, MinFPScalar, s64);
+      .clampScalar(0, MinFPScalar, s128);
 
   getActionDefinitionsBuilder({G_ICMP, G_FCMP})
       .legalFor({{s32, s32},
                  {s32, s64},
                  {s32, p0},
                  {v4s32, v4s32},
                  {v2s32, v2s32},
                  {v2s64, v2s64},

llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll

 define void @test_write_register_intrin() {
   call void @llvm.write_register.i64(metadata !{!"sp"}, i64 0)
   ret void
 }
 
 @_ZTIi = external global i8*
 declare i32 @__gxx_personality_v0(...)
 
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %0:_(s128) = G_FCONSTANT fp128 0xL00000000000000004000000000000000
-; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for test_quad_dump
-; FALLBACK-WITH-REPORT-OUT-LABEL: test_quad_dump:
-define fp128 @test_quad_dump() {
-  ret fp128 0xL00000000000000004000000000000000
-}
-
 ; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %2:_(<2 x p0>) = G_INSERT_VECTOR_ELT %0:_, %{{[0-9]+}}:_(p0), %{{[0-9]+}}:_(s32) (in function: vector_of_pointers_insertelement)
 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for vector_of_pointers_insertelement
 ; FALLBACK-WITH-REPORT-OUT-LABEL: vector_of_pointers_insertelement:
 define void @vector_of_pointers_insertelement() {
   br label %end
 
 block:
   %dummy = insertelement <2 x i16*> %vec, i16* null, i32 0

llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp128-fconstant.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+...
+---
+name:            fp128-fconstant
+alignment:       16
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: fp128-fconstant
+    ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
+    ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
+    ; CHECK: $q0 = COPY [[LDRQui]]
+    ; CHECK: RET_ReallyLR implicit $q0
+    %0:fpr(s128) = G_FCONSTANT fp128 0xL00000000000000000000000000000000
+    $q0 = COPY %0:fpr(s128)
+    RET_ReallyLR implicit $q0
+...
+