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Differential D94162

[PowerPC] Add variants of 64-bit vector types for vec_sel.
ClosedPublic

Authored by Esme on Jan 6 2021, 2:28 AM.

Details

Reviewers
steven.zhang
nemanjai
qiucf
shchenz
Group Reviewers
Restricted Project
Commits
rGffa67873a3f9: [PowerPC] Add variants of 64-bit vector types for vec_sel.
Summary

This patch added the following variants of vec_sel.

vector bool long long
vec_sel(vector bool long long
        vector bool long long,
        vector bool long long);

vector bool long long
vec_sel(vector bool long long
        vector bool long long,
        vector unsigned long long);

vector signed long long
vec_sel(vector signed long long
        vector signed long long,
        vector bool long long);

vector signed long long
vec_sel(vector signed long long
        vector signed long long,
        vector unsigned long long);

vector unsigned long long
vec_sel(vector unsigned long long
        vector unsigned long long,
        vector bool long long);

vector unsigned long long
vec_sel(vector unsigned long long
        vector unsigned long long,
        vector unsigned long long);

It fixed https://bugs.llvm.org/show_bug.cgi?id=46770

Diff Detail

Event Timeline

Esme created this revision.Jan 6 2021, 2:28 AM
Herald added a subscriber: kbarton. · View Herald TranscriptJan 6 2021, 2:28 AM
Esme requested review of this revision.Jan 6 2021, 2:28 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 6 2021, 2:28 AM
Herald added a subscriber: cfe-commits. · View Herald Transcript
Harbormaster completed remote builds in B84176: Diff 314829.Jan 6 2021, 3:09 AM
qiucf added a comment.Jan 7 2021, 8:10 AM
This comment was removed by qiucf.
steven.zhang edited the summary of this revision. (Show Details)Jan 7 2021, 6:18 PM
nemanjai accepted this revision.Jan 8 2021, 3:02 AM

Kind of bizarre that we missed these, thanks for adding them. LGTM.

This revision is now accepted and ready to land.Jan 8 2021, 3:02 AM
This revision was landed with ongoing or failed builds.Jan 10 2021, 7:56 PM
Closed by commit rGffa67873a3f9: [PowerPC] Add variants of 64-bit vector types for vec_sel. (authored by Esme). · Explain Why
This revision was automatically updated to reflect the committed changes.
Esme added a commit: rGffa67873a3f9: [PowerPC] Add variants of 64-bit vector types for vec_sel..

Revision Contents

PathSize
clang/
lib/
Headers/
40 lines
test/
CodeGen/
60 lines

Diff 315696

clang/lib/Headers/altivec.h

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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} }
static __inline__ vector double __ATTRS_o_ai static __inline__ vector double __ATTRS_o_ai
vec_sel(vector double __a, vector double __b, vector unsigned long long __c) { vec_sel(vector double __a, vector double __b, vector unsigned long long __c) {
vector long long __res = ((vector long long)__a & ~(vector long long)__c) | vector long long __res = ((vector long long)__a & ~(vector long long)__c) |
((vector long long)__b & (vector long long)__c); ((vector long long)__b & (vector long long)__c);
return (vector double)__res; return (vector double)__res;
} }
static __inline__ vector bool long long __ATTRS_o_ai
vec_sel(vector bool long long __a, vector bool long long __b,
vector bool long long __c) {
return (__a & ~__c) | (__b & __c);
}
static __inline__ vector bool long long __ATTRS_o_ai
vec_sel(vector bool long long __a, vector bool long long __b,
vector unsigned long long __c) {
return (__a & ~(vector bool long long)__c) |
(__b & (vector bool long long)__c);
}
static __inline__ vector signed long long __ATTRS_o_ai
vec_sel(vector signed long long __a, vector signed long long __b,
vector bool long long __c) {
return (__a & ~(vector signed long long)__c) |
(__b & (vector signed long long)__c);
}
static __inline__ vector signed long long __ATTRS_o_ai
vec_sel(vector signed long long __a, vector signed long long __b,
vector unsigned long long __c) {
return (__a & ~(vector signed long long)__c) |
(__b & (vector signed long long)__c);
}
static __inline__ vector unsigned long long __ATTRS_o_ai
vec_sel(vector unsigned long long __a, vector unsigned long long __b,
vector bool long long __c) {
return (__a & ~(vector unsigned long long)__c) |
(__b & (vector unsigned long long)__c);
}
static __inline__ vector unsigned long long __ATTRS_o_ai
vec_sel(vector unsigned long long __a, vector unsigned long long __b,
vector unsigned long long __c) {
return (__a & ~__c) | (__b & __c);
}
#endif #endif
/* vec_vsel */ /* vec_vsel */
static __inline__ vector signed char __ATTRS_o_ai vec_vsel( static __inline__ vector signed char __ATTRS_o_ai vec_vsel(
vector signed char __a, vector signed char __b, vector unsigned char __c) { vector signed char __a, vector signed char __b, vector unsigned char __c) {
return (__a & ~(vector signed char)__c) | (__b & (vector signed char)__c); return (__a & ~(vector signed char)__c) | (__b & (vector signed char)__c);
} }
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clang/test/CodeGen/builtins-ppc-vsx.c

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// CHECK: or <2 x i64> // CHECK: or <2 x i64>
// CHECK: bitcast <2 x i64> %{{[0-9]+}} to <2 x double> // CHECK: bitcast <2 x i64> %{{[0-9]+}} to <2 x double>
// CHECK-LE: xor <2 x i64> %{{[0-9]+}}, <i64 -1, i64 -1> // CHECK-LE: xor <2 x i64> %{{[0-9]+}}, <i64 -1, i64 -1>
// CHECK-LE: and <2 x i64> %{{[0-9]+}}, // CHECK-LE: and <2 x i64> %{{[0-9]+}},
// CHECK-LE: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}} // CHECK-LE: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
// CHECK-LE: or <2 x i64> // CHECK-LE: or <2 x i64>
// CHECK-LE: bitcast <2 x i64> %{{[0-9]+}} to <2 x double> // CHECK-LE: bitcast <2 x i64> %{{[0-9]+}} to <2 x double>
res_vbll = vec_sel(vbll, vbll, vbll);
// CHECK: xor <2 x i64> %{{[0-9]+}}, <i64 -1, i64 -1>
// CHECK: and <2 x i64> %{{[0-9]+}},
// CHECK: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
// CHECK: or <2 x i64>
// CHECK-LE: xor <2 x i64> %{{[0-9]+}}, <i64 -1, i64 -1>
// CHECK-LE: and <2 x i64> %{{[0-9]+}},
// CHECK-LE: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
// CHECK-LE: or <2 x i64>
res_vbll = vec_sel(vbll, vbll, vull);
// CHECK: xor <2 x i64> %{{[0-9]+}}, <i64 -1, i64 -1>
// CHECK: and <2 x i64> %{{[0-9]+}},
// CHECK: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
// CHECK: or <2 x i64>
// CHECK-LE: xor <2 x i64> %{{[0-9]+}}, <i64 -1, i64 -1>
// CHECK-LE: and <2 x i64> %{{[0-9]+}},
// CHECK-LE: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
// CHECK-LE: or <2 x i64>
res_vsll = vec_sel(vsll, vsll, vbll);
// CHECK: xor <2 x i64> %{{[0-9]+}}, <i64 -1, i64 -1>
// CHECK: and <2 x i64> %{{[0-9]+}},
// CHECK: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
// CHECK: or <2 x i64>
// CHECK-LE: xor <2 x i64> %{{[0-9]+}}, <i64 -1, i64 -1>
// CHECK-LE: and <2 x i64> %{{[0-9]+}},
// CHECK-LE: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
// CHECK-LE: or <2 x i64>
res_vsll = vec_sel(vsll, vsll, vull);
// CHECK: xor <2 x i64> %{{[0-9]+}}, <i64 -1, i64 -1>
// CHECK: and <2 x i64> %{{[0-9]+}},
// CHECK: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
// CHECK: or <2 x i64>
// CHECK-LE: xor <2 x i64> %{{[0-9]+}}, <i64 -1, i64 -1>
// CHECK-LE: and <2 x i64> %{{[0-9]+}},
// CHECK-LE: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
// CHECK-LE: or <2 x i64>
res_vull = vec_sel(vull, vull, vbll);
// CHECK: xor <2 x i64> %{{[0-9]+}}, <i64 -1, i64 -1>
// CHECK: and <2 x i64> %{{[0-9]+}},
// CHECK: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
// CHECK: or <2 x i64>
// CHECK-LE: xor <2 x i64> %{{[0-9]+}}, <i64 -1, i64 -1>
// CHECK-LE: and <2 x i64> %{{[0-9]+}},
// CHECK-LE: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
// CHECK-LE: or <2 x i64>
res_vull = vec_sel(vull, vull, vull);
// CHECK: xor <2 x i64> %{{[0-9]+}}, <i64 -1, i64 -1>
// CHECK: and <2 x i64> %{{[0-9]+}},
// CHECK: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
// CHECK: or <2 x i64>
// CHECK-LE: xor <2 x i64> %{{[0-9]+}}, <i64 -1, i64 -1>
// CHECK-LE: and <2 x i64> %{{[0-9]+}},
// CHECK-LE: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
// CHECK-LE: or <2 x i64>
res_vf = vec_sqrt(vf); res_vf = vec_sqrt(vf);
// CHECK: call <4 x float> @llvm.sqrt.v4f32(<4 x float> %{{[0-9]+}}) // CHECK: call <4 x float> @llvm.sqrt.v4f32(<4 x float> %{{[0-9]+}})
// CHECK-LE: call <4 x float> @llvm.sqrt.v4f32(<4 x float> %{{[0-9]+}}) // CHECK-LE: call <4 x float> @llvm.sqrt.v4f32(<4 x float> %{{[0-9]+}})
res_vd = vec_sqrt(vd); res_vd = vec_sqrt(vd);
// CHECK: call <2 x double> @llvm.sqrt.v2f64(<2 x double> %{{[0-9]+}}) // CHECK: call <2 x double> @llvm.sqrt.v2f64(<2 x double> %{{[0-9]+}})
// CHECK-LE: call <2 x double> @llvm.sqrt.v2f64(<2 x double> %{{[0-9]+}}) // CHECK-LE: call <2 x double> @llvm.sqrt.v2f64(<2 x double> %{{[0-9]+}})
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