[RISCV] Add a partial test of vector sadd.overflow to demonstrate intrinsics with multiple scalable vector results.

[craig.topper]

Summary

This builds on D94142 where scalable vectors are allowed in structs.

This test is incomplete because our isel patterns aren't ready
for the comparisons needed for overflow checking yet. See the FIXME.

I did have to fix one scalable vector issue in the vector type
creation for these intrinsics.

[frasercrmck]

I was actually going to take the time today/tomorrow to push a patch with what I have for setcc for review. Is that all you need to get on your way to better support for the overflow result?

[craig.topper]

I've committed a modified version of this patch that uses both results.

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

case Intrinsic::smul_with_overflow: {
     }
     SDValue Op1 = getValue(I.getArgOperand(0));
     SDValue Op2 = getValue(I.getArgOperand(1));
 
     EVT ResultVT = Op1.getValueType();
     EVT OverflowVT = MVT::i1;
     if (ResultVT.isVector())
       OverflowVT = EVT::getVectorVT(
-          *Context, OverflowVT, ResultVT.getVectorNumElements());
+          *Context, OverflowVT, ResultVT.getVectorElementCount());
 
     SDVTList VTs = DAG.getVTList(ResultVT, OverflowVT);
     setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
     return;
   }
   case Intrinsic::prefetch: {
     SDValue Ops[5];
     unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();

llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+declare { <vscale x 2 x i32>, <vscale x 2 x i1> } @llvm.sadd.with.overflow.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32>)
+
+define <vscale x 2 x i32> @saddo_nvx2i32(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y) {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmslt.vx v25, v17, zero
+; CHECK-NEXT:    vadd.vv v26, v16, v17
+; CHECK-NEXT:    vmslt.vv v27, v26, v16
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vmxor.mm v0, v25, v27
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmerge.vim v16, v26, 0, v0
+; CHECK-NEXT:    ret
+  %a = call { <vscale x 2 x i32>, <vscale x 2 x i1> } @llvm.sadd.with.overflow.nxv2i32(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y)
+  %b = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i1> } %a, 0
+  %c = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i1> } %a, 1
+  %d = select <vscale x 2 x i1> %c, <vscale x 2 x i32> zeroinitializer, <vscale x 2 x i32> %b
+  ret <vscale x 2 x i32> %d
+}