[AMDGPU] Handle v_fmac_legacy_f32 in SIFoldOperands

[foad]

Summary

Convert it to v_fma_legacy_f32 if it is profitable to do so, just like
other mac instructions that are converted to their mad equivalents.

[foad]

The point of this patch is to remove some unnecessary movs around the v_fma(c)_legacy_f32 instructions. I can pre-commit the new test case to make this clearer if you're happy with it.

[arsenm]

LGTM but another MIR test wouldn't hurt

llvm/lib/Target/AMDGPU/SIFoldOperands.cpp

static unsigned macToMad(unsigned Opc) {
   case AMDGPU::V_MAC_F32_e64:
     return AMDGPU::V_MAD_F32;
   case AMDGPU::V_MAC_F16_e64:
     return AMDGPU::V_MAD_F16;
   case AMDGPU::V_FMAC_F32_e64:
     return AMDGPU::V_FMA_F32;
   case AMDGPU::V_FMAC_F16_e64:
     return AMDGPU::V_FMA_F16_gfx9;
+  case AMDGPU::V_FMAC_LEGACY_F32_e64:
+    return AMDGPU::V_FMA_LEGACY_F32;
   }
   return AMDGPU::INSTRUCTION_LIST_END;
 }
 
 // Wrapper around isInlineConstant that understands special cases when
 // instruction types are replaced during operand folding.
 static bool isInlineConstantIfFolded(const SIInstrInfo *TII,
                                      const MachineInstr &UseMI,

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll

 ; SDAG-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x430
 ; SDAG-NEXT:    v_interp_p1_f32_e32 v2, v0, attr0.x
 ; SDAG-NEXT:    v_interp_p1_f32_e32 v3, v0, attr0.y
 ; SDAG-NEXT:    s_mov_b32 s4, s6
 ; SDAG-NEXT:    v_interp_p2_f32_e32 v2, v1, attr0.x
 ; SDAG-NEXT:    v_interp_p2_f32_e32 v3, v1, attr0.y
 ; SDAG-NEXT:    s_and_b32 exec_lo, exec_lo, s16
 ; SDAG-NEXT:    s_waitcnt lgkmcnt(0)
-; SDAG-NEXT:    image_sample v[7:10], v[2:3], s[8:15], s[0:3] dmask:0xf dim:SQ_RSRC_IMG_2D
-; SDAG-NEXT:    v_mov_b32_e32 v4, -1.0
-; SDAG-NEXT:    v_mov_b32_e32 v5, -1.0
+; SDAG-NEXT:    image_sample v[0:3], v[2:3], s[8:15], s[0:3] dmask:0xf dim:SQ_RSRC_IMG_2D
 ; SDAG-NEXT:    s_waitcnt vmcnt(0)
-; SDAG-NEXT:    v_fmac_legacy_f32_e64 v4, v7, 2.0
-; SDAG-NEXT:    v_fmac_legacy_f32_e64 v5, v8, 2.0
-; SDAG-NEXT:    v_mov_b32_e32 v2, v9
-; SDAG-NEXT:    v_mov_b32_e32 v3, v10
-; SDAG-NEXT:    v_mov_b32_e32 v0, v4
-; SDAG-NEXT:    v_mov_b32_e32 v1, v5
+; SDAG-NEXT:    v_fma_legacy_f32 v0, v0, 2.0, -1.0
+; SDAG-NEXT:    v_fma_legacy_f32 v1, v1, 2.0, -1.0
 ; SDAG-NEXT:    ; return to shader part epilog
 ;
 ; GISEL-LABEL: main:
 ; GISEL:       ; %bb.0:
 ; GISEL-NEXT:    s_mov_b32 s16, exec_lo
 ; GISEL-NEXT:    s_mov_b32 s4, s6
 ; GISEL-NEXT:    s_mov_b32 m0, s7
 ; GISEL-NEXT:    s_wqm_b32 exec_lo, exec_lo
 ; GISEL-NEXT:    s_add_u32 s0, s5, 0x400
 ; GISEL-NEXT:    s_mov_b32 s1, 0
 ; GISEL-NEXT:    v_interp_p1_f32_e32 v3, v0, attr0.y
 ; GISEL-NEXT:    s_load_dwordx8 s[8:15], s[0:1], 0x0
 ; GISEL-NEXT:    s_add_u32 s0, s5, 0x430
 ; GISEL-NEXT:    v_mov_b32_e32 v14, v2
 ; GISEL-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x0
 ; GISEL-NEXT:    v_interp_p1_f32_e32 v2, v0, attr0.x
 ; GISEL-NEXT:    v_interp_p2_f32_e32 v3, v1, attr0.y
 ; GISEL-NEXT:    v_interp_p2_f32_e32 v2, v1, attr0.x
 ; GISEL-NEXT:    s_and_b32 exec_lo, exec_lo, s16
 ; GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; GISEL-NEXT:    image_sample v[7:10], v[2:3], s[8:15], s[0:3] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GISEL-NEXT:    v_mov_b32_e32 v4, -1.0
-; GISEL-NEXT:    v_mov_b32_e32 v5, -1.0
+; GISEL-NEXT:    image_sample v[0:3], v[2:3], s[8:15], s[0:3] dmask:0xf dim:SQ_RSRC_IMG_2D
 ; GISEL-NEXT:    s_waitcnt vmcnt(0)
-; GISEL-NEXT:    v_fmac_legacy_f32_e64 v4, v7, 2.0
-; GISEL-NEXT:    v_fmac_legacy_f32_e64 v5, v8, 2.0
-; GISEL-NEXT:    v_mov_b32_e32 v2, v9
-; GISEL-NEXT:    v_mov_b32_e32 v3, v10
-; GISEL-NEXT:    v_mov_b32_e32 v0, v4
-; GISEL-NEXT:    v_mov_b32_e32 v1, v5
+; GISEL-NEXT:    v_fma_legacy_f32 v0, v0, 2.0, -1.0
+; GISEL-NEXT:    v_fma_legacy_f32 v1, v1, 2.0, -1.0
 ; GISEL-NEXT:    ; return to shader part epilog
   %i = bitcast <2 x i32> %arg7 to <2 x float>
   %i22 = extractelement <2 x float> %i, i32 0
   %i23 = extractelement <2 x float> %i, i32 1
   %i24 = call nsz arcp float @llvm.amdgcn.interp.p1(float %i22, i32 0, i32 0, i32 %arg5)
   %i25 = call nsz arcp float @llvm.amdgcn.interp.p2(float %i24, float %i23, i32 0, i32 0, i32 %arg5)
   %i26 = call nsz arcp float @llvm.amdgcn.interp.p1(float %i22, i32 1, i32 0, i32 %arg5)
   %i27 = call nsz arcp float @llvm.amdgcn.interp.p2(float %i26, float %i23, i32 1, i32 0, i32 %arg5)