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Differential D93930

[NewPM][NVPTX] Port NVPTX opt passes
ClosedPublic

Authored by aeubanks on Dec 29 2020, 9:00 PM.

Details

Reviewers
jholewinski
rnk
asbirlea
ychen
Commits
rG9ccf13c36d1c: [NewPM][NVPTX] Port NVPTX opt passes
Summary

There are only two used in the IR optimization pipeline.
Port these and add them to the default pipeline.

Similar to https://reviews.llvm.org/D93863.

I added -mtriple to some tests since under the new PM, the passes are
only available when the TargetMachine is specified.

Diff Detail

Event Timeline

aeubanks created this revision.Dec 29 2020, 9:00 PM
Herald added a subscriber: hiraditya. · View Herald TranscriptDec 29 2020, 9:00 PM
aeubanks requested review of this revision.Dec 29 2020, 9:00 PM
Herald added a project: Restricted Project. · View Herald TranscriptDec 29 2020, 9:00 PM
Herald added a subscriber: llvm-commits. · View Herald Transcript
aeubanks edited the summary of this revision. (Show Details)Dec 29 2020, 9:05 PM
Harbormaster completed remote builds in B83720: Diff 314062.Dec 29 2020, 9:47 PM
aeubanks added reviewers: rnk, asbirlea, ychen.Jan 7 2021, 2:23 PM
rnk accepted this revision.Jan 7 2021, 2:33 PM

lgtm with nit

llvm/lib/Target/NVPTX/NVVMReflect.cpp
77

static?

This revision is now accepted and ready to land.Jan 7 2021, 2:33 PM
aeubanks updated this revision to Diff 315257.Jan 7 2021, 3:11 PM

rebase
make function static

This revision was landed with ongoing or failed builds.Jan 7 2021, 3:14 PM
Closed by commit rG9ccf13c36d1c: [NewPM][NVPTX] Port NVPTX opt passes (authored by aeubanks). · Explain Why
This revision was automatically updated to reflect the committed changes.
aeubanks added a commit: rG9ccf13c36d1c: [NewPM][NVPTX] Port NVPTX opt passes.
tra added a subscriber: tra.Jan 7 2021, 3:15 PM

LGTM

Harbormaster completed remote builds in B84396: Diff 315257.Jan 7 2021, 3:57 PM

Revision Contents

PathSize
llvm/
lib/
Target/
NVPTX/
19 lines
2 lines
27 lines
40 lines
15 lines
test/
CodeGen/
NVPTX/
5 lines
3 lines
4 lines
tools/
opt/
2 lines

Diff 315259

llvm/lib/Target/NVPTX/NVPTX.h

//===-- NVPTX.h - Top-level interface for NVPTX representation --*- C++ -*-===// //===-- NVPTX.h - Top-level interface for NVPTX representation --*- C++ -*-===//
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file contains the entry points for global functions defined in // This file contains the entry points for global functions defined in
// the LLVM NVPTX back-end. // the LLVM NVPTX back-end.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_NVPTX_NVPTX_H #ifndef LLVM_LIB_TARGET_NVPTX_NVPTX_H
#define LLVM_LIB_TARGET_NVPTX_NVPTX_H #define LLVM_LIB_TARGET_NVPTX_NVPTX_H
#include "llvm/IR/PassManager.h"
#include "llvm/Pass.h" #include "llvm/Pass.h"
#include "llvm/Support/CodeGen.h" #include "llvm/Support/CodeGen.h"
namespace llvm { namespace llvm {
class NVPTXTargetMachine; class NVPTXTargetMachine;
class FunctionPass; class FunctionPass;
class MachineFunctionPass; class MachineFunctionPass;
Show All 17 Lines
MachineFunctionPass *createNVPTXPrologEpilogPass(); MachineFunctionPass *createNVPTXPrologEpilogPass();
MachineFunctionPass *createNVPTXReplaceImageHandlesPass(); MachineFunctionPass *createNVPTXReplaceImageHandlesPass();
FunctionPass *createNVPTXImageOptimizerPass(); FunctionPass *createNVPTXImageOptimizerPass();
FunctionPass *createNVPTXLowerArgsPass(const NVPTXTargetMachine *TM); FunctionPass *createNVPTXLowerArgsPass(const NVPTXTargetMachine *TM);
FunctionPass *createNVPTXLowerAllocaPass(); FunctionPass *createNVPTXLowerAllocaPass();
MachineFunctionPass *createNVPTXPeephole(); MachineFunctionPass *createNVPTXPeephole();
MachineFunctionPass *createNVPTXProxyRegErasurePass(); MachineFunctionPass *createNVPTXProxyRegErasurePass();
struct NVVMIntrRangePass : PassInfoMixin<NVVMIntrRangePass> {
NVVMIntrRangePass();
NVVMIntrRangePass(unsigned SmVersion) : SmVersion(SmVersion) {}
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
private:
unsigned SmVersion;
};
struct NVVMReflectPass : PassInfoMixin<NVVMReflectPass> {
NVVMReflectPass();
NVVMReflectPass(unsigned SmVersion) : SmVersion(SmVersion) {}
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
private:
unsigned SmVersion;
};
namespace NVPTX { namespace NVPTX {
enum DrvInterface { enum DrvInterface {
NVCL, NVCL,
CUDA CUDA
}; };
// A field inside TSFlags needs a shift and a mask. The usage is // A field inside TSFlags needs a shift and a mask. The usage is
// always as follows : // always as follows :
▲ Show 20 Lines • Show All 110 Lines • Show Last 20 Lines

llvm/lib/Target/NVPTX/NVPTXTargetMachine.h

Show First 20 Lines • Show All 56 Lines • ▼ Show 20 Lines bool addPassesToEmitMC(PassManagerBase &, MCContext *&, raw_pwrite_stream &,
bool = true) override { bool = true) override {
return true; return true;
} }
TargetLoweringObjectFile *getObjFileLowering() const override { TargetLoweringObjectFile *getObjFileLowering() const override {
return TLOF.get(); return TLOF.get();
} }
void adjustPassManager(PassManagerBuilder &) override; void adjustPassManager(PassManagerBuilder &) override;
void registerPassBuilderCallbacks(PassBuilder &PB,
bool DebugPassManager) override;
TargetTransformInfo getTargetTransformInfo(const Function &F) override; TargetTransformInfo getTargetTransformInfo(const Function &F) override;
bool isMachineVerifierClean() const override { bool isMachineVerifierClean() const override {
return false; return false;
} }
}; // NVPTXTargetMachine. }; // NVPTXTargetMachine.
Show All 21 Lines

llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp

Show All 18 Lines
#include "TargetInfo/NVPTXTargetInfo.h" #include "TargetInfo/NVPTXTargetInfo.h"
#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/Triple.h" #include "llvm/ADT/Triple.h"
#include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetPassConfig.h" #include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/LegacyPassManager.h" #include "llvm/IR/LegacyPassManager.h"
#include "llvm/Pass.h" #include "llvm/Pass.h"
#include "llvm/Passes/PassBuilder.h"
#include "llvm/Support/CommandLine.h" #include "llvm/Support/CommandLine.h"
#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/TargetRegistry.h"
#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetOptions.h"
#include "llvm/Transforms/IPO/PassManagerBuilder.h" #include "llvm/Transforms/IPO/PassManagerBuilder.h"
#include "llvm/Transforms/Scalar.h" #include "llvm/Transforms/Scalar.h"
#include "llvm/Transforms/Scalar/GVN.h" #include "llvm/Transforms/Scalar/GVN.h"
#include "llvm/Transforms/Vectorize.h" #include "llvm/Transforms/Vectorize.h"
▲ Show 20 Lines • Show All 165 Lines • ▼ Show 20 Linesvoid NVPTXTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
Builder.addExtension( Builder.addExtension(
PassManagerBuilder::EP_EarlyAsPossible, PassManagerBuilder::EP_EarlyAsPossible,
[&](const PassManagerBuilder &, legacy::PassManagerBase &PM) { [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
PM.add(createNVVMReflectPass(Subtarget.getSmVersion())); PM.add(createNVVMReflectPass(Subtarget.getSmVersion()));
PM.add(createNVVMIntrRangePass(Subtarget.getSmVersion())); PM.add(createNVVMIntrRangePass(Subtarget.getSmVersion()));
}); });
} }
void NVPTXTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB,
bool DebugPassManager) {
PB.registerPipelineParsingCallback(
[](StringRef PassName, FunctionPassManager &PM,
ArrayRef<PassBuilder::PipelineElement>) {
if (PassName == "nvvm-reflect") {
PM.addPass(NVVMReflectPass());
return true;
}
if (PassName == "nvvm-intr-range") {
PM.addPass(NVVMIntrRangePass());
return true;
}
return false;
});
PB.registerPipelineStartEPCallback(
[this, DebugPassManager](ModulePassManager &PM,
PassBuilder::OptimizationLevel Level) {
FunctionPassManager FPM(DebugPassManager);
FPM.addPass(NVVMReflectPass(Subtarget.getSmVersion()));
FPM.addPass(NVVMIntrRangePass(Subtarget.getSmVersion()));
PM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
});
}
TargetTransformInfo TargetTransformInfo
NVPTXTargetMachine::getTargetTransformInfo(const Function &F) { NVPTXTargetMachine::getTargetTransformInfo(const Function &F) {
return TargetTransformInfo(NVPTXTTIImpl(this, F)); return TargetTransformInfo(NVPTXTTIImpl(this, F));
} }
void NVPTXPassConfig::addEarlyCSEOrGVNPass() { void NVPTXPassConfig::addEarlyCSEOrGVNPass() {
if (getOptLevel() == CodeGenOpt::Aggressive) if (getOptLevel() == CodeGenOpt::Aggressive)
addPass(createGVNPass()); addPass(createGVNPass());
▲ Show 20 Lines • Show All 185 Lines • Show Last 20 Lines

llvm/lib/Target/NVPTX/NVVMIntrRange.cpp

Show All 11 Lines
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "NVPTX.h" #include "NVPTX.h"
#include "llvm/IR/Constants.h" #include "llvm/IR/Constants.h"
#include "llvm/IR/InstIterator.h" #include "llvm/IR/InstIterator.h"
#include "llvm/IR/Instructions.h" #include "llvm/IR/Instructions.h"
#include "llvm/IR/Intrinsics.h" #include "llvm/IR/Intrinsics.h"
#include "llvm/IR/IntrinsicsNVPTX.h" #include "llvm/IR/IntrinsicsNVPTX.h"
#include "llvm/IR/PassManager.h"
#include "llvm/Support/CommandLine.h" #include "llvm/Support/CommandLine.h"
using namespace llvm; using namespace llvm;
#define DEBUG_TYPE "nvvm-intr-range" #define DEBUG_TYPE "nvvm-intr-range"
namespace llvm { void initializeNVVMIntrRangePass(PassRegistry &); } namespace llvm { void initializeNVVMIntrRangePass(PassRegistry &); }
// Add !range metadata based on limits of given SM variant. // Add !range metadata based on limits of given SM variant.
static cl::opt<unsigned> NVVMIntrRangeSM("nvvm-intr-range-sm", cl::init(20), static cl::opt<unsigned> NVVMIntrRangeSM("nvvm-intr-range-sm", cl::init(20),
cl::Hidden, cl::desc("SM variant")); cl::Hidden, cl::desc("SM variant"));
namespace { namespace {
class NVVMIntrRange : public FunctionPass { class NVVMIntrRange : public FunctionPass {
private: private:
struct { unsigned SmVersion;
unsigned x, y, z;
} MaxBlockSize, MaxGridSize;
public: public:
static char ID; static char ID;
NVVMIntrRange() : NVVMIntrRange(NVVMIntrRangeSM) {} NVVMIntrRange() : NVVMIntrRange(NVVMIntrRangeSM) {}
NVVMIntrRange(unsigned int SmVersion) : FunctionPass(ID) { NVVMIntrRange(unsigned int SmVersion)
MaxBlockSize.x = 1024; : FunctionPass(ID), SmVersion(SmVersion) {
MaxBlockSize.y = 1024;
MaxBlockSize.z = 64;
MaxGridSize.x = SmVersion >= 30 ? 0x7fffffff : 0xffff;
MaxGridSize.y = 0xffff;
MaxGridSize.z = 0xffff;
initializeNVVMIntrRangePass(*PassRegistry::getPassRegistry()); initializeNVVMIntrRangePass(*PassRegistry::getPassRegistry());
} }
bool runOnFunction(Function &) override; bool runOnFunction(Function &) override;
}; };
} }
Show All 16 Linesstatic bool addRangeMetadata(uint64_t Low, uint64_t High, CallInst *C) {
IntegerType *Int32Ty = Type::getInt32Ty(Context); IntegerType *Int32Ty = Type::getInt32Ty(Context);
Metadata *LowAndHigh[] = { Metadata *LowAndHigh[] = {
ConstantAsMetadata::get(ConstantInt::get(Int32Ty, Low)), ConstantAsMetadata::get(ConstantInt::get(Int32Ty, Low)),
ConstantAsMetadata::get(ConstantInt::get(Int32Ty, High))}; ConstantAsMetadata::get(ConstantInt::get(Int32Ty, High))};
C->setMetadata(LLVMContext::MD_range, MDNode::get(Context, LowAndHigh)); C->setMetadata(LLVMContext::MD_range, MDNode::get(Context, LowAndHigh));
return true; return true;
} }
bool NVVMIntrRange::runOnFunction(Function &F) { static bool runNVVMIntrRange(Function &F, unsigned SmVersion) {
struct {
unsigned x, y, z;
} MaxBlockSize, MaxGridSize;
MaxBlockSize.x = 1024;
MaxBlockSize.y = 1024;
MaxBlockSize.z = 64;
MaxGridSize.x = SmVersion >= 30 ? 0x7fffffff : 0xffff;
MaxGridSize.y = 0xffff;
MaxGridSize.z = 0xffff;
// Go through the calls in this function. // Go through the calls in this function.
bool Changed = false; bool Changed = false;
for (Instruction &I : instructions(F)) { for (Instruction &I : instructions(F)) {
CallInst *Call = dyn_cast<CallInst>(&I); CallInst *Call = dyn_cast<CallInst>(&I);
if (!Call) if (!Call)
continue; continue;
if (Function *Callee = Call->getCalledFunction()) { if (Function *Callee = Call->getCalledFunction()) {
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines if (Function *Callee = Call->getCalledFunction()) {
default: default:
break; break;
} }
} }
} }
return Changed; return Changed;
} }
bool NVVMIntrRange::runOnFunction(Function &F) {
return runNVVMIntrRange(F, SmVersion);
}
NVVMIntrRangePass::NVVMIntrRangePass() : NVVMIntrRangePass(NVVMIntrRangeSM) {}
PreservedAnalyses NVVMIntrRangePass::run(Function &F,
FunctionAnalysisManager &AM) {
return runNVVMIntrRange(F, SmVersion) ? PreservedAnalyses::none()
: PreservedAnalyses::all();
}

llvm/lib/Target/NVPTX/NVVMReflect.cpp

Show All 23 Lines
#include "llvm/IR/Constants.h" #include "llvm/IR/Constants.h"
#include "llvm/IR/DerivedTypes.h" #include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h" #include "llvm/IR/Function.h"
#include "llvm/IR/InstIterator.h" #include "llvm/IR/InstIterator.h"
#include "llvm/IR/Instructions.h" #include "llvm/IR/Instructions.h"
#include "llvm/IR/Intrinsics.h" #include "llvm/IR/Intrinsics.h"
#include "llvm/IR/IntrinsicsNVPTX.h" #include "llvm/IR/IntrinsicsNVPTX.h"
#include "llvm/IR/Module.h" #include "llvm/IR/Module.h"
#include "llvm/IR/PassManager.h"
#include "llvm/IR/Type.h" #include "llvm/IR/Type.h"
#include "llvm/Pass.h" #include "llvm/Pass.h"
#include "llvm/Support/CommandLine.h" #include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h" #include "llvm/Support/Debug.h"
#include "llvm/Support/raw_os_ostream.h" #include "llvm/Support/raw_os_ostream.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
#include "llvm/Transforms/Scalar.h" #include "llvm/Transforms/Scalar.h"
#include <sstream> #include <sstream>
Show All 28 Lines
NVVMReflectEnabled("nvvm-reflect-enable", cl::init(true), cl::Hidden, NVVMReflectEnabled("nvvm-reflect-enable", cl::init(true), cl::Hidden,
cl::desc("NVVM reflection, enabled by default")); cl::desc("NVVM reflection, enabled by default"));
char NVVMReflect::ID = 0; char NVVMReflect::ID = 0;
INITIALIZE_PASS(NVVMReflect, "nvvm-reflect", INITIALIZE_PASS(NVVMReflect, "nvvm-reflect",
"Replace occurrences of __nvvm_reflect() calls with 0/1", false, "Replace occurrences of __nvvm_reflect() calls with 0/1", false,
false) false)
bool NVVMReflect::runOnFunction(Function &F) { static bool runNVVMReflect(Function &F, unsigned SmVersion) {
rnkUnsubmitted
Not Done
ReplyInline Actions

static?

rnk: `static`?
if (!NVVMReflectEnabled) if (!NVVMReflectEnabled)
return false; return false;
if (F.getName() == NVVM_REFLECT_FUNCTION) { if (F.getName() == NVVM_REFLECT_FUNCTION) {
assert(F.isDeclaration() && "_reflect function should not have a body"); assert(F.isDeclaration() && "_reflect function should not have a body");
assert(F.getReturnType()->isIntegerTy() && assert(F.getReturnType()->isIntegerTy() &&
"_reflect's return type should be integer"); "_reflect's return type should be integer");
return false; return false;
▲ Show 20 Lines • Show All 89 Lines • ▼ Show 20 Lines for (Instruction &I : instructions(F)) {
ToRemove.push_back(Call); ToRemove.push_back(Call);
} }
for (Instruction *I : ToRemove) for (Instruction *I : ToRemove)
I->eraseFromParent(); I->eraseFromParent();
return ToRemove.size() > 0; return ToRemove.size() > 0;
} }
bool NVVMReflect::runOnFunction(Function &F) {
return runNVVMReflect(F, SmVersion);
}
NVVMReflectPass::NVVMReflectPass() : NVVMReflectPass(0) {}
PreservedAnalyses NVVMReflectPass::run(Function &F,
FunctionAnalysisManager &AM) {
return runNVVMReflect(F, SmVersion) ? PreservedAnalyses::none()
: PreservedAnalyses::all();
}

llvm/test/CodeGen/NVPTX/intrinsic-old.ll

; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck -allow-deprecated-dag-overlap %s ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck -allow-deprecated-dag-overlap %s
; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck -allow-deprecated-dag-overlap %s ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck -allow-deprecated-dag-overlap %s
; RUN: opt < %s -S -mtriple=nvptx-nvidia-cuda -nvvm-intr-range \ ; RUN: opt < %s -S -mtriple=nvptx-nvidia-cuda -nvvm-intr-range \
; RUN: | FileCheck -allow-deprecated-dag-overlap --check-prefix=RANGE --check-prefix=RANGE_20 %s ; RUN: | FileCheck -allow-deprecated-dag-overlap --check-prefix=RANGE --check-prefix=RANGE_20 %s
; RUN: opt < %s -S -mtriple=nvptx-nvidia-cuda -passes=nvvm-intr-range \
; RUN: | FileCheck -allow-deprecated-dag-overlap --check-prefix=RANGE --check-prefix=RANGE_20 %s
; RUN: opt < %s -S -mtriple=nvptx-nvidia-cuda \ ; RUN: opt < %s -S -mtriple=nvptx-nvidia-cuda \
; RUN: -nvvm-intr-range -nvvm-intr-range-sm=30 \ ; RUN: -nvvm-intr-range -nvvm-intr-range-sm=30 \
; RUN: | FileCheck -allow-deprecated-dag-overlap --check-prefix=RANGE --check-prefix=RANGE_30 %s ; RUN: | FileCheck -allow-deprecated-dag-overlap --check-prefix=RANGE --check-prefix=RANGE_30 %s
; RUN: opt < %s -S -mtriple=nvptx-nvidia-cuda \
; RUN: -passes=nvvm-intr-range -nvvm-intr-range-sm=30 \
; RUN: | FileCheck -allow-deprecated-dag-overlap --check-prefix=RANGE --check-prefix=RANGE_30 %s
define ptx_device i32 @test_tid_x() { define ptx_device i32 @test_tid_x() {
; CHECK: mov.u32 %r{{[0-9]+}}, %tid.x; ; CHECK: mov.u32 %r{{[0-9]+}}, %tid.x;
; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !range ![[BLK_IDX_XY:[0-9]+]] ; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !range ![[BLK_IDX_XY:[0-9]+]]
; CHECK: ret; ; CHECK: ret;
%x = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() %x = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
ret i32 %x ret i32 %x
} }
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llvm/test/CodeGen/NVPTX/nvvm-reflect-module-flag.ll

; RUN: opt < %s -S -nvvm-reflect | FileCheck %s ; RUN: opt < %s -S -mtriple=nvptx-nvidia-cuda -nvvm-reflect | FileCheck %s
; RUN: opt < %s -S -mtriple=nvptx-nvidia-cuda -passes=nvvm-reflect | FileCheck %s
declare i32 @__nvvm_reflect(i8*) declare i32 @__nvvm_reflect(i8*)
@str = private unnamed_addr addrspace(1) constant [11 x i8] c"__CUDA_FTZ\00" @str = private unnamed_addr addrspace(1) constant [11 x i8] c"__CUDA_FTZ\00"
define i32 @foo() { define i32 @foo() {
%call = call i32 @__nvvm_reflect(i8* addrspacecast (i8 addrspace(1)* getelementptr inbounds ([11 x i8], [11 x i8] addrspace(1)* @str, i32 0, i32 0) to i8*)) %call = call i32 @__nvvm_reflect(i8* addrspacecast (i8 addrspace(1)* getelementptr inbounds ([11 x i8], [11 x i8] addrspace(1)* @str, i32 0, i32 0) to i8*))
; CHECK: ret i32 42 ; CHECK: ret i32 42
ret i32 %call ret i32 %call
} }
!llvm.module.flags = !{!0} !llvm.module.flags = !{!0}
!0 = !{i32 4, !"nvvm-reflect-ftz", i32 42} !0 = !{i32 4, !"nvvm-reflect-ftz", i32 42}

llvm/test/CodeGen/NVPTX/nvvm-reflect.ll

; We run nvvm-reflect (and then optimize) this module twice, once with metadata ; We run nvvm-reflect (and then optimize) this module twice, once with metadata
; that enables FTZ, and again with metadata that disables it. ; that enables FTZ, and again with metadata that disables it.
; RUN: cat %s > %t.noftz ; RUN: cat %s > %t.noftz
; RUN: echo '!0 = !{i32 4, !"nvvm-reflect-ftz", i32 0}' >> %t.noftz ; RUN: echo '!0 = !{i32 4, !"nvvm-reflect-ftz", i32 0}' >> %t.noftz
; RUN: opt %t.noftz -S -nvvm-reflect -O2 \ ; RUN: opt %t.noftz -S -mtriple=nvptx-nvidia-cuda -nvvm-reflect -O2 \
; RUN: | FileCheck %s --check-prefix=USE_FTZ_0 --check-prefix=CHECK ; RUN: | FileCheck %s --check-prefix=USE_FTZ_0 --check-prefix=CHECK
; RUN: cat %s > %t.ftz ; RUN: cat %s > %t.ftz
; RUN: echo '!0 = !{i32 4, !"nvvm-reflect-ftz", i32 1}' >> %t.ftz ; RUN: echo '!0 = !{i32 4, !"nvvm-reflect-ftz", i32 1}' >> %t.ftz
; RUN: opt %t.ftz -S -nvvm-reflect -O2 \ ; RUN: opt %t.ftz -S -mtriple=nvptx-nvidia-cuda -nvvm-reflect -O2 \
; RUN: | FileCheck %s --check-prefix=USE_FTZ_1 --check-prefix=CHECK ; RUN: | FileCheck %s --check-prefix=USE_FTZ_1 --check-prefix=CHECK
@str = private unnamed_addr addrspace(4) constant [11 x i8] c"__CUDA_FTZ\00" @str = private unnamed_addr addrspace(4) constant [11 x i8] c"__CUDA_FTZ\00"
declare i32 @__nvvm_reflect(i8*) declare i32 @__nvvm_reflect(i8*)
declare i8* @llvm.nvvm.ptr.constant.to.gen.p0i8.p4i8(i8 addrspace(4)*) declare i8* @llvm.nvvm.ptr.constant.to.gen.p0i8.p4i8(i8 addrspace(4)*)
; CHECK-LABEL: @foo ; CHECK-LABEL: @foo
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llvm/tools/opt/opt.cpp

Show First 20 Lines • Show All 457 Lines • ▼ Show 20 Lines
}; };
// For use in NPM transition. Currently this contains most codegen-specific // For use in NPM transition. Currently this contains most codegen-specific
// passes. Remove passes from here when porting to the NPM. // passes. Remove passes from here when porting to the NPM.
// TODO: use a codegen version of PassRegistry.def/PassBuilder::is*Pass() once // TODO: use a codegen version of PassRegistry.def/PassBuilder::is*Pass() once
// it exists. // it exists.
static bool shouldPinPassToLegacyPM(StringRef Pass) { static bool shouldPinPassToLegacyPM(StringRef Pass) {
std::vector<StringRef> PassNameExactToIgnore = { std::vector<StringRef> PassNameExactToIgnore = {
"nvvm-reflect",
"nvvm-intr-range",
"amdgpu-simplifylib", "amdgpu-simplifylib",
"amdgpu-usenative", "amdgpu-usenative",
"amdgpu-promote-alloca", "amdgpu-promote-alloca",
"amdgpu-promote-alloca-to-vector", "amdgpu-promote-alloca-to-vector",
"amdgpu-lower-kernel-attributes", "amdgpu-lower-kernel-attributes",
"amdgpu-propagate-attributes-early", "amdgpu-propagate-attributes-early",
"amdgpu-propagate-attributes-late", "amdgpu-propagate-attributes-late",
"amdgpu-unify-metadata", "amdgpu-unify-metadata",
▲ Show 20 Lines • Show All 576 Lines • Show Last 20 Lines