[AIX][XCOFF] emit traceback table for function in aix

[DiggerLin]

Summary

1. added a new option -xcoff-traceback-table to control whether generate traceback table for function.
2. implement the functionality of emit traceback table of a function.

[jasonliu]

llvm/include/llvm/Target/TargetMachine.h

275–277

I don't think it's necessary for us to mention about asm or XCOFF object file.

llvm/include/llvm/Target/TargetOptions.h

250

No need to mention about asm or object file.

llvm/lib/CodeGen/CommandFlags.cpp

358

Same as above, no need to mention about asm or object file.

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

1746

Could we put traceback table emission into its own function(e.g. emitTracebackTable() )? And call that function in emitFunctionBodyEnd() instead?
I think that would make the code cleaner and express the intent better.

1764

Use a lambda instead if you don't need to take the advantage of a macro.

1773

Do you need the cast? If you really do, please use static_cast.

1779

Is there any macro trick we could perform here, instead of having another array of literals?
e.g. could we stringyfy the enum you have in XCOFF.h?

1782–1783

Could you declare the variables near where you would use them?

1818

Undef these macros when you finished use with it.

1824

No c-style cast please.

1986

Why do you need OUTPUTCOMMENT here?

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

3594

Please rebase on the latest master, this part does not apply any more.

[hubert.reinterpretcast]

llvm/include/llvm/BinaryFormat/XCOFF.h

309–313

LLVM's use of CamelCase includes capitalizing acronyms in the same style as non-acronym words.

314–315

Both PL8 and PLIX use the same value.

[hubert.reinterpretcast]

llvm/include/llvm/Target/TargetMachine.h

275–277

s/xcoff/XCOFF/; in comments and messages.

llvm/include/llvm/Target/TargetOptions.h

250

Same comment re: "XCOFF".

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

1740–1742

Match AIX documentation on style used for language names (for documented cases).

[jasonliu]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

3594

Also, it seems test/CodeGen/PowerPC/aix-cc-ext-vec-abi.ll fails with this patch because of the newly added vector register support. Please fix that after rebase.

[jasonliu]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

1767

I don't think it's worth to add this function/macro if it just saves one extra line OutStreamer->emitIntValueInHexWithPadding(X, S). And it's actually more helpful for people to see that extra line and know a byte have been printed.

1767

Do you really need to emit these values with Paddings?

1818

I would suggest to rename this macro. As we don't do the "printing" here. I get confused of this when I read we have another OUTPUTCOMMENT later.
This is more like SAVEBOOLCOMMENT.

1896

Not sure why we still modify the FPRSaved area in SecondHalfOfMandatoryField when we already "print out" FPRSaved above?

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h

26

nit: Para -> Param
I think Param is the most used short form and we should use that.

llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable.ll

119

The algorithm of getting NumOfFPRsSaved and NumOfGPRsSaved are not actually put to the test.

163

I would prefer to leave the object file generation and disassemble of it out of this patch. Otherwise, we would have to land the disassemble patch first before we could land this one.

[DiggerLin]

llvm/include/llvm/BinaryFormat/XCOFF.h

314–315

thanks

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

1746

good idea , thanks

1767

I am prefer with paddings.

1767

it save two lines. and there are several places invoke OutStreamer->emitIntValueInHexWithPadding(X, S), I think it worth it. if I want to change the format of the output, I only need change the macro , I do not several place, for example, if you do not agree with pad, I only need to change the macro.

1773

raw_string_ostream do not accept the operator << (uint8_t ) ,

1818

change to GENBOOLCOMMENT and GENVALUECOMMENT

llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable.ll

163

I think we need to land the dissemble patch first. for the patch is based on the dissemble patch.

[DiggerLin]

address comment.

[jasonliu]

llvm/include/llvm/Target/TargetOptions.h

133–136

Is this the wrong default? By default llc should emit traceback table for XCOFF object file.

[jasonliu]

llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable.ll

108

To match the style with the llvm-objdump, we would want to print a space after ,.

109

Extra space printed after #.

117

Extra # here and the line below.

[DiggerLin]

llvm/include/llvm/Target/TargetOptions.h

133–136

if this the default should be emit traceback table. why we need the option -xcoff-traceback-table ? instead we need -disable-xcoff-traceback-table.

[jasonliu]

llvm/include/llvm/Target/TargetOptions.h

133–136

It's the same thing. Just different naming and switched the default value.
You could have -disable-xcoff-traceback-table if you want, but it's just longer name.
Also, we would need a driver option later, and I suppose the driver option is something like -fxcoff-traceback-table and -fno-xcoff-traceback-table, with -fxcoff-traceback-table being default to true on AIX. So with the current name, it's going to match the driver option better.

[DiggerLin]

address comment

[jasonliu]

llvm/include/llvm/BinaryFormat/XCOFF.h

20–21

Could you forward declare the SmallString class and get rid of the header inclusion above?

template <unsigned InternalLen> class SmallString;

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

204

Could this function be private?

1741

nit: a slight preference to have this early return inside of emitTracebackTable() function.

1760

nit: I would prefer the name to be EmitComment and EmitCommentAndValue.

1767

Any reason you need to emit with Paddings though?
If not, why not just call emitIntValue instead.

1782

I don't think IsGlobalLinkage is mapped to hasExternalLinkage() here.
Global linkage on AIX is referring to the glue code that enables intermodule calls via TOC, which should have mapping class as [GL].
Since we don't generate it, it should be safe for it to be false.

1788

I'm not sure what internal procedure means here. But it seems xlC/xlclang compilers does not set it for static functions.
So should we error on the safe side and not set it as well?

1819

You could pass the name in directly as a string without needing to stringfy it in the macro.
I think that's better because people who looked at the caller could tell it's a string.
For example:
GENVALUECOMMENT(", ", SecondHalfOfMandatoryField, FPRSaved, "NumOfFPRsSaved");

1974

use static_cast instead.

1981

nit: Alloc_Reg -> AllocReg.

1982

This seems to be just fixed value. You don't really need to compute them?

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h

120

nit: Fixed -> fixed

123

NumFloatPara -> NumFloatingPointParam
float point -> floating point

126–127

129

float point -> floating point.

218

We should rename getFixedParameter to getNumFixedParam so that the function name and member definition matches.

220

getFloatPointParameter() -> getNumFloatingPointParam()

[DiggerLin]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

1741

putting if (!TM.getXCOFFTracebackTable()) here, it do not need extra function call emitTracebackTable when getXCOFFTracebackTable is false.

1767

for example , if the value is 3, if use the emitIntValue. it will be display
.byte 0x3,
with
emitIntValueInHexWithPadding will show as 0x03. I can know , it is only byte value.

if it is two bytes value , it will show as 0x0003. even there is (.vbytes 2, 0x3), but I prefer show as (.vbytes 2, 0x0003) .

[DiggerLin]

address comment

[jasonliu]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

7311

Do you actually need to traverse to find out exactly what register is used?
Could you use queries in VA.getValVT() to find out whether it's a fixed param or float param?
For example, VA.getValVT().isScalarInteger().

[jasonliu]

llvm/lib/BinaryFormat/XCOFF.cpp

101

nit :I think it's fine to return "CPlusPlus" in the string and no need for a special case here.

[hubert.reinterpretcast]

llvm/lib/BinaryFormat/XCOFF.cpp

113

Minor nit: avoid implicit conversion to bool when comparing against zero for integers.

136

Is assert right for all expected callers of this function? This seems to be a reusable implementation where the error handling policy should be left to the caller.

138

Why is this hardcoded (as opposed to a named constant representing the width of the ParmTypeMask)?

[hubert.reinterpretcast]

llvm/lib/BinaryFormat/XCOFF.cpp

139–141

The message text here is wrong. The correct ParmsNum here needs to include the number of vector parameters, which the XL compilers consider as neither "fixed-point" nor floating-point.

@DiggerLin, please confirm that the caller of this function correctly includes the vector parameter count.

Also, same comment as above re: assert.

165

Would a Value == 0u check here make sense? The other function has a check that serves a similar purpose.

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

1758

I don't think a std::string in needed here; using raw_svector_ostream should work.

[hubert.reinterpretcast]

llvm/include/llvm/BinaryFormat/XCOFF.h

407

getNameForTracebackTableLanguageId or maybe just getDisplayName. In any case, it's a name that's retrieved and not a "language".

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

1775

There should be a comment as to why this is considered the conservatively correct setting (between C and C++) when there is a lack of information in the IR to assist with determining the source language.

1781

s/3th/3rd/;

1790

Use prefix ++.

1790

There are signs that XL will consider usage of the VSX registers that overlay the floating point registers as FP_PRESENT.

1798

Add parens around Prefix and V.

1801

What is "Prefixi" supposed to mean?

1802–1803

Same comment about parens.

1806

Globa(no l)Linkage?

[hubert.reinterpretcast]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

1779

Please add at least a comment that this is only populated for the third and fourth bytes.

1788

Just for information: an "internal procedure" in this context is one that does not manipulate the stack pointer. Procedures that fit this description nevertheless don't have the flag set by xlc, etc.

[DiggerLin]

llvm/lib/BinaryFormat/XCOFF.cpp

139–141

yes, the ParmsNum in function only includes the fixed and floating parameter count currently.
so in the function , when decoding we do not have ++I in the
"case TracebackTable::ParmTypeIsVectorBits" , we grantee all the vector parameter meter will be decoded by the Value != 0u . actually if we only put fixed parameter count as parameter of the function, we can also decode the ParmsType correctly by Value != 0u.

that is why the message text is "The total parameters number of fixed-point or floating-point " not have vector ,

if you not agreed with only pass fixed and floating parameter count, I can create a NFC patch later.

[DiggerLin]

llvm/lib/BinaryFormat/XCOFF.cpp

136

the code should not came to default. added assert here we don't get surprised.

165

Added, thanks.

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

1758

using raw_svector_ostream here. it need SmallString , for example.
SmallString<128> InstPrinterStr;

raw_svector_ostream OSS(InstPrinterStr);

if you think we need to raw_svector_ostream , I can move to raw_svector_ostream.

1790

Yes, I think isPhysRegUsed(Reg) will also let usage of the VSX registers that overlay the floating point registers as FP_PRESENT too.
in the function
bool MachineRegisterInfo::isPhysRegUsed(MCRegister PhysReg) const {

if (UsedPhysRegMask.test(PhysReg))
  return true;
const TargetRegisterInfo *TRI = getTargetRegisterInfo();
for (MCRegAliasIterator AliasReg(PhysReg, TRI, true); AliasReg.isValid();
     ++AliasReg) {
  if (!reg_nodbg_empty(*AliasReg))
    return true;
}
return false;

}
it will iterator all the overlay registers.

1801

change to prefix

1806

David Edelsohn told me in the gcc
The “global linkage”, “out-of-line prologue/epilogue”, “internal function”, “controlled storage”, and “function has no toc” are unset.

[DiggerLin]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

1806

yes , it is typo error, I will create a NFC later to deal with it later.

[DiggerLin]

address comment

[hubert.reinterpretcast]

llvm/lib/BinaryFormat/XCOFF.cpp

136

Okay; this is not just "should". It's actually impossible unless if the constants are incorrectly defined. Got it; thanks.

139–141

yes, the ParmsNum in function only includes the fixed and floating parameter count currently.

This is an interface surprise that should have copious comments if it were to be left around.

so in the function , when decoding we do not have ++I in the
"case TracebackTable::ParmTypeIsVectorBits" , we grantee all the vector parameter meter will be decoded by the Value != 0u .

If this is true, then it's worth having a comment where the ++I is intentionally omitted.

actually if we only put fixed parameter count as parameter of the function, we can also decode the ParmsType correctly by Value != 0u.

There are 8 GPRs and 12 VRs for function arguments. So, just with registers, there can be more than the 16 parameters that can be encoded in the 32 bits. The assert can be hit and it's not always an error. Trying to say that there is an infinite number of 0 bits to the right may be too clever because it makes it difficult to draw the line for other unambiguous situations involving having only vector parameters left to account for. An alternative solution where the number of encoding bits left is tracked and unencoded parameters are represented by an ellipsis would be something to consider.

that is why the message text is "The total parameters number of fixed-point or floating-point " not have vector ,

if you not agreed with only pass fixed and floating parameter count, I can create a NFC patch later.

Thanks for your enlightening response. I think we have more to fix here.

[hubert.reinterpretcast]

llvm/include/llvm/BinaryFormat/XCOFF.h

33

Seems weird to me that this is not defined as part of TracebackTable.

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

1758

Yes, please make that change.

1775

We use C++ as the Language here because ...? Please ask @jasonliu if help is needed on the explanation.

[DiggerLin]

address comment

[DiggerLin]

llvm/lib/BinaryFormat/XCOFF.cpp

139–141

yes, the ParmsNum in function only includes the fixed and floating parameter count currently.

This is an interface surprise that should have copious comments if it were to be left around.

so in the function , when decoding we do not have ++I in the
"case TracebackTable::ParmTypeIsVectorBits" , we grantee all the vector parameter meter will be decoded by the Value != 0u .

If this is true, then it's worth having a comment where the ++I is intentionally omitted.

actually if we only put fixed parameter count as parameter of the function, we can also decode the ParmsType correctly by Value != 0u.

There are 8 GPRs and 12 VRs for function arguments. So, just with registers, there can be more than the 16 parameters that can be encoded in the 32 bits. The assert can be hit and it's not always an error. Trying to say that there is an infinite number of 0 bits to the right may be too clever because it makes it difficult to draw the line for other unambiguous situations involving having only vector parameters left to account for. An alternative solution where the number of encoding bits left is tracked and unencoded parameters are represented by an ellipsis would be something to consider.

Actually we do not use the function in the patch, we just move it the function from xcoffobject.cpp file to here, We can change it in a NFC patch or in encoding vector info patch later.

that is why the message text is "The total parameters number of fixed-point or floating-point " not have vector ,

if you not agreed with only pass fixed and floating parameter count, I can create a NFC patch later.

Thanks for your enlightening response. I think we have more to fix here.

[jasonliu]

llvm/lib/BinaryFormat/XCOFF.cpp

139–141

@DiggerLin I don't really see this part of the comment being addressed:

There are 8 GPRs and 12 VRs for function arguments. So, just with registers, there can be more than the 16 parameters that can be encoded in the 32 bits. The assert can be hit and it's not always an error. Trying to say that there is an infinite number of 0 bits to the right may be too clever because it makes it difficult to draw the line for other unambiguous situations involving having only vector parameters left to account for. An alternative solution where the number of encoding bits left is tracked and unencoded parameters are represented by an ellipsis would be something to consider.

But I don't think this function actually gets called in this patch. So maybe we should consider to remove this function out of this patch.

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

1788

Okay; Thanks. So it's like a leaf function.

[jasonliu]

Thanks. LGTM.
Please allow some time for @hubert.reinterpretcast to go over again before you land.

[hubert.reinterpretcast]

llvm/lib/BinaryFormat/XCOFF.cpp

107

When we revisit for vector parameters, we should also revisit this function.

127–128

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

1775

Minor nit: Use period instead of comma.

1867

Minor nit: preincrement.

1889

Minor nit: same comment re: ++.

1899–1900

The values of the constants reflect the XL order but the output order doesn't.

[DiggerLin]

llvm/lib/BinaryFormat/XCOFF.cpp

107

ok, thanks

[hubert.reinterpretcast]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

1838

Use static_assert to relate the registers being checked against the register we will claim is being associated with alloca.

1939

Assert here that HasVectorInfo is false.

1954–1957

Fix misplaced comment.

1959

Fix typo.

1963

I did not check the XL behaviour here, but it seems that the safe thing to do is to truncate the name to INT16_MAX characters. Also, using int16_t will better match the type of the field.

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h

26

There seems to be no requirement for the enumerators to take on these particular values.

127

131

This corresponds to a field with a specific width.

223

Same comment.

[hubert.reinterpretcast]

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h

26

Okay, this is used by setParameterType. It seems that the values should be written as hex here alongside comments indicating the bitstrings used in the encoding format.

[hubert.reinterpretcast]

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp

68

Is RegNo a correct name for this parameter? It's not used like a register number (e.g., PPC::R3).

69

71

Prefix ++ please.

72

This is ParmTypeIsFloatingBit?

80

Same comment re: ++.

84–87

There can be 8 GPRs of arguments followed by 13 FPRs of arguments. 8 + 13 * 2 = 34. Shifting by a negative number of bits is undefined behaviour.

llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable.ll

17

Please add a test where a struct taking more than one register occurs prior to a float.

[hubert.reinterpretcast]

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp

68

Perhaps this function should use and also be responsible for adjusting FixedParamNum and FloatingPointParamNum. The function should be renamed to something like appendParameterType.

[DiggerLin]

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp

68

change to ParamNo

68

change the interface from setParameterType(ParamType Type, unsigned RegNo) to setParameterType(ParamType Type)

[DiggerLin]

address comment including fixing a paramtype bug and adding a new content in test case.

[DiggerLin]

change function from setParameterType to appendParameterType

[hubert.reinterpretcast]

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp

71

@DiggerLin, can you merge the updates for FixedParamNum and FloatingPointParamNum into this function? You might have missed my comment this morning about making this appendParameterType.

[hubert.reinterpretcast]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

1941

Minor nit: grammar.

1963

Please add a line before getting NameLength to update the length of the StringRef to truncate to INT16_MAX characters.

[hubert.reinterpretcast]

LGTM with comments; thanks.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

7311–7315

Minor nit: braces no longer needed.

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp

82

Minor nit: since the wrapping behaviour of unsigned is unwanted here, using a signed type assists in expressing the intent.

96

This seems to be an off-by-one error? It's fine to set the rightmost two bits together.

[DiggerLin]

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp

96

yes, you are correct. thanks

[RKSimon]

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp

97

@DiggerLin This is causing "comparison of unsigned expression >= 0 is always true" gcc warnings.

Maybe change to:

if (Bits < 31)

or change Bits to an int ?

[morehouse]

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp

98

This line is causing UBSan errors: http://lab.llvm.org:8011/#/builders/5/builds/2407/steps/2/logs/stdio
Please fix or revert.

FAIL: LLVM :: CodeGen/PowerPC/aix-cc-abi.ll (45237 of 72201)
******************** TEST 'LLVM :: CodeGen/PowerPC/aix-cc-abi.ll' FAILED ********************
...
Exit Code: 2
Command Output (stderr):
--
/b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp:98:27: runtime error: shift exponent 4294967294 is too large for 32-bit type 'int'

[DiggerLin]

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp

98

https://reviews.llvm.org/rG15f2d4f198380762e9fcf6b456d405078b87ae7a

llvm/include/llvm/BinaryFormat/XCOFF.h

 
 #ifndef LLVM_BINARYFORMAT_XCOFF_H
 #define LLVM_BINARYFORMAT_XCOFF_H
 
 #include <stddef.h>
 #include <stdint.h>
 
 namespace llvm {
 class StringRef;
+template <unsigned> class SmallString;
 
 namespace XCOFF {
 
 // Constants used in the XCOFF definition.
 
 constexpr size_t FileNamePadSize = 6;
 constexpr size_t NameSize = 8;
 constexpr size_t SymbolTableEntrySize = 18;
 constexpr size_t RelocationSerializationSize32 = 10;
 constexpr uint16_t RelocOverflow = 65535;
+constexpr uint8_t AllocRegNo = 31;
 
 enum ReservedSectionNum : int16_t { N_DEBUG = -2, N_ABS = -1, N_UNDEF = 0 };
 
 // x_smclas field of x_csect from system header: /usr/include/syms.h
 /// Storage Mapping Class definitions.
 enum StorageMappingClass : uint8_t {
   //     READ ONLY CLASSES
   XMC_PR = 0,      ///< Program Code
   XMC_RO = 1,      ///< Read Only Constant

 enum CFileCpuId : uint8_t {
   TCPU_PPC64 = 2, ///< PowerPC common architecture 64-bit mode.
   TCPU_COM = 3,   ///< POWER and PowerPC architecture common.
   TCPU_970 = 19   ///< PPC970 - PowerPC 64-bit architecture.
 };
 
 StringRef getMappingClassString(XCOFF::StorageMappingClass SMC);
 StringRef getRelocationTypeString(XCOFF::RelocationType Type);
+SmallString<32> parseParmsType(uint32_t Value, unsigned ParmsNum);
 
 struct TracebackTable {
+  enum LanguageID : uint8_t {
+    C,
+    Fortran,
+    Pascal,
+    Ada,
+    PL1,
+    Basic,
+    Lisp,
+    Cobol,
+    Modula2,
+    CPlusPlus,
+    Rpg,
+    PL8,
+    PLIX = PL8,
+    Assembly,
+    Java,
+    ObjectiveC
+  };
   // Byte 1
   static constexpr uint32_t VersionMask = 0xFF00'0000;
   static constexpr uint8_t VersionShift = 24;
 
   // Byte 2
   static constexpr uint32_t LanguageIdMask = 0x00FF'0000;
   static constexpr uint8_t LanguageIdShift = 16;
 

 enum ExtendedTBTableFlag : uint8_t {
   TB_OS1 = 0x80,         ///< Reserved for OS use
   TB_RESERVED = 0x40,    ///< Reserved for compiler
   TB_SSP_CANARY = 0x20,  ///< stack smasher canary present on stack
   TB_OS2 = 0x10,         ///< Reserved for OS use
   TB_LONGTBTABLE2 = 0x01 ///< Additional tbtable extension exists
 };
 
+StringRef getNameForTracebackTableLanguageId(TracebackTable::LanguageID LangId);
+
 } // end namespace XCOFF
 } // end namespace llvm
 
 #endif

llvm/include/llvm/CodeGen/CommandFlags.h

 bool getDataSections();
 Optional<bool> getExplicitDataSections();
 
 bool getFunctionSections();
 Optional<bool> getExplicitFunctionSections();
 
 bool getIgnoreXCOFFVisibility();
 
+bool getXCOFFTracebackTable();
+
 std::string getBBSections();
 
 std::string getStackProtectorGuard();
 unsigned getStackProtectorGuardOffset();
 std::string getStackProtectorGuardReg();
 
 unsigned getTLSSize();
 

llvm/include/llvm/Target/TargetMachine.h

public:
   }
 
   /// Return true if functions should be emitted into their own section,
   /// corresponding to -ffunction-sections.
   bool getFunctionSections() const {
     return Options.FunctionSections;
   }
 
-  /// Return true if visibility attribute should not be emitted in xcoff,
+  /// Return true if visibility attribute should not be emitted in XCOFF,
   /// corresponding to -mignore-xcoff-visibility.
   bool getIgnoreXCOFFVisibility() const {
     return Options.IgnoreXCOFFVisibility;
   }
 
+  /// Return true if XCOFF traceback table should be emitted,
+  /// corresponding to -xcoff-traceback-table.
+  bool getXCOFFTracebackTable() const { return Options.XCOFFTracebackTable; }
+
   /// If basic blocks should be emitted into their own section,
   /// corresponding to -fbasic-block-sections.
   llvm::BasicBlockSection getBBSectionsType() const {
     return Options.BBSections;
   }
 
   /// Get the list of functions and basic block ids that need unique sections.
   const MemoryBuffer *getBBSectionsFuncListBuf() const {

llvm/include/llvm/Target/TargetOptions.h

TargetOptions()
         : UnsafeFPMath(false), NoInfsFPMath(false), NoNaNsFPMath(false),
           NoTrappingFPMath(true), NoSignedZerosFPMath(false),
           EnableAIXExtendedAltivecABI(false),
           HonorSignDependentRoundingFPMathOption(false), NoZerosInBSS(false),
           GuaranteedTailCallOpt(false), StackSymbolOrdering(true),
           EnableFastISel(false), EnableGlobalISel(false), UseInitArray(false),
           DisableIntegratedAS(false), RelaxELFRelocations(false),
           FunctionSections(false), DataSections(false),
-          IgnoreXCOFFVisibility(false), UniqueSectionNames(true),
-          UniqueBasicBlockSectionNames(false), TrapUnreachable(false),
-          NoTrapAfterNoreturn(false), TLSSize(0), EmulatedTLS(false),
-          ExplicitEmulatedTLS(false), EnableIPRA(false),
+          IgnoreXCOFFVisibility(false), XCOFFTracebackTable(true),
+          UniqueSectionNames(true), UniqueBasicBlockSectionNames(false),
+          TrapUnreachable(false), NoTrapAfterNoreturn(false), TLSSize(0),
+          EmulatedTLS(false), ExplicitEmulatedTLS(false), EnableIPRA(false),
           EmitStackSizeSection(false), EnableMachineOutliner(false),
           EnableMachineFunctionSplitter(false), SupportsDefaultOutlining(false),
           EmitAddrsig(false), EmitCallSiteInfo(false),
           SupportsDebugEntryValues(false), EnableDebugEntryValues(false),
           PseudoProbeForProfiling(false), ValueTrackingVariableLocations(false),
           ForceDwarfFrameSection(false), XRayOmitFunctionIndex(false),
           FPDenormalMode(DenormalMode::IEEE, DenormalMode::IEEE) {}
 
public:
     unsigned FunctionSections : 1;
 
     /// Emit data into separate sections.
     unsigned DataSections : 1;
 
     /// Do not emit visibility attribute for xcoff.
     unsigned IgnoreXCOFFVisibility : 1;
 
+    /// Emit XCOFF traceback table.
+    unsigned XCOFFTracebackTable : 1;
+
     unsigned UniqueSectionNames : 1;
 
     /// Use unique names for basic block sections.
     unsigned UniqueBasicBlockSectionNames : 1;
 
     /// Emit target-specific trap instruction for 'unreachable' IR instructions.
     unsigned TrapUnreachable : 1;
 

llvm/lib/BinaryFormat/XCOFF.cpp

 //===-- llvm/BinaryFormat/XCOFF.cpp - The XCOFF file format -----*- C++/-*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/BinaryFormat/XCOFF.h"
+#include "llvm/ADT/SmallString.h"
 #include "llvm/ADT/StringRef.h"
 
 using namespace llvm;
 
 #define SMC_CASE(A)                                                            \
   case XCOFF::XMC_##A:                                                         \
     return #A;
 StringRef XCOFF::getMappingClassString(XCOFF::StorageMappingClass SMC) {
switch (Type) {
     RELOC_CASE(R_TLS_LE)
     RELOC_CASE(R_TLSM)
     RELOC_CASE(R_TLSML)
     RELOC_CASE(R_TOCU)
     RELOC_CASE(R_TOCL)
   }
   return "Unknown";
 }
+
+#define LANG_CASE(A)                                                           \
+  case XCOFF::TracebackTable::A:                                               \
+    return #A;
+
+StringRef XCOFF::getNameForTracebackTableLanguageId(
+    XCOFF::TracebackTable::LanguageID LangId) {
+  switch (LangId) {
+    LANG_CASE(C)
+    LANG_CASE(Fortran)
+    LANG_CASE(Pascal)
+    LANG_CASE(Ada)
+    LANG_CASE(PL1)
+    LANG_CASE(Basic)
+    LANG_CASE(Lisp)
+    LANG_CASE(Cobol)
+    LANG_CASE(Modula2)
+    LANG_CASE(Rpg)
+    LANG_CASE(PL8)
+    LANG_CASE(Assembly)
+    LANG_CASE(Java)
+    LANG_CASE(ObjectiveC)
+    LANG_CASE(CPlusPlus)
+  }
+  return "Unknown";
+}
+#undef LANG_CASE
+
+SmallString<32> XCOFF::parseParmsType(uint32_t Value, unsigned ParmsNum) {
+  SmallString<32> ParmsType;
+  for (unsigned I = 0; I < ParmsNum; ++I) {
+    if (I != 0)
+      ParmsType += ", ";
+    if ((Value & TracebackTable::ParmTypeIsFloatingBit) == 0) {
+      // Fixed parameter type.
+      ParmsType += "i";
+      Value <<= 1;
+    } else {
+      if ((Value & TracebackTable::ParmTypeFloatingIsDoubleBit) == 0)
+        // Float parameter type.
+        ParmsType += "f";
+      else
+        // Double parameter type.
+        ParmsType += "d";
+
+      Value <<= 2;
+    }
+  }
+  assert(Value == 0u && "ParmsType encodes more than ParmsNum parameters.");
+  return ParmsType;
+}
+
 #undef RELOC_CASE

llvm/lib/CodeGen/CommandFlags.cpp

 CGOPT(unsigned, OverrideStackAlignment)
 CGOPT(bool, StackRealign)
 CGOPT(std::string, TrapFuncName)
 CGOPT(bool, UseCtors)
 CGOPT(bool, RelaxELFRelocations)
 CGOPT_EXP(bool, DataSections)
 CGOPT_EXP(bool, FunctionSections)
 CGOPT(bool, IgnoreXCOFFVisibility)
+CGOPT(bool, XCOFFTracebackTable)
 CGOPT(std::string, BBSections)
 CGOPT(std::string, StackProtectorGuard)
 CGOPT(unsigned, StackProtectorGuardOffset)
 CGOPT(std::string, StackProtectorGuardReg)
 CGOPT(unsigned, TLSSize)
 CGOPT(bool, EmulatedTLS)
 CGOPT(bool, UniqueSectionNames)
 CGOPT(bool, UniqueBasicBlockSectionNames)
#define CGBINDOPT(NAME)                                                        \
 
   static cl::opt<bool> IgnoreXCOFFVisibility(
       "ignore-xcoff-visibility",
       cl::desc("Not emit the visibility attribute for asm in AIX OS or give "
                "all symbols 'unspecified' visibility in XCOFF object file"),
       cl::init(false));
   CGBINDOPT(IgnoreXCOFFVisibility);
 
+  static cl::opt<bool> XCOFFTracebackTable(
+      "xcoff-traceback-table", cl::desc("Emit the XCOFF traceback table"),
+      cl::init(true));
+  CGBINDOPT(XCOFFTracebackTable);
+
   static cl::opt<std::string> BBSections(
       "basic-block-sections",
       cl::desc("Emit basic blocks into separate sections"),
       cl::value_desc("all | <function list (file)> | labels | none"),
       cl::init("none"));
   CGBINDOPT(BBSections);
 
   static cl::opt<std::string> StackProtectorGuard(
codegen::InitTargetOptionsFromCodeGenFlags(const Triple &TheTriple) {
   Options.StackAlignmentOverride = getOverrideStackAlignment();
   Options.StackSymbolOrdering = getStackSymbolOrdering();
   Options.UseInitArray = !getUseCtors();
   Options.RelaxELFRelocations = getRelaxELFRelocations();
   Options.DataSections =
       getExplicitDataSections().getValueOr(TheTriple.hasDefaultDataSections());
   Options.FunctionSections = getFunctionSections();
   Options.IgnoreXCOFFVisibility = getIgnoreXCOFFVisibility();
+  Options.XCOFFTracebackTable = getXCOFFTracebackTable();
   Options.BBSections = getBBSectionsMode(Options);
   Options.UniqueSectionNames = getUniqueSectionNames();
   Options.UniqueBasicBlockSectionNames = getUniqueBasicBlockSectionNames();
   Options.StackProtectorGuard = getStackProtectorGuardMode(Options);
   Options.StackProtectorGuardOffset = getStackProtectorGuardOffset();
   Options.StackProtectorGuardReg = getStackProtectorGuardReg();
   Options.TLSSize = getTLSSize();
   Options.EmulatedTLS = getEmulatedTLS();

llvm/lib/Object/XCOFFObjectFile.cpp

while (I < ParmsNum || Value) {
     Value <<= 2;
   }
   assert(I == ParmsNum &&
          "The total parameters number of fixed-point or floating-point "
          "parameters not equal to the number in the parameter type!");
   return ParmsType;
 }
 
-static SmallString<32> parseParmsType(uint32_t Value, unsigned ParmsNum) {
-  SmallString<32> ParmsType;
-  for (unsigned I = 0; I < ParmsNum; ++I) {
-    if (I != 0)
-      ParmsType += ", ";
-    if ((Value & TracebackTable::ParmTypeIsFloatingBit) == 0) {
-      // Fixed parameter type.
-      ParmsType += "i";
-      Value <<= 1;
-    } else {
-      if ((Value & TracebackTable::ParmTypeFloatingIsDoubleBit) == 0)
-        // Float parameter type.
-        ParmsType += "f";
-      else
-        // Double parameter type.
-        ParmsType += "d";
-
-      Value <<= 2;
-    }
-  }
-  return ParmsType;
-}
-
 Expected<XCOFFTracebackTable> XCOFFTracebackTable::create(const uint8_t *Ptr,
                                                           uint64_t &Size) {
   Error Err = Error::success();
   XCOFFTracebackTable TBT(Ptr, Size, Err);
   if (Err)
     return std::move(Err);
   return TBT;
 }

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

 #include "llvm/Transforms/Utils/ModuleUtils.h"
 #include <algorithm>
 #include <cassert>
 #include <cstdint>
 #include <memory>
 #include <new>
 
 using namespace llvm;
+using namespace llvm::XCOFF;
 
 #define DEBUG_TYPE "asmprinter"
 
 namespace {
 
 class PPCAsmPrinter : public AsmPrinter {
 protected:
   MapVector<const MCSymbol *, MCSymbol *> TOC;
private:
   std::string FormatIndicatorAndUniqueModId;
 
   static void ValidateGV(const GlobalVariable *GV);
   // Record a list of GlobalAlias associated with a GlobalObject.
   // This is used for AIX's extra-label-at-definition aliasing strategy.
   DenseMap<const GlobalObject *, SmallVector<const GlobalAlias *, 1>>
       GOAliasMap;
 
+  void emitTracebackTable();
+
 public:
   PPCAIXAsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
       : PPCAsmPrinter(TM, std::move(Streamer)) {
     if (MAI->isLittleEndian())
       report_fatal_error(
           "cannot create AIX PPC Assembly Printer for a little-endian target");
   }
 
   StringRef getPassName() const override { return "AIX PPC Assembly Printer"; }
 
   bool doInitialization(Module &M) override;
 
   void emitXXStructorList(const DataLayout &DL, const Constant *List,
                           bool IsCtor) override;
 
   void SetupMachineFunction(MachineFunction &MF) override;
 
   void emitGlobalVariable(const GlobalVariable *GV) override;
 
   void emitFunctionDescriptor() override;
 
   void emitFunctionEntryLabel() override;
 
+  void emitFunctionBodyEnd() override;
+
   void emitEndOfAsmFile(Module &) override;
 
   void emitLinkage(const GlobalValue *GV, MCSymbol *GVSym) const override;
 
   void emitInstruction(const MachineInstr *MI) override;
 
   bool doFinalization(Module &M) override;
 
   void emitTTypeReference(const GlobalValue *GV, unsigned Encoding) override;
 };
 
 } // end anonymous namespace
 
 void PPCAsmPrinter::PrintSymbolOperand(const MachineOperand &MO,
                                        raw_ostream &O) {
   // Computing the address of a global symbol, not calling it.
   const GlobalValue *GV = MO.getGlobal();
   getSymbol(GV)->print(O, MAI);
   printOffset(MO.getOffset(), O);
MCSectionXCOFF *FnDescSec =
           &MF.getFunction(), TM));
   FnDescSec->setAlignment(Align(Subtarget->isPPC64() ? 8 : 4));
 
   CurrentFnDescSym = FnDescSec->getQualNameSymbol();
 
   return AsmPrinter::SetupMachineFunction(MF);
 }
 
+void PPCAIXAsmPrinter::emitFunctionBodyEnd() {
+
+  if (!TM.getXCOFFTracebackTable())
+    return;
+
+  emitTracebackTable();
+}
+
+void PPCAIXAsmPrinter::emitTracebackTable() {
+
+  // Create a symbol for the end of function.
+  MCSymbol *FuncEnd = createTempSymbol(MF->getName());
+  OutStreamer->emitLabel(FuncEnd);
+
+  OutStreamer->AddComment("Traceback table begin");
+  // Begin with a fullword of zero.
+  OutStreamer->emitIntValueInHexWithPadding(0, 4 /*size*/);
+
+  SmallString<128> CommentString;
+  raw_svector_ostream CommentOS(CommentString);
+
+  auto EmitComment = [&]() {
+    OutStreamer->AddComment(CommentOS.str());
+    CommentString.clear();
+  };
+
+  auto EmitCommentAndValue = [&](uint64_t Value, int Size) {
+    EmitComment();
+    OutStreamer->emitIntValueInHexWithPadding(Value, Size);
+  };
+
+  unsigned int Version = 0;
+  CommentOS << "Version = " << Version;
+  EmitCommentAndValue(Version, 1);
+
+  // There is a lack of information in the IR to assist with determining the
+  // source language. AIX exception handling mechanism would only search for
+  // personality routine and LSDA area when such language supports exception
+  // handling. So to be conservatively correct and allow runtime to do its job,
+  // we need to set it to C++ for now.
+  TracebackTable::LanguageID LanguageIdentifier =
+      TracebackTable::CPlusPlus; // C++
+
+  CommentOS << "Language = "
+            << getNameForTracebackTableLanguageId(LanguageIdentifier);
+  EmitCommentAndValue(LanguageIdentifier, 1);
+
+  //  This is only populated for the third and fourth bytes.
+  uint32_t FirstHalfOfMandatoryField = 0;
+
+  // Emit the 3rd byte of the mandatory field.
+
+  // We always set traceback offset bit to true.
+  FirstHalfOfMandatoryField |= TracebackTable::HasTraceBackTableOffsetMask;
+
+  const PPCFunctionInfo *FI = MF->getInfo<PPCFunctionInfo>();
+  const MachineRegisterInfo &MRI = MF->getRegInfo();
+
+  // Check the function uses floating-point processor instructions or not
+  for (unsigned Reg = PPC::F0; Reg <= PPC::F31; ++Reg) {
+    if (MRI.isPhysRegUsed(Reg)) {
+      FirstHalfOfMandatoryField |= TracebackTable::IsFloatingPointPresentMask;
+      break;
+    }
+  }
+
+#define GENBOOLCOMMENT(Prefix, V, Field)                                       \
+  CommentOS << (Prefix) << ((V) & (TracebackTable::Field##Mask) ? "+" : "-")   \
+            << #Field
+
+#define GENVALUECOMMENT(PrefixAndName, V, Field)                               \
+  CommentOS << (PrefixAndName) << " = "                                        \
+            << static_cast<unsigned>(((V) & (TracebackTable::Field##Mask)) >>  \
+                                     (TracebackTable::Field##Shift))
+
+  GENBOOLCOMMENT("", FirstHalfOfMandatoryField, IsGlobaLinkage);
+  GENBOOLCOMMENT(", ", FirstHalfOfMandatoryField, IsOutOfLineEpilogOrPrologue);
+  EmitComment();
+
+  GENBOOLCOMMENT("", FirstHalfOfMandatoryField, HasTraceBackTableOffset);
+  GENBOOLCOMMENT(", ", FirstHalfOfMandatoryField, IsInternalProcedure);
+  EmitComment();
+
+  GENBOOLCOMMENT("", FirstHalfOfMandatoryField, HasControlledStorage);
+  GENBOOLCOMMENT(", ", FirstHalfOfMandatoryField, IsTOCless);
+  EmitComment();
+
+  GENBOOLCOMMENT("", FirstHalfOfMandatoryField, IsFloatingPointPresent);
+  EmitComment();
+  GENBOOLCOMMENT("", FirstHalfOfMandatoryField,
+                 IsFloatingPointOperationLogOrAbortEnabled);
+  EmitComment();
+
+  OutStreamer->emitIntValueInHexWithPadding(
+      (FirstHalfOfMandatoryField & 0x0000ff00) >> 8, 1);
+
+  // Set the 4th byte of the mandatory field.
+  FirstHalfOfMandatoryField |= TracebackTable::IsFunctionNamePresentMask;
+
+  static_assert(XCOFF::AllocRegNo == 31, "Unexpected register usage!");
+  if (MRI.isPhysRegUsed(Subtarget->isPPC64() ? PPC::X31 : PPC::R31))
+    FirstHalfOfMandatoryField |= TracebackTable::IsAllocaUsedMask;
+
+  const SmallVectorImpl<Register> &MustSaveCRs = FI->getMustSaveCRs();
+  if (!MustSaveCRs.empty())
+    FirstHalfOfMandatoryField |= TracebackTable::IsCRSavedMask;
+
+  if (FI->mustSaveLR())
+    FirstHalfOfMandatoryField |= TracebackTable::IsLRSavedMask;
+
+  GENBOOLCOMMENT("", FirstHalfOfMandatoryField, IsInterruptHandler);
+  GENBOOLCOMMENT(", ", FirstHalfOfMandatoryField, IsFunctionNamePresent);
+  GENBOOLCOMMENT(", ", FirstHalfOfMandatoryField, IsAllocaUsed);
+  EmitComment();
+  GENVALUECOMMENT("OnConditionDirective", FirstHalfOfMandatoryField,
+                  OnConditionDirective);
+  GENBOOLCOMMENT(", ", FirstHalfOfMandatoryField, IsCRSaved);
+  GENBOOLCOMMENT(", ", FirstHalfOfMandatoryField, IsLRSaved);
+  EmitComment();
+  OutStreamer->emitIntValueInHexWithPadding((FirstHalfOfMandatoryField & 0xff),
+                                            1);
+
+  // Set the 5th byte of mandatory field.
+  uint32_t SecondHalfOfMandatoryField = 0;
+
+  // Always store back chain.
+  SecondHalfOfMandatoryField |= TracebackTable::IsBackChainStoredMask;
+
+  uint32_t FPRSaved = 0;
+  for (unsigned Reg = PPC::F14; Reg <= PPC::F31; ++Reg) {
+    if (MRI.isPhysRegModified(Reg)) {
+      FPRSaved = PPC::F31 - Reg + 1;
+      break;
+    }
+  }
+  SecondHalfOfMandatoryField |= (FPRSaved << TracebackTable::FPRSavedShift) &
+                                TracebackTable::FPRSavedMask;
+  GENBOOLCOMMENT("", SecondHalfOfMandatoryField, IsBackChainStored);
+  GENBOOLCOMMENT(", ", SecondHalfOfMandatoryField, IsFixup);
+  GENVALUECOMMENT(", NumOfFPRsSaved", SecondHalfOfMandatoryField, FPRSaved);
+  EmitComment();
+  OutStreamer->emitIntValueInHexWithPadding(
+      (SecondHalfOfMandatoryField & 0xff000000) >> 24, 1);
+
+  // Set the 6th byte of mandatory field.
+  uint32_t GPRSaved = 0;
+
+  // X13 is reserved under 64-bit environment.
+  unsigned GPRBegin = Subtarget->isPPC64() ? PPC::X14 : PPC::R13;
+  unsigned GPREnd = Subtarget->isPPC64() ? PPC::X31 : PPC::R31;
+
+  for (unsigned Reg = GPRBegin; Reg <= GPREnd; ++Reg) {
+    if (MRI.isPhysRegModified(Reg)) {
+      GPRSaved = GPREnd - Reg + 1;
+      break;
+    }
+  }
+
+  SecondHalfOfMandatoryField |= (GPRSaved << TracebackTable::GPRSavedShift) &
+                                TracebackTable::GPRSavedMask;
+
+  GENBOOLCOMMENT("", SecondHalfOfMandatoryField, HasVectorInfo);
+  GENBOOLCOMMENT(", ", SecondHalfOfMandatoryField, HasExtensionTable);
+  GENVALUECOMMENT(", NumOfGPRsSaved", SecondHalfOfMandatoryField, GPRSaved);
+  EmitComment();
+  OutStreamer->emitIntValueInHexWithPadding(
+      (SecondHalfOfMandatoryField & 0x00ff0000) >> 16, 1);
+
+  // Set the 7th byte of mandatory field.
+  uint32_t NumberOfFixedPara = FI->getFixedParamNum();
+  SecondHalfOfMandatoryField |=
+      (NumberOfFixedPara << TracebackTable::NumberOfFixedParmsShift) &
+      TracebackTable::NumberOfFixedParmsMask;
+  GENVALUECOMMENT("NumberOfFixedParms", SecondHalfOfMandatoryField,
+                  NumberOfFixedParms);
+  EmitComment();
+  OutStreamer->emitIntValueInHexWithPadding(
+      (SecondHalfOfMandatoryField & 0x0000ff00) >> 8, 1);
+
+  // Set the 8th byte of mandatory field.
+
+  // Always set parameter on stack.
+  SecondHalfOfMandatoryField |= TracebackTable::HasParmsOnStackMask;
+
+  uint32_t NumberOfFPPara = FI->getFloatingPointParamNum();
+  SecondHalfOfMandatoryField |=
+      (NumberOfFPPara << TracebackTable::NumberOfFloatingPointParmsShift) &
+      TracebackTable::NumberOfFloatingPointParmsMask;
+
+  GENVALUECOMMENT("NumberOfFPParms", SecondHalfOfMandatoryField,
+                  NumberOfFloatingPointParms);
+  GENBOOLCOMMENT(", ", SecondHalfOfMandatoryField, HasParmsOnStack);
+  EmitComment();
+  OutStreamer->emitIntValueInHexWithPadding(SecondHalfOfMandatoryField & 0xff,
+                                            1);
+
+  // Generate the optional fields of traceback table.
+
+  // Parameter type.
+  if (NumberOfFixedPara || NumberOfFPPara) {
+    assert((SecondHalfOfMandatoryField & TracebackTable::HasVectorInfoMask) ==
+               0 &&
+           "VectorInfo has not been implemented.");
+    uint32_t ParaType = FI->getParameterType();
+    CommentOS << "Parameter type = "
+              << XCOFF::parseParmsType(ParaType,
+                                       NumberOfFixedPara + NumberOfFPPara);
+    EmitComment();
+    OutStreamer->emitIntValueInHexWithPadding(ParaType, sizeof(ParaType));
+  }
+
+  // Traceback table offset.
+  OutStreamer->AddComment("Function size");
+  if (FirstHalfOfMandatoryField & TracebackTable::HasTraceBackTableOffsetMask) {
+    MCSymbol *FuncSectSym = getObjFileLowering().getFunctionEntryPointSymbol(
+        &(MF->getFunction()), TM);
+    OutStreamer->emitAbsoluteSymbolDiff(FuncEnd, FuncSectSym, 4);
+  }
+
+  // Since we unset the Int_Handler.
+  if (FirstHalfOfMandatoryField & TracebackTable::IsInterruptHandlerMask)
+    report_fatal_error("Hand_Mask not implement yet");
+
+  if (FirstHalfOfMandatoryField & TracebackTable::HasControlledStorageMask)
+    report_fatal_error("Ctl_Info not implement yet");
+
+  if (FirstHalfOfMandatoryField & TracebackTable::IsFunctionNamePresentMask) {
+    StringRef Name = MF->getName().substr(0, INT16_MAX);
+    int16_t NameLength = Name.size();
+    CommentOS << "Function name len = "
+              << static_cast<unsigned int>(NameLength);
+    EmitCommentAndValue(NameLength, 2);
+    OutStreamer->AddComment("Function Name");
+    OutStreamer->emitBytes(Name);
+  }
+
+  if (FirstHalfOfMandatoryField & TracebackTable::IsAllocaUsedMask) {
+    uint8_t AllocReg = XCOFF::AllocRegNo;
+    OutStreamer->AddComment("AllocaUsed");
+    OutStreamer->emitIntValueInHex(AllocReg, sizeof(AllocReg));
+  }
+#undef GENBOOLCOMMENT
+#undef GENVALUECOMMENT
+}
+
 void PPCAIXAsmPrinter::ValidateGV(const GlobalVariable *GV) {
   // Early error checking limiting what is supported.
   if (GV->isThreadLocal())
     report_fatal_error("Thread local not yet supported on AIX.");
 
   if (GV->hasComdat())
     report_fatal_error("COMDAT not yet supported by AIX.");
 }
 
 static bool isSpecialLLVMGlobalArrayToSkip(const GlobalVariable *GV) {
   return GV->hasAppendingLinkage() &&

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

 /// on Darwin and AIX.
 static const MCPhysReg FPR[] = {PPC::F1,  PPC::F2,  PPC::F3, PPC::F4, PPC::F5,
                                 PPC::F6,  PPC::F7,  PPC::F8, PPC::F9, PPC::F10,
                                 PPC::F11, PPC::F12, PPC::F13};
 
 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
 /// the stack.
 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
                                        unsigned PtrByteSize) {
   unsigned ArgSize = ArgVT.getStoreSize();
   if (Flags.isByVal())
     ArgSize = Flags.getByValSize();
 
   // Round up to multiples of the pointer size, except for array members,
   // which are always packed.
   if (!Flags.isInConsecutiveRegs())
     ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
SDValue PPCTargetLowering::LowerFormalArguments_AIX(
 
   const bool IsPPC64 = Subtarget.isPPC64();
   const unsigned PtrByteSize = IsPPC64 ? 8 : 4;
 
   // Assign locations to all of the incoming arguments.
   SmallVector<CCValAssign, 16> ArgLocs;
   MachineFunction &MF = DAG.getMachineFunction();
   MachineFrameInfo &MFI = MF.getFrameInfo();
+  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
   CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
 
   const EVT PtrVT = getPointerTy(MF.getDataLayout());
   // Reserve space for the linkage area on the stack.
   const unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
   CCInfo.AllocateStack(LinkageSize, Align(PtrByteSize));
   CCInfo.AnalyzeFormalArguments(Ins, CC_AIX);
 
for (size_t I = 0, End = ArgLocs.size(); I != End; /* No increment here */) {
     // parameter save area are initialized even if the argument is available
     // in register.  The caller is required to initialize both the register
     // and memory, however, the callee can choose to expect it in either.
     // The memloc is dismissed here because the argument is retrieved from
     // the register.
     if (VA.isMemLoc() && VA.needsCustom())
       continue;
 
+    if (VA.isRegLoc()) {
+      if (VA.getValVT().isScalarInteger())
+        FuncInfo->appendParameterType(PPCFunctionInfo::FixedType);
+      else if (VA.getValVT().isFloatingPoint() && !VA.getValVT().isVector())
+        FuncInfo->appendParameterType(VA.getValVT().SimpleTy == MVT::f32
+                                          ? PPCFunctionInfo::ShortFloatPoint
+                                          : PPCFunctionInfo::LongFloatPoint);
+    }
+
     if (Flags.isByVal() && VA.isMemLoc()) {
       const unsigned Size =
           alignTo(Flags.getByValSize() ? Flags.getByValSize() : PtrByteSize,
                   PtrByteSize);
       const int FI = MF.getFrameInfo().CreateFixedObject(
           Size, VA.getLocMemOffset(), /* IsImmutable */ false,
           /* IsAliased */ true);
       SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
if (Flags.isByVal()) {
       Offset += PtrByteSize;
       for (; Offset != StackSize && ArgLocs[I].isRegLoc();
            Offset += PtrByteSize) {
         assert(ArgLocs[I].getValNo() == VA.getValNo() &&
                "RegLocs should be for ByVal argument.");
 
         const CCValAssign RL = ArgLocs[I++];
         HandleRegLoc(RL.getLocReg(), Offset);
+        FuncInfo->appendParameterType(PPCFunctionInfo::FixedType);
       }
 
       if (Offset != StackSize) {
         assert(ArgLocs[I].getValNo() == VA.getValNo() &&
                "Expected MemLoc for remaining bytes.");
         assert(ArgLocs[I].isMemLoc() && "Expected MemLoc for remaining bytes.");
         // Consume the MemLoc.The InVal has already been emitted, so nothing
         // more needs to be done.
unsigned CallerReservedArea =
       std::max(CCInfo.getNextStackOffset(), LinkageSize + MinParameterSaveArea);
 
   // Set the size that is at least reserved in caller of this function. Tail
   // call optimized function's reserved stack space needs to be aligned so
   // that taking the difference between two stack areas will result in an
   // aligned stack.
   CallerReservedArea =
       EnsureStackAlignment(Subtarget.getFrameLowering(), CallerReservedArea);
-  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
   FuncInfo->setMinReservedArea(CallerReservedArea);
 
   if (isVarArg) {
     FuncInfo->setVarArgsFrameIndex(
         MFI.CreateFixedObject(PtrByteSize, CCInfo.getNextStackOffset(), true));
     SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
 
     static const MCPhysReg GPR_32[] = {PPC::R3, PPC::R4, PPC::R5, PPC::R6,

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h

 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/TargetCallingConv.h"
 
 namespace llvm {
 
 /// PPCFunctionInfo - This class is derived from MachineFunction private
 /// PowerPC target-specific information for each MachineFunction.
 class PPCFunctionInfo : public MachineFunctionInfo {
+public:
+  // The value in the ParamType are used to indicate the bitstrings used in the
+  // encoding format.
+  enum ParamType {
+    FixedType = 0x0,
+    ShortFloatPoint = 0x2,
+    LongFloatPoint = 0x3
+  };
+
+private:
   virtual void anchor();
 
   /// FramePointerSaveIndex - Frame index of where the old frame pointer is
   /// stored.  Also used as an anchor for instructions that need to be altered
   /// when using frame pointers (dyna_add, dyna_sub.)
   int FramePointerSaveIndex = 0;
 
   /// ReturnAddrSaveIndex - Frame index of where the return address is stored.
private:
   /// VarArgsNumGPR - Index of the first unused integer
   /// register for parameter passing.
   unsigned VarArgsNumGPR = 0;
 
   /// VarArgsNumFPR - Index of the first unused double
   /// register for parameter passing.
   unsigned VarArgsNumFPR = 0;
 
+  /// FixedParamNum - Number of fixed parameter.
+  unsigned FixedParamNum = 0;
+
+  /// FloatingParamNum - Number of floating point parameter.
+  unsigned FloatingPointParamNum = 0;
+
+  /// ParamType - Encode type for every parameter
+  /// in the order of parameters passing in.
+  /// Bitstring starts from the most significant (leftmost) bit.
+  /// '0'b => fixed parameter.
+  /// '10'b => floating point short parameter.
+  /// '11'b => floating point long parameter.
+  uint32_t ParameterType = 0;
+
   /// CRSpillFrameIndex - FrameIndex for CR spill slot for 32-bit SVR4.
   int CRSpillFrameIndex = 0;
 
   /// If any of CR[2-4] need to be saved in the prologue and restored in the
   /// epilogue then they are added to this array. This is used for the
   /// 64-bit SVR4 ABI.
   SmallVector<Register, 3> MustSaveCRs;
 
public:
   void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; }
 
   int getVarArgsStackOffset() const { return VarArgsStackOffset; }
   void setVarArgsStackOffset(int Offset) { VarArgsStackOffset = Offset; }
 
   unsigned getVarArgsNumGPR() const { return VarArgsNumGPR; }
   void setVarArgsNumGPR(unsigned Num) { VarArgsNumGPR = Num; }
 
+  unsigned getFixedParamNum() const { return FixedParamNum; }
+
+  unsigned getFloatingPointParamNum() const { return FloatingPointParamNum; }
+
+  uint32_t getParameterType() const { return ParameterType; }
+  void appendParameterType(ParamType Type);
+
   unsigned getVarArgsNumFPR() const { return VarArgsNumFPR; }
   void setVarArgsNumFPR(unsigned Num) { VarArgsNumFPR = Num; }
 
   /// This function associates attributes for each live-in virtual register.
   void addLiveInAttr(Register VReg, ISD::ArgFlagsTy Flags) {
     LiveInAttrs.push_back(std::make_pair(VReg, Flags));
   }
 

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp

 //===-- PPCMachineFunctionInfo.cpp - Private data used for PowerPC --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "PPCMachineFunctionInfo.h"
 #include "llvm/ADT/Twine.h"
+#include "llvm/BinaryFormat/XCOFF.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/Support/CommandLine.h"
 
 using namespace llvm;
 static cl::opt<bool> PPCDisableNonVolatileCR(
     "ppc-disable-non-volatile-cr",
     cl::desc("Disable the use of non-volatile CR register fields"),

 }
 
 bool PPCFunctionInfo::isLiveInZExt(Register VReg) const {
   for (const std::pair<Register, ISD::ArgFlagsTy> &LiveIn : LiveInAttrs)
     if (LiveIn.first == VReg)
       return LiveIn.second.isZExt();
   return false;
 }
+
+void PPCFunctionInfo::appendParameterType(ParamType Type) {
+  uint32_t CopyParamType = ParameterType;
+  unsigned Bits = 0;
+
+  // If it is fixed type, we only need to increase the FixedParamNum, for
+  // the bit encode of fixed type is bit of zero, we do not need to change the
+  // ParamType.
+  if (Type == FixedType) {
+    ++FixedParamNum;
+    return;
+  }
+
+  ++FloatingPointParamNum;
+
+  for (int I = 0;
+       I < static_cast<int>(FloatingPointParamNum + FixedParamNum - 1); ++I) {
+    if (CopyParamType & XCOFF::TracebackTable::ParmTypeIsFloatingBit) {
+      // '10'b => floating point short parameter.
+      // '11'b => floating point long parameter.
+      CopyParamType <<= 2;
+      Bits += 2;
+    } else {
+      // '0'b => fixed parameter.
+      CopyParamType <<= 1;
+      ++Bits;
+    }
+  }
+
+  assert(Type != FixedType && "FixedType should already be handled.");
+  if (30 - Bits >= 0)
+    ParameterType |= Type << (30 - Bits);
+}

llvm/test/CodeGen/PowerPC/aix-alias.ll

 ; TODO: Add object generation test when visibility for object generation
 ;       is implemnted.
 
 ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
-; RUN:     -mattr=-altivec -data-sections=false < %s | \
+; RUN:     -mattr=-altivec -data-sections=false -xcoff-traceback-table=false < %s | \
 ; RUN:   FileCheck --check-prefix=ASM %s
 ; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr4 \
-; RUN:     -mattr=-altivec -data-sections=false < %s | \
+; RUN:     -mattr=-altivec -data-sections=false -xcoff-traceback-table=false < %s | \
 ; RUN:   FileCheck --check-prefix=ASM %s
 
 @var = global i32 42
 @var1 = alias i32, i32* @var
 @var2 = alias i32, i32* @var1
 @var_l = linkonce_odr alias i32, i32* @var
 @var_i = internal alias i32, i32* @var
 @var_h = hidden alias i32, i32* @var

llvm/test/CodeGen/PowerPC/aix-cc-ext-vec-abi.ll

-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec -xcoff-traceback-table=false \
 ; RUN:  -vec-extabi -mtriple powerpc-ibm-aix-xcoff < %s | \
 ; RUN: FileCheck --check-prefixes=ASM32,ASM %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec -xcoff-traceback-table=false \
 ; RUN:  -vec-extabi -mtriple powerpc64-ibm-aix-xcoff < %s | \
 ; RUN: FileCheck --check-prefixes=ASM64,ASM %s
 
 define dso_local <4 x i32> @vec_callee(<4 x i32> %vec1, <4 x i32> %vec2, <4 x i32> %vec3, <4 x i32> %vec4, <4 x i32> %vec5, <4 x i32> %vec6, <4 x i32> %vec7, <4 x i32> %vec8, <4 x i32> %vec9, <4 x i32> %vec10, <4 x i32> %vec11, <4 x i32> %vec12) {
 entry:
   %add = add <4 x i32> %vec1, %vec2
   %add1 = add <4 x i32> %add, %vec3
   %add2 = add <4 x i32> %add1, %vec4

llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-clobber-register.ll

+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN:     -mattr=-altivec -xcoff-traceback-table=true < %s | \
+; RUN:   FileCheck --check-prefixes=CHECK-ASM,COMMON %s
+
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -function-sections \
+; RUN:     -mcpu=pwr4 -mattr=-altivec < %s | \
+; RUN:   FileCheck --check-prefixes=CHECK-FUNC,COMMON %s
+
+define float @bar() #0 {
+entry:
+  %fvalue = alloca float, align 4
+  %taken = alloca i32, align 4
+  %data = alloca i32, align 4
+  store float 1.000000e+00, float* %fvalue, align 4
+  %0 = load float, float* %fvalue, align 4
+  %1 = call float asm "fneg $0,$1\0A\09", "=b,b,~{f31},~{f30},~{f29},~{f28},~{f27}"(float %0)
+  store float %1, float* %fvalue, align 4
+  store i32 123, i32* %data, align 4
+  %2 = load i32, i32* %data, align 4
+  %3 = call i32 asm "cntlzw $0, $1\0A\09", "=b,b,~{r31},~{r30},~{r29},~{r28}"(i32 %2)
+  store i32 %3, i32* %taken, align 4
+  %4 = load i32, i32* %taken, align 4
+  %conv = sitofp i32 %4 to float
+  %5 = load float, float* %fvalue, align 4
+  %add = fadd float %conv, %5
+  ret float %add
+}
+
+; COMMON:       .vbyte  4, 0x00000000                   # Traceback table begin
+; COMMON-NEXT:  .byte   0x00                            # Version = 0
+; COMMON-NEXT:  .byte   0x09                            # Language = CPlusPlus
+; COMMON-NEXT:  .byte   0x22                            # -IsGlobaLinkage, -IsOutOfLineEpilogOrPrologue
+; COMMON-NEXT:                                        # +HasTraceBackTableOffset, -IsInternalProcedure
+; COMMON-NEXT:                                        # -HasControlledStorage, -IsTOCless
+; COMMON-NEXT:                                        # +IsFloatingPointPresent
+; COMMON-NEXT:                                        # -IsFloatingPointOperationLogOrAbortEnabled
+; COMMON-NEXT:  .byte   0x60                            # -IsInterruptHandler, +IsFunctionNamePresent, +IsAllocaUsed
+; COMMON-NEXT:                                        # OnConditionDirective = 0, -IsCRSaved, -IsLRSaved
+; COMMON-NEXT:  .byte   0x85                            # +IsBackChainStored, -IsFixup, NumOfFPRsSaved = 5
+; COMMON-NEXT:  .byte   0x04                            # -HasVectorInfo, -HasExtensionTable, NumOfGPRsSaved = 4
+; COMMON-NEXT:  .byte   0x00                            # NumberOfFixedParms = 0
+; COMMON-NEXT:  .byte   0x01                            # NumberOfFPParms = 0, +HasParmsOnStack
+; CHECK-ASM-NEXT:   .vbyte  4, L..bar0-.bar                 # Function size
+; CHECK-FUNC-NEXT:  .vbyte  4, L..bar0-.bar[PR]             # Function size
+; COMMON-NEXT:  .vbyte  2, 0x0003                       # Function name len = 3
+; COMMON-NEXT:  .byte   'b,'a,'r                        # Function Name
+; COMMON-NEXT:  .byte   0x1f                            # AllocaUsed
+; COMMON-NEXT:                                        # -- End function

llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable.ll

+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN:     -mattr=-altivec -xcoff-traceback-table=true < %s | \
+; RUN:   FileCheck --check-prefixes=CHECK-ASM,COMMON %s
+
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -function-sections \
+; RUN:     -mcpu=pwr4 -mattr=-altivec < %s | \
+; RUN:   FileCheck --check-prefixes=CHECK-FUNC,COMMON %s
+
+
+%struct.S = type { i32, i32 }
+%struct.D = type { float, double }
+%struct.SD = type { %struct.S*, %struct.D }
+
+@__const.main.s = private unnamed_addr constant %struct.S { i32 10, i32 20 }, align 4
+@__const.main.d = private unnamed_addr constant %struct.D { float 1.000000e+01, double 2.000000e+01 }, align 8
+
+define double @_Z10add_structifd1SP2SD1Di(i32 %value, float %fvalue, double %dvalue, %struct.S* byval(%struct.S) align 4 %s, %struct.SD* %dp, %struct.D* byval(%struct.D) align 4 %0, i32 %v2) #0 {
+entry:
+  %d = alloca %struct.D, align 8
+  %value.addr = alloca i32, align 4
+  %fvalue.addr = alloca float, align 4
+  %dvalue.addr = alloca double, align 8
+  %dp.addr = alloca %struct.SD*, align 4
+  %v2.addr = alloca i32, align 4
+  %1 = bitcast %struct.D* %d to i8*
+  %2 = bitcast %struct.D* %0 to i8*
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 %1, i8* align 4 %2, i32 16, i1 false)
+  store i32 %value, i32* %value.addr, align 4
+  store float %fvalue, float* %fvalue.addr, align 4
+  store double %dvalue, double* %dvalue.addr, align 8
+  store %struct.SD* %dp, %struct.SD** %dp.addr, align 4
+  store i32 %v2, i32* %v2.addr, align 4
+  %3 = load double, double* %dvalue.addr, align 8
+  %4 = load float, float* %fvalue.addr, align 4
+  %conv = fpext float %4 to double
+  %add = fadd double %3, %conv
+  %5 = load i32, i32* %value.addr, align 4
+  %conv1 = sitofp i32 %5 to double
+  %add2 = fadd double %add, %conv1
+  %i1 = getelementptr inbounds %struct.S, %struct.S* %s, i32 0, i32 0
+  %6 = load i32, i32* %i1, align 4
+  %conv3 = sitofp i32 %6 to double
+  %add4 = fadd double %add2, %conv3
+  %7 = load %struct.SD*, %struct.SD** %dp.addr, align 4
+  %d5 = getelementptr inbounds %struct.SD, %struct.SD* %7, i32 0, i32 1
+  %d1 = getelementptr inbounds %struct.D, %struct.D* %d5, i32 0, i32 1
+  %8 = load double, double* %d1, align 8
+  %add6 = fadd double %add4, %8
+  %f1 = getelementptr inbounds %struct.D, %struct.D* %d, i32 0, i32 0
+  %9 = load float, float* %f1, align 8
+  %conv7 = fpext float %9 to double
+  %add8 = fadd double %add6, %conv7
+  %10 = load i32, i32* %v2.addr, align 4
+  %conv9 = sitofp i32 %10 to double
+  %add10 = fadd double %add8, %conv9
+  ret double %add10
+}
+
+declare void @llvm.memcpy.p0i8.p0i8.i32(i8* noalias nocapture writeonly, i8* noalias nocapture readonly, i32, i1 immarg) #1
+
+define i32 @main() {
+entry:
+  %retval = alloca i32, align 4
+  %s = alloca %struct.S, align 4
+  %d = alloca %struct.D, align 8
+  %sd = alloca %struct.SD, align 8
+  %agg.tmp = alloca %struct.S, align 4
+  %agg.tmp4 = alloca %struct.D, align 8
+  store i32 0, i32* %retval, align 4
+  %0 = bitcast %struct.S* %s to i8*
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %0, i8* align 4 bitcast (%struct.S* @__const.main.s to i8*), i32 8, i1 false)
+  %1 = bitcast %struct.D* %d to i8*
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 %1, i8* align 8 bitcast (%struct.D* @__const.main.d to i8*), i32 16, i1 false)
+  %sp = getelementptr inbounds %struct.SD, %struct.SD* %sd, i32 0, i32 0
+  store %struct.S* %s, %struct.S** %sp, align 8
+  %d1 = getelementptr inbounds %struct.SD, %struct.SD* %sd, i32 0, i32 1
+  %f1 = getelementptr inbounds %struct.D, %struct.D* %d1, i32 0, i32 0
+  store float 1.000000e+02, float* %f1, align 8
+  %d2 = getelementptr inbounds %struct.SD, %struct.SD* %sd, i32 0, i32 1
+  %d13 = getelementptr inbounds %struct.D, %struct.D* %d2, i32 0, i32 1
+  store double 2.000000e+02, double* %d13, align 8
+  %2 = bitcast %struct.S* %agg.tmp to i8*
+  %3 = bitcast %struct.S* %s to i8*
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %2, i8* align 4 %3, i32 8, i1 false)
+  %4 = bitcast %struct.D* %agg.tmp4 to i8*
+  %5 = bitcast %struct.D* %d to i8*
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 %4, i8* align 8 %5, i32 16, i1 false)
+  %call = call double @_Z10add_structifd1SP2SD1Di(i32 1, float 2.000000e+00, double 3.000000e+00, %struct.S* byval(%struct.S) align 4 %agg.tmp, %struct.SD* %sd, %struct.D* byval(%struct.D) align 4 %agg.tmp4, i32 7)
+  %add = fadd double %call, 1.000000e+00
+  %conv = fptosi double %add to i32
+  ret i32 %conv
+}
+
+define double @_Z7add_bari1SfdP2SD1Di(i32 %value, %struct.S* byval(%struct.S) align 4 %s, float %fvalue, double %dvalue, %struct.SD* %dp, %struct.D* byval(%struct.D) align 4 %0, i32 %v2) #0 {
+entry:
+  %d = alloca %struct.D, align 8
+  %value.addr = alloca i32, align 4
+  %fvalue.addr = alloca float, align 4
+  %dvalue.addr = alloca double, align 8
+  %dp.addr = alloca %struct.SD*, align 4
+  %v2.addr = alloca i32, align 4
+  %1 = bitcast %struct.D* %d to i8*
+  %2 = bitcast %struct.D* %0 to i8*
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 %1, i8* align 4 %2, i32 16, i1 false)
+  store i32 %value, i32* %value.addr, align 4
+  store float %fvalue, float* %fvalue.addr, align 4
+  store double %dvalue, double* %dvalue.addr, align 8
+  store %struct.SD* %dp, %struct.SD** %dp.addr, align 4
+  store i32 %v2, i32* %v2.addr, align 4
+  %3 = load double, double* %dvalue.addr, align 8
+  %4 = load float, float* %fvalue.addr, align 4
+  %conv = fpext float %4 to double
+  %add = fadd double %3, %conv
+  %5 = load i32, i32* %value.addr, align 4
+  %conv1 = sitofp i32 %5 to double
+  %add2 = fadd double %add, %conv1
+  %i1 = getelementptr inbounds %struct.S, %struct.S* %s, i32 0, i32 0
+  %6 = load i32, i32* %i1, align 4
+  %conv3 = sitofp i32 %6 to double
+  %add4 = fadd double %add2, %conv3
+  %7 = load %struct.SD*, %struct.SD** %dp.addr, align 4
+  %d5 = getelementptr inbounds %struct.SD, %struct.SD* %7, i32 0, i32 1
+  %d1 = getelementptr inbounds %struct.D, %struct.D* %d5, i32 0, i32 1
+  %8 = load double, double* %d1, align 8
+  %add6 = fadd double %add4, %8
+  %f1 = getelementptr inbounds %struct.D, %struct.D* %d, i32 0, i32 0
+  %9 = load float, float* %f1, align 8
+  %conv7 = fpext float %9 to double
+  %add8 = fadd double %add6, %conv7
+  %10 = load i32, i32* %v2.addr, align 4
+  %conv9 = sitofp i32 %10 to double
+  %add10 = fadd double %add8, %conv9
+  ret double %add10
+}
+
+; CHECK-ASM-LABEL:  ._Z10add_structifd1SP2SD1Di:{{[[:space:]] *}}# %bb.0:
+; CHECK-FUNC-LABEL: csect ._Z10add_structifd1SP2SD1Di[PR],2{{[[:space:]] *}}# %bb.0:
+; COMMON-NEXT:   lwz 4, L..C0(2)
+; COMMON-NEXT:   stfs 1, -24(1)
+; COMMON-NEXT:   lfs 0, 0(4)
+; COMMON-NEXT:   lwz 4, 56(1)
+; COMMON:        fsub 0, 2, 0
+; COMMON-NEXT:   stw 9, -36(1)
+; COMMON-NEXT:   fadd 1, 1, 0
+; COMMON-NEXT:   blr
+; COMMON-NEXT: L.._Z10add_structifd1SP2SD1Di0:
+; COMMON-NEXT:  .vbyte  4, 0x00000000                   # Traceback table begin
+; COMMON-NEXT:  .byte   0x00                            # Version = 0
+; COMMON-NEXT:  .byte   0x09                            # Language = CPlusPlus
+; COMMON-NEXT:  .byte   0x22                            # -IsGlobaLinkage, -IsOutOfLineEpilogOrPrologue
+; COMMON-NEXT:                                        # +HasTraceBackTableOffset, -IsInternalProcedure
+; COMMON-NEXT:                                        # -HasControlledStorage, -IsTOCless
+; COMMON-NEXT:                                        # +IsFloatingPointPresent
+; COMMON-NEXT:                                        # -IsFloatingPointOperationLogOrAbortEnabled
+; COMMON-NEXT:  .byte   0x40                            # -IsInterruptHandler, +IsFunctionNamePresent, -IsAllocaUsed
+; COMMON-NEXT:                                        # OnConditionDirective = 0, -IsCRSaved, -IsLRSaved
+; COMMON-NEXT:  .byte   0x80                            # +IsBackChainStored, -IsFixup, NumOfFPRsSaved = 0
+; COMMON-NEXT:  .byte   0x00                            # -HasVectorInfo, -HasExtensionTable, NumOfGPRsSaved = 0
+; COMMON-NEXT:  .byte   0x05                            # NumberOfFixedParms = 5
+; COMMON-NEXT:  .byte   0x05                            # NumberOfFPParms = 2, +HasParmsOnStack
+; COMMON-NEXT:  .vbyte  4, 0x58000000                   # Parameter type = i, f, d, i, i, i, i
+; CHECK-ASM-NEXT:   .vbyte  4, L.._Z10add_structifd1SP2SD1Di0-._Z10add_structifd1SP2SD1Di # Function size
+; CHECK-FUNC-NEXT:   .vbyte  4, L.._Z10add_structifd1SP2SD1Di0-._Z10add_structifd1SP2SD1Di[PR] # Function size
+; COMMON-NEXT:  .vbyte  2, 0x001a                       # Function name len = 26
+; COMMON-NEXT:  .byte   '_,'Z,'1,'0,'a,'d,'d,'_,'s,'t,'r,'u,'c,'t,'i,'f,'d,'1,'S,'P,'2,'S,'D,'1,'D,'i # Function Name
+; COMMON-NEXT:                                        # -- End function
+
+
+; CHECK-ASM-LABEL:     .main:{{[[:space:]] *}}# %bb.0:
+; CHECK-FUNC-LABEL:   .csect .main[PR],2{{[[:space:]] *}}# %bb.0
+; COMMON-NEXT:   mflr 0
+; COMMON-NEXT:   stw 0, 8(1)
+; COMMON:        mtlr 0
+; COMMON-NEXT:   blr
+; COMMON-NEXT: L..main0:
+; COMMON-NEXT:  .vbyte  4, 0x00000000                   # Traceback table begin
+; COMMON-NEXT:  .byte   0x00                            # Version = 0
+; COMMON-NEXT:  .byte   0x09                            # Language = CPlusPlus
+; COMMON-NEXT:  .byte   0x22                            # -IsGlobaLinkage, -IsOutOfLineEpilogOrPrologue
+; COMMON-NEXT:                                        # +HasTraceBackTableOffset, -IsInternalProcedure
+; COMMON-NEXT:                                        # -HasControlledStorage, -IsTOCless
+; COMMON-NEXT:                                        # +IsFloatingPointPresent
+; COMMON-NEXT:                                        # -IsFloatingPointOperationLogOrAbortEnabled
+; COMMON-NEXT:  .byte   0x41                            # -IsInterruptHandler, +IsFunctionNamePresent, -IsAllocaUsed
+; COMMON-NEXT:                                        # OnConditionDirective = 0, -IsCRSaved, +IsLRSaved
+; COMMON-NEXT:  .byte   0x80                            # +IsBackChainStored, -IsFixup, NumOfFPRsSaved = 0
+; COMMON-NEXT:  .byte   0x00                            # -HasVectorInfo, -HasExtensionTable, NumOfGPRsSaved = 0
+; COMMON-NEXT:  .byte   0x00                            # NumberOfFixedParms = 0
+; COMMON-NEXT:  .byte   0x01                            # NumberOfFPParms = 0, +HasParmsOnStack
+; CHECK-ASM-NEXT:   .vbyte  4, L..main0-.main               # Function size
+; CHECK-FUNC-NEXT:   .vbyte  4, L..main0-.main[PR]               # Function size
+; COMMON-NEXT:  .vbyte  2, 0x0004                       # Function name len = 4
+; COMMON-NEXT:  .byte   'm,'a,'i,'n                     # Function Name
+; COMMON-NEXT:                                        # -- End function
+
+
+; CHECK-ASM-LABEL:    ._Z7add_bari1SfdP2SD1Di:{{[[:space:]] *}}# %bb.0:
+; CHECK-FUNC-LABEL:   .csect ._Z7add_bari1SfdP2SD1Di[PR],2{{[[:space:]] *}}# %bb.0:
+; COMMON:       .vbyte  4, 0x00000000                   # Traceback table begin
+; COMMON-NEXT:  .byte   0x00                            # Version = 0
+; COMMON-NEXT:  .byte   0x09                            # Language = CPlusPlus
+; COMMON-NEXT:  .byte   0x22                            # -IsGlobaLinkage, -IsOutOfLineEpilogOrPrologue
+; COMMON-NEXT:                                        # +HasTraceBackTableOffset, -IsInternalProcedure
+; COMMON-NEXT:                                        # -HasControlledStorage, -IsTOCless
+; COMMON-NEXT:                                        # +IsFloatingPointPresent
+; COMMON-NEXT:                                        # -IsFloatingPointOperationLogOrAbortEnabled
+; COMMON-NEXT:  .byte   0x40                            # -IsInterruptHandler, +IsFunctionNamePresent, -IsAllocaUsed
+; COMMON-NEXT:                                        # OnConditionDirective = 0, -IsCRSaved, -IsLRSaved
+; COMMON-NEXT:  .byte   0x80                            # +IsBackChainStored, -IsFixup, NumOfFPRsSaved = 0
+; COMMON-NEXT:  .byte   0x00                            # -HasVectorInfo, -HasExtensionTable, NumOfGPRsSaved = 0
+; COMMON-NEXT:  .byte   0x05                            # NumberOfFixedParms = 5
+; COMMON-NEXT:  .byte   0x05                            # NumberOfFPParms = 2, +HasParmsOnStack
+; COMMON-NEXT:  .vbyte  4, 0x16000000                   # Parameter type = i, i, i, f, d, i, i
+; CHECK-ASM-NEXT:  .vbyte  4, L.._Z7add_bari1SfdP2SD1Di0-._Z7add_bari1SfdP2SD1Di # Function size
+; CHECK-FUNC-NEXT:  .vbyte  4, L.._Z7add_bari1SfdP2SD1Di0-._Z7add_bari1SfdP2SD1Di[PR] # Function size
+; COMMON-NEXT:  .vbyte  2, 0x0016                       # Function name len = 22
+; COMMON-NEXT:  .byte   '_,'Z,'7,'a,'d,'d,'_,'b,'a,'r,'i,'1,'S,'f,'d,'P,'2,'S,'D,'1,'D,'i # Function Name
+; COMMON-NEXT:                                        # -- End function

llvm/test/CodeGen/PowerPC/aix-extern-weak.ll

 ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
-; RUN: -mattr=-altivec -data-sections=false < %s | FileCheck --check-prefixes=COMMON,BIT32 %s
+; RUN: -mattr=-altivec -data-sections=false -xcoff-traceback-table=false < %s | FileCheck --check-prefixes=COMMON,BIT32 %s
 
 ; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr4 \
-; RUN: -mattr=-altivec -data-sections=false < %s | FileCheck --check-prefixes=COMMON,BIT64 %s
+; RUN: -mattr=-altivec -data-sections=false -xcoff-traceback-table=false < %s | FileCheck --check-prefixes=COMMON,BIT64 %s
 
 ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
-; RUN: -mattr=-altivec -data-sections=false -filetype=obj -o %t.o < %s
+; RUN: -mattr=-altivec -data-sections=false -xcoff-traceback-table=false -filetype=obj -o %t.o < %s
 ; RUN: llvm-readobj --symbols %t.o | FileCheck --check-prefix=CHECKSYM %s
 
 ; RUN: not --crash llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff \
-; RUN: -mattr=-altivec -data-sections=false -filetype=obj -o %t.o 2>&1 < %s | \
+; RUN: -mattr=-altivec -data-sections=false -xcoff-traceback-table=false -filetype=obj -o %t.o 2>&1 < %s | \
 ; RUN:   FileCheck --check-prefix=XCOFF64 %s
 ; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet.
 
 
 @foo_ext_weak_p = global void (...)* bitcast (void ()* @foo_ext_weak_ref to void (...)*)
 @b_w = extern_weak global i32
 
 declare extern_weak void @foo_ext_weak_ref()

llvm/test/CodeGen/PowerPC/aix-extern.ll

 ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
-; RUN: -mattr=-altivec -data-sections=false < %s | FileCheck --check-prefixes=COMMON,BIT32 %s
+; RUN: -mattr=-altivec -data-sections=false -xcoff-traceback-table=false < %s | FileCheck --check-prefixes=COMMON,BIT32 %s
 
 ; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr4 \
-; RUN: -mattr=-altivec -data-sections=false < %s | FileCheck --check-prefixes=COMMON,BIT64 %s
+; RUN: -mattr=-altivec -data-sections=false -xcoff-traceback-table=false < %s | FileCheck --check-prefixes=COMMON,BIT64 %s
 
 ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
-; RUN: -mattr=-altivec -data-sections=false -filetype=obj -o %t.o < %s
+; RUN: -mattr=-altivec -data-sections=false -xcoff-traceback-table=false -filetype=obj -o %t.o < %s
 ; RUN: llvm-readobj --symbols %t.o | FileCheck --check-prefix=CHECKSYM %s
 
 ; RUN: not --crash llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff \
-; RUN: -mattr=-altivec -data-sections=false -filetype=obj -o %t.o 2>&1 < %s | FileCheck --check-prefix=XCOFF64 %s
+; RUN: -mattr=-altivec -data-sections=false -xcoff-traceback-table=false -filetype=obj -o %t.o 2>&1 < %s | FileCheck --check-prefix=XCOFF64 %s
 ; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet.
 
 @bar_p = global i32 (...)* @bar_ref, align 4
 @b_e = external global i32, align 4
 
 ; Function Attrs: noinline nounwind optnone
 define void @foo() {
 entry:

llvm/test/CodeGen/PowerPC/aix-func-align.ll

 ; This test tries to verify if a csect containing code would have the correct alignment.
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
+; RUN:     -xcoff-traceback-table=false < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
+; RUN:     -xcoff-traceback-table=false < %s | FileCheck %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
+; RUN:     -xcoff-traceback-table=false -filetype=obj -o %t.o < %s
 ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYMS %s
 
 ; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff -filetype=obj < %s 2>&1 | \
 ; RUN:   FileCheck --check-prefix=XCOFF64 %s
 ; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet.
 
 define i32 @foo()  align 32 {
 entry:

llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll

-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
+; RUN:     -xcoff-traceback-table=false -filetype=obj -o %t.o < %s
 ; RUN: llvm-readobj  --symbols %t.o | FileCheck %s
 
 define void @foo() {
 entry:
   ret void
 }
 
 ; CHECK:      File: {{.*}}aix-func-dsc-gen.ll.tmp.o

llvm/test/CodeGen/PowerPC/aix-return55.ll

-; RUN: llc -mcpu=pwr4 -mattr=-altivec -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs -data-sections=false < %s | FileCheck %s
-; RUN: llc -mcpu=pwr4 -mattr=-altivec -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs -data-sections=false -filetype=obj -o %t.o < %s
+; RUN: llc -mcpu=pwr4 -mattr=-altivec -mtriple=powerpc-ibm-aix-xcoff \
+; RUN:     -verify-machineinstrs -data-sections=false -xcoff-traceback-table=false < %s | FileCheck %s
+; RUN: llc -mcpu=pwr4 -mattr=-altivec -mtriple=powerpc-ibm-aix-xcoff \
+; RUN:     -verify-machineinstrs -data-sections=false -xcoff-traceback-table=false -filetype=obj -o %t.o < %s
 ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECKOBJ %s
 ; RUN: llvm-readobj -sections %t.o | FileCheck --check-prefix=CHECKSECT %s
 
 ; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff -filetype=obj < %s 2>&1 | \
 ; RUN: FileCheck --check-prefix=XCOFF64 %s
 ; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet.
 
 @a = global i64 320255973571806, align 8

llvm/test/CodeGen/PowerPC/aix-user-defined-memcpy.ll

 ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
-; RUN: -mattr=-altivec -filetype=obj -o %t.o < %s
+; RUN: -mattr=-altivec -filetype=obj -xcoff-traceback-table=false -o %t.o < %s
 
 ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=32-SYM %s
 
 ; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck \
 ; RUN: --check-prefix=32-REL %s
 
 ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=32-DIS %s
 

llvm/test/CodeGen/PowerPC/aix-weak.ll

-; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -xcoff-traceback-table=false -mcpu=pwr4 \
 ; RUN: -mattr=-altivec -data-sections=false < %s | FileCheck --check-prefixes=COMMON,BIT32 %s
 
-; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -xcoff-traceback-table=false -mcpu=pwr4 \
 ; RUN: -mattr=-altivec -data-sections=false < %s | FileCheck --check-prefixes=COMMON,BIT64 %s
 
-; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -xcoff-traceback-table=false -mcpu=pwr4 \
 ; RUN: -mattr=-altivec -data-sections=false -filetype=obj -o %t.o < %s
 ; RUN: llvm-readobj --symbols %t.o | FileCheck --check-prefix=CHECKSYM %s
 
 ; RUN: not --crash llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -mattr=-altivec -data-sections=false -filetype=obj -o %t.o 2>&1 < %s | \
 ; RUN:   FileCheck --check-prefix=XCOFF64 %s
 ; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet.
 

llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll

-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -data-sections < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
+; RUN:     -data-sections -xcoff-traceback-table=false < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK32 %s
 ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff -data-sections < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK64 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -data-sections -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
+; RUN:     -filetype=obj -data-sections -xcoff-traceback-table=false -o %t.o < %s
 ; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s
 ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s
 
 ;; Test to see if the default is correct for -data-sections on AIX.
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
+; RUN:     -xcoff-traceback-table=false < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK32 %s
 ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK64 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
+; RUN:     -xcoff-traceback-table=false -filetype=obj -o %t.o < %s
 ; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s
 ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s
 
 ;; Test to see if the default is correct for -data-sections on AIX.
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
+; RUN:     -xcoff-traceback-table=false < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK32 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
+; RUN:     -xcoff-traceback-table=false < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK64 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
+; RUN:     -xcoff-traceback-table=false -filetype=obj -o %t.o < %s
 ; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s
 ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s
 
 @ivar = local_unnamed_addr global i32 35, align 4
 @const_ivar = constant i32 35, align 4
 
 @a = common global i32 0, align 4
 @f = common local_unnamed_addr global i32 0, align 4

llvm/test/CodeGen/PowerPC/aix-xcoff-explicit-section.ll

-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
+; RUN:     -xcoff-traceback-table=false < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
+; RUN:     -xcoff-traceback-table=false < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
+; RUN:     -xcoff-traceback-table=false -filetype=obj -o %t.o < %s
 ; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s
 ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s
 
 @ext_const = constant i32 1, section ".ext_const_sec", align 4
 @ext_var = global i32 1, section ".ext_var_sec", align 4
 @ext_zvar = global i32 0, section ".ext_zvar_sec", align 4
 
 define dso_local signext i32 @ext_fun() section ".ext_fun_sec" {

llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll

 ; This file tests the codegen of mergeable const in AIX assembly.
 ; This file also tests mergeable const in XCOFF object file generation.
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -data-sections=false < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
+; RUN:     -data-sections=false -xcoff-traceback-table=false < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK32 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff -data-sections=false < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
+; RUN:     -xcoff-traceback-table=false -data-sections=false < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK64 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -data-sections=false -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
+; RUN:     -xcoff-traceback-table=false -data-sections=false -filetype=obj -o %t.o < %s
 ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECKOBJ %s
 ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s
 
 %struct.Merge_cnst32 = type { i64, i32, i64, i32 }
 %struct.Merge_cnst16 = type { i64, i32 }
 %struct.Merge_cnst8 = type { i32, i32 }
 %struct.Merge_cnst4 = type { i16, i8 }
 

llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll

 ; This file tests the codegen of mergeable strings in AIX assembly only.
 ; Once the codegen of mergeable strings for XCOFF object files is supported
 ; the test in this file should be merged into aix-xcoff-data.ll with additional
 ; tests for XCOFF object files.
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -xcoff-traceback-table=false \
 ; RUN:     -mtriple powerpc-ibm-aix-xcoff  -data-sections=false < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -xcoff-traceback-table=false \
 ; RUN:     -mtriple powerpc64-ibm-aix-xcoff -data-sections=false < %s | FileCheck %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -data-sections=false -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
+; RUN:     -xcoff-traceback-table=false -data-sections=false -filetype=obj -o %t.o < %s
 ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECKOBJ %s
 
 @magic16 = private unnamed_addr constant [4 x i16] [i16 264, i16 272, i16 213, i16 0], align 2
 @magic32 =  private unnamed_addr constant [4 x i32] [i32 464, i32 472, i32 413, i32 0], align 4
 @strA = private unnamed_addr constant [14 x i8] c"hello world!\0A\00", align 1
 @.str = private unnamed_addr constant [9 x i8] c"abcdefgh\00", align 1
 @p = global i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), align 4
 

llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-symb.mir

-# RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -x mir -verify-machineinstrs -start-after=lazy-machine-block-freq -filetype=obj -o %t.o < %s
+# RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -x mir -verify-machineinstrs \
+# RUN:     -xcoff-traceback-table=false -start-after=lazy-machine-block-freq -filetype=obj -o %t.o < %s
 # RUN: llvm-readobj --relocs --expand-relocs -t %t.o | FileCheck --check-prefixes=RELOC,SYM %s
 # RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=DIS %s
 
 ---
 name:            foo
 alignment:       16
 tracksRegLiveness: true
 jumpTable:

llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll

-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -mattr=-altivec -data-sections=false -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -mattr=-altivec \
+; RUN:     -xcoff-traceback-table=false -data-sections=false -filetype=obj -o %t.o < %s
 ; RUN: llvm-readobj --section-headers --file-header %t.o | \
 ; RUN: FileCheck --check-prefix=OBJ %s
 ; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefix=RELOC %s
 ; RUN: llvm-readobj -t %t.o | FileCheck --check-prefix=SYM %s
 ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=DIS %s
 ; RUN: llvm-objdump -r %t.o | FileCheck --check-prefix=DIS_REL %s
 
 ; RUN: not --crash llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -mattr=-altivec -data-sections=false -filetype=obj < %s 2>&1 | \

llvm/test/CodeGen/PowerPC/aix-xcoff-symbol-rename.ll

 ;; This file tests how llc handles symbols containing invalid characters on an
 ;; XCOFF platform.
 ;; Since symbol name resolution is the same between 32-bit and 64-bit,
 ;; tests for 64-bit mode are omitted.
 
 ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
-; RUN:     -mattr=-altivec -data-sections=false < %s | \
+; RUN:     -mattr=-altivec -data-sections=false -xcoff-traceback-table=false < %s | \
 ; RUN:   FileCheck --check-prefix=ASM %s
 
 ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
-; RUN:     -mattr=-altivec -data-sections=false -filetype=obj -o %t.o < %s
+; RUN:     -mattr=-altivec -data-sections=false -xcoff-traceback-table=false -filetype=obj -o %t.o < %s
 ; RUN: llvm-objdump -D -r --symbol-description %t.o | \
 ; RUN:   FileCheck --check-prefix=OBJ %s
 
 ; This is f`o
 @"f\60o" = global i32 10, align 4
 
 ; This is f"o"
 @"f\22o\22" = common global i32 0, align 4

llvm/test/CodeGen/PowerPC/aix-xcoff-textdisassembly.ll

-; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o  < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
+; RUN:     -xcoff-traceback-table=false -filetype=obj -o %t.o  < %s
 ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECK %s
 
 define i32 @foo() #0 {
 entry:
   ret i32 0
 }
 
 define i32 @foo1() #0 {

llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll

 ; This file tests TOC entry generation and undefined symbol generation.
 
-; RUN: llc  -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefixes CHECK,CHECK32 %s
-; RUN: llc  -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck --check-prefixes CHECK,CHECK64  %s
+; RUN: llc  -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
+; RUN:      -xcoff-traceback-table=false < %s | FileCheck --check-prefixes CHECK,CHECK32 %s
+; RUN: llc  -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
+; RUN:      -xcoff-traceback-table=false < %s 2>&1 | FileCheck --check-prefixes CHECK,CHECK64  %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
+; RUN:     --xcoff-traceback-table=false -filetype=obj -o %t.o < %s
 ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM %s
 
 ; RUN: not --crash llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff -filetype=obj -o %t.o 2>&1 \
 ; RUN: < %s | FileCheck --check-prefix=XCOFF64 %s
 ; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet.
 
 @a = external global i32, align 4
 @b = external global i64, align 8