This is an archive of the discontinued LLVM Phabricator instance.

Differential D92365

[PowerPC] Fix chain for i1-to-fp operation
ClosedPublic

Authored by qiucf on Nov 30 2020, 10:24 PM.

Details

Reviewers
steven.zhang
jsji
nemanjai
uweigand
Group Reviewers
Restricted Project
Commits
rGefdd4630507e: [PowerPC] Fix chain for i1-to-fp operation

Diff Detail

Event Timeline

qiucf created this revision.Nov 30 2020, 10:24 PM
Herald added a project: Restricted Project. · View Herald TranscriptNov 30 2020, 10:24 PM
Herald added subscribers: llvm-commits, shchenz, kbarton, hiraditya. · View Herald Transcript
qiucf requested review of this revision.Nov 30 2020, 10:24 PM
steven.zhang accepted this revision.Dec 6 2020, 5:22 PM

LGTM. Thank you for fixing this.

This revision is now accepted and ready to land.Dec 6 2020, 5:22 PM
steven.zhang added inline comments.Dec 6 2020, 5:25 PM
llvm/test/CodeGen/PowerPC/i1-to-fp-chain.ll
5

Can you move this into fp-strict-conv.ll instead of creating new test file ?

qiucf added inline comments.Dec 6 2020, 6:33 PM
llvm/test/CodeGen/PowerPC/i1-to-fp-chain.ll
5

I think we don't want ppc32 content for other test functions in the file.

Closed by commit rGefdd4630507e: [PowerPC] Fix chain for i1-to-fp operation (authored by qiucf). · Explain WhyDec 6 2020, 6:42 PM
This revision was automatically updated to reflect the committed changes.
qiucf added a commit: rGefdd4630507e: [PowerPC] Fix chain for i1-to-fp operation.

Revision Contents

PathSize
llvm/
lib/
Target/
PowerPC/
13 lines
test/
CodeGen/
PowerPC/
59 lines

Diff 309800

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 8,712 Lines • ▼ Show 20 LinesSDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
// Conversions to f128 are legal. // Conversions to f128 are legal.
if (Op.getValueType() == MVT::f128) if (Op.getValueType() == MVT::f128)
return Op; return Op;
// Don't handle ppc_fp128 here; let it be lowered to a libcall. // Don't handle ppc_fp128 here; let it be lowered to a libcall.
if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
return SDValue(); return SDValue();
if (Src.getValueType() == MVT::i1) if (Src.getValueType() == MVT::i1) {
return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Src, SDValue Sel = DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Src,
DAG.getConstantFP(1.0, dl, Op.getValueType()), DAG.getConstantFP(1.0, dl, Op.getValueType()),
DAG.getConstantFP(0.0, dl, Op.getValueType())); DAG.getConstantFP(0.0, dl, Op.getValueType()));
if (IsStrict)
return DAG.getMergeValues({Sel, Chain}, dl);
else
return Sel;
}
// If we have direct moves, we can do all the conversion, skip the store/load // If we have direct moves, we can do all the conversion, skip the store/load
// however, without FPCVT we can't do most conversions. // however, without FPCVT we can't do most conversions.
if (Subtarget.hasDirectMove() && directMoveIsProfitable(Op) && if (Subtarget.hasDirectMove() && directMoveIsProfitable(Op) &&
Subtarget.isPPC64() && Subtarget.hasFPCVT()) Subtarget.isPPC64() && Subtarget.hasFPCVT())
return LowerINT_TO_FPDirectMove(Op, DAG, dl); return LowerINT_TO_FPDirectMove(Op, DAG, dl);
assert((IsSigned || Subtarget.hasFPCVT()) && assert((IsSigned || Subtarget.hasFPCVT()) &&
▲ Show 20 Lines • Show All 8,314 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/i1-to-fp-chain.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=ppc32 < %s | FileCheck %s
@foo = dso_local global double 0.000000e+00, align 8
steven.zhangUnsubmitted
Not Done
ReplyInline Actions

Can you move this into fp-strict-conv.ll instead of creating new test file ?

steven.zhang: Can you move this into fp-strict-conv.ll instead of creating new test file ?
qiucfAuthorUnsubmitted
Done
ReplyInline Actions

I think we don't want ppc32 content for other test functions in the file.

qiucf: I think we don't want ppc32 content for other test functions in the file.
; Verify the cases won't crash because of missing chains
define double @u1tofp(i1 %i, double %d) #0 {
; CHECK-LABEL: u1tofp:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li 4, .LCPI0_0@l
; CHECK-NEXT: andi. 3, 3, 1
; CHECK-NEXT: addis 3, 4, .LCPI0_0@ha
; CHECK-NEXT: li 4, .LCPI0_1@l
; CHECK-NEXT: addis 4, 4, .LCPI0_1@ha
; CHECK-NEXT: bc 12, 1, .LBB0_1
; CHECK-NEXT: b .LBB0_2
; CHECK-NEXT: .LBB0_1: # %entry
; CHECK-NEXT: addi 3, 4, 0
; CHECK-NEXT: .LBB0_2: # %entry
; CHECK-NEXT: fmr 0, 1
; CHECK-NEXT: lfs 1, 0(3)
; CHECK-NEXT: lis 3, foo@ha
; CHECK-NEXT: stfd 0, foo@l(3)
; CHECK-NEXT: blr
entry:
%conv = tail call double @llvm.experimental.constrained.uitofp.f64.i1(i1 %i, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
store volatile double %d, double* @foo, align 8
ret double %conv
}
define double @s1tofp(i1 %i, double %d) #0 {
; CHECK-LABEL: s1tofp:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li 4, .LCPI1_0@l
; CHECK-NEXT: andi. 3, 3, 1
; CHECK-NEXT: addis 3, 4, .LCPI1_0@ha
; CHECK-NEXT: li 4, .LCPI1_1@l
; CHECK-NEXT: addis 4, 4, .LCPI1_1@ha
; CHECK-NEXT: bc 12, 1, .LBB1_1
; CHECK-NEXT: b .LBB1_2
; CHECK-NEXT: .LBB1_1: # %entry
; CHECK-NEXT: addi 3, 4, 0
; CHECK-NEXT: .LBB1_2: # %entry
; CHECK-NEXT: fmr 0, 1
; CHECK-NEXT: lfs 1, 0(3)
; CHECK-NEXT: lis 3, foo@ha
; CHECK-NEXT: stfd 0, foo@l(3)
; CHECK-NEXT: blr
entry:
%conv = tail call double @llvm.experimental.constrained.sitofp.f64.i1(i1 %i, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
store volatile double %d, double* @foo, align 8
ret double %conv
}
declare double @llvm.experimental.constrained.uitofp.f64.i1(i1, metadata, metadata)
declare double @llvm.experimental.constrained.sitofp.f64.i1(i1, metadata, metadata)
attributes #0 = { strictfp }