[PowerPC] Fix altivec feature on pwr cpus pre pwr6.

[sfertile]

Summary

The altivec feature was an optional part of the 2.03 (pwr4) and 2.04 (pwr5) ISAs, and it was not implemented by any IBM CPUs until Power6.

[hubert.reinterpretcast]

The altivec feature was an optional part of the 2.03 (pwr4) and 2.04 (pwr5) ISAs, and it was not implemented by any IBM CPUs until Power6.

The Power Processing Element in various IBM CPUs (including the Cell Broadband Engine) incorporate VMX. With this change, which of the CPU options should a user targeting a PPE use?

[sfertile]

In D92324#2422992, @hubert.reinterpretcast wrote:

The altivec feature was an optional part of the 2.03 (pwr4) and 2.04 (pwr5) ISAs, and it was not implemented by any IBM CPUs until Power6.

The Power Processing Element in various IBM CPUs (including the Cell Broadband Engine) incorporate VMX. With this change, which of the CPU options should a user targeting a PPE use?

I'm not really familiar with PPEs or CELL, but my understanding was that the generic ppc64 was what they targeted. From your question I'm guessing that understanding is wrong. If the best CPU to target for a PPE is one of the ones modified in this patch, they can still do so, but will have to explicitly add -mattr=+altivec when invoking llc. IR with '-mattr=+altivec,... will continue to enable altivec as well. If there are no objections I'll add -mattr=+altivec' to the vector-popcnt-128-ult-ugt.ll test, and add a test showing that the altivec attribute continues to work on pwr4/5.

[hubert.reinterpretcast]

In D92324#2423833, @sfertile wrote:

If the best CPU to target for a PPE is one of the ones modified in this patch, they can still do so, but will have to explicitly add -mattr=+altivec when invoking llc.

That sounds okay.

If there are no objections I'll add `-mattr=+altivec' to the vector-popcnt-128-ult-ugt.ll test, and add a test showing that the altivec attribute continues to work on pwr4/5.

No objections here.

[hubert.reinterpretcast]

llvm/lib/Target/PowerPC/PPC.td

532–533

Remove the last sentence here.

[sfertile]

• Added -mattr=+altivec to vector pop count test to keep pwr5 testing
• Added a test to show enabling altivec through function attribute.

[sfertile]

llvm/lib/Target/PowerPC/PPC.td

532–533

I think we need to keep a comment indicating the Power Systems didn't implement the optional extension to avoid having them enabled again in the future.

[hubert.reinterpretcast]

llvm/lib/Target/PowerPC/PPC.td

532–533

Yup, that's fine. I saw that you changed it to say "IBM Power system", which I guess is correct (the QS blade servers are "Cell BE" as opposed to "Power" systems).

llvm/lib/Target/PowerPC/PPC.td

 def : ProcessorModel<"a2", PPCA2Model,
                   [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
                    FeatureSTFIWX, FeatureLFIWAX,
                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
                    FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX,
                    Feature64Bit /*, Feature64BitRegs */, FeatureMFTB]>;
+
+// The first IBM designed processor with Altivec was the PPC970 aka G5,
+// but that did not appear in any IBM systems. While VMX/Altivec was added in
+// ISA 2.03 (pwr4), the extension was optional. The first IBM processor with
+// Altivec implemented in an IBM Power system was Power6.
 def : ProcessorModel<"pwr3", G5Model,
-                  [DirectivePwr3, FeatureAltivec,
-                   FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
+                  [DirectivePwr3, FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
                    FeatureSTFIWX, Feature64Bit]>;
 def : ProcessorModel<"pwr4", G5Model,
-                  [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
-                   FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
-                   FeatureSTFIWX, Feature64Bit, FeatureMFTB]>;
+                  [DirectivePwr4, FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
+                   FeatureFRSQRTE, FeatureSTFIWX, Feature64Bit, FeatureMFTB]>;
 def : ProcessorModel<"pwr5", G5Model,
-                  [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
-                   FeatureFSqrt, FeatureFRE, FeatureFRES,
-                   FeatureFRSQRTE, FeatureFRSQRTES,
-                   FeatureSTFIWX, Feature64Bit,
-                   FeatureMFTB, DeprecatedDST]>;
+                  [DirectivePwr5, FeatureMFOCRF, FeatureFSqrt, FeatureFRE,
+                   FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, FeatureSTFIWX,
+                   Feature64Bit, FeatureMFTB, DeprecatedDST]>;
 def : ProcessorModel<"pwr5x", G5Model,
-                  [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
-                   FeatureFSqrt, FeatureFRE, FeatureFRES,
-                   FeatureFRSQRTE, FeatureFRSQRTES,
-                   FeatureSTFIWX, FeatureFPRND, Feature64Bit,
-                   FeatureMFTB, DeprecatedDST]>;
+                  [DirectivePwr5x, FeatureMFOCRF, FeatureFSqrt, FeatureFRE,
+                   FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, FeatureSTFIWX,
+                   FeatureFPRND, Feature64Bit, FeatureMFTB, DeprecatedDST]>;
 def : ProcessorModel<"pwr6", G5Model,
                   [DirectivePwr6, FeatureAltivec,
                    FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
                    FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
                    FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
                    FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
                    FeatureMFTB, DeprecatedDST]>;
 def : ProcessorModel<"pwr6x", G5Model,

llvm/test/CodeGen/PowerPC/aix-AppendingLinkage.ll

-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < \
 ; RUN: %s | FileCheck %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < \
 ; RUN: %s | FileCheck %s
 
 @llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @foo, i8* null }]
 @llvm.global_dtors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @bar, i8* null }]
 
 define dso_local void @foo() {
 entry:
   ret void

llvm/test/CodeGen/PowerPC/aix-func-align.ll

 ; This test tries to verify if a csect containing code would have the correct alignment.
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
 ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYMS %s
 
 ; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff -filetype=obj < %s 2>&1 | \
 ; RUN:   FileCheck --check-prefix=XCOFF64 %s
 ; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet.
 
 define i32 @foo()  align 32 {
 entry:

llvm/test/CodeGen/PowerPC/aix-internal.ll

-; RUN: llc -mtriple powerpc-ibm-aix -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
+; RUN: llc -mtriple powerpc-ibm-aix -verify-machineinstrs -mcpu=pwr4 \
 ; RUN: -filetype=obj -o %t.o < %s
 ; RUN: llvm-readobj --syms %t.o | FileCheck %s
 ; RUN: not --crash llc -mtriple powerpc64-ibm-aix -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
 ; RUN: -filetype=obj -o %t.o < %s 2>&1 | FileCheck --check-prefix=64-CHECK %s
 
 define internal i32 @foo() {
   ret i32 1
 }

llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll

-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff \
 ; RUN:     -data-sections=false < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN:     -data-sections=false < %s | FileCheck --check-prefix=CHECK64 %s
 
 @foo_ptr = global void (...)* @foo
 declare void @foo(...)
 
 @bar_ptr1 = global void (...)* bitcast (void ()* @bar to void (...)*)
 define void @bar() {
 entry:

llvm/test/CodeGen/PowerPC/aix-return55.ll

-; RUN: llc -mcpu=pwr4 -mattr=-altivec -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs -data-sections=false < %s | FileCheck %s
-; RUN: llc -mcpu=pwr4 -mattr=-altivec -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs -data-sections=false -filetype=obj -o %t.o < %s
+; RUN: llc -mcpu=pwr4 -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs -data-sections=false < %s | FileCheck %s
+; RUN: llc -mcpu=pwr4 -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs -data-sections=false -filetype=obj -o %t.o < %s
 ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECKOBJ %s
 ; RUN: llvm-readobj -sections %t.o | FileCheck --check-prefix=CHECKSECT %s
 
 ; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff -filetype=obj < %s 2>&1 | \
 ; RUN: FileCheck --check-prefix=XCOFF64 %s
 ; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet.
 
 @a = global i64 320255973571806, align 8

llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll

-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -data-sections < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -data-sections < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK32 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff -data-sections < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -data-sections < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK64 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -data-sections -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -data-sections -o %t.o < %s
 ; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s
 ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s
 
 ;; Test to see if the default is correct for -data-sections on AIX.
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK32 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK64 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
 ; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s
 ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s
 
 ;; Test to see if the default is correct for -data-sections on AIX.
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK32 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK64 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
 ; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s
 ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s
 
 @ivar = local_unnamed_addr global i32 35, align 4
 @const_ivar = constant i32 35, align 4
 
 @a = common global i32 0, align 4
 @f = common local_unnamed_addr global i32 0, align 4

llvm/test/CodeGen/PowerPC/aix-xcoff-explicit-section.ll

-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
 ; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s
 ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s
 
 @ext_const = constant i32 1, section ".ext_const_sec", align 4
 @ext_var = global i32 1, section ".ext_var_sec", align 4
 @ext_zvar = global i32 0, section ".ext_zvar_sec", align 4
 
 define dso_local signext i32 @ext_fun() section ".ext_fun_sec" {

llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll

 ; This file tests the codegen of mergeable const in AIX assembly.
 ; This file also tests mergeable const in XCOFF object file generation.
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -data-sections=false < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -data-sections=false < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK32 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff -data-sections=false < %s | \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -data-sections=false < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK,CHECK64 %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -data-sections=false -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -data-sections=false -filetype=obj -o %t.o < %s
 ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECKOBJ %s
 ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s
 
 %struct.Merge_cnst32 = type { i64, i32, i64, i32 }
 %struct.Merge_cnst16 = type { i64, i32 }
 %struct.Merge_cnst8 = type { i32, i32 }
 %struct.Merge_cnst4 = type { i16, i8 }
 

llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll

 ; This file tests the codegen of mergeable strings in AIX assembly only.
 ; Once the codegen of mergeable strings for XCOFF object files is supported
 ; the test in this file should be merged into aix-xcoff-data.ll with additional
 ; tests for XCOFF object files.
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
-; RUN:     -mtriple powerpc-ibm-aix-xcoff  -data-sections=false < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
-; RUN:     -mtriple powerpc64-ibm-aix-xcoff -data-sections=false < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4  -mtriple powerpc-ibm-aix-xcoff \
+; RUN:     -data-sections=false < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN:     -data-sections=false < %s | FileCheck %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -data-sections=false -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -data-sections=false -filetype=obj -o %t.o < %s
 ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECKOBJ %s
 
 @magic16 = private unnamed_addr constant [4 x i16] [i16 264, i16 272, i16 213, i16 0], align 2
 @magic32 =  private unnamed_addr constant [4 x i32] [i32 464, i32 472, i32 413, i32 0], align 4
 @strA = private unnamed_addr constant [14 x i8] c"hello world!\0A\00", align 1
 @.str = private unnamed_addr constant [9 x i8] c"abcdefgh\00", align 1
 @p = global i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), align 4
 

llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll

-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff \
 ; RUN:     -filetype=obj -code-model=large -o %t.o < %s
 ; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefixes=RELOC %s
 ; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS %s
 
 @a = global i32 2, align 4
 @b = global i32 10, align 4
 @c = global i32 11, align 4
 

llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll

 ; This file tests TOC entry generation and undefined symbol generation.
 
-; RUN: llc  -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefixes CHECK,CHECK32 %s
-; RUN: llc  -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck --check-prefixes CHECK,CHECK64  %s
+; RUN: llc  -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefixes CHECK,CHECK32 %s
+; RUN: llc  -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck --check-prefixes CHECK,CHECK64  %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
 ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM %s
 
-; RUN: not --crash llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff -filetype=obj -o %t.o 2>&1 \
+; RUN: not --crash llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -filetype=obj -o %t.o 2>&1 \
 ; RUN: < %s | FileCheck --check-prefix=XCOFF64 %s
 ; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet.
 
 @a = external global i32, align 4
 @b = external global i64, align 8
 @c = external global i16, align 2
 @globa = common global i32 0, align 4
 

llvm/test/CodeGen/PowerPC/aix32-crsave.mir

-# RUN: llc -mtriple powerpc-unknown-aix-xcoff -x mir -mcpu=pwr4 -mattr=-altivec \
-# RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
-# RUN: FileCheck %s --check-prefixes=CHECK
+# RUN: llc -mtriple powerpc-unknown-aix-xcoff -x mir -mcpu=pwr4 \
+# RUN:     -run-pass=prologepilog --verify-machineinstrs < %s | \
+# RUN:   FileCheck %s --check-prefixes=CHECK
 
 ---
 name:            CRMultiSave
 alignment:       16
 tracksRegLiveness: true
 liveins:
   - { reg: '$r3', virtual-reg: '' }
 body:             |

llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll

-; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 -mattr=-altivec \
-; RUN: -mtriple=powerpc-ibm-aix-xcoff 2>&1 | FileCheck %s
+; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 \
+; RUN:     -mtriple=powerpc-ibm-aix-xcoff 2>&1 | FileCheck %s
 
-; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 -mattr=-altivec \
+; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 \
 ; RUN: -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s
 
 ; When we convert an `i64` to `f32` on 32-bit PPC target, a `setcc` will be
 ; generated. And this testcase verifies that the operand expansion of `setcc`
 ; will not crash.
 
 %struct.A = type { float }
 

llvm/test/CodeGen/PowerPC/ppc64-crsave.mir

 # RUN: llc -mtriple powerpc64le-unknown-linux-gnu -x mir -mcpu=pwr8 -mattr=-altivec \
 # RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
 # RUN: FileCheck %s --check-prefixes=CHECK,SAVEONE
 
 # RUN: llc -mtriple powerpc64-unknown-linux-gnu -x mir -mcpu=pwr7 -mattr=-altivec \
 # RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
 # RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL
 
 
-# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -x mir -mcpu=pwr4 -mattr=-altivec \
+# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -x mir -mcpu=pwr4 \
 # RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
 # RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL
 
 ---
 name:            CRAllSave
 alignment:       16
 tracksRegLiveness: true
 liveins:

llvm/test/CodeGen/PowerPC/pwr4-altivec.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr4 < %s | FileCheck %s
+
+define <16 x i8> @default(<16 x i8> %0) {
+; CHECK-LABEL: default:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    std 29, -24(1) # 8-byte Folded Spill
+; CHECK-NEXT:    addi 29, 7, -1
+; CHECK-NEXT:    addi 12, 4, -1
+; CHECK-NEXT:    and 7, 7, 29
+; CHECK-NEXT:    and 4, 4, 12
+; CHECK-NEXT:    lbz 29, 127(1)
+; CHECK-NEXT:    addi 0, 5, -1
+; CHECK-NEXT:    clrlwi 7, 7, 24
+; CHECK-NEXT:    std 30, -16(1) # 8-byte Folded Spill
+; CHECK-NEXT:    addi 30, 6, -1
+; CHECK-NEXT:    and 5, 5, 0
+; CHECK-NEXT:    and 6, 6, 30
+; CHECK-NEXT:    clrlwi 5, 5, 24
+; CHECK-NEXT:    lbz 11, 143(1)
+; CHECK-NEXT:    clrlwi 6, 6, 24
+; CHECK-NEXT:    cntlzw 5, 5
+; CHECK-NEXT:    lbz 12, 135(1)
+; CHECK-NEXT:    cntlzw 6, 6
+; CHECK-NEXT:    srwi 5, 5, 5
+; CHECK-NEXT:    srwi 6, 6, 5
+; CHECK-NEXT:    cntlzw 7, 7
+; CHECK-NEXT:    std 24, -64(1) # 8-byte Folded Spill
+; CHECK-NEXT:    xori 6, 6, 1
+; CHECK-NEXT:    xori 5, 5, 1
+; CHECK-NEXT:    std 27, -40(1) # 8-byte Folded Spill
+; CHECK-NEXT:    addi 27, 9, -1
+; CHECK-NEXT:    neg 6, 6
+; CHECK-NEXT:    and 9, 9, 27
+; CHECK-NEXT:    addi 27, 29, -1
+; CHECK-NEXT:    std 28, -32(1) # 8-byte Folded Spill
+; CHECK-NEXT:    addi 28, 8, -1
+; CHECK-NEXT:    and 29, 29, 27
+; CHECK-NEXT:    lbz 30, 119(1)
+; CHECK-NEXT:    and 8, 8, 28
+; CHECK-NEXT:    clrlwi 9, 9, 24
+; CHECK-NEXT:    clrlwi 8, 8, 24
+; CHECK-NEXT:    srwi 7, 7, 5
+; CHECK-NEXT:    lbz 24, 159(1)
+; CHECK-NEXT:    addi 0, 30, -1
+; CHECK-NEXT:    cntlzw 8, 8
+; CHECK-NEXT:    std 26, -48(1) # 8-byte Folded Spill
+; CHECK-NEXT:    addi 26, 10, -1
+; CHECK-NEXT:    and 0, 30, 0
+; CHECK-NEXT:    and 10, 10, 26
+; CHECK-NEXT:    addi 26, 12, -1
+; CHECK-NEXT:    lbz 28, 151(1)
+; CHECK-NEXT:    and 12, 12, 26
+; CHECK-NEXT:    addi 26, 24, -1
+; CHECK-NEXT:    std 25, -56(1) # 8-byte Folded Spill
+; CHECK-NEXT:    addi 25, 11, -1
+; CHECK-NEXT:    addi 30, 28, -1
+; CHECK-NEXT:    and 11, 11, 25
+; CHECK-NEXT:    and 26, 24, 26
+; CHECK-NEXT:    lbz 27, 167(1)
+; CHECK-NEXT:    and 30, 28, 30
+; CHECK-NEXT:    srwi 8, 8, 5
+; CHECK-NEXT:    lbz 25, 175(1)
+; CHECK-NEXT:    addi 28, 27, -1
+; CHECK-NEXT:    xori 8, 8, 1
+; CHECK-NEXT:    and 28, 27, 28
+; CHECK-NEXT:    clrlwi 30, 30, 24
+; CHECK-NEXT:    lbz 24, 183(1)
+; CHECK-NEXT:    addi 27, 25, -1
+; CHECK-NEXT:    neg 8, 8
+; CHECK-NEXT:    and 27, 25, 27
+; CHECK-NEXT:    addi 25, 24, -1
+; CHECK-NEXT:    stb 6, 2(3)
+; CHECK-NEXT:    and 25, 24, 25
+; CHECK-NEXT:    clrlwi 27, 27, 24
+; CHECK-NEXT:    stb 8, 4(3)
+; CHECK-NEXT:    clrlwi 25, 25, 24
+; CHECK-NEXT:    neg 5, 5
+; CHECK-NEXT:    cntlzw 6, 25
+; CHECK-NEXT:    cntlzw 9, 9
+; CHECK-NEXT:    stb 5, 1(3)
+; CHECK-NEXT:    srwi 6, 6, 5
+; CHECK-NEXT:    xori 7, 7, 1
+; CHECK-NEXT:    cntlzw 8, 30
+; CHECK-NEXT:    cntlzw 30, 27
+; CHECK-NEXT:    xori 5, 6, 1
+; CHECK-NEXT:    srwi 9, 9, 5
+; CHECK-NEXT:    clrlwi 28, 28, 24
+; CHECK-NEXT:    neg 7, 7
+; CHECK-NEXT:    stb 7, 3(3)
+; CHECK-NEXT:    neg 5, 5
+; CHECK-NEXT:    srwi 6, 30, 5
+; CHECK-NEXT:    xori 9, 9, 1
+; CHECK-NEXT:    cntlzw 7, 28
+; CHECK-NEXT:    stb 5, 15(3)
+; CHECK-NEXT:    xori 5, 6, 1
+; CHECK-NEXT:    clrlwi 12, 12, 24
+; CHECK-NEXT:    clrlwi 26, 26, 24
+; CHECK-NEXT:    neg 9, 9
+; CHECK-NEXT:    stb 9, 5(3)
+; CHECK-NEXT:    neg 5, 5
+; CHECK-NEXT:    srwi 6, 7, 5
+; CHECK-NEXT:    cntlzw 9, 12
+; CHECK-NEXT:    cntlzw 12, 26
+; CHECK-NEXT:    stb 5, 14(3)
+; CHECK-NEXT:    xori 5, 6, 1
+; CHECK-NEXT:    srwi 6, 12, 5
+; CHECK-NEXT:    neg 5, 5
+; CHECK-NEXT:    clrlwi 10, 10, 24
+; CHECK-NEXT:    stb 5, 13(3)
+; CHECK-NEXT:    xori 5, 6, 1
+; CHECK-NEXT:    clrlwi 11, 11, 24
+; CHECK-NEXT:    neg 5, 5
+; CHECK-NEXT:    srwi 6, 8, 5
+; CHECK-NEXT:    stb 5, 12(3)
+; CHECK-NEXT:    cntlzw 10, 10
+; CHECK-NEXT:    cntlzw 11, 11
+; CHECK-NEXT:    xori 5, 6, 1
+; CHECK-NEXT:    srwi 10, 10, 5
+; CHECK-NEXT:    neg 5, 5
+; CHECK-NEXT:    srwi 6, 11, 5
+; CHECK-NEXT:    stb 5, 11(3)
+; CHECK-NEXT:    xori 10, 10, 1
+; CHECK-NEXT:    xori 5, 6, 1
+; CHECK-NEXT:    clrlwi 0, 0, 24
+; CHECK-NEXT:    clrlwi 29, 29, 24
+; CHECK-NEXT:    neg 10, 10
+; CHECK-NEXT:    neg 5, 5
+; CHECK-NEXT:    stb 10, 6(3)
+; CHECK-NEXT:    srwi 6, 9, 5
+; CHECK-NEXT:    cntlzw 10, 0
+; CHECK-NEXT:    cntlzw 0, 29
+; CHECK-NEXT:    stb 5, 10(3)
+; CHECK-NEXT:    xori 5, 6, 1
+; CHECK-NEXT:    clrlwi 4, 4, 24
+; CHECK-NEXT:    neg 5, 5
+; CHECK-NEXT:    stb 5, 9(3)
+; CHECK-NEXT:    srwi 6, 0, 5
+; CHECK-NEXT:    cntlzw 4, 4
+; CHECK-NEXT:    xori 5, 6, 1
+; CHECK-NEXT:    srwi 6, 10, 5
+; CHECK-NEXT:    neg 5, 5
+; CHECK-NEXT:    srwi 4, 4, 5
+; CHECK-NEXT:    stb 5, 8(3)
+; CHECK-NEXT:    xori 5, 6, 1
+; CHECK-NEXT:    xori 4, 4, 1
+; CHECK-NEXT:    neg 5, 5
+; CHECK-NEXT:    neg 4, 4
+; CHECK-NEXT:    stb 5, 7(3)
+; CHECK-NEXT:    stb 4, 0(3)
+; CHECK-NEXT:    ld 30, -16(1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld 29, -24(1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld 28, -32(1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld 27, -40(1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld 26, -48(1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld 25, -56(1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld 24, -64(1) # 8-byte Folded Reload
+; CHECK-NEXT:    blr
+  %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
+  %3 = icmp ugt <16 x i8> %2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  %4 = sext <16 x i1> %3 to <16 x i8>
+  ret <16 x i8> %4
+}
+
+define <16 x i8> @altivec_enabled(<16 x i8> %0) #0 {
+; CHECK-LABEL: altivec_enabled:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vspltisb 3, -1
+; CHECK-NEXT:    vaddubm 3, 2, 3
+; CHECK-NEXT:    vand 2, 2, 3
+; CHECK-NEXT:    vxor 3, 3, 3
+; CHECK-NEXT:    vcmpequb 2, 2, 3
+; CHECK-NEXT:    vnot 2, 2
+; CHECK-NEXT:    blr
+  %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0)
+  %3 = icmp ugt <16 x i8> %2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  %4 = sext <16 x i1> %3 to <16 x i8>
+  ret <16 x i8> %4
+}
+
+declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>)
+
+attributes #0 = { norecurse nounwind readnone "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="+altivec,-bpermd,-crypto,-direct-move,-extdiv,-htm,-power8-vector,-power9-vector,-spe,-vsx" "unsafe-fp-math"="false" "use-soft-float"="false" }

llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr5 < %s | FileCheck %s --check-prefixes=ANYPWR,PWR5
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr5 -mattr=+altivec < %s | FileCheck %s --check-prefixes=ANYPWR,PWR5
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr6 < %s | FileCheck %s --check-prefixes=ANYPWR,PWR6
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s --check-prefixes=ANYPWR,PWR7
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s --check-prefixes=ANYPWR,PWR8
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s --check-prefixes=ANYPWR,PWR9
 
 
 define <16 x i8> @ugt_1_v16i8(<16 x i8> %0) {
 ; PWR5-LABEL: ugt_1_v16i8: